WO2019024351A1 - 避免贴片元件立碑的pcb板设计方法及封装方法及pcb板 - Google Patents

避免贴片元件立碑的pcb板设计方法及封装方法及pcb板 Download PDF

Info

Publication number
WO2019024351A1
WO2019024351A1 PCT/CN2017/113702 CN2017113702W WO2019024351A1 WO 2019024351 A1 WO2019024351 A1 WO 2019024351A1 CN 2017113702 W CN2017113702 W CN 2017113702W WO 2019024351 A1 WO2019024351 A1 WO 2019024351A1
Authority
WO
WIPO (PCT)
Prior art keywords
pad
pcb board
area
chip component
pads
Prior art date
Application number
PCT/CN2017/113702
Other languages
English (en)
French (fr)
Inventor
王英娜
Original Assignee
郑州云海信息技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 郑州云海信息技术有限公司 filed Critical 郑州云海信息技术有限公司
Priority to US16/097,234 priority Critical patent/US20210227701A1/en
Publication of WO2019024351A1 publication Critical patent/WO2019024351A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3494—Heating methods for reflowing of solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09418—Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099—Coating over pads, e.g. solder resist partly over pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10015—Non-printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10022—Non-printed resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/10886—Other details
    • H05K2201/10916—Terminals having auxiliary metallic piece, e.g. for soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the technical field of PCB board packaging, in particular to a PCB board design method, a packaging method and a PCB board for avoiding the stick component tombstone.
  • the server board is in the production stage of the PCBA (printed circuit board assembly) factory.
  • the chip components such as resistors and capacitors are soldered during the surface mount process, because the solder paste on the pads on both ends of the device is When reflowing, the two solder joints of the component will have different surface tensions. The one end of the tension will pull the component to rotate and the other end will stand up. This phenomenon is the tombstoning phenomenon.
  • the preheating temperature setting is low or the preheating temperature setting is short, the shape and size of the pad pattern at both ends are inconsistent, the thickness of the solder paste is thick, and the offset of the mounting offset is large. Factors such as the small volume and weight of the components will cause the phenomenon of tombstoning.
  • the technical scheme adopted by the present invention is: a method for designing a 0201 component pad is disclosed.
  • the method is provided with a right angle chamfer on the square pad of the 0201 component, the square pad of the 0201 component is two in each group, and two square pads are arranged side by side, and each square pad is chamfered Two, two chamfers are disposed on the outer side of the square pad;
  • the invention can save the layout space by modifying the pad design of the 0201 component, prevent the green oil from being on the pad, and improve the PCB yield;
  • the phenomenon of tombstoning is generated to improve the yield of PCBA process; the invention patent prevents the phenomenon of tombstoning by changing the shape of the pad.
  • the chip components such as resistors and capacitors usually have copper wires at one end.
  • One end is a phenomenon of copper skin, so that at the end of the reflow soldering, the end of the copper skin will cause the solder paste to melt slowly due to the faster heat dissipation, while the solder paste melts faster at the other end, and the adhesion to the component is strong and there will be copper.
  • the chip components such as resistors and capacitors usually manually set the pad properties of the chip components such as resistors and capacitors, in order to avoid the phenomenon of tombstoning.
  • the technical task of the present invention is to provide a PCB board design method, a packaging method and a PCB board for avoiding the sticking of the component of the patch component, so as to solve the problem that the solder paste is melted slowly at one end of the copper strip at the end of the copper wire in the prior art, and the solder paste is melted.
  • the faster end has a stronger adhesion to the patch element and pulls the other end of the patch element to cause a tombstone problem.
  • a PCB board design method for avoiding a patch component totem characterized in that it comprises the following steps:
  • At least one chip component placement area is disposed on the PCB board, and each of the chip component placement areas is provided with a pad, and each of the pads has two pads, and the two pads are arranged side by side;
  • a pad limit area is established around the pad.
  • a pad limiting area is established around the periphery of all the pads on the PCB.
  • a pad limiting area is established around a portion of the pads on the PCB board; the PCB board is printed such that the pad limiting area pattern is printed on the pad limiting area.
  • a PCB board packaging method for avoiding the mounting of a chip component the chip component has a copper skin at one end and a copper wire at the other end; or both ends of the chip component are copper skin; in step a2, all the PCB boards are used.
  • a pad limiting area is established around the pad to obtain a PCB board; both ends of the chip component are mounted on the pad for reflow soldering.
  • a PCB board packaging method for avoiding the mounting of a chip component the chip component has a copper skin at one end and a copper wire at the other end; or both ends of the chip component are copper skin; in step a2, the PCB board is used. a pad-restricted area is formed around a portion of the pad; the PCB board is printed such that a pad-restricted area pattern is printed on the pad-restricted area to obtain a PCB board; and a pad-restricted area pattern is printed on a portion of the pad on the PCB board.
  • the copper end of the chip component is mounted on the pad on which the pad-restricted area pattern is printed for reflow soldering.
  • the copper end of the chip component is mounted on a pad having no printed pad confinement pattern for reflow soldering.
  • the pad confinement region pattern is divided into a left confinement region pattern and a right confinement region pattern, the left confinement region pattern shape is a symmetric fan shape, and the right confinement region pattern is an arcuate shape.
  • an isolation region is disposed between adjacent two pad confinement region patterns.
  • the PCB board includes a chip component placement area and a pad, and the PCB board is provided with at least one chip component placement area, and each patch element placement area is provided with a pad, and each of the pads has two, and two The pads are arranged side by side; the pad boundaries are established around the pads.
  • the pad confinement region is printed with a pad confinement region pattern; the pad confinement region pattern is divided into a left confinement region pattern and a right confinement region pattern, the left confinement region pattern shape is a symmetric fan shape, and the right confinement region pattern is arcuate Shape; an isolation region is disposed between adjacent two pad restriction regions.
  • One end of the chip component is a copper skin, and the other end is a copper wire.
  • the pad limiting area and the printed PCB board are formed on the periphery of all the pads on the PCB board, so that the pad limiting area is printed on the pad limiting area.
  • the pattern is obtained, the PCB board is obtained; the two ends of the chip component are mounted on the pad for reflow soldering, and the pad limiting area can prevent the connection of the pad and the copper skin, reduce the connection area between the pad and the copper skin, and reduce The heat dissipation speed can effectively prevent the tombstoning phenomenon caused by uneven heat dissipation at both ends of the chip component;
  • One end of the chip component is a copper skin, and the other end is a copper wire.
  • a pad limiting area is formed around a part of the pad on the PCB board, and the PCB board is printed, so that a pad limiting area pattern is printed on a part of the pad limiting area.
  • An isolation region is disposed between adjacent two pad limiting region patterns, and the purpose of the isolation region is to isolate and distinguish adjacent two pads;
  • the disk attribute reduces the contact area between the pad and the copper skin, effectively avoiding the tombstoning phenomenon of the chip components such as the resistor and capacitor, and improves the design efficiency of the engineer, reduces the workload of the manual operation of the engineer, and reduces the error. rate;
  • the design is simple in structure, easy to design, process, produce and use. It not only avoids the phenomenon of stabilizing the components such as resistors and capacitors in the reflow process, but also reduces the labor intensity of the staff, improves work efficiency and saves resources. , to reduce the design and production costs, and therefore, has a good promotion value.
  • 1 is a schematic structural view of a pad confinement region
  • FIG. 2 is a schematic structural view of a PCB board to which a pad restriction region is added.
  • the PCB board design method for avoiding patch element tombstone of the invention comprises the following steps:
  • A1 two chip component placement areas 2 are disposed on the PCB, and each of the chip component placement areas 2 is provided with a pad 3, and each of the pads 3 has two, and two pads 3 are arranged side by side;
  • a pad confinement region 4 is established around the pad 3.
  • step a2 the pad confinement region 4 is established on the periphery of all the pads 3 on the PCB board 1; the PCB board 1 is printed such that the pad confinement region pattern is printed on the pad confinement region 4.
  • the PCB board design method for avoiding patch element tombstone of the invention comprises the following steps:
  • A1 three chip component placement areas 2 are arranged on the PCB board, and each of the chip component placement areas 2 is provided with a pad 3, and each of the pads 3 has two, and two pads 3 are arranged side by side;
  • a pad confinement region 4 is established around the pad 3.
  • the pad restriction region 4 is formed around the periphery of the partial pad 3 on the PCB board 1; the PCB board 1 is printed such that the pad restriction region pattern is printed on the pad restriction region 4.
  • the patch component 8 is a 0402 chip capacitor component, the chip component 8 has a copper skin 5 at one end, and a copper wire 6 at the other end; or a patch component 8 Both ends are copper skins 5; the pad limiting area 4 is established on the periphery of all the pads 3 on the PCB board 1; the PCB board 1 is printed, so that the pad limiting area pattern is printed on the pad limiting area 4, and the PCB is obtained. Plate 1; both ends of the chip component 8 are mounted on the pad 3 and reflowed by using a solder paste.
  • the patch component 8 is a 0201 chip capacitor component, and one end of the patch component 8 is a copper foil 5, and the other end is a copper wire 6; or the patch component 8
  • the both ends are copper bumps 5;
  • the pad limiting regions 4 are formed on the periphery of the partial pads 3 on the PCB board 1;
  • the PCB board 1 is printed, so that the pad limiting area pattern is printed on the pad limiting area 4, and the PCB board is obtained. 1;
  • the copper end 5 of the patch element 8 is mounted on the pad 3 on which the pad-restricted area pattern is printed and reflowed by solder paste.
  • the patch component 8 is a 0402 chip capacitive component, the chip component 8 has a copper skin 5 at one end and a copper wire 6 at the other end;
  • the periphery of the partial pad 3 establishes the pad confinement region 4;
  • the printed PCB board 1 is printed with the pad confinement region pattern printed on the pad confinement region 4, and the pad confinement region pattern is divided into a left confinement region pattern and a right confinement region pattern,
  • the pattern of the left restriction area is a symmetrical fan shape, the pattern of the right restriction area is an arcuate shape, and the PCB board 1 is obtained;
  • the copper end 5 of the patch element 8 is mounted on the pad 3 printed with the pad restriction area pattern and Reflow soldering is performed by solder paste;
  • the copper wire 6 end of the chip component 8 is mounted on the pad 3 having no pattern of the printed pad confinement region and reflow soldered by solder paste;
  • the pattern of adjacent two pad confinement regions is Set the isolation area 7 between.
  • the PCB board of the present invention comprises a chip component placement area 2 and a pad 3, and the PCB board 1 is provided with at least one chip component placement area 2, and each of the chip component placement areas 2 is provided with a pad 3, a pad 3 each group has two, and two pads 3 are arranged side by side; the pad 3 is formed with a pad confinement region 4; by printing the PCB board 1, the pad confinement region 4 is printed with a pad confinement region pattern; Disk restriction area The pattern is divided into a left restriction area pattern and a right restriction area pattern, the left restriction area pattern shape is a symmetrical sector shape, and the right restriction area pattern is an arcuate shape; an isolation area 7 is disposed between adjacent two pad restriction area patterns.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

一种避免贴片元件立碑的PCB板设计方法及封装方法及PCB板，属于PCB板封装技术领域，所要解决的技术问题为：解决现有技术中回流焊时铜皮一端较铜线一端锡膏融化较慢，锡膏融化较快的一端对贴片元件（8）的附着力较强且拉动贴片元件的另一端而出现立碑的问题，采用的技术方案为：在PCB板(1)上设有至少一个贴片元件安置区(2)，每个贴片元件安置区内设有焊盘(3)，焊盘每组有两个，且两个焊盘并排布置；在焊盘的周边建立焊盘限制区(4)；并将贴片元件通过回流焊焊接到PCB板上。能够有效地避免贴片元件发生立碑现象，并且能够提高设计效率，减少工程师手动操作的工作量，降低错误率。

Description

避免贴片元件立碑的PCB板设计方法及封装方法及PCB板
本申请要求于2017年7月31日提交中国专利局、申请号为201710639229.3、发明名称为“避免贴片元件立碑的PCB板设计方法及封装方法及PCB板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及PCB板封装技术领域，具体地说是避免贴片元件立碑的PCB板设计方法及封装方法及PCB板。
背景技术
服务器板卡在PCBA(印刷电路板装配PCBA，printed circuit board assembly)工厂的生产阶段，电阻电容等贴片元件在表面贴装工艺的回流焊过程中，由于元件两端焊盘上的锡膏在回流熔化时，元件两个焊端会产生不同的表面张力，张力较大的一端会拉着元件旋转而使另一端竖立起来，该现象就是立碑现象。而造成表面张力不平衡的因素有很多，例如：预热温度设置较低或预热温度设置较短、两端焊盘图形形状与尺寸不一致、焊膏厚度厚、贴装偏移贴片偏差大、元件体积重量较小等因素都会引起立碑现象。
为避免立碑现象的发生，如专利ZL201611147023.0，名称为“一种0201元件焊盘的设计方法和PCB板”，本发明采用的技术方案为：公开了一种0201元件焊盘的设计方法和PCB板，所述方法在0201元件的方形焊盘上设置直角倒角，所述0201元件的方形焊盘每组为2个，2个方形焊盘并排设置，每个方形焊盘倒角设置2个，2个倒角设置于方形焊盘的外侧；本发明通过修改0201元件的焊盘设计，能够节省layout布局空间，防止绿油上焊盘，提高了PCB良率；能够避免圆形pad产生立碑现象，提升PCBA制程良率；该发明专利是通过改变焊盘形状来防止立碑现象的发生。
然而，在PCB设计过程中，电阻电容等贴片元件通常会有一端是铜线， 一端是铜皮的现象，这样在回流焊时有铜皮的一端会因散热较快致使锡膏熔化较慢，而另一端则锡膏熔化较快，对元件的附着力较强而将有铜皮那端的贴片元件拉起，造成立碑的现象，为避免出现立碑现象，在传统的PCB设计中，电阻电容等贴片元件通常会手动设置电阻电容等贴片元件的焊盘属性，从而减少焊盘与铜皮的接触面积；例如：通过手动设置使用三根铜线和焊盘相连，目的为减小焊盘与铜皮的接触面积，从而降低了散热速度，避免了立碑现象的发生；但是还存在如下缺点：1、由于需要手动设置焊盘属性，导致Layout工程师工作量较大；2、在设计过程中，会因新的电阻、电容等贴片元件的不断添加，容易造成遗漏，设计效率较低；因此，立碑现象的出现降低了PCB板卡生产的可制造性。
发明内容
本发明的技术任务是提供避免贴片元件立碑的PCB板设计方法及封装方法及PCB板，来解决现有技术中回流焊时铜皮一端较铜线一端锡膏融化较慢，锡膏融化较快的一端对贴片元件的附着力较强且拉动贴片元件的另一端而出现立碑的问题。
本发明的技术任务是按以下方式实现的：
避免贴片元件立碑的PCB板设计方法，其特征在于，包括以下步骤：
a1、在PCB板上设有至少一个贴片元件安置区，每个贴片元件安置区内设有焊盘，焊盘每组有两个，且两个焊盘并排布置；
a2、在焊盘的周边建立焊盘限制区。
可选地，步骤a2中，将PCB板上的所有焊盘的周边均建立焊盘限制区。
可选地，步骤a2中，将PCB板上的部分焊盘的周边建立焊盘限制区；印刷PCB板，使得焊盘限制区上印刷有焊盘限制区图案。
避免贴片元件立碑的PCB板封装方法，贴片元件的一端为铜皮，另一端为铜线；或贴片元件的两端都为铜皮；使用步骤a2中，将PCB板上的所有焊盘的周边均建立焊盘限制区，得到PCB板；将贴片元件的两端贴装于焊盘上进行回流焊。
避免贴片元件立碑的PCB板封装方法，贴片元件的一端为铜皮，另一端为铜线；或贴片元件的两端都为铜皮；使用步骤a2中，将PCB板上的 部分焊盘的周边建立焊盘限制区；印刷PCB板，使得焊盘限制区上印刷有焊盘限制区图案，得到PCB板；所述PCB板上部分焊盘周边印刷有焊盘限制区图案，将贴片元件的铜皮端贴装于印刷有焊盘限制区图案的焊盘上进行回流焊。
可选地，贴片元件的铜线端贴装于没有印刷焊盘限制区图案的焊盘上进行回流焊。
可选地，焊盘限制区图案分为左限制区图案和右限制区图案，左限制区图案形状为对称的扇形形状，右限制区图案为弓形形状。
可选地，相邻两个焊盘限制区图案之间设置有隔离区。
PCB板，包括贴片元件安置区和焊盘，PCB板上设有至少一个贴片元件安置区，每个贴片元件安置区内设有焊盘，焊盘每组有两个，且两个焊盘并排布置；焊盘的周边建立有焊盘限制区。
可选地，焊盘限制区印刷有焊盘限制区图案；焊盘限制区图案分为左限制区图案和右限制区图案，左限制区图案形状为对称的扇形形状，右限制区图案为弓形形状；相邻两个焊盘限制区图案之间设置有隔离区。
本发明的避免贴片元件立碑的PCB板设计方法及封装方法及PCB板具有以下优点：
1、贴片元件的一端为铜皮，另一端为铜线，将PCB板上的所有焊盘的周边均建立焊盘限制区、印刷PCB板，使得焊盘限制区上印刷有焊盘限制区图案，得到PCB板；将贴片元件的两端贴装于焊盘上进行回流焊，焊盘限制区能够阻止焊盘和铜皮的连接，减小焊盘与铜皮间的连接面积，降低了散热速度，能够有效防止贴片元件两端散热不均造成的立碑现象；
2、贴片元件的一端为铜皮，另一端为铜线，将PCB板上的部分焊盘四周建立焊盘限制区，印刷PCB板，使得部分焊盘限制区上印刷有焊盘限制区图案，得到PCB板；将贴片元件的铜皮端贴装于印刷有焊盘限制区图案的焊盘上进行回流焊，而贴片元件的铜线端贴装没有印刷焊盘限制区图案的焊盘上进行回流焊，不仅能够防止立碑现象的发生而且只在与铜皮端焊接的焊盘周边印刷焊盘限制区图案有利于降低设计、生产成本；
3、相邻两个焊盘限制区图案之间设置有隔离区，隔离区的目的是用于隔离和区分相邻的两个焊盘；
4、通过在焊盘周边建立焊盘限制区，避免了传统采用人工手动设置焊 盘属性来减小焊盘与铜皮的接触面积，有效避免了电阻电容等贴片元件发生立碑现象，同时提高了工程师的的设计效率，减少了工程师手动操作的工作量，并且降低了错误率；
5、该设计结构简单、易于设计加工生产、使用方便，不仅能够避免电阻电容等贴片元件在回流焊过程中的立碑现象，而且还能够减轻工作人员的劳动强度，提高工作效率，节省资源，降低设计和生产成本，因而，具有很好的推广使用价值。
附图说明
下面结合附图对本发明进一步说明。
附图1为焊盘限制区的结构示意图；
附图2为添加焊盘限制区的PCB板的结构示意图。
图中：1、PCB板，2、贴片元件安置区，3、焊盘，4、焊盘限制区，5、铜皮，6、铜线，7、隔离区，8、贴片元件。
具体实施方式
参照说明书附图和具体实施例对本发明的一种避免贴片元件立碑的PCB封装设计方法及PCB板作以下详细地说明。
实施例1：
本发明的避免贴片元件立碑的PCB板设计方法，包括以下步骤：
a1、在PCB板上设有两个贴片元件安置区2，每个贴片元件安置区2内设有焊盘3，焊盘3每组有两个，且两个焊盘3并排布置；
a2、在焊盘3的周边建立焊盘限制区4。
在步骤a2中，将PCB板1上的所有焊盘3的周边均建立焊盘限制区4；印刷PCB板1，使得焊盘限制区4上印刷有焊盘限制区图案。
实施例2：
本发明的避免贴片元件立碑的PCB板设计方法，包括以下步骤：
a1、在PCB板上设有三个贴片元件安置区2，每个贴片元件安置区2内设有焊盘3，焊盘3每组有两个，且两个焊盘3并排布置；
a2、在焊盘3的周边建立焊盘限制区4。
在步骤a2中，将PCB板1上的部分焊盘3的周边建立焊盘限制区4；印刷PCB板1，使得焊盘限制区4上印刷有焊盘限制区图案。
实施例3：
本发明的避免贴片元件立碑的PCB板封装方法，贴片元件8为0402贴片电容元件，贴片元件8的一端为铜皮5，另一端为铜线6；或贴片元件8的两端都为铜皮5；将PCB板1上的所有焊盘3的周边均建立焊盘限制区4；印刷PCB板1，使得焊盘限制区4上印刷有焊盘限制区图案，得到PCB板1；将贴片元件8的两端贴装于焊盘3上并通过使用锡膏进行回流焊。
实施例4：
本发明的避免贴片元件立碑的PCB板封装方法，贴片元件8为0201贴片电容元件，贴片元件8的一端为铜皮5，另一端为铜线6；或贴片元件8的两端都为铜皮5；将PCB板1上的部分焊盘3的周边建立焊盘限制区4；印刷PCB板1，使得焊盘限制区4上印刷有焊盘限制区图案，得到PCB板1；将贴片元件8的铜皮5端贴装于印刷有焊盘限制区图案的焊盘3上并通过锡膏进行回流焊。
实施例5：
本发明的避免贴片元件立碑的PCB板封装方法，贴片元件8为0402贴片电容元件，贴片元件8的一端为铜皮5，另一端为铜线6；将PCB板1上的部分焊盘3的周边建立焊盘限制区4；印刷PCB板1，使得焊盘限制区4上印刷有焊盘限制区图案，焊盘限制区图案分为左限制区图案和右限制区图案，左限制区图案形状为对称的扇形形状，右限制区图案为弓形形状，得到PCB板1；将贴片元件8的铜皮5端贴装于印刷有焊盘限制区图案的焊盘3上并通过锡膏进行回流焊；将贴片元件8的铜线6端贴装于没有印刷焊盘限制区图案的焊盘3上并通过锡膏进行回流焊；相邻两个焊盘限制区图案之间设置隔离区7。
实施例6：
本发明的PCB板，包括贴片元件安置区2和焊盘3，PCB板1上设有至少一个贴片元件安置区2，每个贴片元件安置区2内设有焊盘3，焊盘3每组有两个，且两个焊盘3并排布置；焊盘3的周边建立有焊盘限制区4；通过印刷PCB板1，使焊盘限制区4印刷有焊盘限制区图案；焊盘限制区 图案分为左限制区图案和右限制区图案，左限制区图案形状为对称的扇形形状，右限制区图案为弓形形状；相邻两个焊盘限制区图案之间设置有隔离区7。
通过上面具体实施方式，所述技术领域的技术人员可容易的实现本发明。但是应当理解，本发明并不限于上述的6种具体实施方式。在公开的实施方式的基础上，所述技术领域的技术人员可任意组合不同的技术特征，从而实现不同的技术方案。
除说明书所述的技术特征外，均为本专业技术人员的已知技术。

Claims (10)

  1. 避免贴片元件立碑的PCB板设计方法，其特征在于，包括以下步骤：
    a1、在PCB板上设有至少一个贴片元件安置区，每个贴片元件安置区内设有焊盘，焊盘每组有两个，且两个焊盘并排布置；
    a2、在焊盘的周边建立焊盘限制区。
  2. 根据权利要求1所述的避免贴片元件立碑的PCB板设计方法，其特征在于，步骤a2中，将PCB板上的所有焊盘的周边均建立焊盘限制区。
  3. 根据权利要求1所述的避免贴片元件立碑的PCB板设计方法，其特征在于，步骤a2中，将PCB板上的部分焊盘的周边建立焊盘限制区；印刷PCB板，使得焊盘限制区上印刷有焊盘限制区图案。
  4. 避免贴片元件立碑的PCB板封装方法，贴片元件的一端为铜皮，另一端为铜线；或贴片元件的两端都为铜皮；其特征在于，使用权利要求2中的避免贴片元件立碑的PCB板设计方法，得到PCB板；将贴片元件的两端贴装于焊盘上进行回流焊。
  5. 避免贴片元件立碑的PCB板封装方法，贴片元件的一端为铜皮，另一端为铜线；或贴片元件的两端都为铜皮；其特征在于，使用权利要求3中的避免贴片元件立碑的PCB板设计方法，得到PCB板；所述PCB板上部分焊盘周边印刷有焊盘限制区图案，将贴片元件的铜皮端贴装于印刷有焊盘限制区图案的焊盘上进行回流焊。
  6. 根据权利要求5所述的避免贴片元件立碑的PCB板封装方法，其特征在于，将贴片元件的铜线端贴装于没有印刷焊盘限制区图案的焊盘上进行回流焊。
  7. 根据权利要求5所述的避免贴片元件立碑的PCB板封装方法，其特征在于，焊盘限制区图案分为左限制区图案和右限制区图案，左限制区图案形状为对称的扇形形状，右限制区图案为弓形形状。
  8. 根据权利要求7所述的避免贴片元件立碑的PCB板封装方法，其特征在于，相邻两个焊盘限制区图案之间设置有隔离区。
  9. PCB板，包括贴片元件安置区和焊盘，其特征在于，PCB板上设有至少一个贴片元件安置区，每个贴片元件安置区内设有焊盘，焊盘每组 有两个，且两个焊盘并排布置；焊盘的周边建立有焊盘限制区。
  10. 根据权利要求9所述的PCB板，其特征在于，焊盘限制区印刷有焊盘限制区图案；焊盘限制区图案分为左限制区图案和右限制区图案，左限制区图案形状为对称的扇形形状，右限制区图案为弓形形状；相邻两个焊盘限制区图案之间设置有隔离区。
PCT/CN2017/113702 2017-07-31 2017-11-30 避免贴片元件立碑的pcb板设计方法及封装方法及pcb板 WO2019024351A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/097,234 US20210227701A1 (en) 2017-07-31 2017-11-30 Design and packaging method for pcb board to avoid patch element tombstone and pcb board

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710639229.3A CN107231746A (zh) 2017-07-31 2017-07-31 避免贴片元件立碑的pcb板设计方法及封装方法及pcb板
CN201710639229.3 2017-07-31

Publications (1)

Publication Number Publication Date
WO2019024351A1 true WO2019024351A1 (zh) 2019-02-07

Family

ID=59957315

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/113702 WO2019024351A1 (zh) 2017-07-31 2017-11-30 避免贴片元件立碑的pcb板设计方法及封装方法及pcb板

Country Status (3)

Country Link
US (1) US20210227701A1 (zh)
CN (1) CN107231746A (zh)
WO (1) WO2019024351A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107231746A (zh) * 2017-07-31 2017-10-03 郑州云海信息技术有限公司 避免贴片元件立碑的pcb板设计方法及封装方法及pcb板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101009968A (zh) * 2006-01-25 2007-08-01 矽品精密工业股份有限公司 电子载板
CN101795533A (zh) * 2009-12-11 2010-08-04 福建星网锐捷网络有限公司 一种电路板及电路板的铺铜方法
CN105208792A (zh) * 2015-08-07 2015-12-30 深圳崇达多层线路板有限公司 一种改善元件立碑现象的pcb制作方法
CN107231746A (zh) * 2017-07-31 2017-10-03 郑州云海信息技术有限公司 避免贴片元件立碑的pcb板设计方法及封装方法及pcb板

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004319778A (ja) * 2003-04-16 2004-11-11 Mitsubishi Electric Corp プリント基板
CN200947702Y (zh) * 2006-08-31 2007-09-12 华为技术有限公司 一种具有焊盘结构的电路板
CN106455315A (zh) * 2016-12-13 2017-02-22 郑州云海信息技术有限公司 一种0201元件焊盘的设计方法和pcb板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101009968A (zh) * 2006-01-25 2007-08-01 矽品精密工业股份有限公司 电子载板
CN101795533A (zh) * 2009-12-11 2010-08-04 福建星网锐捷网络有限公司 一种电路板及电路板的铺铜方法
CN105208792A (zh) * 2015-08-07 2015-12-30 深圳崇达多层线路板有限公司 一种改善元件立碑现象的pcb制作方法
CN107231746A (zh) * 2017-07-31 2017-10-03 郑州云海信息技术有限公司 避免贴片元件立碑的pcb板设计方法及封装方法及pcb板

Also Published As

Publication number Publication date
US20210227701A1 (en) 2021-07-22
CN107231746A (zh) 2017-10-03

Similar Documents

Publication Publication Date Title
CN106604564A (zh) 印制线路板及其表面贴装方法
TWI393504B (zh) 缺口定位型銲接結構及防止引腳偏移的方法
CN106413281A (zh) 一种双面板混装贴装工艺
WO2016058225A1 (zh) 一种多层印刷电路板
US10843284B2 (en) Method for void reduction in solder joints
CN110459667B (zh) 一种led倒装基板
JP2006303392A (ja) プリント配線板と電子回路基板及びその製造方法
WO2019024351A1 (zh) 避免贴片元件立碑的pcb板设计方法及封装方法及pcb板
CN108463053B (zh) 一种pcb板设计方法及pcb板
WO2021057320A1 (zh) 一种厚金属led长灯带及制作方法
WO2006008850A1 (ja) 低耐熱性表面実装部品及びこれをバンプ接続した実装基板
CN211656532U (zh) 一种d2pak封装mos管的pcb贴片结构
CN211267300U (zh) 一种钢网及焊接结构
CN209882204U (zh) 一种pcb板
JP2010080667A (ja) 実装基板、および実装方法
CN110958786A (zh) 一种片上贴片的pcba侧面上锡焊接的方法
TWI387420B (zh) 切邊定位型銲接結構及防止引腳偏移的方法
JP2019062000A (ja) スクリーン印刷用マスク、及びプリント配線基板
JP2003249746A (ja) プリント基板
CN209120528U (zh) 一种防焊接点短路的印刷电路板
TW508986B (en) Structure and method for mounting an electronic circuit unit to a printed board
JP5185831B2 (ja) コンポーネントを順序付けて固定することによる電子モジュールの生産方法
JP4838277B2 (ja) 電子部品実装基板の配線基板構造と電子部品の実装構造
JP2009026927A (ja) 配線基板の部品実装構造
CN206164974U (zh) 一种阻焊性能良好的电路板结构

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17920336

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17920336

Country of ref document: EP

Kind code of ref document: A1