WO2019019747A1 - 像素电路及像素电路的驱动方法 - Google Patents

像素电路及像素电路的驱动方法 Download PDF

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WO2019019747A1
WO2019019747A1 PCT/CN2018/084996 CN2018084996W WO2019019747A1 WO 2019019747 A1 WO2019019747 A1 WO 2019019747A1 CN 2018084996 W CN2018084996 W CN 2018084996W WO 2019019747 A1 WO2019019747 A1 WO 2019019747A1
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Prior art keywords
transistor
signal line
pixel circuit
gate
light emitting
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PCT/CN2018/084996
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English (en)
French (fr)
Inventor
韩媛媛
曹朝干
祝晓钊
王龙
冯敏强
廖良生
Original Assignee
江苏集萃有机光电技术研究所有限公司
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Priority to US16/617,784 priority Critical patent/US11049450B2/en
Publication of WO2019019747A1 publication Critical patent/WO2019019747A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes

Definitions

  • the present application relates to the field of pixel driving technology of displays, for example, to a pixel circuit and a driving method of the pixel circuit.
  • Pixels per inch (PPI) products (such as microdisplays), because the pixel layout space is smaller, the line width of the pixel circuit plan is narrowed, causing the voltage drop of the power supply voltage to increase, resulting in the screen signal writing of the display screen. Inconsistent, resulting in uneven display.
  • the embodiment of the present application provides a pixel circuit and a driving method of the pixel circuit.
  • the present application provides a pixel circuit for an active matrix organic light emitting display, the pixel circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a first scan signal line, and a second scan signal line , data signal lines, control signal lines, capacitors and light emitting diodes;
  • a second plate of the capacitor is connected to a drain of the third transistor
  • a gate of the second transistor is connected to the second scan signal line, a drain of the second transistor is connected to a gate of the fourth transistor, a source of the second transistor and the data signal Line connected
  • a source of the third transistor is disposed to be connected to a power source, a drain of the third transistor is connected to a source of the fourth transistor, and a gate of the third transistor is connected to the control signal line;
  • a drain of the fourth transistor is coupled to an anode of the light emitting diode
  • the cathode of the light emitting diode is disposed to be grounded;
  • the first scan signal line is configured to send a control signal to a gate of the first transistor to control opening or closing of the first transistor; and the second scan signal line is configured to send a control signal to the The gate of the second transistor is controlled to control the second transistor to be turned on and off; the control signal line is arranged to send a control signal to the gate of the third transistor to control the third transistor to be turned on and off.
  • the present application also provides a driving method of a pixel circuit, which uses the above pixel circuit, and the method includes:
  • the signal of the power source can be written to the fourth transistor through the third transistor.
  • the present application also provides a driving method of a pixel circuit, which is applied to the above pixel circuit, and the method includes:
  • the first scan signal line controls the first transistor to be turned off
  • the second scan signal line control controls the second transistor to be turned on
  • the second signal of the data signal line high level is written to the gate of the fourth transistor a pole
  • the source voltage of the fourth transistor is clamped to a third signal
  • the third signal is determined by the threshold voltage of the second signal and the fourth transistor
  • the first scan signal line controls the first transistor to be turned on, and the control signal line controls the third transistor to be turned on, the source voltage of the fourth transistor is the same as the power supply voltage of the power source; and the coupling effect of the capacitor
  • the gate voltage of the fourth transistor is clamped to a fourth signal, and the fourth signal is determined by the first signal, the third signal, and a power supply voltage.
  • the pixel circuit and the pixel circuit driving method provided by the embodiments of the present application can effectively cancel the influence of the power supply voltage and the threshold voltage of the fourth transistor itself by using fewer transistors and capacitors, so that the display of the display using the pixel circuit is more displayed. Evenly.
  • the pixel circuit provided by the embodiment of the present application has a simple structure, fewer signals, and a relatively simple circuit layout, which is beneficial to the layout of the pixel circuit.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment.
  • FIG. 2 is a timing diagram of a pixel circuit provided by an embodiment.
  • FIG. 3 is a schematic structural diagram of still another pixel circuit according to an embodiment.
  • FIG. 4 is a schematic structural diagram of still another pixel circuit according to an embodiment.
  • FIG. 5 is a schematic structural diagram of still another pixel circuit according to an embodiment.
  • FIG. 6 is a flowchart of a driving method of a pixel circuit according to an embodiment.
  • Icon M1-first transistor; M2-second transistor; M3-third transistor; M4-fourth transistor; M5-fifth transistor; M6-sixth transistor; Scan1-first scan signal line; Scan2-second Scanning signal line; Vdata-data signal line; EM-control signal line; OLED-light emitting diode; Vd-power supply; C-capacitor; Vss-regional power supply.
  • the embodiment provides a pixel circuit.
  • the pixel circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first scan signal line Scan1, and a second scan.
  • Signal line Scan2 data signal line Vdata, control signal line EM, capacitor C, and light emitting diode OLED.
  • the gate of the first transistor M1 is connected to the first scan signal line Scan1, and the source of the first transistor M1 is electrically connected to the first plate of the capacitor C, the first transistor The drain of M1 is connected to the source of the second transistor M2.
  • the first transistor M1 may be a dual gate transistor, and the double gate of the first transistor M1 is connected to the first scan signal line Scan1.
  • the leakage current can be effectively reduced by using a double gate transistor to improve the stability of the capacitance C signal connected to the first transistor M1.
  • the second plate of the capacitor C is connected to the drain of the third transistor M3.
  • the gate of the second transistor M2 is connected to the second scan signal line Scan2
  • the drain of the second transistor M2 is connected to the gate of the fourth transistor M4, and the source of the second transistor M2 Connected to the data signal line Vdata.
  • the source of the third transistor M3 is connected to the power source Vd
  • the drain of the third transistor M3 is connected to the source of the fourth transistor M4
  • the third transistor M3 The gate is connected to the control signal line EM.
  • the drain of the fourth transistor M4 is connected to the anode of the light emitting diode OLED, and the cathode of the light emitting diode OLED is grounded. As shown in FIG. 1, the light emitting diode OLED is grounded to a power source Vss.
  • the first scan signal line Scan1 sends a control signal to the gate of the first transistor M1 to control the opening or closing of the first transistor M1;
  • the second scan signal line Scan2 sends control Signaling to the gate of the second transistor M2 to control the second transistor M2 to be turned on and off;
  • the control signal line EM transmitting a control signal to the gate of the third transistor M3 to control the third transistor M3 to be turned on shut down.
  • the first to fourth transistors M1 to M4 may be N-type Metal-Oxide Semiconductor (NMOS) or P-type Metal (P-type Metal). -Oxide Semiconductor, PMOS).
  • NMOS N-type Metal-Oxide Semiconductor
  • PMOS P-type Metal
  • the pixel circuit can be driven by the following three stages to achieve the threshold voltage cancellation of the power supply voltage and the fourth transistor M4 by the pixel circuit.
  • the first stage the first scan signal line Scan1 controls the first transistor M1 to be turned on, and the second scan signal line Scan2 controls the second transistor M2 to be turned on, and the first signal of the data signal line Vdata low level is written to the fourth a gate of the transistor M4 and a first plate of the capacitor C.
  • the first scan signal line Scan1 controls the first transistor M1 to be turned off
  • the second scan signal line Scan2 controls the second transistor M2 to be turned on
  • the second signal of the data signal line Vdata high level is written
  • the gate of the fourth transistor M4 clamps the source voltage of the fourth transistor M4 to a third signal, which is determined by the threshold voltage of the second signal and the fourth transistor M4.
  • the first scan signal line Scan1 controls the first transistor M1 to be turned on
  • the control signal line EM controls the third transistor M3 to be turned on
  • the source voltage of the fourth transistor M4 is equal to the power supply voltage of the power source
  • the coupling of the capacitor C, the gate voltage of the fourth transistor M4 is clamped to a fourth signal, and the fourth signal is determined by the first signal, the third signal, and the power supply voltage.
  • the transistor is turned on when the gate of the transistor is input low.
  • the first scan signal line Scan1 and the second scan signal line Scan2 respectively provide a low level to turn on the first transistor M1 and the second transistor M2.
  • the first signal of the data signal line Vdata low level is written to the gate of the fourth transistor M4 and the first plate of the capacitor C.
  • the first signal is recorded as Vdata1.
  • the plurality of transistors in this embodiment may also be turned on when the gate of the transistor is input to a high level.
  • the embodiment of the present application is not limited to the manner in which the transistor is turned on or off. The following description will be made by taking an example in which the transistor is turned on when the gate of the transistor is input with a low level.
  • the first scan signal line Scan1 provides a high level
  • the first transistor M1 is turned off after receiving the signal provided by the first scan signal line Scan1.
  • the second scan signal line Scan2 is supplied with a low level
  • the second transistor M2 is turned on after receiving the signal supplied from the second scan signal line Scan2.
  • the data signal line Vdata outputs a second signal of a high level
  • the fourth transistor M4 is in a closed state after receiving the second signal outputted by the data signal line Vdata, the source of the fourth transistor M4.
  • the voltage of the pole is clamped to a third signal, which is determined by the second signal input by the data signal line Vdata and the threshold voltage of the fourth transistor M4.
  • the second signal is recorded as Vdata2
  • the threshold voltage is recorded as Vth
  • the third signal is Vdata2-Vth.
  • the second scan signal line Scan2 is supplied with a high level to turn off the second transistor M2.
  • the first scan signal line Scan1 and the control signal line EM provide a low level, and the first transistor M1 and the third transistor M3 are turned on after receiving a low level signal.
  • the source voltage of the fourth transistor M4 is a power supply voltage.
  • the power supply voltage of the power supply Vd is recorded as Vdd.
  • the gate voltage of the fourth transistor M4 is Vdata1+(Vdd-Vdata2+Vth).
  • the voltage difference between the gate and the source of the fourth transistor M4 in the third stage T3 is:
  • Vgs Vdata1+(Vdd-Vdata2+Vth)-Vdd
  • Vgs represents a voltage difference between a gate and a source of the fourth transistor M4, Vdata1 represents the first signal, Vdata2 represents the second signal, and Vth represents a threshold voltage of the fourth transistor M4; Vdd represents the power supply voltage;
  • the Ids represents a current flowing through the fourth transistor M4, and the ⁇ represents a magnification of the fourth transistor M4.
  • the pixel circuit can effectively cancel the influence of the power supply voltage and the threshold voltage of the fourth transistor M4 on the display effect of the light emitting diode OLED with fewer components.
  • the pixel circuit provided by the embodiment of the present application has a simple structure, fewer signals, and a relatively simple circuit layout, which is beneficial to the layout of the pixel circuit.
  • the present embodiment provides a pixel circuit.
  • This embodiment is similar to the first embodiment except that the pixel circuit in this embodiment has a fifth transistor M5 added to the pixel circuit in the first embodiment.
  • the pixel circuit further includes a fifth transistor M5.
  • the drain of the fifth transistor M5 is connected to the anode of the light emitting diode OLED, the source of the fifth transistor M5 is connected to the drain of the fourth transistor M4, and the fifth transistor
  • the gate of M5 is connected to the control signal line EM; the control signal line EM sends a control signal to the gate of the fifth transistor M5 to control the fifth transistor M5 to be turned on or off.
  • the fifth transistor M5 is added on the basis of the first embodiment, and the leakage current can be prevented from flowing into the light emitting diode OLED when the fourth transistor M4 is in the off state, thereby causing the light emitting diode OLED. Abnormal brightness.
  • the embodiment provides a pixel circuit.
  • the embodiment is similar to the first embodiment in that the pixel circuit in the embodiment adds a sixth transistor M6 and a reference power to the pixel circuit in the first embodiment.
  • Flat signal line Referring to FIG. 5, the pixel circuit further includes a sixth transistor M6 and a reference level signal line Verf.
  • the gate of the sixth transistor M6 is connected to the first scan signal line Scan1
  • the drain of the sixth transistor M6 is connected to the light emitting diode OLED
  • the first scan signal line Scan1 is sent.
  • a control signal is applied to the gate of the sixth transistor M6 to control the sixth transistor M6 to be turned on or off.
  • the reference level signal line Verf is connected to the source of the sixth transistor M6, and the reference level signal line Verf is used to supply an initial current to the light emitting diode OLED through the sixth transistor M6 to initialize the light emitting diode OLED.
  • the light-emitting diode OLED is initialized by the signal provided by the reference level signal line Verf to prevent the light-emitting diode from being
  • the parasitic charge of the OLED affects the signal received later, thereby improving the stability of the light emitting diode OLED.
  • the pixel circuit may include all of the elements in the first embodiment, the second embodiment, and the third embodiment.
  • the pixel circuit may include all of the elements in the first embodiment, the second embodiment, and the third embodiment.
  • the embodiment provides a driving method of a pixel circuit, and the method includes:
  • the data signal line Vdata transmitting digital signal can be written to the fourth transistor M4 through the second transistor M2;
  • a digital signal of the data signal line Vdata is rewritable to the capacitor C or the fourth transistor M4 via the first transistor M1;
  • the signal of the power source can be written to the fourth transistor M4 via the third transistor M3.
  • the driving method of the pixel circuit in this embodiment controls the pixel circuit through three stages, and the above method can be applied to any one of the above pixel circuits. As shown in FIG. 6, the method includes:
  • the first stage 101 the first scan signal line Scan1 controls the first transistor M1 to be turned on, and the second scan signal line Scan2 controls the second transistor M2 to be turned on, and the first signal of the data signal line Vdata low level is written into the first stage The gate of the four transistor M4 and the first plate of the capacitor C.
  • the second stage 102 the first scan signal line Scan1 controls the first transistor M1 to be turned off, the second scan signal line Scan2 controls the second transistor M2 to be turned on, and the second signal write line of the data signal line Vdata high level
  • the gate of the fourth transistor M4 clamps the source voltage of the fourth transistor M4 to a third signal, and the third signal is determined by the threshold voltage of the second signal and the fourth transistor M4.
  • the third stage 103 the first scan signal line Scan1 controls the first transistor M1 to be turned on, and the control signal line EM controls the third transistor M3 to be turned on, the source voltage of the fourth transistor M4 is equal to the power supply voltage of the power source Vd;
  • the coupling of the capacitor C, the gate voltage of the fourth transistor M4 is clamped to a fourth signal, and the fourth signal is determined by the first signal, the third signal, and a power supply voltage.
  • the third signal of the second phase 102 is the difference between the threshold voltage of the second signal and the fourth transistor M4;
  • the voltage difference between the gate and the source of the fourth transistor M4 of the third stage 103 is:
  • Vgs Vdata1+(Vdd-Vdata2+Vth)-Vdd
  • Vgs represents a voltage difference between a gate and a source of the fourth transistor M4, Vdata1 represents the first signal, Vdata2 represents the second signal, and Vth represents a threshold voltage of the fourth transistor M4. ; Vdd represents the power supply voltage;
  • the Ids represents a current flowing through the fourth transistor M4, and the ⁇ represents a magnification of the fourth transistor M4.
  • the method further includes: when the fourth transistor M4 has a current, the The current of the fourth transistor M4 flows into the light emitting diode OLED after passing through the fifth transistor M5.
  • the method further includes: the first scan signal line Scan1 sends an initialization control signal to the sixth transistor M6, and controls The sixth transistor M6 is turned on, and the reference level signal line supplies an initial current to the light emitting diode OLED through the sixth transistor M6 to initialize the light emitting diode OLED.
  • the influence of the power supply voltage and the threshold voltage of the fourth transistor itself can be effectively canceled by fewer transistors and capacitors to make the display of the display connected to the pixel circuit more uniform.
  • the pixel circuit provided by the embodiment of the present application has a simple structure, fewer signals, and a relatively simple circuit layout, which is beneficial to the layout of the pixel circuit.
  • the pixel circuit and the pixel circuit driving method provided by the present application can effectively offset the influence of the power supply voltage and the threshold voltage of the fourth transistor itself by using fewer transistors and capacitors, so that the display of the OLED is more uniform, and the pixel circuit structure is simple. Conducive to the layout of the pixel circuit.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

像素电路及像素电路的驱动方法，所述像素电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一扫描信号线、第二扫描信号线、数据信号线、控制信号线、电容、电源及发光二极管。所述第一晶体管的源极与所述电容的第一极板连接，所述第一晶体管的漏极与第二晶体管的源极相连；所述电容的第二极板与所述第三晶体管的漏极连接；所述第二晶体管的漏极与第四晶体管的栅极相连，所述第二晶体管的源极与所述数据信号线相连；所述第三晶体管的源极与所述电源连接，所述第三晶体管的漏极与所述第四晶体管的源极连接；所述第四晶体管的漏极连接所述发光二极管；所述发光二极管的阴极接地。

Description

像素电路及像素电路的驱动方法 技术领域
本申请涉及显示器的像素驱动技术领域，例如，涉及一种像素电路及像素电路的驱动方法。
背景技术
有源矩阵有机发光二极体(Active-matrix organic light emitting diode，AMOLED)显示技术因其色域广、视角宽、对比度高、功耗低等优点正逐步取代传统的显示技术(如液晶显示)。AMOLED显示屏中，像素电路作为像素点的信号控制电路，在显示面板中具有重要的作用。目前主流的低温多晶硅技术(Low Temperature Poly-silicon，LTPS)工艺，因工艺本身的缺陷，造成像素电路存在电压阈值(Vth)不均一的问题，故像素电路主要以补偿Vth为主，对高像素密度(pixels per inch，PPI)产品(如微型显示器)，因像素版图空间更小，导致像素电路规划图的线宽变窄，造成电源电压的压降增大，导致显示屏的屏体信号写入不一致，而造成显示不均匀。
发明内容
有鉴于此，本申请实施例提供一种像素电路及像素电路的驱动方法。
本申请提供一种像素电路，应用于有源矩阵有机发光显示屏，所述像素电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一扫描信号线、第二扫描信号线、数据信号线、控制信号线、电容及发光二极管；
所述第一晶体管的栅极与所述第一扫描信号线连接，所述第一晶体管的源极与所述电容的第一极板连接，所述第一晶体管的漏极与所述第二晶体管的源极相连；
所述电容的第二极板与所述第三晶体管的漏极连接；
所述第二晶体管的栅极与所述第二扫描信号线连接，所述第二晶体管的漏极与所述第四晶体管的栅极相连，所述第二晶体管的源极与所述数据信号线相连；
所述第三晶体管的源极设置为与电源连接，所述第三晶体管的漏极与所述 第四晶体管的源极连接，所述第三晶体管的栅极与所述控制信号线连接；
所述第四晶体管的漏极与所述发光二极管的阳极连接；
所述发光二极管的阴极设置为接地；
其中，所述第一扫描信号线设置为发送控制信号到所述第一晶体管的栅极，以控制所述第一晶体管的打开或关闭；所述第二扫描信号线设置为发送控制信号到所述第二晶体管的栅极，以控制第二晶体管打开和关闭；所述控制信号线设置为发送控制信号到所述第三晶体管的栅极，以控制第三晶体管打开和关闭。
本申请还提供一种像素电路的驱动方法，应用上述像素电路，所述方法包括：
由第一扫描信号线发送控制信号到第一晶体管的栅极，以控制所述第一晶体管的打开和关闭；
由第二扫描信号线发送控制信号到第二晶体管的栅极，以控制所述第二晶体管的打开和关闭；
数据信号线发送数字信号经过所述第二晶体管可写入第四晶体管；
数据信号线的数字信号经过所述第一晶体管可写入电容；以及
电源的信号经过第三晶体管可写入所述第四晶体管。
本申请还提供一种像素电路的驱动方法，应用于上述像素电路，所述方法包括：
第一阶段：第一扫描信号线控制第一晶体管打开，以及第二扫描信号线控制第二晶体管打开，所述数据信号线低电平的第一信号写入所述第四晶体管的栅极及所述电容的第一极板；
第二阶段：第一扫描信号线控制所述第一晶体管关闭，第二扫描信号线控制控制第二晶体管打开，所述数据信号线高电平的第二信号写入所述第四晶体管的栅极，使所述第四晶体管的源极电压钳位到第三信号，所述第三信号由所述第二信号与所述第四晶体管的阈值电压确定；
第三阶段：第一扫描信号线控制第一晶体管打开，以及控制信号线控制第三晶体管打开，所述第四晶体管的源极电压与所述电源的电源电压相同；在所述电容的耦合作用下，所述第四晶体管的栅极电压钳位到第四信号，所述第四信号由所述第一信号、第三信号及电源电压确定。
本申请实施例提供的像素电路及像素电路的驱动方法，通过更少的晶体管及电容能够有效抵消电源电压及第四晶体管本身的阈值电压的影响，以使应用 所述像素电路的显示器的显示更加均匀。另外，本申请实施例提供的像素电路架构简单，信号少，电路版图相对更简单，有利于像素电路的布局。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定。
图1为一实施例提供的像素电路的结构示意图。
图2为一实施例提供的一种像素电路的时序图。
图3为一实施例提供的又一种像素电路的结构示意图。
图4为一实施例提供的又一种像素电路的结构示意图。
图5为一实施例提供的又一种像素电路的结构示意图。
图6为一实施例提供的像素电路的驱动方法的流程图。
图标：M1-第一晶体管；M2-第二晶体管；M3-第三晶体管；M4-第四晶体管；M5-第五晶体管；M6-第六晶体管；Scan1-第一扫描信号线；Scan2-第二扫描信号线；Vdata-数据信号线；EM-控制信号线；OLED-发光二极管；Vd-电源；C-电容；Vss-地域电源。
具体实施方式
下面将结合本申请实施例中附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围，而是仅表示本申请的选定实施例。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。同时，在本申请的描述中，术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
第一实施例
本实施例提供一种像素电路，如图1所示，所述像素电路包括第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第一扫描信号线Scan1、第二扫描信号线Scan2、数据信号线Vdata、控制信号线EM、电容C及发光二极管OLED。
本实施例中，所述第一晶体管M1的栅极连接第一扫描信号线Scan1，所述第一晶体管M1的源极与所述电容C的第一极板电性连接，所述第一晶体管M1的漏极与第二晶体管M2的源极相连。
在一种实施方式中，如图3所述，所述第一晶体管M1可以是双栅晶体管，所述第一晶体管M1的双栅极均与所述第一扫描信号线Scan1相连。通过使用双栅晶体管可以有效降低漏电流的情况，以提高与所述第一晶体管M1连接的电容C信号的稳定性。
本实施例中，所述电容C的第二极板与所述第三晶体管M3的漏极连接。
本实施例中，所述第二晶体管M2的栅极连接第二扫描信号线Scan2，所述第二晶体管M2的漏极与第四晶体管M4的栅极相连，所述第二晶体管M2的源极与所述数据信号线Vdata相连。
本实施例中，所述第三晶体管M3的源极设置为与所述电源Vd连接，所述第三晶体管M3的漏极与所述第四晶体管M4的源极连接，所述第三晶体管M3的栅极与控制信号线EM连接。
本实施例中，所述第四晶体管M4的漏极连接所述发光二极管OLED的阳极，所述发光二极管OLED的阴极接地。如图1所示，所述发光二极管OLED接地域电源Vss。
本实施例中，所述第一扫描信号线Scan1发送控制信号到所述第一晶体管M1的栅极，以控制所述第一晶体管M1的打开或关闭；所述第二扫描信号线Scan2发送控制信号到所述第二晶体管M2的栅极，以控制第二晶体管M2打开和关闭；所述控制信号线EM发送控制信号到所述第三晶体管M3的栅极，以控制第三晶体管M3打开和关闭。
在一实施例中，第一晶体管M1～第四晶体管M4可以分别是N型金属氧化 物半导体(N-type Metal-Oxide Semiconductor，NMOS)，也可以是P型金属氧化物半导体(P-type Metal-Oxide Semiconductor，PMOS)。
在一种实施方式中，可以通过以下三个阶段驱动所述像素电路以实现所述像素电路对电源电压及所述第四晶体管M4的阈值电压抵消。
第一阶段：第一扫描信号线Scan1控制第一晶体管M1打开，及第二扫描信号线Scan2控制第二晶体管M2打开，所述数据信号线Vdata低电平的第一信号写入所述第四晶体管M4的栅极及所述电容C的第一极板。
第二阶段：第一扫描信号线Scan1控制所述第一晶体管M1关闭，第二扫描信号线Scan2控制控制第二晶体管M2打开，所述数据信号线Vdata高电平的第二信号写入所述第四晶体管M4的栅极，使所述第四晶体管M4的源极电压钳位到第三信号，所述第三信号由所述第二信号与所述第四晶体管M4的阈值电压确定。
第三阶段：第一扫描信号线Scan1控制第一晶体管M1打开，及控制信号线EM控制第三晶体管M3打开，所述第四晶体管M4的源极电压等同所述电源的电源电压；在所述电容C的耦合作用，所述第四晶体管M4的栅极电压钳位到第四信号，所述第四信号由所述第一信号、第三信号及电源电压确定。
在一个实例中，在晶体管的栅极输入低电平时该晶体管被打开。如图2所示，第一阶段T1，所述第一扫描信号线Scan1及第二扫描信号线Scan2分别提供低电平以使第一晶体管M1及第二晶体管M2打开。所述数据信号线Vdata低电平的第一信号写入所述第四晶体管M4的栅极及所述电容C的第一极板。在一个实例中，将所述第一信号记录为Vdata1。在其它实例中，本实施例中的多个晶体管也可以是在晶体管的栅极输入高电平时该晶体管被开启。本申请实施例并不以晶体管的打开或关闭的方式为限。下面以在晶体管的栅极输入低电平时该晶体管打开为例进行描述。
第二阶段T2，所述第一扫描信号线Scan1提供高电平，所述第一晶体管M1接收到所述第一扫描信号线Scan1提供的信号后关闭。所述第二扫描信号线Scan2提供低电平，所述第二晶体管M2接收到所述第二扫描信号线Scan2提供 的信号后打开。此时，所述数据信号线Vdata输出高电平的第二信号，所述第四晶体管M4接收到所述数据信号线Vdata输出的第二信号后处于关闭状态，所述第四晶体管M4的源极的电压钳位到第三信号，所述第三信号由所述数据信号线Vdata输入的第二信号及该第四晶体管M4的阈值电压确定。在一个实例中，所述第二信号记录为Vdata2，所述阈值电压记录为Vth，则所述第三信号为Vdata2-Vth。
第三阶段T3，所述第二扫描信号线Scan2提供高电平以使第二晶体管M2关闭。所述第一扫描信号线Scan1与所述控制信号线EM提供低电平，所述第一晶体管M1与所述第三晶体管M3接收到低电平信号后打开。此时，所述第四晶体管M4的源极电压为电源电压。在一个实例中，将所述电源Vd的电源电压记录为Vdd。在所述电容C的耦合作用下，所述第四晶体管M4的栅极电压为Vdata1+(Vdd-Vdata2+Vth)。
在第三阶段T3的第四晶体管M4的栅极与源极的压差为：
Vgs＝Vdata1+(Vdd-Vdata2+Vth)-Vdd
＝Vdata1-(Vdata2-Vth)；
其中，所述Vgs表示所述第四晶体管M4的栅极与源极的压差，Vdata1表示所述第一信号，Vdata2表示所述第二信号，Vth表示所述第四晶体管M4的阈值电压；Vdd表示所述电源电压；
此时，流过所述第四晶体管M4的电流为：
Figure PCTCN2018084996-appb-000001
其中，所述Ids表示流过所述第四晶体管M4的电流，所述β表示所述第四晶体管M4的放大倍数。
由上述Ids的计算结果可以知道此时流过所述第四晶体管M4的电流不受所 述电源电压及所述第四晶体管M4的阈值电压影响。通过上述的像素电路可以在使用更少的部件的情况下能够有效抵消所述电源电压及所述第四晶体管M4的阈值电压对发光二极管OLED显示的效果的影响。另外，本申请实施例提供的像素电路架构简单，信号少，电路版图相对更简单，有利于像素电路的布局。
第二实施例
本实施例提供一种像素电路，本实施例与第一实施例类似，其不同之处在于，本实施例中的像素电路比第一实施例中的像素电路增加了第五晶体管M5。如图3所示，所述像素电路还包括第五晶体管M5。
本实施例中，所述第五晶体管M5的漏极与所述发光二极管OLED的阳极连接，所述第五晶体管M5的源极与所述第四晶体管M4的漏极连接，所述第五晶体管M5的栅极与所述控制信号线EM连接；所述控制信号线EM发送控制信号到所述第五晶体管M5的栅极，以控制第五晶体管M5打开或关闭。
关于本实施例中的其它细节可以参考第一实施例中的描述，在此不再赘述。
根据本实施例中的像素电路，在第一实施例的基础上增加第五晶体管M5，可以有效防止第四晶体管M4处于截止态时漏电流流入所述发光二极管OLED中，造成所述发光二极管OLED亮度异常。
第三实施例
本实施例提供一种像素电路，本实施例与第一实施例类似，其不同之处在于，本实施例中的像素电路比第一实施例中的像素电路增加了第六晶体管M6及参考电平信号线。请参阅图5，所述像素电路还包括第六晶体管M6及参考电平信号线Verf。
本实施例中，所述第六晶体管M6的栅极与所述第一扫描信号线Scan1连接，所述第六晶体管M6的漏极连接所述发光二极管OLED；所述第一扫描信号线Scan1发送控制信号到所述第六晶体管M6的栅极，以控制第六晶体管M6打开或关闭。
所述参考电平信号线Verf连接所述第六晶体管M6的源极，所述参考电平信号线Verf用于提供初始电流通过第六晶体管M6流入发光二极管OLED，对 发光二极管OLED进行初始化。
关于本实施例中的其它细节可以参考第一实施例中的描述，在此不再赘述。
根据本实施例中的像素电路，通过增加所述第六晶体管M6及参考电平信号线Verf，通过所述参考电平信号线Verf提供信号对所述发光二极管OLED进行初始化，防止所述发光二极管OLED的寄生电荷对后面接收到的信号的影响，从而提高所述发光二极管OLED的稳定性。
在其它实施例中，如图5所示，像素电路可包括第一实施例、第二实施例及第三实施例中的全部元件。关于本实施例的其他内容可以参考第一至第三实施例中的描述，在此不再赘述。
第四实施例
本实施例提供一种像素电路的驱动方法，所述方法包括：
由第一扫描信号线Scan1发送控制信号到第一晶体管M1的栅极，以控制所述第一晶体管M1的打开和关闭；
由第二扫描信号线Scan2发送控制信号到第二晶体管M2的栅极，以控制所述第二晶体管M2的打开和关闭；
数据信号线Vdata发送数字信号经过所述第二晶体管M2可写入第四晶体管M4；
数据信号线Vdata的数字信号经过所述第一晶体管M1可写入电容C或所述第四晶体管M4；以及
电源的信号经过第三晶体管M3可写入所述第四晶体管M4。
在一种实施方式中，本实施例中的像素电路的驱动方法通过三个阶段控制所述像素电路，上述方法可应用于上述任意一种像素电路中，如图6所示，上述方法包括：
第一阶段101：第一扫描信号线Scan1控制第一晶体管M1打开，及第二扫描信号线Scan2控制第二晶体管M2打开，所述数据信号线Vdata低电平的第一信号写入所述第四晶体管M4的栅极及所述电容C的第一极板。
第二阶段102：第一扫描信号线Scan1控制所述第一晶体管M1关闭，第二 扫描信号线Scan2控制控制第二晶体管M2打开，所述数据信号线Vdata高电平的第二信号写入所述第四晶体管M4的栅极，使所述第四晶体管M4的源极电压钳位到第三信号，所述第三信号由所述第二信号与所述第四晶体管M4的阈值电压确定。
第三阶段103：第一扫描信号线Scan1控制第一晶体管M1打开，及控制信号线EM控制第三晶体管M3打开，所述第四晶体管M4的源极电压等同所述电源Vd的电源电压；在所述电容C的耦合作用，所述第四晶体管M4的栅极电压钳位到第四信号，所述第四信号由所述第一信号、第三信号及电源电压确定。
本实施例中，所述第二阶段102的第三信号为所述第二信号与所述第四晶体管M4的阈值电压之差；
所述第三阶段103的第四晶体管M4的栅极与源极的电压差值为：
Vgs＝Vdata1+(Vdd-Vdata2+Vth)-Vdd
＝Vdata1-(Vdata2-Vth)；
其中，所述Vgs表示所述第四晶体管M4的栅极与源极的电压差值，Vdata1表示所述第一信号，Vdata2表示所述第二信号，Vth表示所述第四晶体管M4的阈值电压；Vdd表示所述电源电压；
此时，流过所述第四晶体管M4的电流为：
Figure PCTCN2018084996-appb-000002
其中，所述Ids表示流过所述第四晶体管M4的电流，所述β表示所述第四晶体管M4的放大倍数。
本实施例中，当所述像素电路包括连接在所述第四晶体管M4与发光二极管OLED之间的第五晶体管M5时，所述方法还包括：当第四晶体管M4有电流通过时，所述第四晶体管M4的电流经过所述第五晶体管M5后流入所述发光二极 管OLED。
本实施例中，当所述像素电路包括第六晶体管M6及参考电平信号线时，所述方法还包括：所述第一扫描信号线Scan1发送初始化控制信号给所述第六晶体管M6，控制第六晶体管M6打开，所述参考电平信号线提供初始电流通过第六晶体管M6流入发光二极管OLED，对发光二极管OLED进行初始化。
关于本实施例的其它细节可以参考第一至第三实施例中的描述，在此不再赘述。
根据本实施例中的方法，通过更少的晶体管及电容能够有效抵消电源电压及第四晶体管本身的阈值电压的影响，以使连接所述像素电路的显示器的显示更加均匀。另外，本申请实施例提供的像素电路架构简单，信号少，电路版图相对更简单，有利于像素电路的布局。
工业实用性
本申请提供的像素电路及像素电路的驱动方法，通过更少的晶体管及电容能够有效抵消电源电压及第四晶体管本身的阈值电压的影响，以使OLED的显示更加均匀，像素电路架构简单，有利于像素电路的布局。

Claims (12)

  1. 一种像素电路，应用于有源矩阵有机发光显示屏，所述像素电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一扫描信号线、第二扫描信号线、数据信号线、控制信号线、电容及发光二极管；
    所述第一晶体管的栅极与所述第一扫描信号线连接，所述第一晶体管的源极与所述电容的第一极板连接，所述第一晶体管的漏极与所述第二晶体管的源极相连；
    所述电容的第二极板与所述第三晶体管的漏极连接；
    所述第二晶体管的栅极与所述第二扫描信号线连接，所述第二晶体管的漏极与所述第四晶体管的栅极相连，所述第二晶体管的源极与所述数据信号线相连；
    所述第三晶体管的源极设置为与电源连接，所述第三晶体管的漏极与所述第四晶体管的源极连接，所述第三晶体管的栅极与所述控制信号线连接；
    所述第四晶体管的漏极与所述发光二极管的阳极连接；
    所述发光二极管的阴极设置为接地；
    其中，所述第一扫描信号线设置为发送控制信号到所述第一晶体管的栅极，以控制所述第一晶体管的打开或关闭；所述第二扫描信号线设置为发送控制信号到所述第二晶体管的栅极，以控制第二晶体管打开和关闭；所述控制信号线设置为发送控制信号到所述第三晶体管的栅极，以控制第三晶体管打开和关闭。
  2. 如权利要求1所述的像素电路，其中，所述第一晶体管是双栅晶体管，所述第一晶体管的两个栅极均与所述第一扫描信号线相连。
  3. 如权利要求1所述的像素电路，其中，所述像素电路还包括第五晶体管，所述第五晶体管的漏极与所述发光二极管的阳极连接，所述第五晶体管的源极与所述第四晶体管的漏极连接，所述第五晶体管的栅极与所述控制信号线连接；所述控制信号线设置为发送控制信号到所述第五晶体管的栅极，以控制所述第五晶体管打开或关闭。
  4. 如权利要求1所述的像素电路，其中，所述像素电路还包括第六晶体管，所述第六晶体管的栅极与所述第一扫描信号线连接，所述第六晶体管的漏极与 所述发光二极管连接；所述第一扫描信号线设置为发送控制信号到所述第六晶体管的栅极，以控制第六晶体管打开或关闭。
  5. 如权利要求4所述的像素电路，其中，所述像素电路还包括参考电平信号线，所述参考电平信号线与所述第六晶体管的源极连接，所述参考电平信号线设置为提供初始电流通过所述第六晶体管流入所述发光二极管，对所述发光二极管进行初始化。
  6. 如权利要求1所述的像素电路，其中，所述像素电路还包括第五晶体管、第六晶体管及参考电平信号线；
    所述第五晶体管的漏极与所述发光二极管连接，所述第五晶体管的源极与所述第四晶体管的漏极连接，所述第五晶体管的栅极与所述控制信号线连接；所述控制信号线设置为发送控制信号到所述第五晶体管的栅极，以控制第五晶体管打开或关闭；
    所述第六晶体管的栅极与所述第一扫描信号线连接，所述第六晶体管的漏极与所述发光二极管连接；所述第一扫描信号线设置为发送控制信号到所述第六晶体管的栅极，以控制第六晶体管打开或关闭；
    所述参考电平信号线与所述第六晶体管的源极连接，所述参考电平信号线设置为提供初始电流通过第六晶体管流入所述发光二极管，对所述发光二极管进行初始化。
  7. 如权利要求1-6任意一项所述的像素电路，所述有源矩阵有机发光显示屏为微型有源矩阵有机发光显示屏。
  8. 如权利要求1-7任意一项所述的像素电路，所述有源矩阵有机发光显示屏为硅基有源矩阵有机发光显示屏。
  9. 一种像素电路的驱动方法，应用于权利要求1-8任意一项所述的像素电路，所述方法包括：
    第一阶段：第一扫描信号线控制第一晶体管打开，以及第二扫描信号线控制第二晶体管打开，所述数据信号线低电平的第一信号写入所述第四晶体管的栅极及所述电容的第一极板；
    第二阶段：第一扫描信号线控制所述第一晶体管关闭，第二扫描信号线控制控制第二晶体管打开，所述数据信号线高电平的第二信号写入所述第四晶体管的栅极，使所述第四晶体管的源极电压钳位到第三信号，所述第三信号由所述第二信号与所述第四晶体管的阈值电压确定；
    第三阶段：第一扫描信号线控制第一晶体管打开，以及控制信号线控制第三晶体管打开，所述第四晶体管的源极电压与所述电源的电源电压相同；在所述电容的耦合作用下，所述第四晶体管的栅极电压钳位到第四信号，所述第四信号由所述第一信号、第三信号及电源电压确定。
  10. 如权利要求9所述的像素电路的驱动方法，其中，所述第二阶段的第三信号为所述第二信号与所述第四晶体管的阈值电压之差；
    所述第三阶段中的第四晶体管的栅极与源极的电压差值为：
    Vgs＝Vdata1+(Vdd-Vdata2+Vth)-Vdd
    ＝Vdata1-(Vdata2-Vth)；
    其中，所述Vgs表示所述第四晶体管的栅极与源极的电压差值，Vdata1表示所述第一信号，Vdata2表示所述第二信号，Vth表示所述第四晶体管的阈值电压；Vdd表示所述电源电压；
    此时，流过所述第四晶体管的电流为：
    Figure PCTCN2018084996-appb-100001
    其中，所述Ids表示流过所述第四晶体管的电流，所述β表示所述第四晶体管的放大倍数。
  11. 如权利要求9所述的像素电路的驱动方法，其中，当所述像素电路包括连接在所述第四晶体管与发光二极管之间的第五晶体管时，所述方法还包括：
    当所述第四晶体管有电流通过时，所述第四晶体管的电流经过所述第五晶 体管后流入所述发光二极管。
  12. 如权利要求9所述的像素电路的驱动方法，其中，当所述像素电路包括第六晶体管及参考电平信号线时，所述方法还包括：
    所述第一扫描信号线发送初始化控制信号给所述第六晶体管，控制所述第六晶体管打开，所述参考电平信号线提供初始电流通过所述第六晶体管流入所述发光二极管，对所述发光二极管进行初始化。
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