WO2019015024A1 - 一种栅极驱动电路及其驱动方法 - Google Patents

一种栅极驱动电路及其驱动方法 Download PDF

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Publication number
WO2019015024A1
WO2019015024A1 PCT/CN2017/099590 CN2017099590W WO2019015024A1 WO 2019015024 A1 WO2019015024 A1 WO 2019015024A1 CN 2017099590 W CN2017099590 W CN 2017099590W WO 2019015024 A1 WO2019015024 A1 WO 2019015024A1
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Prior art keywords
pull
transistor
module
signal
drain
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English (en)
French (fr)
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徐向阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/568,220 priority Critical patent/US10332468B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention belongs to the field of display control technologies, and in particular, to a gate driving circuit and a driving method thereof.
  • the GOA circuit of the display panel can generally realize the Q(n) point reset function only by the high potential scan signal outputted by the G (n+2)th stage gate drive circuit. If the G(n+2) output is abnormal, the Q(n) point of the nth stage of the GOA circuit cannot be reset to affect the normal display of the next frame. Sometimes, this abnormality will cause the gate output to generate a multi-pulse waveform, which in turn activates the overcurrent protection function and automatically shuts down.
  • the present invention provides a gate driving circuit and a driving method thereof for ensuring that the panel is not normally driven due to an abnormality of the GOA control signal.
  • a gate driving circuit comprising:
  • a pull-up control module configured to input an upward interval one-level scan signal under the control of the upward interval one-level scan start signal
  • a pull-up module configured to input a clock signal to generate a scan signal of the current level under the control of the upward interval one-level scan signal output by the pull-up control module;
  • a pull-down module configured to pull down the output potential of the pull-up control module and the potential of the scanning signal of the current stage under the control of the clock signal separated by one step;
  • a pull-down maintaining module configured to keep the output potential of the pull-up control module and the potential of the scan signal of the current stage at a predetermined low potential under the control of the output potential and the external signal of the pull-up control module.
  • the pull-up control module comprises:
  • the first transistor has a gate for inputting an upward interval one-stage scan enable signal, a source for inputting an upper interval one-level scan signal, and a drain for connecting the pull-up module.
  • the pull-up module comprises:
  • the second transistor has a gate connected to the drain of the first transistor, a source for inputting a clock signal, and a drain for outputting a scan signal of the current stage.
  • the pull-down module comprises:
  • a third transistor having a gate for inputting a first-level clock signal, a source connected to a drain of the second transistor, and a drain connected to the predetermined low potential;
  • a fourth transistor having a gate for inputting a clock signal that is spaced downwardly, a source connected to a gate of the second transistor, and a drain connected to the predetermined low potential.
  • the pull-down maintaining module includes a first pull-down maintaining sub-module, and the first pull-down maintaining sub-module includes:
  • a fifth transistor having a gate for inputting the first applied signal and a source connected to the gate thereof;
  • a sixth transistor having a gate connected to an output end of the pull-up control module, a source connected to a drain of the fifth transistor, and a drain connected to the predetermined low potential;
  • a seventh transistor having a gate connected to a drain of the fifth transistor and a source connected to a source of the fifth transistor;
  • An eighth transistor having a gate connected to an output end of the pull-up control module, a source connected to a drain of the seventh transistor, and a drain connected to the predetermined low potential;
  • a ninth transistor having a gate connected to a drain of the seventh transistor, a source connected to an output end of the pull-up control module, and a drain connected to the predetermined low potential;
  • a tenth transistor having a gate connected to a drain of the seventh transistor, a source connected to an output end of the pull-up module, and an output terminal connected to the pull-up control module via a coupling capacitor, and a drain connected to the predetermined low Potential.
  • the pull-down maintaining module includes a second pull-down maintaining sub-module, and the second pull-down maintaining sub-module includes:
  • An eleventh transistor having a gate for inputting a second applied signal, a source connected to the gate thereof, and the second applied control signal and the first applied control signal alternately driving the corresponding pull-down maintaining module to operate;
  • a twelfth transistor having a gate connected to an output end of the pull-up control module, a source connected to a drain of the eleventh transistor, and a drain connected to the predetermined low potential;
  • a thirteenth transistor having a gate connected to a drain of the eleventh transistor and a source connected to a source of the eleventh transistor;
  • a fourteenth transistor having a gate connected to an output end of the pull-up control module, a source connected to a drain of the thirteenth transistor, and a drain connected to the predetermined low potential;
  • a fifteenth transistor having a gate connected to a drain of the thirteenth transistor, a source connected to an output end of the pull-up control module, and a drain connected to the predetermined low potential;
  • a sixteenth transistor having a gate connected to a drain of the thirteenth transistor, a source connected to an output end of the pull-up module, and an output terminal connected to the pull-up control module via a coupling capacitor, and a drain connection
  • the low potential is predetermined.
  • the reset module comprising a seventeenth transistor
  • the gate of the seventeenth transistor is used to input a reset signal, the source is connected to the output of the pull-up control module, and the drain is connected to the predetermined low potential.
  • the scan enable signal generating module comprising an eighteenth transistor
  • the gate of the eighteenth transistor is connected to the output end of the pull-up control module, the source is used to input the clock signal, and the drain is used to output the scan enable signal of the current level.
  • the clock signal is composed of eight sub-clock square wave signals having a duty ratio of 1/4 and sequentially delayed by 1/8 clock cycles.
  • a method for driving a gate driving circuit comprising:
  • the pull-up module is controlled by the upward interval one-level scan signal output by the pull-up control module, so that a clock signal is output through the pull-up module to generate a scan signal of the current level;
  • An applied signal is applied to the pull-down sustaining module, and at a predetermined low potential of the output of the pull-up control module, the output potential of the pull-up control module and the potential of the scanning signal of the current stage are both at the predetermined low potential.
  • the present invention can ensure that the normal driving of the panel is not affected by the abnormality of the GOA control signal.
  • FIG. 1 is a schematic structural view of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 2 is a timing sequence corresponding to the gate driving circuit of FIG. 1;
  • FIG. 3 is a flow chart of a method for driving the circuit of FIG. 1 in accordance with one embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a G (n)th stage gate driving circuit according to an embodiment of the present invention. Referring to FIG. 1 below, adjacent G(n-2), G(n), and G ( The n+2) stage gate drive circuit is taken as an example to explain the present invention in detail.
  • G(n-2), G(n), and G(n+2) are used to drive an odd-numbered sequence or an even-numbered sequence gate line, and a gate drive circuit outputs a corresponding scan signal;
  • G(n-1), G(n+1) and G(n+3) are used to drive the corresponding even sequence or odd sequence gate lines, and the other gate drive circuit outputs a corresponding scan signal.
  • the gate driving circuit includes a pull-up control module 11 , a pull-up module 12 , a pull-down module 13 , and a pull-down maintaining module 14 .
  • the pull-up control module 11 is configured to input an upward interval first-level scan signal G(n-2) under the control of the upward interval first-level scan enable signal ST(n-2). That is, the G(n)-level gate drive circuit starts operating under the control of the gate drive circuit G(n-2)-level gate drive circuit spaced apart by one stage.
  • the output of the pull-up control module 11 is generally identified as a Q(n) point, which is mainly used to output the upward-interval scan signal G(n-2) to Q(n) under the control of ST(n-2). point.
  • the pull-up module 12 is configured to input the clock signal CK under the control of the Q(n) point of the pull-up control module 11 and the upper-stage scan signal G(n-2) to generate the current-level scan signal G(n).
  • the pull-down module 13 is configured to pull down the output potential of the pull-up control module 11 and the current-level scan signal potential G(n) under the control of the downward-interval clock signal CK(n+2). As shown in FIG. 3, when the G(n)-level scan signal is output, the pull-up module 12 inputs the clock signal CK1, and at this time, the pull-down module 13 is controlled by the clock signal CK3. The pull-up module 12 inputs the clock signal CK2. At this time, the pull-down module 13 is controlled by the clock signal CK4, and so on, when the pull-up module 12 inputs the clock signals CK7 and CK8, the return is controlled by the clock signals CK1 and CK2.
  • the pull-down maintaining module 14 is configured to maintain the potential of the output terminal of the pull-up control module 11 and the potential of the scanning signal G(n) of the current stage at a predetermined low potential Vss under the control of the output potential of the pull-up control module 11 and the applied signal LC. . That is, after the pull-down module 13 pulls the potential of the output terminal of the pull-up control module 11 and the potential of the scanning signal of the current stage to a predetermined low potential Vss, the potential of the pull-down maintaining module 14 at the output of the pull-up control module 11 and the applied signal are applied. Under the control of the LC, the output potential of the pull-up control module and the potential of the scanning signal of the current stage are both at a predetermined low potential Vss.
  • the pull-down module 13 in the gate driving circuit is controlled by dividing the first-order clock signal CK(n+2) downward, instead of using G(n+2) for control, then G(n+2) When the output is abnormal, Q(n) is pulled low by the CK signal. Even if the G(n+2) signal is abnormal, the gate drive circuit can operate normally when the next frame is refreshed.
  • the pull-up control module 11 includes a first transistor T11 having a gate for inputting an upward interval level one scan enable signal CK(n-2), and a source for inputting an upper interval.
  • the signal G(n-2) is scanned, and the pull-up module 12 is connected to the drain.
  • the scan enable signal ST(n-2) outputted by the G (n-2)th stage gate driving circuit causes the first transistor T11 to be turned on, and the scan signal outputted by the Gth (n-2)th stage gate driving circuit G(n-2) reaches the pull-up module through the first transistor T11, thereby controlling the pull-up module 12 to generate the local-level scan signal G(n).
  • the pull-up module 12 includes a second transistor T21 with a gate connected The drain of the first transistor T11 is connected to the source for inputting the clock signal CK, and the drain is for outputting the scan signal G(n) of the current stage.
  • the scan enable signal ST(n-2) outputted by the pull-up control module 11 turns on the second transistor T21, and the clock signal CK is output from the source of the second transistor T21 to the drain, thereby obtaining the scan signal G of the current stage ( n).
  • the pull-down module 13 includes a third transistor T31 and a fourth transistor T41.
  • the gate of the third transistor T31 is used for inputting the clock signal CK which is spaced downward, the source is connected to the drain of the second transistor T21, and the drain is connected to the predetermined low potential Vss.
  • the gate of the fourth transistor T41 is used to input a clock signal CK that is spaced downward, the source is connected to the gate of the second transistor T21, and the drain is connected to a predetermined low potential Vss.
  • the third transistor T31 and the fourth transistor T41 are both turned on, and the predetermined low potential Vss is connected to the output end of the pull-up control module 11 through the third transistor T31.
  • the fourth transistor T41 is connected to the output terminal of the pull-up module 12, thereby pulling the potentials of Q(n) and G(n) to a predetermined low potential Vss.
  • the pull-down maintenance module 14 includes a first pull-down maintenance sub-module 141.
  • the first pull-down maintaining sub-module 141 includes a fifth transistor T51 having a gate for inputting the first applied signal LC1 and a source connected to the gate thereof.
  • the gate of the sixth transistor T52 is connected to the output terminal of the pull-up control module 11, the source is connected to the drain of the fifth transistor T51, and the drain is connected to the predetermined low potential Vss.
  • the gate of the seventh transistor T53 is connected to the drain of the fifth transistor T51, and the source is connected to the source of the fifth transistor T51.
  • the eighth transistor T54 is connected to the output terminal of the pull-up control module 11, the source is connected to the drain of the seventh transistor T53, and the drain is connected to the predetermined low potential Vss.
  • the gate of the ninth transistor T42 is connected to the drain of the seventh transistor T53, the source is connected to the output terminal of the pull-up control module 11, and the drain is connected to the predetermined low potential Vss.
  • the gate of the tenth transistor T32 is connected to the drain of the seventh transistor T53, the source is connected to the output terminal of the pull-up module 12, and the output terminal of the pull-up control module 11 is connected through the coupling capacitor Cb, and the drain is connected to the predetermined low potential Vss.
  • the high-potential G(3) scan signal at a high potential pulls the Q(1) and G(1) point potentials down to Vss.
  • the sixth transistor T52 and the eighth transistor T54 are turned off. Applying the high potential first applied signal LC1, the fifth transistor T51 and the seventh transistor T53 are turned on, thereby causing the ninth transistor T42 to be turned on such that Q(1) is connected to the predetermined low potential Vss, so that the tenth transistor T32 is turned on such that G(1) Connected to a predetermined low potential Vss. This allows Q(1) and G(1) to remain at a predetermined low level until a high potential G(1) scan signal is output.
  • the sixth transistor T52 and the eighth transistor T54 are turned on, so that the ninth transistor T42 and the tenth transistor T32 are turned off, and the first pull-down maintaining sub-module 141 does not function.
  • the pull-down maintenance module 14 includes a second pull-down maintenance sub-module 142.
  • the second pull-down maintaining sub-module 142 includes an eleventh transistor T61, a twelfth transistor T62, a thirteenth transistor T63, a fourteenth transistor T64, a fifteenth transistor T43, and a sixteenth transistor T33.
  • the eleventh transistor T61 has a gate for inputting the second applied signal LC2, a source connected to the gate thereof, and a second applied control signal LC2 and the first applied control signal LC1 alternately driving the corresponding pull-down maintaining module to operate.
  • the gate of the twelfth transistor T62 is connected to the output terminal of the pull-up control module 11, the source is connected to the drain of the eleventh transistor T51, and the drain is connected to the predetermined low potential Vss.
  • the gate of the thirteenth transistor T63 is connected to the drain of the eleventh transistor T51, and the source is connected to the source of the eleventh transistor T51.
  • the gate of the fourteenth transistor T64 is connected to the output terminal of the pull-up control module 12, the source is connected to the drain of the thirteenth transistor T63, and the drain is connected to a predetermined low potential Vss.
  • the gate of the fifteenth transistor T43 is connected to the drain of the thirteenth transistor T63, the source is connected to the output terminal of the pull-up control module 11, and the drain is connected to the predetermined low potential Vss.
  • the gate of the sixteenth transistor T33 is connected to the drain of the thirteenth transistor T63, the source is connected to the output end of the pull-up module 11 and the output terminal of the pull-up control module 11 is connected through the coupling capacitor Cb, and the drain is connected to the predetermined low potential Vss.
  • LC1 and LC2 are low frequency signals with a period of 200 times the frame period and a duty ratio of 1/2.
  • the phase difference between LC1 and LC2 is 1/2 cycle, LC1 drives the first pull-down maintaining sub-module 141, LC2 drives the second pull-down maintaining sub-module 142 to work, and the first pull-down maintaining sub-module 141 and the second pull-down maintaining sub-module 142 are alternately performed. jobs.
  • the working process of the second pull-down maintaining sub-module 142 is the same as that of the first pull-down maintaining sub-module 141, and details are not described herein.
  • the gate drive circuit further includes a reset module 15.
  • the reset module 15 includes a seventeenth transistor T71.
  • the gate of the seventeenth transistor T71 is used to input a reset signal, the source is connected to the output terminal of the pull-up control module 11, and the drain is connected to a predetermined low potential Vss.
  • the seventeenth transistor T71 is for resetting the potential of the Q(n) point when the control signal Reset is applied.
  • the gate drive circuit further includes a scan enable signal generation module 16.
  • the scan enable signal generating module 16 includes an eighteenth transistor T22.
  • the gate of the eighteenth transistor T22 is connected to the output terminal of the pull-up control module 11, the source is used for inputting the clock signal CK, and the drain is used for outputting the current level scan. Start signal ST(n).
  • step S110 the pull-up control module 11 applies an upward interval one-level scan enable signal such that the upward interval one-level scan signal is output through the pull-up control module 11.
  • a start signal STV is generally applied to cause the G1(1)-stage gate drive circuit to start operating.
  • step S120 the pull-up module 12 is controlled by the upward interval one-level scan signal output by the pull-up control module 11 to cause the clock signal to be output through the pull-up module to generate the current-level scan signal.
  • step S130 a downward interval primary clock signal is applied to the pull-down module 13 to pull down the output potential of the pull-up control module and the potential of the current-level scan signal to a predetermined low potential.
  • step S140 an applied signal is applied to the pull-down maintaining module 14, and at the predetermined low potential of the output of the pull-up control module 11, the output potential of the pull-up control module 22 and the potential of the scanning signal of the current stage are both at The low potential is predetermined.

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Abstract

一种栅极驱动电路及其驱动方法，栅极驱动电路包括：上拉控制模块（11）；上拉模块（12）；下拉模块（13），用于在向下间隔一级时钟信号的控制下，拉低上拉控制模块（12）的输出端电位和本级扫描信号电位；下拉维持模块（14），用于在上拉控制模块（12）的输出端电位和外加信号控制下保持上拉控制模块（12）的输出端电位和本级扫描信号电位均处于预定低电位。

Description

一种栅极驱动电路及其驱动方法
相关申请的交叉引用
本申请要求享有2017年7月17日提交的名称为“一种栅极驱动电路及其驱动方法”的中国专利申请CN201710580980.0的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明属于显示控制技术领域，具体地说，尤其涉及一种栅极驱动电路及其驱动方法。
背景技术
随着平板显示技术的发展，高分辨率、高对比度、高刷新速率、窄边框、薄型化已成为平板显示的发展趋势。目前，液晶面板仍为平板显示的主流产品。为了实现液晶面板的窄边框、薄型化和低成本，GOA(Gate Driver On Array，阵列基板行驱动技术)的开发与应用已相对成熟。
现有技术中，显示面板的GOA电路一般仅能通过第G(n+2)级栅极驱动电路输出的的高电位扫描信号才能实现Q(n)点复位功能。如果G(n+2)输出异常时，GOA电路第n级的Q(n)点就不能被复位而影响下一帧的正常显示。有时，这种异常还会使得栅极输出产生多脉冲波形，进而启动过流保护功能而自动关机。
发明内容
为解决以上问题，本发明提供了一种栅极驱动电路及其驱动方法，用以保证不会因GOA控制信号的异常而影响面板正常驱动。
根据本发明的一个方面，提供了一种栅极驱动电路，包括：
上拉控制模块，用于在向上间隔一级扫描启动信号控制下，输入向上间隔一级扫描信号；
上拉模块，用于在所述上拉控制模块输出的向上间隔一级扫描信号控制下，输入时钟信号以产生本级扫描信号；
下拉模块，用于在向下间隔一级时钟信号的控制下，拉低所述上拉控制模块的输出端电位和本级扫描信号电位；
下拉维持模块，用于在所述上拉控制模块的输出端电位和外加信号控制下保持所述上拉控制模块的输出端电位和本级扫描信号电位均处于预定低电位。
根据本发明的一个实施例，所述上拉控制模块包括：
第一晶体管，其栅极用于输入向上间隔一级扫描启动信号，源极用于输入向上间隔一级扫描信号，漏极连接所述上拉模块。
根据本发明的一个实施例，所述上拉模块包括：
第二晶体管，其栅极连接所述第一晶体管的漏极，源极用于输入时钟信号，漏极用于输出本级扫描信号。
根据本发明的一个实施例，所述下拉模块包括：
第三晶体管，其栅极用于输入向下间隔一级时钟信号，源极连接所述第二晶体管的的漏极，漏极连接所述预定低电位；
第四晶体管，其栅极用于输入向下间隔一级时钟信号，源极连接所述第二晶体管的栅极，漏极连接所述预定低电位。
根据本发明的一个实施例，所述下拉维持模块包括第一下拉维持子模块，所述第一下拉维持子模块包括：
第五晶体管，其栅极用于输入第一外加信号，源极连接其栅极；
第六晶体管，其栅极连接所述上拉控制模块的输出端，源极连接所述第五晶体管的漏极，漏极连接所述预定低电位；
第七晶体管，其栅极连接所述第五晶体管的漏极，源极连接所述第五晶体管的源极；
第八晶体管，其栅极连接所述上拉控制模块的输出端，源极连接所述第七晶体管的漏极，漏极连接所述预定低电位；
第九晶体管，其栅极连接所述第七晶体管的漏极，源极连接所述上拉控制模块的输出端，漏极连接所述预定低电位；
第十晶体管，其栅极连接所述第七晶体管的漏极，源极连接所述上拉模块的输出端及通过耦合电容连接所述上拉控制模块的输出端，漏极连接所述预定低电位。
根据本发明的一个实施例，所述下拉维持模块包括第二下拉维持子模块，所述第二下拉维持子模块包括：
第十一晶体管，其栅极用于输入第二外加信号，源极连接其栅极，所述第二外加控制信号和所述第一外加控制信号交替驱动对应的下拉维持模块进行工作；
第十二晶体管，其栅极连接所述上拉控制模块的输出端，源极连接所述第十一晶体管的漏极，漏极连接所述预定低电位；
第十三晶体管，其栅极连接所述第十一晶体管的漏极，源极连接所述第十一晶体管的源极；
第十四晶体管，其栅极连接所述上拉控制模块的输出端，源极连接所述第十三晶体管的漏极，漏极连接所述预定低电位；
第十五晶体管，其栅极连接所述第十三晶体管的漏极，源极连接所述上拉控制模块的输出端，漏极连接所述预定低电位；
第十六晶体管，其栅极连接所述第十三晶体管的漏极，源极连接所述上拉模块的输出端及通过耦合电容连接所述上拉控制模块的输出端，漏极连接所述预定低电位。
根据本发明的一个实施例，还包括复位模块，所述复位模块包括第十七晶体管，
所述第十七晶体管的栅极用于输入复位信号，源极连接所述上拉控制模块的输出端，漏极连接所述预定低电位。
根据本发明的一个实施例，还包括扫描启动信号产生模块，所述扫描启动信号产生模块包括第十八晶体管，
所述第十八晶体管的栅极连接所述上拉控制模块的输出端，源极用于输入所述时钟信号，漏极用于输出本级扫描启动信号。
根据本发明的一个实施例，所述时钟信号由占空比为1/4、依次延迟1/8时钟周期的8个子时钟方波信号组成。
根据本发明的另一个方面，还提供了一种用于驱动栅极驱动电路的方法，包括：
向上拉控制模块施加向上间隔一级扫描启动信号，以使得向上间隔一级扫描信号经所述上拉控制模块输出；
上拉模块在所述上拉控制模块输出的向上间隔一级扫描信号控制下，以使得时钟信号通过所述上拉模块输出以产生本级扫描信号；
向下拉模块施加向下间隔一级时钟信号，以拉低所述上拉控制模块的输出端电位和本级扫描信号电位至预定低电位；
向下拉维持模块施加外加信号，并在所述上拉控制模块的输出端的预定低电位配合下，保持所述上拉控制模块的输出端电位和本级扫描信号电位均处于所述预定低电位。
本发明的有益效果：
本发明通过通过采用时钟信号CK下拉Q(n)点电位，而不采用扫描信号，可保证不会因GOA控制信号的异常而影响面板正常驱动。
本发明的其他优点、目标，和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书，权利要求书，以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。
图1是根据本发明的一个实施例的栅极驱动电路结构示意图；
图2是对应图1的栅极驱动电路输出时序；
图3是根据本发明的一个实施例的用于驱动图1所示电路的方法流程图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成相应技术效果的实现过程能充分理解并据以实施。本申请实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
本发明提供了一种栅极驱动电路，通过采用时钟信号将Q点电位拉低，可以保证不会因扫描信号异常而影响面板正常驱动。如图1所示为根据本发明的一个实施例的第G(n)级栅极驱动电路结构示意图，以下参考图1，以相邻的G(n-2)、G(n)和G(n+2)级栅极驱动电路为例来对本发明进行详细说明。G(n-2)、G(n)和G(n+2)……用于驱动奇数序列或偶数序列栅线，由一栅极驱动电路输出对应的扫描信号；G(n-1)、G(n+1)和G(n+3)……用于驱动对应的偶数序列或奇数序列栅线，由另一栅极驱动电路输出对应的扫描信号。
如图1所示，该栅极驱动电路包括上拉控制模块11、上拉模块12、下拉模块13和下拉维持模块14。其中，上拉控制模块11用于在向上间隔一级扫描启动信号ST(n-2)控制下，输入向上间隔一级扫描信号G(n-2)。也就是说，G(n)级栅极驱动电路是在其上间隔一级栅极驱动电路G(n-2)级栅极驱动电路的控制下开始工作的。上拉控制模块11的输出端通常标识为Q(n)点，其主要用于在ST(n-2)控制下，将向上间隔一级扫描信号G(n-2)输出至Q(n)点。
上拉模块12用于在上拉控制模块11输出的Q(n)点向上间隔一级扫描信号G(n-2)控制下，输入时钟信号CK，以产生本级扫描信号G(n)。
下拉模块13用于在向下间隔一级时钟信号CK(n+2)的控制下，拉低上拉控制模块11的输出端电位和本级扫描信号电位G(n)。如图3所示，在输出G(n)级扫描信号时，上拉模块12输入时钟信号CK1，此时下拉模块13由时钟信号CK3控制。在上拉模块12输入时钟信号CK2，此时下拉模块13由时钟信号CK4控制，依次类推至上拉模块12输入时钟信号CK7和CK8时，返回由时钟信号CK1和CK2控制。
下拉维持模块14用于在上拉控制模块11的输出端电位和外加信号LC控制下，保持上拉控制模块11的输出端电位和本级扫描信号G(n)的电位均处于预定低电位Vss。也就是说，在下拉模块13将上拉控制模块11的输出端电位和本级扫描信号电位拉低至预定低电位Vss后，下拉维持模块14在上拉控制模块11的输出端电位和外加信号LC控制下保持上拉控制模块的输出端电位和本级扫描信号电位均处于预定低电位Vss。
在本发明中，该栅极驱动电路中的下拉模块13采用向下间隔一级时钟信号CK(n+2)控制，而不采用G(n+2)进行控制，则在G(n+2)输出异常时，Q(n)通过CK信号被拉低。即使G(n+2)信号发生异常，在下一帧画面刷新时，栅极驱动电路仍能正常工作。
在本发明的一个实施例中，该上拉控制模块11包括第一晶体管T11，其栅极用于输入向上间隔一级扫描启动信号CK(n-2)，源极用于输入向上间隔一级扫描信号G(n-2)，漏极连接上拉模块12。具体工作时，第G(n-2)级栅极驱动电路输出的扫描启动信号ST(n-2)使得第一晶体管T11打开，第G(n-2)级栅极驱动电路输出的扫描信号G(n-2)通过第一晶体管T11到达上拉模块，进而控制上拉模块12产生本级扫描信号G(n)。
在本发明的一个实施例中，该上拉模块12包括第二晶体管T21，其栅极连 接第一晶体管T11的漏极，源极用于输入时钟信号CK，漏极用于输出本级扫描信号G(n)。具体工作时，上拉控制模块11输出的扫描启动信号ST(n-2)打开第二晶体管T21，时钟信号CK由第二晶体管T21的源极输出至漏极，从而得到本级扫描信号G(n)。
在本发明的一个实施例中，该下拉模块13包括第三晶体管T31和第四晶体管T41。其中，第三晶体管T31的栅极用于输入向下间隔一级时钟信号CK，源极连接第二晶体管T21的的漏极，漏极连接预定低电位Vss。第四晶体管T41的栅极用于输入向下间隔一级时钟信号CK，源极连接第二晶体管T21的栅极，漏极连接预定低电位Vss。具体工作时，在向下间隔一级时钟信号CK为高电位时，第三晶体管T31和第四晶体管T41均打开，预定低电位Vss通过第三晶体管T31连通上拉控制模块11的输出端，通过第四晶体管T41连通上拉模块12的输出端，从而将Q(n)和G(n)的电位拉至预定低电位Vss。例如，
由于向下间隔一级时钟信号CK只在该级栅极驱动电路输出扫描信号时为高电平，其余时间为低电平，为保证本级栅极驱动电路在不输出扫描信号时Q(n)和G(n)的电位保持预定低电位，需设置下拉维持模块来保持Q(n)和G(n)处于低电位。在本发明的一个实施例中，该下拉维持模块14包括包括第一下拉维持子模块141。该第一下拉维持子模块141包括第五晶体管T51，其栅极用于输入第一外加信号LC1，源极连接其栅极。第六晶体管T52的栅极连接上拉控制模块11的输出端，源极连接第五晶体管T51的漏极，漏极连接预定低电位Vss。第七晶体管T53的栅极连接第五晶体管T51的漏极，源极连接第五晶体管T51的源极。第八晶体管T54栅极连接上拉控制模块11的输出端，源极连接第七晶体管T53的漏极，漏极连接预定低电位Vss。第九晶体管T42的栅极连接第七晶体管T53的漏极，源极连接上拉控制模块11的输出端，漏极连接预定低电位Vss。第十晶体管T32的栅极连接第七晶体管T53的漏极，源极连接上拉模块12的输出端及通过耦合电容Cb连接上拉控制模块11的输出端，漏极连接预定低电位Vss。
具体的，在输出第G(3)级扫描信号时，处于高电位的高电位G(3)扫描信号将Q(1)和G(1)点电位拉低至Vss。此时，第六晶体管T52和第八晶体管T54关闭。施加高电位第一外加信号LC1，第五晶体管T51和第七晶体管T53打开，进而使得第九晶体管T42打开使得Q(1)连接至预定低电位Vss，使得第十晶体管T32打开使得G(1)连接至预定低电位Vss。这样就可以使Q(1)和G(1)一直保持预定低电位，直到输出高电位G(1)扫描信号。另外，在输出高电位G(1) 扫描信号时，第六晶体管T52和第八晶体管T54打开，使得第九晶体管T42和第十晶体管T32关闭，第一下拉维持子模块141不发挥作用。
在本发明的一个实施例中，该下拉维持模块14包括第二下拉维持子模块142。该第二下拉维持子模块142包括第十一晶体管T61、第十二晶体管T62、第十三晶体管T63、第十四晶体管T64、第十五晶体管T43和第十六晶体管T33。第十一晶体管T61，其栅极用于输入第二外加信号LC2，源极连接其栅极，第二外加控制信号LC2和第一外加控制信号LC1交替驱动对应的下拉维持模块进行工作。第十二晶体管T62的栅极连接上拉控制模块11的输出端，源极连接第十一晶体管T51的漏极，漏极连接预定低电位Vss。第十三晶体管T63的栅极连接第十一晶体管T51的漏极，源极连接第十一晶体管T51的源极。第十四晶体管T64的栅极连接上拉控制模块12的输出端，源极连接第十三晶体管T63的漏极，漏极连接预定低电位Vss。第十五晶体管T43的栅极连接第十三晶体管T63的漏极，源极连接上拉控制模块11的输出端，漏极连接预定低电位Vss。第十六晶体管T33的栅极连接第十三晶体管T63的漏极，源极连接上拉模块11的输出端及通过耦合电容Cb连接上拉控制模块11的输出端，漏极连接预定低电位Vss。LC1和LC2是周期为200倍帧周期、占空比为1/2的低频信号。LC1和LC2相位相差1/2周期，LC1驱动第一下拉维持子模块141，LC2驱动第二下拉维持子模块142工作，第一下拉维持子模块141和第二下拉维持子模块142交替进行工作。第二下拉维持子模块142的工作过程与第一下拉维持子模块141相同，此处不加赘述。
在本发明的一个实施例中，该栅极驱动电路还包括复位模块15。该复位模块15包括第十七晶体管T71。该第十七晶体管T71的栅极用于输入复位信号，源极连接上拉控制模块11的输出端，漏极连接预定低电位Vss。该第十七晶体管T71用于在外加控制信号Reset时，对Q(n)点电位进行复位。
在本发明的一个实施例中，该栅极驱动电路还包括扫描启动信号产生模块16。该扫描启动信号产生模块16包括第十八晶体管T22，该第十八晶体管T22的栅极连接上拉控制模块11的输出端，源极用于输入时钟信号CK，漏极用于输出本级扫描启动信号ST(n)。
现有技术中，栅极驱动电路中通常采用占空比为1/2的4个子时钟方波信号。但是，在本发明中采用占空比1/4、依次延迟1/8时钟周期的8个子时钟方波信号组成的时钟信号，如图2所示。这样可以减少每根CK的线路负载，降低错充 风险。同时，采用方波信号下拉可提升下拉模块中的薄膜晶体管依赖性，延长其工作寿命。另外，通过方波信号CK下拉Q(n)点，可提升信号的抗干扰能力，不至于因为某一行的瞬间输出异常而影响下一帧画面的输出。
根据本发明的另一个方面，还提供了一种用于驱动以上所述栅极驱动电路的方法，包括如图3所示的几个步骤，其对应的时序图参见图2。
首先，在步骤S110中，向上拉控制模块11施加向上间隔一级扫描启动信号，以使得向上间隔一级扫描信号经该上拉控制模块11输出。在对应G1(1)级栅极驱动电路时，由于无向上间隔一级扫描启动信号，一般施加一启动信号STV来使G1(1)级栅极驱动电路开始工作。
接着，在步骤S120中，上拉模块12在上拉控制模块11输出的向上间隔一级扫描信号控制下，以使得时钟信号通过该上拉模块输出以产生本级扫描信号。
接着，在步骤S130中，向下拉模块13施加向下间隔一级时钟信号，以拉低上拉控制模块的输出端电位和本级扫描信号电位至预定低电位。
接着，在步骤S140中，向下拉维持模块14施加外加信号，并在上拉控制模块11的输出端的预定低电位配合下，保持上拉控制模块22的输出端电位和本级扫描信号电位均处于预定低电位。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种栅极驱动电路，包括：
    上拉控制模块，用于在向上间隔一级扫描启动信号控制下，输入向上间隔一级扫描信号；
    上拉模块，用于在所述上拉控制模块输出的向上间隔一级扫描信号控制下，输入时钟信号以产生本级扫描信号；
    下拉模块，用于在向下间隔一级时钟信号的控制下，拉低所述上拉控制模块的输出端电位和本级扫描信号电位；
    下拉维持模块，用于在所述上拉控制模块的输出端电位和外加信号控制下保持所述上拉控制模块的输出端电位和本级扫描信号电位均处于预定低电位。
  2. 根据权利要求1所述的电路，其中，所述上拉控制模块包括：
    第一晶体管，其栅极用于输入向上间隔一级扫描启动信号，源极用于输入向上间隔一级扫描信号，漏极连接所述上拉模块。
  3. 根据权利要求2所述的电路，其中，所述上拉模块包括：
    第二晶体管，其栅极连接所述第一晶体管的漏极，源极用于输入时钟信号，漏极用于输出本级扫描信号。
  4. 根据权利要求3所述的电路，其中，所述下拉模块包括：
    第三晶体管，其栅极用于输入向下间隔一级时钟信号，源极连接所述第二晶体管的的漏极，漏极连接所述预定低电位；
    第四晶体管，其栅极用于输入向下间隔一级时钟信号，源极连接所述第二晶体管的栅极，漏极连接所述预定低电位。
  5. 根据权利要求3所述的电路，其中，所述下拉维持模块包括第一下拉维持子模块，所述第一下拉维持子模块包括：
    第五晶体管，其栅极用于输入第一外加信号，源极连接其栅极；
    第六晶体管，其栅极连接所述上拉控制模块的输出端，源极连接所述第五晶体管的漏极，漏极连接所述预定低电位；
    第七晶体管，其栅极连接所述第五晶体管的漏极，源极连接所述第五晶体管的源极；
    第八晶体管，其栅极连接所述上拉控制模块的输出端，源极连接所述第七晶体管的漏极，漏极连接所述预定低电位；
    第九晶体管，其栅极连接所述第七晶体管的漏极，源极连接所述上拉控制模 块的输出端，漏极连接所述预定低电位；
    第十晶体管，其栅极连接所述第七晶体管的漏极，源极连接所述上拉模块的输出端及通过耦合电容连接所述上拉控制模块的输出端，漏极连接所述预定低电位。
  6. 根据权利要求5所述的电路，其中，所述下拉维持模块包括第二下拉维持子模块，所述第二下拉维持子模块包括：
    第十一晶体管，其栅极用于输入第二外加信号，源极连接其栅极，所述第二外加控制信号和所述第一外加控制信号交替驱动对应的下拉维持模块进行工作；
    第十二晶体管，其栅极连接所述上拉控制模块的输出端，源极连接所述第十一晶体管的漏极，漏极连接所述预定低电位；
    第十三晶体管，其栅极连接所述第十一晶体管的漏极，源极连接所述第十一晶体管的源极；
    第十四晶体管，其栅极连接所述上拉控制模块的输出端，源极连接所述第十三晶体管的漏极，漏极连接所述预定低电位；
    第十五晶体管，其栅极连接所述第十三晶体管的漏极，源极连接所述上拉控制模块的输出端，漏极连接所述预定低电位；
    第十六晶体管，其栅极连接所述第十三晶体管的漏极，源极连接所述上拉模块的输出端及通过耦合电容连接所述上拉控制模块的输出端，漏极连接所述预定低电位。
  7. 根据权利要求1所述的电路，其中，还包括复位模块，所述复位模块包括第十七晶体管，
    所述第十七晶体管的栅极用于输入复位信号，源极连接所述上拉控制模块的输出端，漏极连接所述预定低电位。
  8. 根据权利要求2所述的电路，其中，还包括复位模块，所述复位模块包括第十七晶体管，
    所述第十七晶体管的栅极用于输入复位信号，源极连接所述上拉控制模块的输出端，漏极连接所述预定低电位。
  9. 根据权利要求3所述的电路，其中，还包括复位模块，所述复位模块包括第十七晶体管，
    所述第十七晶体管的栅极用于输入复位信号，源极连接所述上拉控制模块的输出端，漏极连接所述预定低电位。
  10. 根据权利要求4所述的电路，其中，还包括复位模块，所述复位模块包括第十七晶体管，
    所述第十七晶体管的栅极用于输入复位信号，源极连接所述上拉控制模块的输出端，漏极连接所述预定低电位。
  11. 根据权利要求5所述的电路，其中，还包括复位模块，所述复位模块包括第十七晶体管，
    所述第十七晶体管的栅极用于输入复位信号，源极连接所述上拉控制模块的输出端，漏极连接所述预定低电位。
  12. 根据权利要求6所述的电路，其中，还包括复位模块，所述复位模块包括第十七晶体管，
    所述第十七晶体管的栅极用于输入复位信号，源极连接所述上拉控制模块的输出端，漏极连接所述预定低电位。
  13. 根据权利要求1所述的电路，其中，还包括扫描启动信号产生模块，所述扫描启动信号产生模块包括第十八晶体管，
    所述第十八晶体管的栅极连接所述上拉控制模块的输出端，源极用于输入所述时钟信号，漏极用于输出本级扫描启动信号。
  14. 根据权利要求1所述的电路，其中，所述时钟信号由占空比为1/4、依次延迟1/8时钟周期的8个子时钟方波信号组成。
  15. 一种用于驱动栅极驱动电路的方法，所述栅极驱动电路包括：
    上拉控制模块，用于在向上间隔一级扫描启动信号控制下，输入向上间隔一级扫描信号；
    上拉模块，用于在所述上拉控制模块输出的向上间隔一级扫描信号控制下，输入时钟信号以产生本级扫描信号；
    下拉模块，用于在向下间隔一级时钟信号的控制下，拉低所述上拉控制模块的输出端电位和本级扫描信号电位；
    下拉维持模块，用于在所述上拉控制模块的输出端电位和外加信号控制下保持所述上拉控制模块的输出端电位和本级扫描信号电位均处于预定低电位，
    所述方法包括：
    向上拉控制模块施加向上间隔一级扫描启动信号，以使得向上间隔一级扫描信号经所述上拉控制模块输出；
    上拉模块在所述上拉控制模块输出的向上间隔一级扫描信号控制下，以使 得时钟信号通过所述上拉模块输出以产生本级扫描信号；
    向下拉模块施加向下间隔一级时钟信号，以拉低所述上拉控制模块的输出端电位和本级扫描信号电位至预定低电位；
    向下拉维持模块施加外加信号，并在所述上拉控制模块的输出端的预定低电位配合下，保持所述上拉控制模块的输出端电位和本级扫描信号电位均处于所述预定低电位。
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