WO2018040321A1 - 一种goa驱动单元及驱动电路 - Google Patents

一种goa驱动单元及驱动电路 Download PDF

Info

Publication number
WO2018040321A1
WO2018040321A1 PCT/CN2016/107602 CN2016107602W WO2018040321A1 WO 2018040321 A1 WO2018040321 A1 WO 2018040321A1 CN 2016107602 W CN2016107602 W CN 2016107602W WO 2018040321 A1 WO2018040321 A1 WO 2018040321A1
Authority
WO
WIPO (PCT)
Prior art keywords
pull
down transistor
unit
transistor
row
Prior art date
Application number
PCT/CN2016/107602
Other languages
English (en)
French (fr)
Inventor
曾勉
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/324,700 priority Critical patent/US10192505B2/en
Publication of WO2018040321A1 publication Critical patent/WO2018040321A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration

Definitions

  • the invention belongs to the field of liquid crystal display, and in particular relates to a GOA driving unit and a driving circuit.
  • the driving circuit of the conventional liquid crystal display is generally in the form of an externally mounted integrated circuit module, such as a commonly used TAB (Tape Automated Bonding) package structure.
  • TAB Tunnel Automated Bonding
  • LTPS low temperature polysilicon
  • integrated circuit technology based on panel periphery has gradually become the focus of research.
  • Typical applications are array substrate rows. Drive Technology (GOA, Gate Driver On Array).
  • the GOA driving circuit uses a liquid crystal display Array process to fabricate a gate scan driving signal circuit on the array substrate to realize progressive driving scanning of the pixel unit.
  • the GOA drive circuit can not only reduce the welding process of external integrated circuits, improve integration, but also increase production capacity and reduce production costs. It is the first choice for small and medium-sized liquid crystal display products (such as mobile phones, PDAs, etc.). In addition, as the mobile phone intelligentization process is accelerating, the touch technology of small and medium-sized liquid crystal display devices also needs corresponding technical support, so more requirements are put on the drive circuit.
  • the existing GOA driving circuit has the following problems.
  • the parameters of the transistor have great dispersibility, and the performance of the transistor may be affected after long-term operation, the parameter is changed, so that the voltage of some key circuit nodes in the driving circuit is made. Changes will occur, causing failures in the timing and function of the design in severe cases, which in turn leads to failure of the entire GOA drive circuit.
  • the GOA driver circuit process due to the large number of circuit stages and the large number of transistors, faults such as short circuit or open circuit are prone to occur, and since the repair is difficult, such a situation will cause the liquid crystal panel to become a secondary Product, seriously affecting the yield of LCD panel output.
  • One of the technical problems to be solved by the present invention is to provide an improved GOA driving circuit for stabilizing the voltage of critical circuit nodes and preventing failure due to parameter variations of components.
  • the embodiment of the present application first provides a GOA driving unit, including a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down maintaining unit, and a bootstrap capacitor, which further includes a neighboring row pull-down. a transistor, the adjacent row pull-down transistor pulls down and maintains the row scan signal of the adjacent row of the previous scan timing when the pull-down sustaining unit pulls the scan control signal and the row scan signal of the current row low and maintains the low level At low level.
  • the pull-down maintaining unit includes a first pull-down transistor for pulling down and maintaining the scan control signal of the current line at a low level, and a line for pulling down and maintaining the line scan signal of the line at a low level.
  • a pull-down transistor, the drains of the first pull-down transistor and the second pull-down transistor are respectively connected with a scan control signal and a row scan signal;
  • the drain of the adjacent-line pull-down transistor is connected to a row scan of an adjacent row of a previous scan timing a signal whose gate is coupled to the gates of the first pull-down transistor and the second pull-down transistor;
  • the sources of the first pull-down transistor, the second pull-down transistor, and the adjacent pull-down transistor are commonly coupled to DC pull-down voltage.
  • the pull-down maintaining unit further includes: a third pull-down transistor, the gate and the drain are coupled together to receive the pull-down clock signal; and the fourth pull-down transistor has a gate and a drain respectively and the third pull-down The source and the drain of the transistor are coupled to each other; the fifth pull-down transistor and the sixth pull-down transistor have a drain coupled to a gate and a source of the fourth pull-down transistor, respectively, and a source thereof is coupled to a DC pull-down voltage, The gates are coupled together to receive the scan control signal; the drain of the sixth pull-down transistor is coupled to the gate coupling node of the first pull-down transistor, the second pull-down transistor, and the adjacent pull-down transistor .
  • the pull-down clock signal is equal in frequency and opposite in phase to the scan clock signal of the GOA driving unit of the row.
  • the method further includes a downlink transmission unit, the downlink transmission unit includes a downlink transistor, a gate of the lower transmission transistor is connected to the scan control signal, and a drain thereof is connected to the scan clock signal of the GOA driving unit, and a source generating function thereof is The downstream signal of the GOA drive unit of the latter stage.
  • the downlink transmission unit includes a downlink transistor, a gate of the lower transmission transistor is connected to the scan control signal, and a drain thereof is connected to the scan clock signal of the GOA driving unit, and a source generating function thereof is The downstream signal of the GOA drive unit of the latter stage.
  • the pull-down maintaining unit includes a mirrored circuit structure
  • the mirrored circuit structure includes: a first pull-down transistor and a third pull-down transistor for pulling down and maintaining a scan control signal of the current line at a low level a second pull-down transistor and a fourth pull-down transistor for pulling down and maintaining a row scan signal of the row at a low level
  • the adjacent row pull-down transistor includes a first adjacent row pull-down transistor and a second adjacent row pull-down transistor, the drain thereof a row scan signal of an adjacent row connected to a previous scan timing, said first adjacent row pull-down crystal a gate and a source of the tube are coupled to a gate and a source of the first pull-down transistor and a second pull-down transistor, respectively, and a gate and a source of the second adjacent-row pull-down transistor are respectively associated with the third
  • the gate and the source of the pull-down transistor and the fourth pull-down transistor are coupled; the source of each pull-down transistor is coupled to the DC pull-down voltage.
  • the pull-down maintaining unit further comprises a mirrored first alternating control circuit and a second alternating control circuit, the first alternating control circuit comprising: a fifth pull-down transistor, the gate and the drain being coupled together, receiving a first alternate control signal; a sixth pull-down transistor having a gate and a drain coupled to a source and a drain of the fifth pull-down transistor, respectively; a seventh pull-down transistor and an eighth pull-down transistor having a drain and a drain
  • the gate and the source of the sixth pull-down transistor are coupled, the source thereof is coupled to the DC pull-down voltage, and the gates are coupled together to receive the scan control signal; the drain and the drain of the eighth pull-down transistor a first pull-down transistor, a second pull-down transistor, and a gate coupling node of the first adjacent row pull-down transistor are coupled;
  • the second alternate control circuit has a structure mirrored with the first alternate control circuit, and The second alternate control signal is controlled; the first alternate control signal and the second alternate control signal alternate between a high level and
  • the frequency of the first alternating control signal and the second alternating control signal is less than a frequency of a scan clock signal of the GOA driving unit.
  • the method further includes a downlink transmission unit, the downlink transmission unit includes a downlink transistor, a gate of the lower transmission transistor is connected to the scan control signal, and a drain thereof is connected to the scan clock signal of the GOA driving unit, and a source generating function thereof is The downstream signal of the GOA drive unit of the latter stage.
  • the downlink transmission unit includes a downlink transistor, a gate of the lower transmission transistor is connected to the scan control signal, and a drain thereof is connected to the scan clock signal of the GOA driving unit, and a source generating function thereof is The downstream signal of the GOA drive unit of the latter stage.
  • another GOA driving circuit is further provided, which is constructed by cascading the GOA driving units, and two scanning clock signals of equal frequency and opposite phases are interlaced and input to the respective GOA driving units.
  • the low potential sustaining capability of the GOA circuit output can be improved, and the performance of the circuit can be further improved.
  • the circuit can also maintain the pull-down by the pull-down sustain circuit of the lower stage, and increase the self-repair capability of the GOA circuit.
  • FIG. 1 is a schematic structural view of a GOA driving unit in the prior art
  • FIG. 2 is a schematic structural diagram of a GOA driving unit according to an embodiment of the invention.
  • FIG. 3 is a schematic diagram of signal waveforms when a GOA driving unit is in operation according to an embodiment of the invention
  • FIG. 4 is a schematic structural diagram of a GOA driving unit according to another embodiment of the present invention.
  • FIG. 5 is a schematic diagram of signal waveforms when a GOA driving unit is in operation according to another embodiment of the present invention.
  • the existing GOA driving circuit generally includes a plurality of cascaded GOA driving units, and each stage of the GOA driving unit corresponds to driving a horizontal scanning line of one level.
  • 1 is a schematic structural diagram of a GOA driving unit in the prior art. As shown in the figure, the main structure of the GOA driving unit includes a pull-up control unit 110 and a pull-up unit 120. , a pull-down unit 140 and a pull-down holding unit 150, and a bootstrap capacitor 130.
  • the voltage of each circuit node is determined by the structure of the GOA drive unit itself.
  • scanning control signal Q(N) point which activates the active high level signal of transistor T21 of pull-up unit 120 is generated by transistor T11 of pull-up control unit 110, while maintaining Q(N) during line scan of other lines
  • the low level signal of the point is completed by the pull-down maintaining unit 150 of the stage. If the circuit in the GOA drive unit of this stage fails, for example, the transistor in which the transistor is short-circuited or disconnected due to the process, it will affect the output of the drive unit of the stage.
  • the GOA driving unit of the present invention is improved based on the above-described basic structure, so that when the scanning control signal and the line scanning signal of the current line are pulled low and maintained at a low level, the line scanning signals of adjacent lines of the previous scanning timing can be simultaneously simultaneously simultaneously It is also pulled low and maintained at a low level, so that the drive unit has self-repairing capability, which will be described in detail below in conjunction with specific embodiments.
  • the Nth stage GOA driving unit controls charging of the Nth horizontal scanning line G(N) of the display area, including the pull-up control unit 210, the pull-up unit 220, the bootstrap capacitor 230, the pull-down unit 240, the pull-down maintaining unit 250, and the neighboring The row pull down transistor T72 and the down pass unit 260.
  • the pull-up control unit 210 is mainly used to control the turn-on time of the pull-up unit 220 to implement progressive scan of the liquid crystal panel.
  • the pull-up control unit 210 may be constituted by a pull-up control transistor T11.
  • the gate of the pull-up control transistor T11 receives an ST(N-1) signal which is a down-converted signal generated by the GOA driving unit of the previous stage (N-1th stage).
  • the output signal of the upper stage that is, the line scan signal G(N-1) is generally used to start the driving unit of the next stage, and the drain and the gate of the control transistor T11 are pulled up. Coupled together, receiving a row scan signal output by the GOA driving unit of the previous stage, and a source generating a scan control signal applied to the input of the control signal of the pull-up unit.
  • T11 is equivalent to one diode, that is, the gate-source voltage Vgs of T11 is 0, and there is a large leakage current inside T11.
  • the downlink unit 260 is added. As shown in FIG. 2, the downlink unit 260 is mainly composed of a down transistor T22. The gate and the drain of the down transistor T22 are both connected to the pull-up unit 220. The gate of the T22 is coupled to the control signal input terminal of the pull-up unit 220, and the clock signal of the drain of the T22 and the pull-up unit 220. The input terminal is coupled, and the source of T22 generates and outputs a downlink signal ST(N) for the gate of the pull-up control transistor T11 of the GOA driving unit of the subsequent stage (N+1th stage).
  • the drain and source of T11 are connected to the N-1th horizontal scanning line G(N-1) and the Nth order Q(N) point, respectively. Since the low potential of the down signal ST(N-1) is the low level of the clock signal CK (or XCK), it is generally -8V. The low potential of the row scan signal G(N-1) is VSS, which is generally -6V, that is, the gate-source voltage Vgs ⁇ 0 of T11. Therefore, by increasing the down-transfer unit 260, the leakage of the Q-point at the present level during holding can be reduced.
  • the pull-up control unit 210 generates a scan control signal Q(N) by the down signal ST(N-1) and the line scan output signal G(N-1) generated by the upper stage drive unit.
  • the scan control signal Q(N) is responsible for the correct operation timing of the entire GOA drive unit.
  • Q(N) is a high level, which can be used to turn on the pull-up unit 220 to output a line scan signal.
  • the Nth stage is in the non-row scanning state, it is necessary to ensure that Q(N) is a reliable low level, so that the pull-up unit 220 does not output. Therefore, in the design of the GOA driving unit and the driving circuit, it is necessary to ensure that the timing of Q(N) is correct.
  • the pull-up unit 220 is mainly responsible for outputting a scan clock signal (Clock) as a row scan signal of the gate.
  • the pull-up unit 220 may be constituted by a pull-up transistor T21.
  • the gate of the pull-up transistor T21 receives the scan control signal Q(N) generated by the pull-up control unit 210 as a control signal input terminal of the pull-up unit 220, and the drain of the T21 receives the scan as the clock signal input terminal of the pull-up unit 220.
  • Clock letter The source of the XCK, T21 is used as the line scan signal output terminal of the pull-up unit 220, and is connected to the Nth horizontal scanning line G(N) to generate and output the line scan signal G(N).
  • 230 in FIG. 2 is a bootstrap capacitor, and the function of the bootstrap capacitor is to store the voltage of the gate terminal of the pull-up transistor T21 when Q(N) is high, and to output a high level when G(N) is output.
  • the bootstrap capacitor can second raise the potential of the gate of the pull-up transistor T21 to ensure that the pull-up transistor T21 reliably turns on and outputs the line scan signal. After completing the scan timing of this line, G(N) outputs a low level and maintains this low level while other lines are being scanned.
  • the pull-down unit 240 is configured to pull the source potential and the gate potential of the pull-up transistor T21 low to the first time, that is, turn off the row scan signal G(N).
  • the pull-down unit 240 includes a pull-down transistor T31 and a pull-down transistor T41.
  • T31 is used to pull down the potential of the line scan signal G(N)
  • the drain of T31 is coupled to the line scan signal output end of the pull-up unit 220, that is, to the horizontal scan line of the Nth line.
  • T41 is used to pull down the scan control signal Q(N) to turn off the pull-up transistor T21.
  • the drain of T41 is coupled to the control signal input terminal of pull-up unit 220.
  • the gates of T31 and T41 are coupled together and connected to the horizontal scanning line G(N+1) of the N+1th row, that is, the row scanning signal G(N+1) of the GOA driving unit of the subsequent stage is received.
  • the line scan signal is controlled by the effective line scan signal of the next line to realize the progressive scan.
  • the sources of T31 and T41 are commonly coupled to a DC low level VSS.
  • the pull-down sustaining unit is used. 250 holds G(N) and Q(N) in a closed state (ie, a negative potential).
  • the pull-down maintaining unit 250 includes transistors T42 and T32, wherein T42 (first pull-down transistor) is used to pull down and maintain the scan control signal Q(N) of the current line during the line scan of other lines. Level, T32 (second pull-down transistor) is used to pull down and maintain the low level of the row scan signal G(N) of the row during the line scan of other rows. Further, the drain of T42 is connected to the scan control signal Q(N), the drain of T32 is connected to the row scan signal G(N), the gate and the source of T42 and T32 are respectively coupled together, and the source thereof is coupled to A fixed DC pull-down voltage VSS, the potential of its gate (such as the P(N) point in FIG. 2) is controlled by the control circuit of the pull-down maintaining unit 250.
  • T42 first pull-down transistor
  • Level, T32 second pull-down transistor
  • the drain of T42 is connected to the scan control signal Q(N)
  • the drain of T32 is connected to the row scan signal G(N)
  • the control circuit of the pull-down maintaining unit 250 includes transistors T51, T52, T53, and T54.
  • the gate and the drain of the transistor T51 are coupled together to receive the pull-down clock signal (XCK), and the gate and the drain of the transistor T53 (the fourth pull-down transistor) are respectively connected to the source of the T51.
  • the drain is coupled, and the source (P(N) point) of T53 is a voltage signal that controls the action of transistors T42 and T32.
  • T52 (the fifth pull-down transistor) is coupled to the gate of T53, T54 (sixth The drain of the pull-down transistor is coupled to the source of T53, the gates of T52 and T54 are coupled together, and the scan control signal Q(N) is connected, and the sources thereof are commonly coupled to the DC pull-down voltage VSS.
  • a plurality of scanning clock signals are generally used for joint driving.
  • the embodiment in FIG. 3 is described by taking two scan clock signals CK and XCK as an example.
  • CK and XCK are equal in frequency and opposite in phase, and are interlaced to the clock signal input terminal of the pull-up unit 220 of each GOA driving unit.
  • the clock signal XCK is not shown at the clock signal input end of the pull-up unit 220 in FIG. 2, and XCK is connected to the N-1th stage driving unit.
  • the row scan signal G(N-1) and the down signal ST(N-1) of the previous scan timing are outputted to a high level by the scan clock signal XCK, and the Nth stage driving unit is
  • the pull-up control transistor T11 is turned on, and the scan control signal Q(N) reaches a first voltage value, which can turn on the pull-up transistor T21 and the down-transfer transistor T22 of the N-th stage driving unit.
  • the line scan signal G(N) and the down signal ST(N) simultaneously output a high level of CK, and perform line scan on the pixel of the Nth line.
  • the pull-up control transistor of the (N+1)th driving unit receives the high level of G(N) and ST(N), and when the row scanning signal G(N+1) of the next row is high level, the Nth The pull-down transistors T31 and T41 of the stage drive unit are turned on, thereby pulling G(N) and Q(N) low to turn off the scanning of the pixels of the Nth row.
  • G(N+1) returns to the low level, the low levels of G(N) and Q(N) are maintained by the pull-down maintaining unit 250.
  • the first voltage value of the scan control signal Q(N) turns on T52 and T54, and when T52 and T54 turn on, S(N) and P(N) are simultaneously pulled low. Since the voltage at the P(N) point simultaneously controls the gate potentials of the transistors T32 and T42, T32 and T42 can be reliably turned off at this time, and there is no influence on Q(N) and G(N). The voltage at the Q(N) point will rise after the G(N) output is high, and thus the G(N-1) output level is high, although G(N-1) and ST(N-1) have become Low, the voltage at P(N) can still maintain T32 and T42 off.
  • the pull-down clock signal of the pull-down maintaining unit 250 uses the XCK signal in the interlaced clock signal, and when the S(N) point is low, it is in the high level of XCK, and T51 is in the The state of being turned on, so when T52 is turned off, the potential of S(N) will rise due to the high level of XCK, and when S(N) rises to the difference between its potential and the potential of P(N) When the turn-on threshold of transistor T53 is reached, T53 is turned on. After T53 is turned on, the P(N) point is raised to high power by the high level of XCK. Flat, and then turn on T32 and T42 to maintain the low level of Q(N) and G(N).
  • T42 and T32 are turned off, and the Q(N) point is maintained at a low level by itself during the low potential of XCK.
  • T51 and T53 are both on, XCK's high level is transmitted to P(N) point, then T42 and T32 are turned on, and Q(N) is pulled down to maintain.
  • the pull-down clock signal uses the scan clock signal XCK and the frequency is high, the pull-down maintenance function can be correctly realized.
  • the XCK signal is directly used as the pull-down clock signal, the introduction of other signal lines is omitted, which can save wiring space and facilitate production and processing.
  • the adjacent row pull-down transistor is disposed. Further, as shown in FIG. 2, the drain of the adjacent row pull-down transistor T72 is connected to the row scan signal G of the adjacent row of the previous scan timing (the N-1th row in FIG. 2). (N-1), its gate is coupled to the gates of T42 and T32. Since the gate of the adjacent row pull-down transistor T72 is also connected to the P(N) point, its turn-on and turn-off are also controlled by P(N), that is, synchronized with T42 and T32, so when P(N) is high, G( N-1) can be maintained low by T72.
  • the adjacent row pull-down transistor can improve the reliability of the circuit and increase the self-repairing capability of the circuit.
  • the pull-down maintaining unit is a circuit having a mirror image structure.
  • the image circuit can reduce the DC stress caused by the DC signal.
  • the GOA driving unit is composed of a pull-up control unit, a pull-up unit, a bootstrap capacitor, a pull-down unit, and a pull-down maintaining unit, wherein the pull-up control unit, the pull-up unit, the bootstrap capacitor, and the pull-down unit
  • the structure and function are the same as those of the previous embodiment, and will not be described again here.
  • the pull-down sustaining unit of this embodiment includes a pair of mirrored circuit structures. Specifically, it is used to pull down and dimension
  • the transistor T42 (first pull-down transistor) and the transistor T43 (third pull-down transistor) holding the scan control signal Q(N) of the current line are used to pull down and maintain the line scan signal G(N) of the line.
  • the pull-down maintaining unit further includes a mirrored first alternate control circuit and a second alternate control circuit, wherein the first alternate control circuit includes a transistor T51 (a fifth pull-down transistor), a T53 (a sixth pull-down transistor), and a T52 (a seventh pull-down transistor) And T54 (eighth pull-down transistor).
  • the connection mode is the same as that of the control circuit in the previous embodiment.
  • the gate and the drain of the T51 are coupled together to receive the first alternate control signal LC1, and the gate and the drain of the T53 and the source of the T51 are respectively
  • the drain is coupled, the drains of T52 and T54 are respectively coupled to the gate and the source of T53, and the sources thereof are all coupled to the DC pull-down voltage VSS, and the gates are coupled together to receive the scan control signal Q(N). ).
  • the drain of T54 is coupled to the gates of T42 and T32, and the voltage signal for controlling the operation of transistors T42 and T32 is output from the drain (P(N) point) of T54.
  • the second alternate control circuit has a structure mirrored with the first alternate control circuit, and its action is controlled by the second alternate control signal LC2, LC1 and LC2 alternately at a high level and a low level, and when LC1 is at a high level, LC2 is low.
  • the first alternate control circuit controls the mirror circuits on the left (T32, T42, T51, T52, T53, and T54).
  • the second alternate control circuit controls the mirror on the right.
  • the circuits (T33, T43, T61, T62, T63, and T64) operate.
  • a first adjacent row pull-down transistor T72 and a second adjacent row pull-down transistor T73 are respectively disposed, and the drains of T72 and T73 are connected to adjacent rows of the previous scan timing (Fig. Line scan signal G(N-1) of line 4-1, wherein the gate of T72 is coupled to the gates of T42 and T32, and the voltage of P(N) is controlled to turn on and off. .
  • the gate of T73 is coupled to the gates of T43 and T33, which are controlled to turn on and off by the voltage at point K(N).
  • the sources of T72 and T73 are both coupled to the DC pull-down voltage VSS.
  • the mirror circuit structure (T32, T42, T51, T52, T53, and T54) on the left side controlled by LC1 can be combined with FIG. 4 and FIG. 5, and reference is made to the previous embodiment.
  • the working process of the control circuit is carried out, and will not be described here.
  • the alternate control signals LC1 and LC2 are no longer high frequency signals, and the frequency is less than the frequency of the scan clock signal of the GOA driving unit, so the P(N) point is always kept at the high level during the pull-down sustaining phase, which is more effective. It is guaranteed to maintain Q(N), G(N) and G(N-1) at a low level.
  • the pull-down maintaining unit performs pull-down maintenance only for the Q point and the line scan signal output point of the current stage circuit.
  • a pull-down transistor for performing operation on the adjacent row is added, and at the same time, a pull-down maintaining operation is performed on the output signal of the row scanning signal of the upper-level circuit, which can greatly improve the low-potential maintaining capability of the output of the GOA circuit, and further improve The driving performance of the circuit improves the quality of the liquid crystal panel.
  • the pull-down maintaining unit of the lower stage can also be used to maintain the pull-down, thereby improving the self-repairing capability of the GOA circuit.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)

Abstract

公开了一种GOA驱动单元及驱动电路，该GOA驱动单元包括上拉单元、上拉控制单元、下拉单元、下拉维持单元及自举电容，邻行下拉晶体管在下拉维持单元将本行的扫描控制信号和行扫描信号拉低并维持在低电平时，将前一扫描时序的相邻行的行扫描信号也拉低并维持在低电平。该驱动单元能够增加GOA电路的自修复能力。

Description

一种GOA驱动单元及驱动电路
相关申请的交叉引用
本申请要求享有2016年08月31日提交的名称为“一种GOA驱动单元及驱动电路”的中国专利申请CN201610790773.3的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明属于液晶显示领域，尤其涉及一种GOA驱动单元及驱动电路。
背景技术
传统的液晶显示器的驱动电路一般为外部搭载的集成电路模组的形式，如普遍采用的TAB(Tape Automated Bonding)封装结构。而随着具有超高载流子迁移率特性的低温多晶硅(LTPS，Low Temperature Poly silicon)半导体薄膜晶体管的发展，基于面板周边的集成电路技术逐渐成为研究的焦点，其中典型的应用是阵列基板行驱动技术(GOA，Gate Driver On Array)。
GOA驱动电路是利用液晶显示器Array制程将行(Gate)扫描驱动信号电路制作在阵列基板上来实现对像素单元的逐行驱动扫描。GOA驱动电路不仅能够减少外接集成电路的焊接工序，提高集成度，还可以提升产能降低生产成本，是中小尺寸液晶显示产品(例如手机，PDA等)的首选。另外，随着手机智能化进程日益加快，中小尺寸液晶显示设备的触控技术也需要得到相应的技术支持，因此对驱动电路提出了更多要求。
现有的GOA驱动电路存在如下问题，一方面，由于晶体管的参数具有很大的分散性，且长期工作后其性能有可能受到影响进一步使其参数改变，使得驱动电路中一些关键电路节点的电压会发生变化，严重时引发设计的时序和功能的失效，进而导致整个GOA驱动电路的失效。另一方面，在GOA驱动电路制程中，由于电路级数多，晶体管数量巨大等原因，容易发生短路或断路等故障，而由于修复难度较高，因此一旦出现这种情况将导致液晶面板成为次品，严重影响液晶面板产出的良率。
发明内容
本发明所要解决的技术问题之一是需要提供一种改进的GOA驱动电路以稳定关键电路节点的电压，防止因元件的参数变化而导致的失效。
为了解决上述技术问题，本申请的实施例首先提供了一种GOA驱动单元，包括上拉单元、上拉控制单元、下拉单元、下拉维持单元及自举电容，其特征在于，还包括邻行下拉晶体管，所述邻行下拉晶体管在下拉维持单元将本行的扫描控制信号和行扫描信号拉低并维持在低电平时，将前一扫描时序的相邻行的行扫描信号也拉低并维持在低电平。
优选地，所述下拉维持单元包括用于拉低并维持本行的扫描控制信号在低电平的第一下拉晶体管及用于拉低并维持本行的行扫描信号在低电平的第二下拉晶体管，所述第一下拉晶体管和第二下拉晶体管的漏极分别连接扫描控制信号和行扫描信号；所述邻行下拉晶体管的漏极连接前一扫描时序的相邻行的行扫描信号，其栅极与所述第一下拉晶体管和第二下拉晶体管的栅极耦接在一起；所述第一下拉晶体管、第二下拉晶体管和邻行下拉晶体管的源极共同耦接于直流下拉电压。
优选地，所述下拉维持单元还包括：第三下拉晶体管，其栅极与漏极耦接在一起，接收下拉时钟信号；第四下拉晶体管，其栅极与漏极分别与所述第三下拉晶体管的源极和漏极耦接；第五下拉晶体管和第六下拉晶体管，其漏极分别与所述第四下拉晶体管的栅极和源极耦接，其源极均耦接直流下拉电压，其栅极耦接在一起，接收所述扫描控制信号；所述第六下拉晶体管的漏极与所述第一下拉晶体管、第二下拉晶体管和邻行下拉晶体管的栅极耦接节点耦接。
优选地，所述下拉时钟信号与本行GOA驱动单元的扫描时钟信号频率相等，相位相反。
优选地，还包括下传单元，所述下传单元包括下传晶体管，所述下传晶体管的栅极连接扫描控制信号，其漏极连接GOA驱动单元的扫描时钟信号，其源极生成作用于后一级GOA驱动单元的下传信号。
优选地，所述下拉维持单元包括镜像的电路结构，所述镜像的电路结构包括：用于拉低并维持本行的扫描控制信号在低电平的第一下拉晶体管和第三下拉晶体管及用于拉低并维持本行的行扫描信号在低电平的第二下拉晶体管和第四下拉晶体管；所述邻行下拉晶体管包括第一邻行下拉晶体管和第二邻行下拉晶体管，其漏极均连接前一扫描时序的相邻行的行扫描信号，所述第一邻行下拉晶体 管的栅极和源极分别与所述第一下拉晶体管和第二下拉晶体管的栅极和源极耦接，所述第二邻行下拉晶体管的栅极和源极分别与所述第三下拉晶体管和第四下拉晶体管的栅极和源极耦接；各下拉晶体管的源极均耦接于直流下拉电压。
优选地，所述下拉维持单元还包括镜像的第一交替控制电路和第二交替控制电路，所述第一交替控制电路包括，第五下拉晶体管，其栅极与漏极耦接在一起，接收第一交替控制信号；第六下拉晶体管，其栅极与漏极分别与所述第五下拉晶体管的源极和漏极耦接；第七下拉晶体管和第八下拉晶体管，其漏极分别与所述第六下拉晶体管的栅极和源极耦接，其源极均耦接直流下拉电压，其栅极耦接在一起，接收所述扫描控制信号；所述第八下拉晶体管的漏极与所述第一下拉晶体管、第二下拉晶体管和第一邻行下拉晶体管的栅极耦接节点耦接；所述第二交替控制电路具有与所述第一交替控制电路镜像的结构，且其由第二交替控制信号控制；所述第一交替控制信号与所述第二交替控制信号交替为高电平和低电平。
优选地，所述第一交替控制信号和所述第二交替控制信号的频率小于GOA驱动单元的扫描时钟信号频率。
优选地，还包括下传单元，所述下传单元包括下传晶体管，所述下传晶体管的栅极连接扫描控制信号，其漏极连接GOA驱动单元的扫描时钟信号，其源极生成作用于后一级GOA驱动单元的下传信号。
另一方面，还提供了另一种GOA驱动电路，由所述GOA驱动单元级联构成，将频率相等、相位相反的两个扫描时钟信号隔行输入至各GOA驱动单元。
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：
通过在现有GOA电路本级中增加下拉晶体管，同时针对上一级电路的G(N-1)输出点进行下拉维持操作，可提高GOA电路输出的低电位维持能力，进一步提高其电路的性能，进而改善产品品质。并且在本级电路的下拉维持电路失效时，电路还可以通过下级的下拉维持电路来起到下拉维持作用，增加GOA电路的自修复能力。
本发明的其他优点、目标，和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书，权利要求书，以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。
图1为现有技术中的GOA驱动单元的结构示意图；
图2为根据本发明一实施例的GOA驱动单元的结构示意图；
图3为根据本发明一实施例的GOA驱动单元工作时的信号波形示意图；
图4为根据本发明另一实施例的GOA驱动单元的结构示意图；
图5为根据本发明另一实施例的GOA驱动单元工作时的信号波形示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成相应技术效果的实现过程能充分理解并据以实施。本申请实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
现有的GOA驱动电路通常包括级联的多个GOA驱动单元，每一级GOA驱动单元对应驱动一级水平的行扫描线。图1为现有技术中的GOA驱动单元的结构示意图，如图所示，GOA驱动单元的主要结构包括上拉控制单元110(Pull-up control part)，上拉单元120(Pull-up part)，下拉单元140(Key Pull-down Part)和下拉维持单元150(Pull-down Holding Part)，以及自举(Boast)电容130。
从图中可以看出，各电路节点的电压均由该级GOA驱动单元自身的结构决定。例如扫描控制信号Q(N)点，其开启上拉单元120的晶体管T21的有效的高电平信号由上拉控制单元110的晶体管T11生成，而在其他行的行扫描期间维持Q(N)点的低电平信号则是由该级的下拉维持单元150完成的。如果本级GOA驱动单元内的电路发生故障，例如其中的晶体管由于制程的原因发生短路或断路，则必将影响该级驱动单元的输出。本发明的GOA驱动单元基于上述基本结构进行改进，使得在本行的扫描控制信号和行扫描信号被拉低并维持在低电平时，可以同时将前一扫描时序的相邻行的行扫描信号也拉低并维持在低电平，使驱动单元具有自修复能力，下面结合具体的实施例详细说明。
图2为根据本发明一实施例的GOA驱动单元的结构示意图，如图所示，该 第N级GOA驱动单元控制对显示区域的第N行水平扫描线G(N)充电，包括上拉控制单元210，上拉单元220，自举电容230，下拉单元240，下拉维持单元250、邻行下拉晶体管T72和下传单元260。
具体的，上拉控制单元210主要用于控制上拉单元220的开启时间，实现液晶面板的逐行扫描。上拉控制单元210可以由上拉控制晶体管T11构成。从图2中可以看出，该上拉控制晶体管T11的栅极接收ST(N-1)信号，该信号为来自上一级(第N-1级)的GOA驱动单元产生的下传信号。
现有技术中(如图1所示)，一般采用上一级的输出信号，即行扫描信号G(N-1)来启动下一级的驱动单元，上拉控制晶体管T11的漏极和栅极耦接在一起，接收前一级GOA驱动单元输出的行扫描信号，其源极生成作用于上拉单元的控制信号输入端的扫描控制信号。则此时T11相当于一个二极管，即T11的栅源电压Vgs＝0，在T11内部会存在较大的漏电流。
在本发明的实施例中，增加了下传单元260。如图2所示，下传单元260主要由下传晶体管T22构成。该下传晶体管T22的栅极和漏极均与上拉单元220相连接，其中T22的栅极与上拉单元220的控制信号输入端耦接，T22的漏极与上拉单元220的时钟信号输入端耦接，T22的源极生成并输出下传信号ST(N)，作用于后一级(第N+1级)GOA驱动单元的上拉控制晶体管T11的栅极。T11的漏极和源极分别连接第N-1级水平扫描线G(N-1)和第N级的Q(N)点。由于下传信号ST(N-1)的低电位为时钟信号CK(或XCK)的低电平，一般为-8V。行扫描信号G(N-1)的低电位则为VSS，一般为-6V，即T11的栅源电压Vgs<0，因此通过增加下传单元260可以减少本级Q点在holding时的漏电。
上拉控制单元210在上一级驱动单元产生的下传信号ST(N-1)和行扫描输出信号G(N-1)的作用下，生成扫描控制信号Q(N)。扫描控制信号Q(N)负责整个GOA驱动单元的正确工作时序。当行扫描进行到第N级时，Q(N)为高电平，可用于开启上拉单元220输出行扫描信号。当第N级处于非行扫描状态时，需要保证Q(N)为可靠的低电平，使上拉单元220不输出。因此，在GOA驱动单元以及驱动电路的设计中，必须保证Q(N)的时序正确。
上拉单元220主要负责将扫描时钟信号(Clock)输出为栅极的行扫描信号。如图2所示，上拉单元220可以由上拉晶体管T21构成。上拉晶体管T21的栅极作为上拉单元220的控制信号输入端接收由上拉控制单元210生成的扫描控制信号Q(N)，T21的漏极作为上拉单元220的时钟信号输入端接收扫描时钟信 号XCK，T21的源极作为上拉单元220的行扫描信号输出端，连接第N行水平扫描线G(N)，生成并输出行扫描信号G(N)。
另外，图2中的230为自举电容，该自举电容的作用是在Q(N)为高电平时，存储上拉晶体管T21栅源端的电压，当G(N)输出高电平的行扫描信号后，自举电容可以二次抬升上拉晶体管T21的栅极的电位，以保证上拉晶体管T21可靠地开启与输出行扫描信号。在完成本行的扫描时序后，G(N)输出低电平，并在其他行进行扫描的时候一直维持这个低电平。
下拉单元240用于在第一时间将上拉晶体管T21的源极电位和栅极电位拉低为低电位，即关闭行扫描信号G(N)。如图2所示，下拉单元240包括下拉晶体管T31和下拉晶体管T41。其中，T31用于下拉行扫描信号G(N)的电位，T31的漏极与上拉单元220的行扫描信号输出端耦接，即作用于第N行水平扫描线。T41用于下拉扫描控制信号Q(N)，以便关闭上拉晶体管T21。T41的漏极与上拉单元220的控制信号输入端耦接。T31与T41的栅极耦接在一起，并与第N+1行的水平扫描线G(N+1)相连接，即接收接后一级GOA驱动单元的行扫描信号G(N+1)，由下一行的有效的行扫描信号控制本行行扫描信号的关闭，实现逐行扫描。T31与T41的源极共同耦接于直流低电平VSS。
当后一级的行扫描信号G(N+1)回到低电平后，将不能维持G(N)和Q(N)的低电平，因此，在GOA驱动单元中，采用下拉维持单元250将G(N)和Q(N)维持(Holding)在关闭状态(即负电位)。
如图2所示，下拉维持单元250包括晶体管T42和T32，其中T42(第一下拉晶体管)用于拉低并维持本行的扫描控制信号Q(N)在其他行的行扫描期间的低电平，T32(第二下拉晶体管)用于拉低并维持本行的行扫描信号G(N)在其他行的行扫描期间的低电平。进一步地，T42的漏极连接扫描控制信号Q(N)，T32的漏极连接行扫描信号G(N)，T42和T32的栅极和源极分别耦接在一起，其源极耦接于一固定的直流下拉电压VSS，其栅极(如图2中的P(N)点)的电位由下拉维持单元250的控制电路进行控制。
如图2所示，下拉维持单元250的控制电路包括晶体管T51、T52、T53和T54。其中，晶体管T51(第三下拉晶体管)的栅极与漏极耦接在一起，接收下拉时钟信号(XCK)，晶体管T53(第四下拉晶体管)的栅极与漏极分别与T51的源极和漏极耦接，T53的源极(P(N)点)即输出控制晶体管T42和T32动作的电压信号。T52(第五下拉晶体管)的漏极与T53的栅极耦接，T54(第六 下拉晶体管)的漏极与T53的源极耦接，T52和T54的栅极耦接在一起，连接扫描控制信号Q(N)，其源极共同耦接于直流下拉电压VSS。
当将多级驱动单元级联构成GOA驱动电路时，为了减轻GOA驱动电路的负载，提高驱动能力，一般采用多个扫描时钟信号联合驱动。图3中的实施例以两个扫描时钟信号CK和XCK为例进行说明，CK和XCK频率相等、相位相反，隔行输入至各GOA驱动单元的上拉单元220的时钟信号输入端。需要注意的是，在图2中未在上拉单元220的时钟信号输入端示出时钟信号XCK，XCK连接于第N-1级驱动单元。
如图3所示，前一扫描时序的行扫描信号G(N-1)和下传信号ST(N-1)在扫描时钟信号XCK的作用下输出为高电平，第N级驱动单元的上拉控制晶体管T11即被开启，扫描控制信号Q(N)达到第一电压值，该第一电压值能够开启第N级驱动单元的上拉晶体管T21和下传晶体管T22。
T21和T22开启后，当CK时钟信号的高电平到达时，行扫描信号G(N)和下传信号ST(N)同时输出CK的高电平，在对第N行像素进行行扫描的同时，第N+1级驱动单元的上拉控制晶体管接收到G(N)和ST(N)的高电平，当下一行的行扫描信号G(N+1)为高电平后，第N级驱动单元的下拉晶体管T31和T41被开启，进而将G(N)和Q(N)拉低为低电平，关闭第N行像素的扫描。当G(N+1)回复到低电平后，G(N)和Q(N)的低电平由下拉维持单元250维持。
扫描控制信号Q(N)的第一电压值使T52和T54开启，T52和T54开启后会将S(N)和P(N)同时拉低为低电平。由于P(N)点的电压同时控制晶体管T32和T42的栅极电位，因此此时T32和T42能够可靠的处于关闭状态，对Q(N)和G(N)不会产生影响。Q(N)点的电压在G(N)输出高电平后会有一个抬升，因而在G(N)输出高电平时，尽管G(N-1)和ST(N-1)已经变为低电平，P(N)点的电压仍能维持T32和T42处于关闭状态。
当Q(N)和G(N)被拉低为低电平后，T52和T54和关闭。另外，如图2所示，下拉维持单元250的下拉时钟信号采用的是隔行扫描时钟信号中的XCK信号，当S(N)点为低电平时正处于XCK的高电平期间，T51处于被开启的状态，因此当T52关闭后，由于XCK的高电平的作用，S(N)点的电位将升高，当S(N)升高到其电位与P(N)的电位的差值达到晶体管T53的开启阈值时，T53被开启。T53被开启后，P(N)点在XCK的高电平的作用下被抬升为高电 平，进而开启T32和T42，维持Q(N)和G(N)的低电平。
进一步如图3所示，当XCK处于低电平时，T51关闭，S(N)点的电位会有一定的下降。S(N)点模拟结果如图所示，如果XCK的高电位和低电位分别为28V和-8V，则当XCK由高电平变为低电平时，S(N)点的电位会先下降至5V左右，然后再逐渐漏电到-1.5V左右。5V左右的电压已经足够开启T53，因此，T53在XCK变为低电平的初期将维持开启的状态，进而将XCK的低电位传输至P(N)点。也就是说，此时T42和T32会被关闭，Q(N)点在XCK的低电位期间靠自身维持在低电位。当XCK的下一个高电平到来时，T51和T53均处于开启状态，XCK的高电平传输至P(N)点，进而开启T42和T32，对Q(N)进行下拉维持。
虽然Q(N)点在下拉维持期间有部分时间需要靠自身来维持低电位状态，但由于下拉时钟信号采用的是与扫描时钟信号XCK，频率较高，因此能够正确的实现下拉维持的功能。另外，由于直接采用XCK信号作为下拉时钟信号，省去了其他信号线的引入，可以节约布线空间，有利于生产加工。
在本实施例中设置邻行下拉晶体管，进一步如图2所示，邻行下拉晶体管T72的漏极连接前一扫描时序的相邻行(图2中第N-1行)的行扫描信号G(N-1)，其栅极与T42和T32的栅极耦接在一起。由于邻行下拉晶体管T72的栅极也连接P(N)点，其开启与关闭同样由P(N)控制，即与T42和T32同步，因此，当P(N)为高电平时，G(N-1)可以由T72维持为低电平。邻行下拉晶体管能够提升电路的可靠性，增加电路的自修复能力。因为，如果驱动电路的第N-1行的下拉维持单元存在故障，例如晶体管T32发生断路，那么仍然可以通过T72保证电路的正常工作而不至于使电路功能失效。本实施例能够显著地增加其GOA驱动电路的可靠性
图4为根据本发明另一实施例的GOA驱动单元的结构示意图，该实施例中，下拉维持单元是具有镜像结构的电路。当晶体管长期处于直流信号作用时，会产生直流应力(DC Stress)，其性能会受到影响，引发晶体管的失效，镜像电路能够降低直流信号作用所导致的直流应力的影响。
如图所示，该GOA驱动单元由上拉控制单元、上拉单元、自举电容、下拉单元以及下拉维持单元等结构组成，其中上拉控制单元、上拉单元、自举电容、下拉单元的结构和功能与前一实施例相同，此处不再赘述。
该实施例的下拉维持单元包括一对镜像的电路结构。具体为，用于拉低并维 持本行的扫描控制信号Q(N)在低电平的晶体管T42(第一下拉晶体管)和晶体管T43(第三下拉晶体管)，用于拉低并维持本行的行扫描信号G(N)在低电平的晶体管T32(第二下拉晶体管)和晶体管T33(第四下拉晶体管)。
下拉维持单元还包括镜像的第一交替控制电路和第二交替控制电路，其中第一交替控制电路包括晶体管T51(第五下拉晶体管)、T53(第六下拉晶体管)、T52(第七下拉晶体管)和T54(第八下拉晶体管)。其连接方式与前一实施例中的控制电路相同，具体为T51的栅极与漏极耦接在一起，接收第一交替控制信号LC1，T53的栅极与漏极分别与T51的源极和漏极耦接，T52和T54的漏极分别与T53的栅极和源极耦接，它们的源极均耦接直流下拉电压VSS，其栅极耦接在一起，接收扫描控制信号Q(N)。其中，T54的漏极与T42、T32的栅极耦接在一起，由T54的漏极(P(N)点)输出控制晶体管T42和T32动作的电压信号。
第二交替控制电路具有与第一交替控制电路镜像的结构，且其动作由第二交替控制信号LC2控制，LC1和LC2交替为高电平和低电平，当LC1为高电平，LC2为低电平时，第一交替控制电路控制左边的镜像电路(T32、T42、T51、T52、T53和T54)工作，当LC1为低电平，LC2为高电平时，第二交替控制电路控制右边的镜像电路(T33、T43、T61、T62、T63和T64)工作。
进一步如图4所示，对应于镜像电路结构，分别设置了第一邻行下拉晶体管T72和第二邻行下拉晶体管T73，T72和T73的漏极均连接前一扫描时序的相邻行(图4中第N-1行)的行扫描信号G(N-1)，其中，T72的栅极与T42和T32的栅极耦接在一起，由P(N)点的电压控制其开启与关闭。T73的栅极与T43和T33的栅极耦接在一起，由K(N)点的电压控制其开启与关闭。T72和T73的源极均耦接于直流下拉电压VSS。
假设LC1为高电平，LC2为低电平，由LC1控制左边的镜像电路结构(T32、T42、T51、T52、T53和T54)可以结合图4和图5，并参照前一实施例中的控制电路的工作过程进行，此处不再赘述。需要注意的是，交替控制信号LC1和LC2不再是高频信号，其频率小于GOA驱动单元的扫描时钟信号频率，因此P(N)点在下拉维持阶段始终保持为高电平，能够更有效地保证将Q(N)、G(N)和G(N-1)维持在低电平。
现有技术的GOA驱动电路，其下拉维持单元都是只针对本级电路的Q点和行扫描信号输出点进行下拉维持作用。而在本发明实施例中，通过在现有GOA 驱动单元的本级中增加对邻行实施操作的下拉晶体管，同时针对上一级电路的行扫描信号输出点进行下拉维持操作，可以较大程度上提高GOA电路输出的低电位维持能力，进一步提高其电路的驱动性能，进而改善液晶面板的品质。
由于增加了对相邻行的操作，当在本级驱动单元的下拉维持单元失效时，还可以通过下级的下拉维持单元来起到下拉维持作用，提高了GOA电路的自修复能力。当驱动电路由于制程的原因，或是由于长时间工作失效而存在元件故障时，在相邻行的互操作作用下，有可能保证电路继续正确动作，从另一方面来讲有助于提高GOA面板的良率。
虽然本发明所揭露的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

  1. 一种GOA驱动单元，包括上拉单元、上拉控制单元、下拉单元、下拉维持单元及自举电容，其中，
    还包括邻行下拉晶体管，所述邻行下拉晶体管在下拉维持单元将本行的扫描控制信号和行扫描信号拉低并维持在低电平时，将前一扫描时序的相邻行的行扫描信号也拉低并维持在低电平。
  2. 根据权利要求1所述的GOA驱动单元，其中，
    所述下拉维持单元包括用于拉低并维持本行的扫描控制信号在低电平的第一下拉晶体管及用于拉低并维持本行的行扫描信号在低电平的第二下拉晶体管，所述第一下拉晶体管和第二下拉晶体管的漏极分别连接扫描控制信号和行扫描信号；
    所述邻行下拉晶体管的漏极连接前一扫描时序的相邻行的行扫描信号，其栅极与所述第一下拉晶体管和第二下拉晶体管的栅极耦接在一起；
    所述第一下拉晶体管、第二下拉晶体管和邻行下拉晶体管的源极共同耦接于直流下拉电压。
  3. 根据权利要求2所述的GOA驱动单元，其中，所述下拉维持单元还包括：
    第三下拉晶体管，其栅极与漏极耦接在一起，接收下拉时钟信号；
    第四下拉晶体管，其栅极与漏极分别与所述第三下拉晶体管的源极和漏极耦接；
    第五下拉晶体管和第六下拉晶体管，其漏极分别与所述第四下拉晶体管的栅极和源极耦接，其源极均耦接直流下拉电压，其栅极耦接在一起，接收所述扫描控制信号；
    所述第六下拉晶体管的漏极与所述第一下拉晶体管、第二下拉晶体管和邻行下拉晶体管的栅极耦接节点耦接。
  4. 根据权利要求3所述的GOA驱动单元，其中，所述下拉时钟信号与本行GOA驱动单元的扫描时钟信号频率相等，相位相反。
  5. 根据权利要求1所述的GOA驱动单元，其中，还包括下传单元，所述下传单元包括下传晶体管，所述下传晶体管的栅极连接扫描控制信号，其漏极连接GOA驱动单元的扫描时钟信号，其源极生成作用于后一级GOA驱动单元的下传信号。
  6. 根据权利要求1所述的GOA驱动单元，其中，所述下拉维持单元包括镜像的电路结构，所述镜像的电路结构包括：
    用于拉低并维持本行的扫描控制信号在低电平的第一下拉晶体管和第三下拉晶体管及用于拉低并维持本行的行扫描信号在低电平的第二下拉晶体管和第四下拉晶体管；
    所述邻行下拉晶体管包括第一邻行下拉晶体管和第二邻行下拉晶体管，其漏极均连接前一扫描时序的相邻行的行扫描信号，所述第一邻行下拉晶体管的栅极和源极分别与所述第一下拉晶体管和第二下拉晶体管的栅极和源极耦接，所述第二邻行下拉晶体管的栅极和源极分别与所述第三下拉晶体管和第四下拉晶体管的栅极和源极耦接；
    各下拉晶体管的源极均耦接于直流下拉电压。
  7. 根据权利要求6所述的GOA驱动单元，其中，所述下拉维持单元还包括镜像的第一交替控制电路和第二交替控制电路，
    所述第一交替控制电路包括，
    第五下拉晶体管，其栅极与漏极耦接在一起，接收第一交替控制信号；
    第六下拉晶体管，其栅极与漏极分别与所述第五下拉晶体管的源极和漏极耦接；
    第七下拉晶体管和第八下拉晶体管，其漏极分别与所述第六下拉晶体管的栅极和源极耦接，其源极均耦接直流下拉电压，其栅极耦接在一起，接收所述扫描控制信号；
    所述第八下拉晶体管的漏极与所述第一下拉晶体管、第二下拉晶体管和第一邻行下拉晶体管的栅极耦接节点耦接；
    所述第二交替控制电路具有与所述第一交替控制电路镜像的结构，且其由第二交替控制信号控制；
    所述第一交替控制信号与所述第二交替控制信号交替为高电平和低电平。
  8. 根据权利要求7所述的GOA驱动单元，其中，所述第一交替控制信号和所述第二交替控制信号的频率小于GOA驱动单元的扫描时钟信号频率。
  9. 根据权利要求6所述的GOA驱动单元，其中，还包括下传单元，所述下传单元包括下传晶体管，所述下传晶体管的栅极连接扫描控制信号，其漏极连接GOA驱动单元的扫描时钟信号，其源极生成作用于后一级GOA驱动单元的下传信号。
  10. 一种由GOA驱动单元级联构成的GOA驱动电路，所述GOA驱动单元包括上拉单元、上拉控制单元、下拉单元、下拉维持单元及自举电容，其中，
    还包括邻行下拉晶体管，所述邻行下拉晶体管在下拉维持单元将本行的扫描控制信号和行扫描信号拉低并维持在低电平时，将前一扫描时序的相邻行的行扫描信号也拉低并维持在低电平；
    其中，所述GOA驱动电路将频率相等、相位相反的两个扫描时钟信号隔行输入至各GOA驱动单元。
PCT/CN2016/107602 2016-08-31 2016-11-29 一种goa驱动单元及驱动电路 WO2018040321A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/324,700 US10192505B2 (en) 2016-08-31 2016-11-29 GOA drive unit and drive circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610790773.3 2016-08-31
CN201610790773.3A CN106128397B (zh) 2016-08-31 2016-08-31 一种goa驱动单元及驱动电路

Publications (1)

Publication Number Publication Date
WO2018040321A1 true WO2018040321A1 (zh) 2018-03-08

Family

ID=57270968

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/107602 WO2018040321A1 (zh) 2016-08-31 2016-11-29 一种goa驱动单元及驱动电路

Country Status (3)

Country Link
US (1) US10192505B2 (zh)
CN (1) CN106128397B (zh)
WO (1) WO2018040321A1 (zh)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106128397B (zh) * 2016-08-31 2019-03-15 深圳市华星光电技术有限公司 一种goa驱动单元及驱动电路
CN106710503B (zh) * 2016-12-30 2019-11-22 深圳市华星光电技术有限公司 扫描驱动电路及显示装置
CN107068032B (zh) * 2017-01-22 2020-06-12 上海中航光电子有限公司 一种扫描单元以及栅极驱动电路
CN107068087B (zh) * 2017-03-31 2019-11-26 深圳市华星光电技术有限公司 一种goa驱动电路
CN107154244B (zh) * 2017-07-10 2019-08-02 深圳市华星光电技术有限公司 Goa电路及液晶显示装置
CN107154245B (zh) * 2017-07-17 2019-06-25 深圳市华星光电技术有限公司 一种栅极驱动电路及其驱动方法
US10386663B2 (en) 2017-08-14 2019-08-20 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. GOA circuit and liquid crystal display device
CN107331360B (zh) * 2017-08-14 2019-12-24 深圳市华星光电半导体显示技术有限公司 Goa电路及液晶显示装置
CN107369426B (zh) * 2017-09-04 2019-12-03 深圳市华星光电半导体显示技术有限公司 防止时钟信号丢失的goa电路
CN107610668B (zh) * 2017-10-20 2019-05-24 深圳市华星光电半导体显示技术有限公司 一种goa电路及液晶面板、显示装置
US10599242B2 (en) 2017-10-31 2020-03-24 Wuhan China Star Optoelectronics Technology Co., Ltd. Single-type GOA circuit and display apparatus
CN107742509A (zh) * 2017-10-31 2018-02-27 武汉华星光电技术有限公司 一种单型goa电路及显示装置
CN108831398B (zh) * 2018-07-25 2020-05-05 深圳市华星光电半导体显示技术有限公司 Goa电路及显示装置
CN109509459B (zh) * 2019-01-25 2020-09-01 深圳市华星光电技术有限公司 Goa电路及显示装置
CN110047438B (zh) * 2019-04-29 2020-09-01 深圳市华星光电技术有限公司 Goa电路
TWI726523B (zh) * 2019-12-06 2021-05-01 友達光電股份有限公司 驅動電路
CN111145680B (zh) * 2020-02-24 2021-07-27 苏州华星光电技术有限公司 驱动电路及显示面板
CN111292672B (zh) * 2020-03-31 2023-11-28 Tcl华星光电技术有限公司 Goa电路及显示面板
CN111710274B (zh) * 2020-06-12 2023-06-27 深圳市华星光电半导体显示技术有限公司 时钟信号判断电路及显示面板
CN112925442B (zh) * 2021-02-24 2024-01-26 福州京东方光电科技有限公司 触摸屏的驱动方法、装置、触摸屏、电子设备及存储介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1457059A (zh) * 2002-05-10 2003-11-19 阿尔卑斯电气株式会社 移位寄存器装置及显示装置
US20070035505A1 (en) * 2005-08-11 2007-02-15 Au Optronics Corp. Shift register circuit
US20110150169A1 (en) * 2009-12-22 2011-06-23 Au Optronics Corp. Shift register
CN104517577A (zh) * 2014-12-30 2015-04-15 深圳市华星光电技术有限公司 液晶显示装置及其栅极驱动器
CN104517575A (zh) * 2014-12-15 2015-04-15 深圳市华星光电技术有限公司 移位寄存器及级传栅极驱动电路
CN106128397A (zh) * 2016-08-31 2016-11-16 深圳市华星光电技术有限公司 一种goa驱动单元及驱动电路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202443728U (zh) * 2012-03-05 2012-09-19 京东方科技集团股份有限公司 移位寄存器、栅极驱动器及显示装置
CN103578433B (zh) * 2012-07-24 2015-10-07 北京京东方光电科技有限公司 一种栅极驱动电路、方法及液晶显示器
KR102034060B1 (ko) * 2013-06-21 2019-10-18 엘지디스플레이 주식회사 쉬프트 레지스터
CN104157259B (zh) * 2014-09-10 2016-06-22 深圳市华星光电技术有限公司 基于igzo制程的栅极驱动电路
CN104517564B (zh) * 2015-01-04 2017-10-27 京东方科技集团股份有限公司 阵列基板和显示装置
CN105185292B (zh) * 2015-10-09 2017-11-07 昆山龙腾光电有限公司 栅极驱动电路及显示装置
CN105355175B (zh) 2015-11-24 2018-06-22 深圳市华星光电技术有限公司 液晶驱动电路与栅极驱动面板
CN105575349B (zh) * 2015-12-23 2018-03-06 武汉华星光电技术有限公司 Goa电路及液晶显示装置
CN105390115B (zh) * 2015-12-24 2018-10-16 深圳市华星光电技术有限公司 液晶显示设备及goa电路
US9972261B2 (en) 2015-12-24 2018-05-15 Shenzhen China Star Optoelectronics Technology Co. Ltd. Liquid crystal display device and GOA circuit
CN105469766B (zh) * 2016-01-04 2019-04-30 武汉华星光电技术有限公司 Goa电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1457059A (zh) * 2002-05-10 2003-11-19 阿尔卑斯电气株式会社 移位寄存器装置及显示装置
US20070035505A1 (en) * 2005-08-11 2007-02-15 Au Optronics Corp. Shift register circuit
US20110150169A1 (en) * 2009-12-22 2011-06-23 Au Optronics Corp. Shift register
CN104517575A (zh) * 2014-12-15 2015-04-15 深圳市华星光电技术有限公司 移位寄存器及级传栅极驱动电路
CN104517577A (zh) * 2014-12-30 2015-04-15 深圳市华星光电技术有限公司 液晶显示装置及其栅极驱动器
CN106128397A (zh) * 2016-08-31 2016-11-16 深圳市华星光电技术有限公司 一种goa驱动单元及驱动电路

Also Published As

Publication number Publication date
CN106128397B (zh) 2019-03-15
US20180330687A1 (en) 2018-11-15
CN106128397A (zh) 2016-11-16
US10192505B2 (en) 2019-01-29

Similar Documents

Publication Publication Date Title
WO2018040321A1 (zh) 一种goa驱动单元及驱动电路
WO2018040322A1 (zh) 一种goa驱动单元及驱动电路
US11361693B2 (en) Shift register unit, gate driving circuit, display device, and driving method
US10685616B2 (en) Shift register circuit, method for driving the same, gate drive circuit, and display panel
US11081058B2 (en) Shift register unit, gate drive circuit, display device and driving method
US11087855B2 (en) Shift register unit and driving method, gate drive circuit and display device
US11127478B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display device
US10235958B2 (en) Gate driving circuits and liquid crystal devices
KR101944641B1 (ko) Igzo 프로세스 기반인 게이트 전극 구동회로
US9472155B2 (en) Gate driver circuit basing on IGZO process
WO2019091168A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
WO2020010852A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
US10121442B2 (en) Driving methods and driving devices of gate driver on array (GOA) circuit
WO2018233306A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2018014381A1 (zh) Goa电路及液晶显示器
GB2548760A (en) GOA circuit and liquid crystal display device
WO2010146738A1 (ja) シフトレジスタおよび表示装置
US10580375B2 (en) Gate drive circuit
US20190019471A1 (en) Gate driver on array circuit and liquid crystal display
WO2017107294A1 (zh) Goa电路及液晶显示装置
US10535414B2 (en) Shift register element, method for driving the same, and display device
WO2016150103A1 (zh) 一种移位寄存器单元、栅极驱动电路及显示装置
US20180040273A1 (en) Shift register unit, driving method, gate driving circuit and display apparatus
WO2019075792A1 (zh) 一种goa电路及液晶面板、显示装置
CN110890077A (zh) 一种goa电路及液晶显示面板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15324700

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16914883

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16914883

Country of ref document: EP

Kind code of ref document: A1