WO2018040322A1 - 一种goa驱动单元及驱动电路 - Google Patents

一种goa驱动单元及驱动电路 Download PDF

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Publication number
WO2018040322A1
WO2018040322A1 PCT/CN2016/107603 CN2016107603W WO2018040322A1 WO 2018040322 A1 WO2018040322 A1 WO 2018040322A1 CN 2016107603 W CN2016107603 W CN 2016107603W WO 2018040322 A1 WO2018040322 A1 WO 2018040322A1
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Prior art keywords
pull
down transistor
transistor
unit
coupled
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PCT/CN2016/107603
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English (en)
French (fr)
Inventor
曾勉
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深圳市华星光电技术有限公司
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Priority to US15/324,698 priority Critical patent/US10388237B2/en
Publication of WO2018040322A1 publication Critical patent/WO2018040322A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the invention belongs to the field of liquid crystal display, and in particular relates to a GOA driving unit and a driving circuit.
  • the driving circuit of the conventional liquid crystal display is generally in the form of an externally mounted integrated circuit module, such as a commonly used TAB (Tape Automated Bonding) package structure.
  • TAB Tunnel Automated Bonding
  • LTPS low temperature polysilicon
  • integrated circuit technology based on panel periphery has gradually become the focus of research.
  • Typical applications are array substrate rows. Drive Technology (GOA, Gate Driver On Array).
  • the GOA driving circuit uses a liquid crystal display Array process to fabricate a gate scan driving signal circuit on the array substrate to realize progressive driving scanning of the pixel unit.
  • the GOA drive circuit can not only reduce the welding process of external integrated circuits, improve integration, but also increase production capacity and reduce production costs. It is the first choice for small and medium-sized liquid crystal display products (such as mobile phones, PDAs, etc.). In addition, as the mobile phone intelligentization process is accelerating, the touch technology of small and medium-sized liquid crystal display devices also needs corresponding technical support, so more requirements are put on the drive circuit.
  • the existing GOA driving circuit has the following problems.
  • the parameters of the transistor have great dispersibility, and the performance of the transistor may be affected after long-term operation, the parameter is changed, so that the voltage of some key circuit nodes in the driving circuit is made. Changes will occur, causing failures in the timing and function of the design in severe cases, which in turn leads to failure of the entire GOA drive circuit.
  • the GOA driver circuit process due to the large number of circuit stages and the large number of transistors, faults such as short circuit or open circuit are prone to occur, and since the repair is difficult, such a situation will cause the liquid crystal panel to become a secondary Product, seriously affecting the yield of LCD panel output.
  • One of the technical problems to be solved by the present invention is to provide an improved GOA driving circuit for stabilizing the voltage of critical circuit nodes and preventing failure due to parameter variations of components.
  • an embodiment of the present application first provides a GOA driving unit, including a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down maintaining unit, and a bootstrap capacitor, wherein the pull-down maintaining unit A mirror circuit structure including a source and a drain connected via a bridge transistor; the mirror circuit structure including a first pull-down transistor and a second pull-down transistor for maintaining a low voltage of a control signal input terminal of the pull-up unit, a third pull-down transistor and a fourth pull-down transistor for maintaining a low voltage of a row scan signal output terminal of the pull-up unit, and a fifth for maintaining a low voltage of the first pull-down transistor and the third pull-down transistor gate a pull-down transistor and a sixth pull-down transistor for maintaining a low voltage of the second pull-down transistor and the fourth pull-down transistor gate; wherein a drain of the fifth pull-down transistor and the first pull-down transistor and the third pull-down transistor a gate
  • the sources of the fifth pull-down transistor and the sixth pull-down transistor are coupled to the second pull-down voltage, and the second pull-down voltage is less than the first pull-down voltage.
  • the drains of the first pull-down transistor and the second pull-down transistor are commonly coupled to a control signal input end of the pull-up unit, and the drains of the third pull-down transistor and the fourth pull-down transistor are commonly coupled And a line scan signal output end of the pull-up unit.
  • the image circuit structure further comprises a mirrored first alternating control circuit and a second alternating control circuit, the first alternating control circuit comprising a seventh transistor having a gate and a drain coupled together for Receiving a first alternating control signal; an eighth transistor having a gate and a drain coupled to a source and a drain of the seventh transistor, respectively; a ninth transistor having a drain and a source and the eighth transistor, respectively a drain and a source are coupled, a gate thereof for receiving a second alternate control signal, a tenth transistor having a drain coupled to a gate of the eighth transistor, a gate and a source thereof respectively a gate and a source of the fifth pull-down transistor are coupled; the second alternate control circuit has a structure mirrored with the first alternate control circuit, and the first alternate control signal and the input end of the second alternate control signal are mutually The first alternating control signal and the second alternating control signal alternate between a high level and a low level.
  • the frequency of the alternate control signal is less than the frequency of the scan clock signal of the GOA drive unit.
  • the method further includes a downlink transmission unit, the downlink transmission unit includes a downlink transistor, a gate of the downlink transistor is coupled to a control signal input end of the pull-up unit, and a drain thereof and a clock of the pull-up unit The signal input end is coupled, and the source generates a downlink signal that acts on the GOA driving unit of the subsequent stage.
  • the downlink transmission unit includes a downlink transistor, a gate of the downlink transistor is coupled to a control signal input end of the pull-up unit, and a drain thereof and a clock of the pull-up unit The signal input end is coupled, and the source generates a downlink signal that acts on the GOA driving unit of the subsequent stage.
  • a GOA driving circuit is also provided.
  • the GOA driving circuit formed by cascading the GOA driving units cascades two scanning clock signals of equal frequency and opposite phase to each GOA driving unit.
  • Embodiments of the present application also provide another GOA driving unit, such as the GOA driving unit described above, to remove the bridge transistor.
  • the method further includes a downlink transmission unit, the downlink transmission unit includes a downlink transistor, a gate of the downlink transistor is coupled to a control signal input end of the pull-up unit, and a drain thereof and a clock of the pull-up unit The signal input end is coupled, and the source generates a downlink signal that acts on the GOA driving unit of the subsequent stage.
  • the downlink transmission unit includes a downlink transistor, a gate of the downlink transistor is coupled to a control signal input end of the pull-up unit, and a drain thereof and a clock of the pull-up unit The signal input end is coupled, and the source generates a downlink signal that acts on the GOA driving unit of the subsequent stage.
  • the GOA driving circuit formed by cascading the GOA driving units cascades two scanning clock signals of equal frequency and opposite phase to each GOA driving unit.
  • the voltage of key circuit nodes in the circuit can be reliably stabilized, and the signal output capability of the circuit can be improved. At the same time, it has a certain self-repairing ability. In turn, the GOA panel yield is improved and the display quality of the GOA panel is improved.
  • FIG. 1 is a schematic structural view of a GOA driving unit in the prior art
  • FIG. 2 is a schematic structural diagram of a GOA driving unit according to an embodiment of the invention.
  • FIG. 3 is a schematic diagram of signal waveforms when a GOA driving unit is in operation according to an embodiment of the invention
  • FIG. 4 is a schematic structural diagram of a GOA driving unit according to another embodiment of the present invention.
  • 5a-5b are schematic diagrams showing the circuit structure when the bridge transistor T55 is disconnected and short-circuited;
  • FIG. 6 is a schematic structural diagram of a GOA driving unit according to still another embodiment of the present invention.
  • the existing GOA driving circuit generally includes a plurality of cascaded GOA driving units, and each stage of the GOA driving unit corresponds to driving a horizontal scanning line of one level.
  • 1 is a schematic structural diagram of a GOA driving unit in the prior art. As shown in the figure, the main structure of the GOA driving unit includes a pull-up control unit 110 and a pull-up unit 120. , a pull-down unit 140 and a pull-down holding unit 150, and a bootstrap capacitor 130.
  • the pull-down maintaining unit 150 is a circuit having a mirror structure.
  • the GOA driving unit of the present invention is based on the above basic structure. The improvement makes the drive unit self-repairing, which will be described in detail below in conjunction with specific embodiments.
  • the Nth stage GOA driving unit controls charging of the Nth horizontal scanning line G(N) of the display area, including pull-up control.
  • the pull-up control unit 210 is mainly used to control the turn-on time of the pull-up unit 220 to implement progressive scan of the liquid crystal panel.
  • the pull-up control unit 210 may be constituted by a pull-up control transistor T11.
  • the gate of the pull-up control transistor T11 receives an ST(N-1) signal which is a down-converted signal generated by the GOA driving unit of the previous stage (N-1th stage).
  • the output signal of the upper stage is generally used, that is, the line scan signal G (N-1) to start the driving unit of the next stage, the drain and the gate of the pull-up control transistor T11 are coupled together, and receive the line scan signal outputted by the GOA driving unit of the previous stage, and the source is generated on the source.
  • T11 is equivalent to one diode, that is, the gate-source voltage Vgs of T11 is 0, and there is a large leakage current inside T11.
  • the downlink unit 260 is added. As shown in FIG. 2, the downlink unit 260 is mainly composed of a down transistor T22. The gate and the drain of the down transistor T22 are both connected to the pull-up unit 220. The gate of the T22 is coupled to the control signal input terminal of the pull-up unit 220, and the clock signal of the drain of the T22 and the pull-up unit 220. The input terminal is coupled, and the source of T22 generates and outputs a downlink signal ST(N) for the gate of the pull-up control transistor T11 of the GOA driving unit of the subsequent stage (N+1th stage).
  • the drain and source of T11 are connected to the N-1th horizontal scanning line G(N-1) and the Nth order Q(N) point, respectively. Since the low potential of the down signal ST(N-1) is the low level of the clock signal CK (or XCK), it is generally -8V. The low potential of the row scan signal G(N-1) is VSS, which is generally -6V, that is, the gate-source voltage Vgs ⁇ 0 of T11. Therefore, by increasing the down-transfer unit 260, the leakage of the Q-point at the present level during holding can be reduced.
  • the pull-up control unit 210 generates a scan control signal Q(N) by the down signal ST(N-1) and the line scan output signal G(N-1) generated by the upper stage drive unit.
  • the scan control signal Q(N) is responsible for the correct operation timing of the entire GOA drive unit.
  • Q(N) is a high level, which can be used to turn on the pull-up unit 220 to output a line scan signal.
  • the Nth stage is in the non-row scanning state, it is necessary to ensure that Q(N) is a reliable low level, so that the pull-up unit 220 does not output. Therefore, in the design of the GOA driving unit and the driving circuit, it is necessary to ensure that the timing of Q(N) is correct.
  • the pull-up unit 220 is mainly responsible for outputting a scan clock signal (Clock) as a row scan signal of the gate.
  • the pull-up unit 220 may be constituted by a pull-up transistor T21.
  • the gate of the pull-up transistor T21 receives the scan control signal Q(N) generated by the pull-up control unit 210 as a control signal input terminal of the pull-up unit 220, and the drain of the T21 receives the scan as the clock signal input terminal of the pull-up unit 220.
  • the source of the clock signal XCK, T21 serves as a line scan signal output terminal of the pull-up unit 220, and is connected to the Nth horizontal scanning line G(N) to generate and output a line scan signal G(N).
  • 230 in FIG. 2 is a bootstrap capacitor, and the function of the bootstrap capacitor is to store the voltage of the gate terminal of the pull-up transistor T21 when Q(N) is high, and to output a high level when G(N) is output.
  • the bootstrap capacitor can second raise the potential of the gate of the pull-up transistor T21 to ensure that the pull-up transistor T21 reliably turns on and outputs the line scan signal. After completing the scan timing of this line, G(N) outputs a low level and maintains this low level while other lines are being scanned.
  • the pull-down unit 240 is configured to pull down the source potential and the gate potential of the pull-up transistor T21 at the first time. To be low, the line scan signal G(N) is turned off. As shown in FIG. 2, the pull-down unit 240 includes a pull-down transistor T31 and a pull-down transistor T41. Wherein, T31 is used to pull down the potential of the line scan signal G(N), and the drain of T31 is coupled to the line scan signal output end of the pull-up unit 220, that is, to the horizontal scan line of the Nth line. T41 is used to pull down the scan control signal Q(N) to turn off the pull-up transistor T21. The drain of T41 is coupled to the control signal input terminal of pull-up unit 220.
  • the gates of T31 and T41 are coupled together and connected to the horizontal scanning line G(N+1) of the N+1th row, that is, the row scanning signal G(N+1) of the GOA driving unit of the subsequent stage is received.
  • the line scan signal is controlled by the effective line scan signal of the next line to realize the progressive scan.
  • the sources of T31 and T41 are commonly coupled to a DC low level VSS.
  • the pull-down sustaining unit is used. 250 holds G(N) and Q(N) in a closed state (ie, a negative potential).
  • the mirror circuit structure in the pull-down maintaining unit 250 is connected by a bridge transistor T55.
  • the source (or the drain) of the T55 and the mirror circuit structure on the left are coupled to the P(N) point
  • the drain (or source) of the T55 and the mirror circuit structure on the right are coupled to the K(N) point.
  • the left and right circuit structures are mirror symmetrical with respect to T55.
  • the gate of T55 is connected to the control signal input terminal of the pull-up unit 220, that is, controlled by the scan control signal Q(N).
  • the left and right mirror circuit structures work alternately, which can effectively reduce the time when the transistor is in the action of the DC signal, thereby reducing the influence of DC stress, avoiding the transistor failure caused by DC stress, and improving the entire GOA drive unit (GOA drive) Circuit) reliability.
  • GOA drive GOA drive
  • the image circuit structure includes a first pull-down transistor T42 and a second pull-down transistor T43.
  • the gate of T42 is coupled to the source (or drain) of T55
  • the gate of T43 is coupled to the drain (or source) of T55
  • the drains of T42 and T43 are commonly coupled to the control of pull-up unit 220.
  • the signal input terminal is used to maintain the off-state voltage of the control signal input terminal of the pull-up unit 220.
  • the mirror circuit structure further includes a third pull-down transistor T32 and a fourth pull-down transistor T33.
  • the gate of T32 is coupled to the source (or drain) of T55
  • the gate of T33 is coupled to the drain (or source) of T55.
  • the drains of the T34 and T33 are commonly coupled to the row scan signal output terminal of the pull-up unit 220 for maintaining the off-state voltage of the row scan signal output terminal of the pull-up unit 220.
  • the image circuit structure includes a fifth pull-down transistor T56 for maintaining the gate-off voltages of the first pull-down transistor T42 and the third pull-down transistor T32, and for maintaining the second pull-down transistor T43 and The fourth pull-down transistor T66 of the fourth pull-down transistor T33 is off-state voltage.
  • the drain of the fifth pull-down transistor T56 is coupled to the gates of the first pull-down transistor T42 and the third pull-down transistor T32, and the drain of the sixth pull-down transistor T66 and the second pull-down transistor T43 and the fourth pull-down transistor
  • the gate of the body tube T33 is coupled, and the gates of T56 and T66 are commonly coupled to the control signal input terminal of the pull-up unit 220, that is, controlled by the scan control signal Q(N).
  • the sources of the pull-down transistors are all coupled to a first pull-down voltage, that is, a DC low voltage VSS.
  • the first alternate control circuit includes a transistor T51 whose gate and drain are coupled together for receiving the first alternate control signal LC1.
  • the transistor T53 has its gate and drain coupled to the source and drain of the transistor T51, respectively.
  • the transistor T54 has its drain and source coupled to the drain and source of the transistor T53, respectively, and its gate for receiving the second alternate control signal LC2.
  • the transistor T52 has a drain coupled to the gate of the transistor T53, and a gate and a source coupled to the gate and source of the pull-down transistor T56, respectively.
  • the second alternate control circuit has a structure mirrored with the first alternate control circuit and will not be described again. And its first alternate control signal is interchanged with the input of the second alternate control signal, as shown in FIG.
  • the first alternate control signal LC1 and the second alternate control signal LC2 are alternately at a high level and a low level to control the alternate operation of the mirror circuit structure. The above operation will be described below in conjunction with the operational timing diagram of FIG.
  • FIG. 3 shows the signal waveforms of the Nth-level driving unit.
  • a plurality of scanning clock signals are generally used in combination. drive.
  • the embodiment in FIG. 3 is described by taking two scan clock signals CK and XCK as an example.
  • CK and XCK are equal in frequency and opposite in phase, and are interlaced to the clock signal input terminal of the pull-up unit 220 of each GOA driving unit.
  • the clock signal CK is not shown in FIG. 2, and CK is connected to the N-1th stage driving unit.
  • the STV is a line scan trigger signal of the GOA driver circuit and acts on the first stage drive unit of the GOA driver circuit.
  • the N-1th stage driving unit outputs a valid line scan signal G(N-1) and a down signal ST(N-1), and the Nth stage driving unit is pulled up.
  • the control transistor T11 is turned on, and the scan control signal Q(N) reaches a first voltage value, which can turn on the pull-up transistor T21 and the down-transfer transistor T22 of the N-th stage driving unit.
  • the line scan signal G(N) and the down signal ST(N) simultaneously output a high level of XCK, and perform line scan on the pixel of the Nth line.
  • the pull-up control transistor of the (N+1)th driving unit receives the high level of G(N) and ST(N), and when the row scanning signal G(N+1) of the next row is high level, the Nth The pull-down transistors T31 and T41 of the stage drive unit are turned on, thereby pulling G(N) and Q(N) low to turn off the scanning of the pixels of the Nth row.
  • G(N+1) returns to the low level, the low levels of G(N) and Q(N) are maintained by the pull-down maintaining unit 250.
  • the pull-down maintaining unit 250 does not turn on any pull-down transistors (T42, T43, T32, and T33) when Q(N) is high to ensure normal scanning of the driving unit. After Q(N) is low, the mirror circuit structure on the startup side maintains the low level of G(N) and Q(N).
  • the pull-down maintaining unit 150 in the prior art causes LC1 to be at a high level and LC2 to be at a low level.
  • T52 and T62 are turned on.
  • the voltage of the gate of T53 ie, the source of T51
  • T51 is turned on.
  • the gate voltage of T53 is adjusted to T51.
  • the on-resistance of T52 is at a voltage difference of LC1-VSS.
  • the gate voltage of T53 will rise and it may rise to turn T53 on.
  • T64 is turned on, and after being turned on, the potential at the K(N) point is pulled down, so T55 is turned on.
  • the potentials of P(N) and K(N) are the on-resistances of the three transistors of T53, T55 and T64 at a voltage difference of LC1-LC2, and P (N)
  • the point potential is higher than the K (N) point potential. Therefore, the potentials of P(N) and K(N) are not necessarily at the optimal off-state voltages of T42, T32 and T43, T33, which may cause large leakage currents of T42, T32 or T43, T33.
  • T42 and T32 it is possible to cause T42 and T32 to be turned on, so that the holding (Holding) ability of Q(N) is insufficient, thereby affecting the output signal.
  • the transmission of signals such as 1 pass 3 or 1 pass 4 is designed, which requires the Q (N) point to be maintained for 3 to 4 lines. State, the requirements for its holding ability are higher.
  • the pull-down maintaining unit 250 in the embodiment of the present invention solves the above problem.
  • T56 and T66 are also turned on at the same time, wherein P(N) point is turned on after T56 is turned on.
  • the potential is pulled low to low voltage, and the potential of K(N) is pulled down to low voltage after T66 is turned on, so that T42 and T43 and T32 and T33 can be reliably turned off to ensure output and improve Q(N).
  • the ability to hold the point As shown in FIG. 2, when Q(N) is high level, T56 and T66 are also turned on at the same time, wherein P(N) point is turned on after T56 is turned on. The potential is pulled low to low voltage, and the potential of K(N) is pulled down to low voltage after T66 is turned on, so that T42 and T43 and T32 and T33 can be reliably turned off to ensure output and improve Q(N). ) The ability to hold the point.
  • the P(N) point and the K(N) point are pulled down to the same low potential, so the pull-down potential can be designed as the optimal off-state voltage of T42, T32, and T43, T33. It can minimize its leakage current and ensure its potential holding ability at Q(N) point.
  • the sources of pull-down transistors T56 and T66 can be coupled to a second pull-down voltage that is different from the first pull-down voltage, as shown in FIG. Among them, T42 and T43 and T32 and T33 are still coupled to the original first pull-down voltage (indicated by VSS1 in Figure 4), T52 and T62 and T56 and T66 is coupled to the second pull-down voltage VSS2. By adjusting the signal voltage value of VSS2, the potentials of P(N) and K(N) are pulled to the lower level.
  • the liquid crystal panel designed and manufactured does not pass the reliability verification requirements due to process variation, etc., it can be redesigned by re-adjusting the voltage values of VSS1 and VSS2, that is, the liquid crystal panel can be adjusted only by adjusting on the PCB board.
  • the test requirements are met without the need to redesign the GOA circuit. Therefore, the present embodiment can increase the degree of design freedom and increase the self-adjusting capability of the GOA circuit to a greater extent.
  • the GOA driving unit of the embodiment of the invention has strong self-repairing capability, and specifically, when the bridge transistor T55 is disconnected or short-circuited, the driving unit can still work normally to complete the design function, which is performed in conjunction with FIG. 5a and FIG. 5b. Description.
  • FIG. 5a is a schematic diagram of the circuit structure when the bridge transistor T55 is disconnected. As shown in the figure, LC1 is made high and LC2 is low. When Q(N) is high, T52 and T62 and T56 and T66 are simultaneously turned on. T56 and T66 can pull the P(N) and K(N) points low, respectively, so that T42 and T43 and T32 and T33 are both off, ensuring the normal output of the drive unit. When Q(N) is low, T52 and T62 and T56 and T66 are simultaneously turned off. Because T51 is turned on, the potential of the gate of T53 is gradually increased. When the potential rises to the turn-on voltage of T53, T53 is turned on.
  • T42 and T32 are turned on, and T42 and T32 are turned on to pull down the high voltage of the scanning control signal Q(N) point and the line scanning signal G(N) point. value.
  • the circuit shown in FIG. 5a can perform the circuit function of the original embodiment, and thus the circuit shown in FIG. 5a can be directly applied as an embodiment to solve the problem that the voltage of the critical circuit node in the GOA driving circuit is unstable. It is easy to understand that the DC low voltages VSS1 and VSS2 can also be combined into one voltage VSS, which simplifies wiring, although a certain degree of design freedom is sacrificed.
  • FIG. 5b is a schematic diagram of the circuit structure when the bridge transistor T55 is short-circuited.
  • the broken line in the figure indicates that a short circuit occurs in T55, and P(N) and K(N) are equivalent to being connected together, which is used in FIG. 5a.
  • the analysis process is known (not to be described again).
  • the image circuit structure can still complete the design function and exhibit a certain self-repairing capability.
  • the left and right mirror circuit structures work at the same time, that is, they no longer have the ability to work alternately.
  • the GOA driving unit of the embodiment of the present invention can optimize the circuit structure of the GOA driving unit by It is reliable enough to stabilize the voltage of key circuit nodes in the circuit and improve the signal output capability of the circuit. At the same time, it has a certain self-repairing ability. In turn, the GOA panel yield is improved and the display quality of the GOA panel is improved.

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Abstract

公开了一种GOA驱动单元及驱动电路，该GOA驱动单元包括第一下拉晶体管（T42）、第二下拉晶体管（T43）、第三下拉晶体管（T32）和第四下拉晶体管（T33），用于维持第一下拉晶体管（T42）和第三下拉晶体管（T32）栅极低电压的第五下拉晶体管（T56）和用于维持第二下拉晶体管（T43）和第四下拉晶体管（T33）栅极低电压的第六下拉晶体管（T66）。该驱动单元能够可靠地稳定电路中关键电路节点的电压。

Description

一种GOA驱动单元及驱动电路
相关申请的交叉引用
本申请要求享有2016年08月31日提交的名称为“一种GOA驱动单元及驱动电路”的中国专利申请CN201610793464.1的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明属于液晶显示领域，尤其涉及一种GOA驱动单元及驱动电路。
背景技术
传统的液晶显示器的驱动电路一般为外部搭载的集成电路模组的形式，如普遍采用的TAB(Tape Automated Bonding)封装结构。而随着具有超高载流子迁移率特性的低温多晶硅(LTPS，Low Temperature Poly silicon)半导体薄膜晶体管的发展，基于面板周边的集成电路技术逐渐成为研究的焦点，其中典型的应用是阵列基板行驱动技术(GOA，Gate Driver On Array)。
GOA驱动电路是利用液晶显示器Array制程将行(Gate)扫描驱动信号电路制作在阵列基板上来实现对像素单元的逐行驱动扫描。GOA驱动电路不仅能够减少外接集成电路的焊接工序，提高集成度，还可以提升产能降低生产成本，是中小尺寸液晶显示产品(例如手机，PDA等)的首选。另外，随着手机智能化进程日益加快，中小尺寸液晶显示设备的触控技术也需要得到相应的技术支持，因此对驱动电路提出了更多要求。
现有的GOA驱动电路存在如下问题，一方面，由于晶体管的参数具有很大的分散性，且长期工作后其性能有可能受到影响进一步使其参数改变，使得驱动电路中一些关键电路节点的电压会发生变化，严重时引发设计的时序和功能的失效，进而导致整个GOA驱动电路的失效。另一方面，在GOA驱动电路制程中，由于电路级数多，晶体管数量巨大等原因，容易发生短路或断路等故障，而由于修复难度较高，因此一旦出现这种情况将导致液晶面板成为次品，严重影响液晶面板产出的良率。
发明内容
本发明所要解决的技术问题之一是需要提供一种改进的GOA驱动电路以稳定关键电路节点的电压，防止因元件的参数变化而导致的失效。
为了解决上述技术问题，本申请的实施例首先提供了一种GOA驱动单元，包括上拉单元、上拉控制单元、下拉单元、下拉维持单元及自举电容，其特征在于，所述下拉维持单元包括经由桥接晶体管的源极和漏极相连接的镜像电路结构；所述镜像电路结构包括用于维持所述上拉单元的控制信号输入端低电压的第一下拉晶体管和第二下拉晶体管，用于维持所述上拉单元的行扫描信号输出端低电压的第三下拉晶体管和第四下拉晶体管，以及用于维持所述第一下拉晶体管和第三下拉晶体管栅极低电压的第五下拉晶体管和用于维持所述第二下拉晶体管和第四下拉晶体管栅极低电压的第六下拉晶体管；其中，第五下拉晶体管的漏极与所述第一下拉晶体管和第三下拉晶体管的栅极耦接，第六下拉晶体管的漏极与所述第二下拉晶体管和第四下拉晶体管的栅极耦接，所述第五下拉晶体管和第六下拉晶体管的栅极共同耦接于所述上拉单元的控制信号输入端；各下拉晶体管的源极均耦接于第一下拉电压。
优选地，所述第五下拉晶体管和第六下拉晶体管的源极耦接于第二下拉电压，且所述第二下拉电压小于所述第一下拉电压。
优选地，所述第一下拉晶体管和第二下拉晶体管的漏极共同耦接于所述上拉单元的控制信号输入端，所述第三下拉晶体管和第四下拉晶体管的漏极共同耦接于所述上拉单元的行扫描信号输出端。
优选地，所述镜像电路结构还包括镜像的第一交替控制电路和第二交替控制电路，所述第一交替控制电路包括，第七晶体管，其栅极和漏极耦接在一起，用于接收第一交替控制信号；第八晶体管，其栅极和漏极分别与所述第七晶体管的源极和漏极耦接；第九晶体管，其漏极和源极分别与所述第八晶体管的漏极和源极耦接，其栅极用于接收第二交替控制信号；第十晶体管，其漏极与所述第八晶体管的栅极耦接，其栅极和源极分别与所述第五下拉晶体管的栅极和源极耦接；所述第二交替控制电路具有与所述第一交替控制电路镜像的结构，且其第一交替控制信号与第二交替控制信号的输入端互换；所述第一交替控制信号与所述第二交替控制信号交替为高电平和低电平。
优选地，所述交替控制信号的频率小于所述GOA驱动单元的扫描时钟信号的频率。
优选地，还包括下传单元，所述下传单元包括下传晶体管，所述下传晶体管的栅极与上拉单元的控制信号输入端耦接，其漏极与所述上拉单元的时钟信号输入端耦接，其源极生成作用于后一级GOA驱动单元的下传信号。
另一方面，还提供了一种GOA驱动电路，由上述GOA驱动单元级联构成的GOA驱动电路，将频率相等、相位相反的两个扫描时钟信号隔行输入至各GOA驱动单元。
本申请的实施例还提供了另一种GOA驱动单元，如上述GOA驱动单元，去除所述桥接晶体管。
优选地，还包括下传单元，所述下传单元包括下传晶体管，所述下传晶体管的栅极与上拉单元的控制信号输入端耦接，其漏极与所述上拉单元的时钟信号输入端耦接，其源极生成作用于后一级GOA驱动单元的下传信号。
另一方面，还提供了另一种GOA驱动电路，由上述GOA驱动单元级联构成的GOA驱动电路，将频率相等、相位相反的两个扫描时钟信号隔行输入至各GOA驱动单元。
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：
通过优化GOA驱动单元的电路结构，能够可靠地稳定电路中关键电路节点的电压，提高电路的信号输出能力。同时具有一定的自修复能力。进而提高GOA面板良率，改善GOA面板显示品质。
本发明的其他优点、目标，和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书，权利要求书，以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。
图1为现有技术中的GOA驱动单元的结构示意图；
图2为根据本发明一实施例的GOA驱动单元的结构示意图；
图3为根据本发明一实施例的GOA驱动单元工作时的信号波形示意图；
图4为根据本发明另一实施例的GOA驱动单元的结构示意图；
图5a-图5b分别为当桥接晶体管T55发生断路和发生短路时的电路结构示意图；
图6为根据本发明又一实施例的GOA驱动单元的结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成相应技术效果的实现过程能充分理解并据以实施。本申请实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
现有的GOA驱动电路通常包括级联的多个GOA驱动单元，每一级GOA驱动单元对应驱动一级水平的行扫描线。图1为现有技术中的GOA驱动单元的结构示意图，如图所示，GOA驱动单元的主要结构包括上拉控制单元110(Pull-up control part)，上拉单元120(Pull-up part)，下拉单元140(Key Pull-down Part)和下拉维持单元150(Pull-down Holding Part)，以及自举(Boast)电容130。
其中，下拉维持单元150是具有镜像结构的电路，当晶体管长期处于直流信号作用时，会产生直流应力(DC Stress)，其性能会受到影响，引发晶体管的失效，镜像电路能够降低直流信号作用所导致的直流应力的影响。但该镜像电路中的关键电路节点(P(N)和K(N))存在电压不稳定的问题(后面详述)，有可能导致电路的失效，本发明的GOA驱动单元基于上述基本结构进行改进，使驱动单元具有自修复能力，下面结合具体的实施例详细说明。
图2为根据本发明一实施例的GOA驱动单元的结构示意图，如图所示，该第N级GOA驱动单元控制对显示区域的第N行水平扫描线G(N)充电，包括上拉控制单元210，上拉单元220，自举电容230，下拉单元240，下拉维持单元250以及下传单元260。
具体的，上拉控制单元210主要用于控制上拉单元220的开启时间，实现液晶面板的逐行扫描。上拉控制单元210可以由上拉控制晶体管T11构成。从图2中可以看出，该上拉控制晶体管T11的栅极接收ST(N-1)信号，该信号为来自上一级(第N-1级)的GOA驱动单元产生的下传信号。
现有技术中(如图1所示)，一般采用上一级的输出信号，即行扫描信号G (N-1)来启动下一级的驱动单元，上拉控制晶体管T11的漏极和栅极耦接在一起，接收前一级GOA驱动单元输出的行扫描信号，其源极生成作用于上拉单元的控制信号输入端的扫描控制信号。则此时T11相当于一个二极管，即T11的栅源电压Vgs＝0，在T11内部会存在较大的漏电流。
在本发明的实施例中，增加了下传单元260。如图2所示，下传单元260主要由下传晶体管T22构成。该下传晶体管T22的栅极和漏极均与上拉单元220相连接，其中T22的栅极与上拉单元220的控制信号输入端耦接，T22的漏极与上拉单元220的时钟信号输入端耦接，T22的源极生成并输出下传信号ST(N)，作用于后一级(第N+1级)GOA驱动单元的上拉控制晶体管T11的栅极。T11的漏极和源极分别连接第N-1级水平扫描线G(N-1)和第N级的Q(N)点。由于下传信号ST(N-1)的低电位为时钟信号CK(或XCK)的低电平，一般为-8V。行扫描信号G(N-1)的低电位则为VSS，一般为-6V，即T11的栅源电压Vgs<0，因此通过增加下传单元260可以减少本级Q点在holding时的漏电。
上拉控制单元210在上一级驱动单元产生的下传信号ST(N-1)和行扫描输出信号G(N-1)的作用下，生成扫描控制信号Q(N)。扫描控制信号Q(N)负责整个GOA驱动单元的正确工作时序。当行扫描进行到第N级时，Q(N)为高电平，可用于开启上拉单元220输出行扫描信号。当第N级处于非行扫描状态时，需要保证Q(N)为可靠的低电平，使上拉单元220不输出。因此，在GOA驱动单元以及驱动电路的设计中，必须保证Q(N)的时序正确。
上拉单元220主要负责将扫描时钟信号(Clock)输出为栅极的行扫描信号。如图2所示，上拉单元220可以由上拉晶体管T21构成。上拉晶体管T21的栅极作为上拉单元220的控制信号输入端接收由上拉控制单元210生成的扫描控制信号Q(N)，T21的漏极作为上拉单元220的时钟信号输入端接收扫描时钟信号XCK，T21的源极作为上拉单元220的行扫描信号输出端，连接第N行水平扫描线G(N)，生成并输出行扫描信号G(N)。
另外，图2中的230为自举电容，该自举电容的作用是在Q(N)为高电平时，存储上拉晶体管T21栅源端的电压，当G(N)输出高电平的行扫描信号后，自举电容可以二次抬升上拉晶体管T21的栅极的电位，以保证上拉晶体管T21可靠地开启与输出行扫描信号。在完成本行的扫描时序后，G(N)输出低电平，并在其他行进行扫描的时候一直维持这个低电平。
下拉单元240用于在第一时间将上拉晶体管T21的源极电位和栅极电位拉低 为低电位，即关闭行扫描信号G(N)。如图2所示，下拉单元240包括下拉晶体管T31和下拉晶体管T41。其中，T31用于下拉行扫描信号G(N)的电位，T31的漏极与上拉单元220的行扫描信号输出端耦接，即作用于第N行水平扫描线。T41用于下拉扫描控制信号Q(N)，以便关闭上拉晶体管T21。T41的漏极与上拉单元220的控制信号输入端耦接。T31与T41的栅极耦接在一起，并与第N+1行的水平扫描线G(N+1)相连接，即接收接后一级GOA驱动单元的行扫描信号G(N+1)，由下一行的有效的行扫描信号控制本行行扫描信号的关闭，实现逐行扫描。T31与T41的源极共同耦接于直流低电平VSS。
当后一级的行扫描信号G(N+1)回到低电平后，将不能维持G(N)和Q(N)的低电平，因此，在GOA驱动单元中，采用下拉维持单元250将G(N)和Q(N)维持(Holding)在关闭状态(即负电位)。
如图2所示，下拉维持单元250中的镜像电路结构由桥接晶体管T55连接。具体的，T55的源极(或漏极)与左边的镜像电路结构耦接于P(N)点，T55的漏极(或源极)与右边的镜像电路结构耦接于K(N)点。左右电路结构相对于T55镜像对称。T55的栅极接于上拉单元220的控制信号输入端，即由扫描控制信号Q(N)控制。工作时，左右的镜像电路结构交替工作，能够有效减少晶体管处于直流信号作用时的时间，进而降低直流应力的影响，避免由于直流应力所导致的晶体管的失效，提高了整个GOA驱动单元(GOA驱动电路)的可靠性。
如图2所示，镜像电路结构包括第一下拉晶体管T42和第二下拉晶体管T43。T42的栅极与T55的源极(或漏极)耦接，T43的栅极与T55的漏极(或源极)耦接，T42和T43的漏极共同耦接于上拉单元220的控制信号输入端，用于维持上拉单元220的控制信号输入端的关态电压。镜像电路结构还包括第三下拉晶体管T32和第四下拉晶体管T33，T32的栅极与T55的源极(或漏极)耦接，T33的栅极与T55的漏极(或源极)耦接，T32和T33的漏极共同耦接于上拉单元220的行扫描信号输出端，用于维持上拉单元220的行扫描信号输出端的关态电压。
进一步地，如图2所示，镜像电路结构包括用于维持第一下拉晶体管T42和第三下拉晶体管T32栅极关态电压的第五下拉晶体管T56，以及用于维持第二下拉晶体管T43和第四下拉晶体管T33栅极关态电压的第六下拉晶体管T66。其中，第五下拉晶体管T56的漏极与第一下拉晶体管T42和第三下拉晶体管T32的栅极耦接，第六下拉晶体管T66的漏极与第二下拉晶体管T43和第四下拉晶 体管T33的栅极耦接，T56和T66的栅极共同耦接于上拉单元220的控制信号输入端，即由扫描控制信号Q(N)控制。各下拉晶体管的源极均耦接于第一下拉电压，即直流低电压VSS。
协调两个镜像电路结构交替工作由第一交替控制电路和第二交替控制电路完成。如图2所示，第一交替控制电路包括，晶体管T51，其栅极和漏极耦接在一起，用于接收第一交替控制信号LC1。晶体管T53，其栅极和漏极分别与晶体管T51的源极和漏极耦接。晶体管T54，其漏极和源极分别与晶体管T53的漏极和源极耦接，其栅极用于接收第二交替控制信号LC2。晶体管T52，其漏极与晶体管T53的栅极耦接，其栅极和源极分别与下拉晶体管T56的栅极和源极耦接。
第二交替控制电路具有与第一交替控制电路镜像的结构，不再赘述。且其第一交替控制信号与第二交替控制信号的输入端互换，如图2所示。
第一交替控制信号LC1与第二交替控制信号LC2交替为高电平和低电平以控制镜像电路结构的交替工作，下面结合图2的工作时序图说明上述工作过程。
图3给出了第N级驱动单元的各信号波形图，当将多级驱动单元级联构成GOA驱动电路时，为了减轻GOA驱动电路的负载，提高驱动能力，一般采用多个扫描时钟信号联合驱动。图3中的实施例以两个扫描时钟信号CK和XCK为例进行说明，CK和XCK频率相等、相位相反，隔行输入至各GOA驱动单元的上拉单元220的时钟信号输入端。需要注意的是，在图2中未示出时钟信号CK，CK连接于第N-1级驱动单元。
STV是GOA驱动电路的行扫描触发信号，作用于GOA驱动电路的第1级驱动单元。在某个CK时钟信号的高电平期间，第N-1级驱动单元输出有效的行扫描信号G(N-1)和下传信号ST(N-1)，第N级驱动单元的上拉控制晶体管T11即被开启，扫描控制信号Q(N)达到第一电压值，该第一电压值能够开启第N级驱动单元的上拉晶体管T21和下传晶体管T22。
T21和T22开启后，当XCK时钟信号的高电平到达时，行扫描信号G(N)和下传信号ST(N)同时输出XCK的高电平，在对第N行像素进行行扫描的同时，第N+1级驱动单元的上拉控制晶体管接收到G(N)和ST(N)的高电平，当下一行的行扫描信号G(N+1)为高电平后，第N级驱动单元的下拉晶体管T31和T41被开启，进而将G(N)和Q(N)拉低为低电平，关闭第N行像素的扫描。当G(N+1)回复到低电平后，G(N)和Q(N)的低电平由下拉维持单元250维持。
下拉维持单元250在Q(N)为高电平时不开启任何下拉晶体管(T42、T43、T32和T33)，以保证驱动单元的正常扫描。在Q(N)为低电平后，启动一侧的镜像电路结构维持G(N)和Q(N)的低电平。
现有技术中的下拉维持单元150如图1所示，使LC1为高电平，LC2为低电平。当Q(N)为高电平时，T52和T62被开启。其中，由于T52被开启，因此拉低T53的栅极(即T51的源极)电压，在LC1高电平的作用下，T51被开启，在T51开启后，T53的栅极电压被调整为T51和T52的导通电阻在压差为LC1-VSS的分压值。T53的栅极电压会升高，且有可能升高到使T53开启。
另一侧，在LC1和LC2的作用下，T64开启，开启后拉低K(N)点的电位，因此T55开启。在T53、T55和T64均开启的情况下，P(N)和K(N)的电位为T53、T55和T64三个晶体管的导通电阻在压差为LC1-LC2的分压值，且P(N)点电位高于K(N)点电位。因此P(N)和K(N)的电位不一定均处于T42、T32和T43、T33的最佳关态电压处，从而可能造成T42、T32或者T43、T33的漏电流较大，严重者还有可能导致T42和T32开启，使得Q(N)的维持(Holding)能力不够，从而影响了输出信号。特别是针对于大尺寸面板的GOA驱动电路，为了减轻驱动电路的负载，会设计1传3、或1传4等信号的传输，这就要求Q(N)点维持3～4行时间的开启状态，对其Holding能力要求更高。
本发明实施例中的下拉维持单元250解决了上述问题，如图2所示，当Q(N)为高电平时，T56和T66也同时被开启，其中，T56开启后将P(N)点的电位拉低至低电压，T66开启后将K(N)点的电位拉低至低电压，这样就可以使得T42和T43以及T32和T33均处于可靠的关闭状态以保证输出，提高Q(N)点的Holding能力。此时即使T53在T51和T52的分压下开启了，P(N)点的电位仍然可以在T56的作用下下拉至较低的电位，K(N)点的电位仍然可以在T66的作用下下拉至较低的电位，即P(N)点和K(N)点的电位不再仅由T53、T55和T64的分压决定，本实施例能够显著地增加其GOA驱动电路的可靠性。
在本发明的实施例中，P(N)点和K(N)点被拉低至同一低电位，因此可以将该下拉的电位设计成T42、T32和T43、T33的最佳关态电压，可最大程度上降低其漏电流，保证其Q(N)点的电位Holding能力。
在其他的实施例中，可以将下拉晶体管T56和T66的源极耦接于一不同于第一下拉电压的第二下拉电压，如图4所示。其中，T42和T43以及T32和T33仍耦接于原第一下拉电压(在图4中以VSS1表示)，T52和T62以及T56和 T66耦接于第二下拉电压VSS2。通过调节VSS2的信号电压值，同时将P(N)和K(N)的电位拉至更低位。当设计生产的液晶面板由于制程变异等原因未通过信赖性验证等要求时，可以通过重新调整VSS1以及VSS2的电压值来进行重新设计，即只需通过PCB电路板上的调整即可使液晶面板达到测试要求，而不需要重新设计GOA电路。因此，本实施例能够增加设计自由度，更大程度上增加GOA电路的自调节能力。
本发明实施例的GOA驱动单元具有较强的自修复能力，具体体现在，当桥接晶体管T55发生断路或短路时，驱动单元仍能正常工作以完成设计的功能，下面结合图5a和图5b进行说明。
图5a为当桥接晶体管T55发生断路时的电路结构示意图，如图所示，使LC1为高电平，LC2为低电平。当Q(N)为高电平时，T52和T62以及T56和T66同时被开启。T56和T66可以分别将P(N)点和K(N)点拉低为低电平，使得T42和T43以及T32和T33均处于关闭状态，保证驱动单元的正常输出。当Q(N)为低电平时，T52和T62以及T56和T66同时关闭，由于T51的开启，使得T53的栅极的电位逐渐升高，当该电位升至T53的开启电压后，T53被开启，进而P(N)点的电位被拉升至高电平，T42和T32被开启，T42和T32开启后会拉低扫描控制信号Q(N)点和行扫描信号G(N)点的高电压值。
而另一侧，由于T66关闭，T64仍处于开启状态，因此K(N)点的电压经过调整仍然保持为低电平，即T32和T33仍处于关闭的非工作状态。可以看出，当桥接晶体管T55发生断路时，该实施例的驱动单元仍可以正常工作，即具有自修复能力。
进一步地，如图5a所示的电路能够完成原实施例的电路功能，因此可以将图5a所示的电路直接应用为实施例以解决GOA驱动电路中关键电路节点电压不稳定的问题的。容易理解的是，还可以将直流低电压VSS1和VSS2合并为一个电压VSS，虽然牺牲了一定的设计自由度，但可以简化布线。
图5b为当桥接晶体管T55发生短路时的电路结构示意图，如图所示，图中虚线表示T55发生了短路，P(N)和K(N)相当于连接在一起，利用对图5a所采用的分析过程可知(不再赘述)，本实施例的驱动单元发生短路时镜像电路结构仍然能够完成设计功能，表现出一定的自修复能力。但左右的镜像电路结构同时工作，即不再具备交替工作的能力。
本发明实施例的GOA驱动单元，通过优化GOA驱动单元的电路结构，能 够可靠地稳定电路中关键电路节点的电压，提高电路的信号输出能力。同时具有一定的自修复能力。进而提高GOA面板良率，改善GOA面板显示品质。
虽然本发明所揭露的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (9)

  1. 一种GOA驱动单元，包括上拉单元、上拉控制单元、下拉单元、下拉维持单元及自举电容，其中，
    所述下拉维持单元包括经由桥接晶体管的源极和漏极相连接的镜像电路结构；
    所述镜像电路结构包括用于维持所述上拉单元的控制信号输入端低电压的第一下拉晶体管和第二下拉晶体管，用于维持所述上拉单元的行扫描信号输出端低电压的第三下拉晶体管和第四下拉晶体管，以及用于维持所述第一下拉晶体管和第三下拉晶体管栅极低电压的第五下拉晶体管和用于维持所述第二下拉晶体管和第四下拉晶体管栅极低电压的第六下拉晶体管；
    其中，第五下拉晶体管的漏极与所述第一下拉晶体管和第三下拉晶体管的栅极耦接，第六下拉晶体管的漏极与所述第二下拉晶体管和第四下拉晶体管的栅极耦接，所述第五下拉晶体管和第六下拉晶体管的栅极共同耦接于所述上拉单元的控制信号输入端；
    各下拉晶体管的源极均耦接于第一下拉电压。
  2. 根据权利要求1所述的GOA驱动单元，其中，所述第五下拉晶体管和第六下拉晶体管的源极耦接于第二下拉电压，且所述第二下拉电压小于所述第一下拉电压。
  3. 根据权利要求1所述的GOA驱动单元，其中，所述第一下拉晶体管和第二下拉晶体管的漏极共同耦接于所述上拉单元的控制信号输入端，所述第三下拉晶体管和第四下拉晶体管的漏极共同耦接于所述上拉单元的行扫描信号输出端。
  4. 根据权利要求3所述的GOA驱动单元，其中，所述镜像电路结构还包括镜像的第一交替控制电路和第二交替控制电路，
    所述第一交替控制电路包括，
    第七晶体管，其栅极和漏极耦接在一起，用于接收第一交替控制信号；
    第八晶体管，其栅极和漏极分别与所述第七晶体管的源极和漏极耦接；
    第九晶体管，其漏极和源极分别与所述第八晶体管的漏极和源极耦接，其栅极用于接收第二交替控制信号；
    第十晶体管，其漏极与所述第八晶体管的栅极耦接，其栅极和源极分别与所述第五下拉晶体管的栅极和源极耦接；
    所述第二交替控制电路具有与所述第一交替控制电路镜像的结构，且其第一交替控制信号与第二交替控制信号的输入端互换；
    所述第一交替控制信号与所述第二交替控制信号交替为高电平和低电平。
  5. 根据权利要求4所述的GOA驱动单元，其中，所述交替控制信号的频率小于所述GOA驱动单元的扫描时钟信号的频率。
  6. 根据权利要求1所述的GOA驱动单元，其中，还包括下传单元，所述下传单元包括下传晶体管，所述下传晶体管的栅极与上拉单元的控制信号输入端耦接，其漏极与所述上拉单元的时钟信号输入端耦接，其源极生成作用于后一级GOA驱动单元的下传信号。
  7. 一种由GOA驱动单元级联构成的GOA驱动电路，所述GOA驱动单元包括上拉单元、上拉控制单元、下拉单元、下拉维持单元及自举电容，其中，
    所述下拉维持单元包括经由桥接晶体管的源极和漏极相连接的镜像电路结构；
    所述镜像电路结构包括用于维持所述上拉单元的控制信号输入端低电压的第一下拉晶体管和第二下拉晶体管，用于维持所述上拉单元的行扫描信号输出端低电压的第三下拉晶体管和第四下拉晶体管，以及用于维持所述第一下拉晶体管和第三下拉晶体管栅极低电压的第五下拉晶体管和用于维持所述第二下拉晶体管和第四下拉晶体管栅极低电压的第六下拉晶体管；
    其中，第五下拉晶体管的漏极与所述第一下拉晶体管和第三下拉晶体管的栅极耦接，第六下拉晶体管的漏极与所述第二下拉晶体管和第四下拉晶体管的栅极耦接，所述第五下拉晶体管和第六下拉晶体管的栅极共同耦接于所述上拉单元的控制信号输入端；
    各下拉晶体管的源极均耦接于第一下拉电压；
    还包括下传单元，所述下传单元包括下传晶体管，所述下传晶体管的栅极与上拉单元的控制信号输入端耦接，其漏极与所述上拉单元的时钟信号输入端耦接，其源极生成作用于后一级GOA驱动单元的下传信号；
    其中，所述GOA驱动电路将频率相等、相位相反的两个扫描时钟信号隔行输入至各GOA驱动单元。
  8. 一种GOA驱动单元，包括上拉单元、上拉控制单元、下拉单元、下拉维持单元及自举电容，其中，
    所述下拉维持单元包括镜像电路结构；
    所述镜像电路结构包括用于维持所述上拉单元的控制信号输入端低电压的第一下拉晶体管和第二下拉晶体管，用于维持所述上拉单元的行扫描信号输出端低电压的第三下拉晶体管和第四下拉晶体管，以及用于维持所述第一下拉晶体管和第三下拉晶体管栅极低电压的第五下拉晶体管和用于维持所述第二下拉晶体管和第四下拉晶体管栅极低电压的第六下拉晶体管；
    其中，第五下拉晶体管的漏极与所述第一下拉晶体管和第三下拉晶体管的栅极耦接，第六下拉晶体管的漏极与所述第二下拉晶体管和第四下拉晶体管的栅极耦接，所述第五下拉晶体管和第六下拉晶体管的栅极共同耦接于所述上拉单元的控制信号输入端；
    各下拉晶体管的源极均耦接于第一下拉电压；
    所述第一下拉晶体管和第二下拉晶体管的漏极共同耦接于所述上拉单元的控制信号输入端，所述第三下拉晶体管和第四下拉晶体管的漏极共同耦接于所述上拉单元的行扫描信号输出端；
    所述镜像电路结构还包括镜像的第一交替控制电路和第二交替控制电路，
    所述第一交替控制电路包括，
    第七晶体管，其栅极和漏极耦接在一起，用于接收第一交替控制信号；
    第八晶体管，其栅极和漏极分别与所述第七晶体管的源极和漏极耦接；
    第九晶体管，其漏极和源极分别与所述第八晶体管的漏极和源极耦接，其栅极用于接收第二交替控制信号；
    第十晶体管，其漏极与所述第八晶体管的栅极耦接，其栅极和源极分别与所述第五下拉晶体管的栅极和源极耦接；
    所述第二交替控制电路具有与所述第一交替控制电路镜像的结构，且其第一交替控制信号与第二交替控制信号的输入端互换；
    所述第一交替控制信号与所述第二交替控制信号交替为高电平和低电平。
  9. 根据权利要求8所述的GOA驱动单元，其中，还包括下传单元，所述下传单元包括下传晶体管，所述下传晶体管的栅极与上拉单元的控制信号输入端耦接，其漏极与所述上拉单元的时钟信号输入端耦接，其源极生成作用于后一级GOA驱动单元的下传信号。
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