WO2018192050A1 - Goa电路驱动架构 - Google Patents

Goa电路驱动架构 Download PDF

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Publication number
WO2018192050A1
WO2018192050A1 PCT/CN2017/084969 CN2017084969W WO2018192050A1 WO 2018192050 A1 WO2018192050 A1 WO 2018192050A1 CN 2017084969 W CN2017084969 W CN 2017084969W WO 2018192050 A1 WO2018192050 A1 WO 2018192050A1
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WIPO (PCT)
Prior art keywords
nth
thin film
film transistor
gate
frequency clock
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PCT/CN2017/084969
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English (en)
French (fr)
Inventor
郝思坤
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to KR1020197033432A priority Critical patent/KR102277072B1/ko
Priority to EP17906724.4A priority patent/EP3614370A4/en
Priority to US15/539,692 priority patent/US10283066B2/en
Priority to JP2020505954A priority patent/JP6806953B2/ja
Publication of WO2018192050A1 publication Critical patent/WO2018192050A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a GOA circuit driving architecture.
  • the liquid crystal display has become a display terminal for mobile communication devices, PCs, TVs, etc. due to its high display quality, low price, and convenient carrying.
  • the panel driving technology of TV liquid crystal displays generally adopts the GOA technology, that is, the Gate Driver on Array technology, which uses the original process of the flat panel display panel to manufacture the driving circuit of the horizontal scanning line of the panel.
  • GOA technology can simplify the manufacturing process of the flat panel display panel, eliminating the bonding process in the horizontal scanning line direction, which can increase the productivity and reduce the product cost, and at the same time improve the integration of the display panel to make it more It is suitable for making narrow border or borderless display products to meet the visual pursuit of modern people.
  • FIG. 1 is a schematic diagram of a GOA multi-level driving architecture of a conventional flat panel display, showing a multi-level connection method of a GOA circuit for flat panel display in the prior art, and peripherals of GOA circuits at the left and right sides of the panel
  • the metal lines of the first low frequency clock signal LC1, the second low frequency clock signal LC2, the direct current low voltage VSS, and the four high frequency clock signals CK1 to CK4 are placed.
  • each pixel P is electrically connected to one data line and one scan line; and several GOA circuits are sequentially step by step Arranging GOA(1), GOA(n-1), GOA(n), GOA(n+1), each GOA circuit respectively outputting a gate signal to scan a corresponding gate line in the display device,
  • Each of the GOA circuits is electrically connected to one of the first low frequency clock signal LC1, the second low frequency clock signal LC2, the direct current low voltage VSS, and the four high frequency clock signals CK1 to CK4.
  • the nth stage GOA circuit respectively receives the first low frequency clock signal LC1, the second low frequency clock signal LC2, the direct current low voltage VSS, and one of the high frequency clock signals CK1 to CK4, the n-2th stage.
  • the number of thin film transistor components used in the GOA circuit for flat panel display is large, and five metal wires are required on the left and right sides of the display panel to transmit the first low frequency clock signal LC1 and the second low frequency clock.
  • Signal LC2, DC low voltage VSS and one of four high frequency signals This is not conducive to the reduction of production costs, but also is not conducive to the reduction of the size of the GOA circuit.
  • the GOA circuit includes a start signal STV, a first low frequency clock signal LC1, and a second low frequency clock signal LC2.
  • the start signal is used to start the first two stages of the GOA T11, and the last two stages of the T31 and T41 are pulled down.
  • the low frequency signals LC1 and LC2 alternately perform the pull-down maintenance of the GOA circuit.
  • the GOA circuit is mainly used for the gate line.
  • Gn When the state is off, Gn is kept at a stable low potential VSS, and the Gn signal required for the gate line is mainly outputted by one of the four high frequency signals to make a gate signal of the display panel.
  • the TFT for inputting the control data signal can be well turned on even if the pixel P can be normally charged and discharged.
  • the GOA display panel has a large side border of the gate line, which cannot meet the needs of the current narrower frame.
  • the present invention provides a GOA circuit driving architecture, comprising: a plurality of data lines for providing data signals, a plurality of scanning lines for providing scanning signals, and a plurality of pixel arrays, each of which is electrically connected to One data line and one scan line; the odd-numbered GOA circuits are sequentially arranged on the pixel side of the AA area, and the even-numbered GOA circuits are sequentially arranged on the other side of the AA area pixel, and each stage GOA circuit outputs a gate signal to scan Corresponding scanning lines, each level of the GOA circuit is respectively connected to the first low frequency clock signal, the second low frequency clock signal, the direct current low voltage, and the odd number GOA circuit is connected to one of the first high frequency clock signal and the third high frequency clock signal, even number The stage GOA circuit connects one of the second high frequency clock signal and the fourth high frequency clock signal, and the first two stages and the last two stages of the GOA circuit are respectively connected to the enable signal.
  • the Nth stage GOA circuit includes:
  • a first thin film transistor having a gate connected to the N-2th enable signal terminal, and a source and a drain connected to the N-2th gate signal terminal and the Nth first circuit point, respectively;
  • a second thin film transistor having a gate connected to the Nth first circuit point, and a source and a drain respectively connected to the high frequency clock signal and the Nth gate signal terminal;
  • a third thin film transistor having a gate connected to the Nth first circuit point, and a source and a drain respectively connected to the high frequency clock signal and the Nth stage enable signal terminal;
  • a fourth thin film transistor having a gate connected to an N+2th enable signal terminal, a source and a drain respectively Connecting the Nth stage gate signal terminal and the DC low voltage;
  • a fifth thin film transistor having a gate connected to the N+2th stage start signal terminal, the source and the drain being respectively connected to the Nth stage first circuit point and the DC low voltage;
  • a sixth thin film transistor having a gate connected to the Nth second circuit point, the source and the drain being respectively connected to the Nth gate signal terminal and the DC low voltage;
  • a seventh thin film transistor having a gate connected to the Nth second circuit point, the source and the drain being respectively connected to the Nth first circuit point and the DC low voltage;
  • the eighth thin film transistor has a gate connected to the Nth third circuit point, and the source and the drain are respectively connected to the Nth gate signal terminal and the DC low voltage;
  • a ninth thin film transistor having a gate connected to an Nth third circuit point, wherein the source and the drain are respectively connected to the Nth first circuit point and the DC low voltage;
  • a tenth thin film transistor having a gate connected to the first low frequency clock signal, and a source and a drain respectively connected to the first low frequency clock signal and the gate of the eleventh thin film transistor;
  • the eleventh thin film transistor has a source and a drain connected to the first low frequency clock signal and the Nth third circuit point, respectively;
  • a twelfth thin film transistor having a gate connected to an Nth first circuit point, and a source and a drain respectively connected to the Nth third circuit point and a DC low voltage;
  • a thirteenth thin film transistor having a gate connected to the second low frequency clock signal, the source and the drain being respectively connected to the second low frequency clock signal and the gate of the fourteenth thin film transistor;
  • a fourteenth thin film transistor having a source and a drain connected to a second low frequency clock signal and an Nth second circuit point, respectively;
  • a sixteenth thin film transistor having a gate connected to an Nth first circuit point, a source and a drain respectively connected to a gate of the fourteenth thin film transistor and a DC low voltage;
  • a seventeenth thin film transistor having a gate connected to an Nth first circuit point, a source and a drain respectively connected to a gate of the eleventh thin film transistor and a DC low voltage;
  • the eighteenth thin film transistor has a gate connected to the Nth first circuit point, and a source and a drain connected to the N-2th gate signal terminal and the voltage pulldown circuit point, respectively.
  • the voltage pull-down circuit point is a high frequency clock signal.
  • the voltage pull-down circuit point is a DC low voltage.
  • the voltage pull-down circuit point is the Nth stage start signal end.
  • the waveforms of the first, second, third, and fourth high-frequency clock signals are the same, and the phase sequences are different by a quarter cycle.
  • the first low frequency clock signal and the second low frequency clock signal have the same waveform and opposite phases.
  • the invention also provides a GOA circuit driving architecture, comprising: a plurality of data lines providing data signals, a plurality of scanning lines providing scanning signals, a plurality of pixel arrays arranged, each pixel electrically connected to one data line and one Scanning line; odd-numbered GOA circuits are sequentially arranged on the pixel side of the AA area, and even-numbered GOA circuits are sequentially arranged on the other side of the AA area pixel, and each level of the GOA circuit outputs a gate signal to scan the corresponding scanning line, Each level of the GOA circuit is respectively connected to the first low frequency clock signal, the second low frequency clock signal, the direct current low voltage, and the odd number GOA circuit is connected to one of the first high frequency clock signal and the third high frequency clock signal, and the even level GOA circuit is connected. One of the two high frequency clock signals and the fourth high frequency clock signal, the first two stages and the last two stages of the GOA circuit are respectively connected to the start signal;
  • the waveforms of the first, second, third, and fourth high-frequency clock signals are the same, and the phase sequences are different by a quarter cycle;
  • the GOA circuit driver architecture of the present invention can reduce the frame space occupied by the GOA circuit, and enable the display panel to have a narrower border or a borderless design.
  • FIG. 1 is a schematic diagram of a GOA multi-level drive architecture of a conventional flat panel display
  • FIG. 2 is a schematic diagram of a GOA implementation circuit of a conventional flat panel display
  • FIG. 3 is a schematic diagram of a GOA circuit driving architecture of the present invention.
  • FIG. 4 is a schematic diagram of a GOA circuit of Embodiment 1 of a GOA circuit driving architecture of the present invention
  • FIG. 5 is a schematic diagram of a GOA circuit of Embodiment 2 of the GOA circuit driving architecture of the present invention.
  • FIG. 6 is a schematic diagram of a GOA circuit of Embodiment 3 of the GOA circuit driving architecture of the present invention.
  • FIG. 7 is a timing diagram of a GOA circuit of the GOA circuit driving architecture of the present invention.
  • the GOA circuit driver architecture adopts a mode in which the odd-numbered stages of the GOA circuit are driven separately, such as the odd-numbered stage G1 being driven on the left side of the AA (effective display) area pixel, and the even-numbered stage G2 being driven on the right side of the AA area pixel.
  • the odd-numbered G3 is driven on the left side of the AA area pixel
  • the even-numbered level G4 is driven on the right side of the AA area pixel, and so on, to realize the pixel driving.
  • This driving mode can save half of the height space occupied by the GOA circuit.
  • the height of the GOA circuit can be doubled by the area of the first-level GOA circuit, the width of the GOA circuit can be reduced by half, and the number of high-frequency signals CK required for driving the GOA circuit is also Can be reduced by half, which greatly reduces the border on the scan line side.
  • the GOA circuit driver architecture mainly includes:
  • each pixel P being electrically connected to one data line and one scan line; odd-numbered GOA circuits are sequentially arranged in On the pixel side of the AA area, the even-numbered GOA circuits are sequentially arranged on the other side of the AA area pixel, and each level of the GOA circuit outputs a gate signal to scan the corresponding scan line, and the GOA circuits of each level are electrically connected to the first low frequency.
  • the clock signal LC1, the second low frequency clock signal LC2, the DC low voltage VSS, the odd-numbered GOA circuit is connected to one of the high-frequency clock signals CK1 and CK3, and the even-numbered GOA circuit is connected to one of the high-frequency clock signals CK2 and CK4, the first two The stage and last two stages of the GOA circuit are respectively connected to the start signal ST.
  • the Nth stage GOA circuit includes:
  • the thin film transistor T11 has a gate connected to the N-2th stage start signal terminal ST(N-2), and the source and the drain are respectively connected to the N-2th stage gate signal terminal G(N-2) and the Nth stage a circuit point Q(N);
  • the thin film transistor T21 has a gate connected to the Nth stage first circuit point Q(N), and the source and the drain are respectively connected to the high frequency clock signal CK and the Nth stage gate signal terminal G(N);
  • the thin film transistor T22 has a gate connected to the Nth stage first circuit point Q(N), and the source and the drain are respectively connected to the high frequency clock signal CK and the Nth stage start signal terminal ST(N);
  • the thin film transistor T31 has a gate connected to the N+2th stage start signal terminal ST(N+2), and a source and a drain respectively connected to the Nth stage gate signal terminal G(N) and the DC low voltage VSS;
  • the thin film transistor T41 has a gate connected to the N+2th stage start signal terminal ST(N+2), and the source and the drain are respectively connected to the Nth stage first circuit point Q(N) and the DC low voltage VSS;
  • the thin film transistor T33 has a gate connected to the Nth stage second circuit point K(N), and the source and the drain are respectively connected to the Nth stage gate signal terminal G(N) and the DC low voltage VSS;
  • the thin film transistor T43 has a gate connected to the Nth stage second circuit point K(N), and the source and the drain are respectively connected to the Nth stage first circuit point Q(N) and the DC low voltage VSS;
  • the thin film transistor T32 has a gate connected to the Nth third circuit point P(N), the source and the drain Connecting the Nth stage gate signal terminal G(N) and the DC low voltage VSS, respectively;
  • the thin film transistor T42 has a gate connected to the Nth stage third circuit point P(N), and the source and the drain are respectively connected to the Nth stage first circuit point Q(N) and the DC low voltage VSS;
  • the thin film transistor T51 has a gate connected to the first low frequency clock signal LC1, and a source and a drain connected to the gates of the first low frequency clock signal LC1 and the thin film transistor T53, respectively;
  • the thin film transistor T53 has a source and a drain connected to the first low frequency clock signal LC1 and the Nth third circuit point P(N), respectively;
  • the thin film transistor T61 has a gate connected to the second low frequency clock signal LC2, and a source and a drain connected to the gates of the second low frequency clock signal LC2 and the thin film transistor T63, respectively;
  • the thin film transistor T63 has a source and a drain connected to the second low frequency clock signal LC2 and the Nth second circuit point K(N), respectively;
  • the thin film transistor T64 has a gate connected to the Nth stage first circuit point Q(N), and the source and the drain are respectively connected to the Nth stage second circuit point K(N) and the DC low voltage VSS;
  • the thin film transistor T62 has a gate connected to the Nth first circuit point Q(N), and a source and a drain respectively connected to the gate of the thin film transistor T63 and a DC low voltage VSS;
  • the thin film transistor T52 has a gate connected to the Nth stage first circuit point Q(N), and a source and a drain respectively connected to the gate of the thin film transistor T53 and a DC low voltage VSS;
  • the voltage pull-down circuit point of the T71 connection is the high frequency clock signal CK.
  • T71 TFT
  • the driving structure is mainly after the GOA output driving signal Gn, the falling time of the Gn signal is too long, and the falling time is longer at the far end of the AA area on the gate side, so that the panel may have the gate side in the display quality.
  • the brightness at the far end is different, and the color deviation at the far end is different.
  • the GOA circuit in Fig. 4 can realize that the GOA circuit gate output has a greater force pull-down when it becomes a low potential, which can well shorten the Gn fall time.
  • FIG. 5 is a schematic diagram of a GOA circuit of Embodiment 2 of the GOA circuit driving architecture of the present invention, wherein the voltage pull-down circuit point of the T71 connection is a DC low voltage VSS. As shown in FIG. 5, the source end of T71 in FIG. 4 is pulled down to VSS, and the purpose of Gn fast pull-down can also be achieved.
  • FIG 6 is a schematic diagram of a GOA circuit of the third embodiment of the GOA circuit driving architecture of the present invention, wherein the voltage pull-down circuit point of the T71 connection is the Nth stage start signal terminal ST(N).
  • ST(N) the Nth stage start signal terminal
  • T71 is pulled down to STn, and the purpose of Gn fast pull-down can also be achieved.
  • the drop-down of Gn in the implementation case is changed from the original Gn+2 to ST(n+2).
  • the advantage of this is that Gn is not required to participate in the pull-down, because the Gn output is actually interfered by signals such as AA area and date.
  • the pull-down capability is not stable, and if the Gn is abnormal due to in-plane defects, then Gn-2 cannot be pulled down, which will cause the entire GOA circuit to be abnormal. After using STn+2 to pull down, the pulldown will not be affected by any interference in the plane. The most important thing is that the STn pulldown will be faster than Gn, which is beneficial to reduce the falling time of Gn.
  • FIG. 7 is a timing diagram of a GOA circuit of the GOA circuit driving architecture of the present invention, which is applicable to the GOA circuits of all embodiments.
  • the number of CKs of the present invention may be any even number.
  • the waveforms of the first, second, third, and fourth high frequency CK clock signals are the same, and the phase order differs by a quarter cycle.
  • the first low frequency clock signal LC1 and the second low frequency clock signal LC2 have the same waveform and opposite phases.
  • the GOA circuit driver architecture of the present invention can reduce the frame space occupied by the GOA circuit, and enable the display panel to have a narrower border or a borderless design.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Shift Register Type Memory (AREA)

Abstract

一种GOA电路驱动架构，包括：数个提供数据信号的数据线，数个提供扫描信号的扫描线，数个像素（P）阵列排布，每一像素（P）电性连接于一条数据线及一条扫描线；奇数级GOA电路依序排列于AA区像素（P）一侧，偶数级GOA电路依序排列于AA区像素（P）另一侧，每一级GOA电路分别输出一栅极信号以扫描对应的扫描线，各级GOA电路分别连接第一低频时钟信号（LC1）、第二低频时钟信号（LC2）、直流低电压（VSS），奇数级GOA电路连接第一高频时钟信号和第三高频时钟信号其中之一，偶数级GOA电路连接第二高频时钟信号和第四高频时钟信号其中之一，最初两级和最后两级GOA电路分别连接启动信号（ST）。该GOA电路驱动架构能够减少GOA电路所占边框空间，使显示面板做到更窄边框或无边框设计。

Description

GOA电路驱动架构 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种GOA电路驱动架构。
背景技术
液晶显示器以其高显示品质、价格低廉、携带方便等优点，成为在移动通讯设备、PC、TV等的显示终端。目前普遍采用的TV液晶显示器的面板驱动技术逐渐趋向于采用GOA技术，即阵列基板行驱动(Gate Driver on Array)技术，其运用平板显示面板的原有制程将面板水平扫描线的驱动电路制作在显示区周围的基板上，GOA技术能简化平板显示面板的制作工序，省去水平扫描线方向的接合(bonding)工艺，可提升产能并降低产品成本，同时可以提升显示面板的集成度使之更适合制作窄边框或无边框显示产品，满足现代人们的视觉追求。
随着人们对液晶显示器越来越窄边框的视觉需求，GOA技术还需要不断的缩减边框，这就成为技术人员们急需解决的难题。
图1所示为现有平板显示的GOA多级驱动架构示意图，显示了在现有技术中，用于平板显示的GOA电路的一种多级连接方法，面板左右两侧各级GOA电路的外围都放置有第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS、及4个高频时钟信号CK1～CK4的金属线。数个提供数据信号的数据线，数个提供扫描信号的扫描线，数个像素P阵列排布，每一像素P电性连接于一条数据线及一条扫描线；数个GOA电路依序逐级排列GOA(1)、GOA(n-1)、GOA(n)、GOA(n+1)，每一GOA电路分别输出一栅极信号，以扫描显示装置中对应的扫描线(gate line)，各GOA电路分别电性连接第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS、四个高频时钟信号CK1～CK4中的一个高频时钟信号。具体地，第n级GOA电路分别接受第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS、高频时钟信号CK1～CK4中的1个高频时钟信号、第n-2级GOA电路产生的G(n-2)信号和启动信号ST(n-2)、第n+2级GOA电路产生的G(n+2)信号，并产生G(n)、ST(n)和Q(n)信号。由此可见，现有用于平板显示的GOA电路中使用的薄膜晶体管元件数量较多，并且在显示面板的左、右两侧都需要五条金属线来传输第一低频时钟信号LC1与第二低频时钟信号LC2，直流低电压VSS及四个高频信号中一 个，这样既不利于制作成本的降低，也不利于GOA电路尺寸的缩减。
如图2所示，为现有技术中一种GOA电路，同时结合图1进行说明，本显示架构中，GOA电路包括有启动信号STV，第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS、及4个高频时钟信号CK1～CK4。启动信号用于启动GOA的前2级的T11，以及下拉最后两级的T31和T41，低频信号LC1和LC2交替的进行GOA电路的下拉维持，GOA电路主要用于在扫描线(gate line)处于关闭状态时，保持Gn处于稳定的低电位VSS，同时扫描线(gate line)所需Gn信号主要通过四个高频信号中的其中一个进行输出高电平，使显示面板的扫描(gate)信号可以很好地打开控制数据(date)信号输入的TFT，即使像素P可以正常充放电。这种GOA显示面板扫描线(gate line)侧边框较大，无法满足目前更窄边框的需求。
发明内容
因此，本发明的目的在于提供一种GOA电路驱动架构，减少GOA电路所占边框空间。
为实现上述目的，本发明提供了一种GOA电路驱动架构，包括：数个提供数据信号的数据线，数个提供扫描信号的扫描线，数个像素阵列排布，每一像素电性连接于一条数据线及一条扫描线；奇数级GOA电路依序排列于AA区像素一侧，偶数级GOA电路依序排列于AA区像素另一侧，每一级GOA电路分别输出一栅极信号以扫描对应的扫描线，各级GOA电路分别连接第一低频时钟信号、第二低频时钟信号、直流低电压，奇数级GOA电路连接第一高频时钟信号和第三高频时钟信号其中之一，偶数级GOA电路连接第二高频时钟信号和第四高频时钟信号其中之一，最初两级和最后两级GOA电路分别连接启动信号。
其中，第N级GOA电路包括：
第一薄膜晶体管，其栅极连接第N-2级启动信号端，源极和漏极分别连接第N-2级栅极信号端和第N级第一电路点；
第二薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接高频时钟信号和第N级栅极信号端；
第三薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接高频时钟信号和第N级启动信号端；
电容，其连接于第N级第一电路点和第N级栅极信号端之间；
第四薄膜晶体管，其栅极连接第N+2级启动信号端，源极和漏极分别 连接第N级栅极信号端和直流低电压；
第五薄膜晶体管，其栅极连接第N+2级启动信号端，源极和漏极分别连接第N级第一电路点和直流低电压；
第六薄膜晶体管，其栅极连接第N级第二电路点，源极和漏极分别连接第N级栅极信号端和直流低电压；
第七薄膜晶体管，其栅极连接第N级第二电路点，源极和漏极分别连接第N级第一电路点和直流低电压；
第八薄膜晶体管，其栅极连接第N级第三电路点，源极和漏极分别连接第N级栅极信号端和直流低电压；
第九薄膜晶体管，其栅极连接第N级第三电路点，源极和漏极分别连接第N级第一电路点和直流低电压；
第十薄膜晶体管，其栅极连接第一低频时钟信号，源极和漏极分别连接第一低频时钟信号和第十一薄膜晶体管的栅极；
第十一薄膜晶体管，其源极和漏极分别连接第一低频时钟信号和第N级第三电路点；
第十二薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第N级第三电路点和直流低电压；
第十三薄膜晶体管，其栅极连接第二低频时钟信号，源极和漏极分别连接第二低频时钟信号和第十四薄膜晶体管的栅极；
第十四薄膜晶体管，其源极和漏极分别连接第二低频时钟信号和第N级第二电路点；
第十五薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第N级第二电路点和直流低电压；
第十六薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第十四薄膜晶体管的栅极和直流低电压；
第十七薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第十一薄膜晶体管的栅极和直流低电压；
第十八薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第N-2级栅极信号端和电压下拉电路点。
其中，该电压下拉电路点为高频时钟信号。
其中，该电压下拉电路点为直流低电压。
其中，该电压下拉电路点为第N级启动信号端。
其中，所述第一、第二、第三及第四高频时钟信号的波形相同，相位顺序相差四分之一周期。
其中，所述第一低频时钟信号和第二低频时钟信号波形相同，相位相反。
本发明还提供一种GOA电路驱动架构，包括：数个提供数据信号的数据线，数个提供扫描信号的扫描线，数个像素阵列排布，每一像素电性连接于一条数据线及一条扫描线；奇数级GOA电路依序排列于AA区像素一侧，偶数级GOA电路依序排列于AA区像素另一侧，每一级GOA电路分别输出一栅极信号以扫描对应的扫描线，各级GOA电路分别连接第一低频时钟信号、第二低频时钟信号、直流低电压，奇数级GOA电路连接第一高频时钟信号和第三高频时钟信号其中之一，偶数级GOA电路连接第二高频时钟信号和第四高频时钟信号其中之一，最初两级和最后两级GOA电路分别连接启动信号；
其中，所述第一、第二、第三及第四高频时钟信号的波形相同，相位顺序相差四分之一周期；
其中，所述第一低频时钟信号和第二低频时钟信号波形相同，相位相反。
综上所述，本发明的GOA电路驱动架构能够减少GOA电路所占边框空间，使显示面板做到更窄边框或无边框设计。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有平板显示的GOA多级驱动架构示意图；
图2为现有平板显示的一种GOA实施电路示意图；
图3为本发明的GOA电路驱动架构示意图；
图4为本发明的GOA电路驱动架构实施方案一的GOA电路原理图；
图5为本发明的GOA电路驱动架构实施方案二的GOA电路原理图；
图6为本发明的GOA电路驱动架构实施方案三的GOA电路原理图；
图7为本发明的GOA电路驱动架构的GOA电路时序图。
具体实施方式
如图3所示，其为本发明的GOA电路驱动架构。该GOA电路驱动架构采用的是GOA电路奇数偶数级左右分开驱动的方式，如奇数级G1在AA(有效显示)区像素的左侧驱动，偶数级G2则在AA区像素的右侧驱动， 依次奇数级G3在AA区像素的左侧驱动，偶数级G4则在AA区像素的右侧驱动，依次类推，实现像素的驱动，此种驱动方式可以省去一半的GOA电路所占的高度空间，如果以一级GOA电路的面积来计算，在GOA电路的高度可以增加一倍的前提下，GOA电路的宽度就可以减少一半，再加上GOA电路驱动所需要的高频信号CK的数量也可以减少一半，这样就极大的缩减了扫描线侧的边框。
该GOA电路驱动架构主要包括：
数个提供数据信号的数据线，数个提供扫描信号的扫描线，数个像素P阵列排布，每一像素P电性连接于一条数据线及一条扫描线；奇数级GOA电路依序排列于AA区像素一侧，偶数级GOA电路依序排列于AA区像素另一侧，每一级GOA电路分别输出一栅极信号以扫描对应的扫描线，各级GOA电路分别电性连接第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS，奇数级GOA电路连接高频时钟信号CK1和CK3其中之一，偶数级GOA电路连接高频时钟信号CK2和CK4其中之一，最初两级和最后两级GOA电路分别连接启动信号ST。
图4为本发明的GOA电路驱动架构实施方案一的GOA电路原理图。第N级GOA电路包括：
薄膜晶体管T11，其栅极连接第N-2级启动信号端ST(N-2)，源极和漏极分别连接第N-2级栅极信号端G(N-2)和第N级第一电路点Q(N)；
薄膜晶体管T21，其栅极连接第N级第一电路点Q(N)，源极和漏极分别连接高频时钟信号CK和第N级栅极信号端G(N)；
薄膜晶体管T22，其栅极连接第N级第一电路点Q(N)，源极和漏极分别连接高频时钟信号CK和第N级启动信号端ST(N)；
电容Cb，其连接于第N级第一电路点Q(N)和第N级栅极信号端G(N)之间；
薄膜晶体管T31，其栅极连接第N+2级启动信号端ST(N+2)，源极和漏极分别连接第N级栅极信号端G(N)和直流低电压VSS；
薄膜晶体管T41，其栅极连接第N+2级启动信号端ST(N+2)，源极和漏极分别连接第N级第一电路点Q(N)和直流低电压VSS；
薄膜晶体管T33，其栅极连接第N级第二电路点K(N)，源极和漏极分别连接第N级栅极信号端G(N)和直流低电压VSS；
薄膜晶体管T43，其栅极连接第N级第二电路点K(N)，源极和漏极分别连接第N级第一电路点Q(N)和直流低电压VSS；
薄膜晶体管T32，其栅极连接第N级第三电路点P(N)，源极和漏极 分别连接第N级栅极信号端G(N)和直流低电压VSS；
薄膜晶体管T42，其栅极连接第N级第三电路点P(N)，源极和漏极分别连接第N级第一电路点Q(N)和直流低电压VSS；
薄膜晶体管T51，其栅极连接第一低频时钟信号LC1，源极和漏极分别连接第一低频时钟信号LC1和第薄膜晶体管T53的栅极；
薄膜晶体管T53，其源极和漏极分别连接第一低频时钟信号LC1和第N级第三电路点P(N)；
薄膜晶体管T54，其栅极连接第N级第一电路点Q(N)，源极和漏极分别连接第N级第三电路点P(N)和直流低电压VSS；
薄膜晶体管T61，其栅极连接第二低频时钟信号LC2，源极和漏极分别连接第二低频时钟信号LC2和薄膜晶体管T63的栅极；
薄膜晶体管T63，其源极和漏极分别连接第二低频时钟信号LC2和第N级第二电路点K(N)；
薄膜晶体管T64，其栅极连接第N级第一电路点Q(N)，源极和漏极分别连接第N级第二电路点K(N)和直流低电压VSS；
薄膜晶体管T62，其栅极连接第N级第一电路点Q(N)，源极和漏极分别连接薄膜晶体管T63的栅极和直流低电压VSS；
薄膜晶体管T52，其栅极连接第N级第一电路点Q(N)，源极和漏极分别连接薄膜晶体管T53的栅极和直流低电压VSS；
薄膜晶体管T71，其栅极连接第N级第一电路点Q(N)，源极和漏极分别连接第N-2级栅极信号端G(N-2)和电压下拉电路点。
图4中，T71连接的电压下拉电路点为高频时钟信号CK。要想使用图3所示的驱动架构，只需要在图2所示原有的GOA电路中增加一颗TFT(T71)即可实现，原因为目前GOA电路之所以使用图1所示原有的驱动架构，主要在于GOA输出驱动信号Gn后，Gn信号的下降时间(falling time)过长，在AA区gate侧的远端，falling time会更长，这样面板在显示品质在就可能存在gate侧远近端亮度不同，远端色偏等问题。而图4中的GOA电路即可实现GOA电路gate输出在变成低电位的时候，有更大的力度下拉，可以很好的将Gn的falling time缩短。
图5为本发明的GOA电路驱动架构实施方案二的GOA电路原理图，其中T71连接的电压下拉电路点为直流低电压VSS。如图5，将图4中T71的Source端下拉到VSS，同样也可以实现Gn快速下拉的目的。
图6为本发明的GOA电路驱动架构实施方案三的GOA电路原理图，其中T71连接的电压下拉电路点为第N级启动信号端ST(N)。如图6，将 图4中T71下拉到STn，同样也可以实现Gn快速下拉的目的。同时实施案例中Gn的下拉全部由原来的Gn+2变化成ST(n+2)，这样做的好处在于不需要Gn参与下拉，原因为Gn输出实际上会受到AA区，date等信号的干扰，下拉能力是不太稳定的，同时如果由于面内不良造成Gn异常，那么Gn-2就无法下拉，从而将造成整个GOA电路异常。使用STn+2来下拉后，下拉不会受到面内的任何干扰，最主要是STn下拉会较Gn更快，有利于减小Gn的falling time。
图7为本发明的GOA电路驱动架构的GOA电路时序图，适用于所有实施例的GOA电路，另外，本发明的CK的数量可以是任何偶数。第一、第二、第三及第四高频CK时钟信号的波形相同，相位顺序相差四分之一周期。第一低频时钟信号LC1和第二低频时钟信号LC2波形相同，相位相反。
综上所述，本发明的GOA电路驱动架构能够减少GOA电路所占边框空间，使显示面板做到更窄边框或无边框设计。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (12)

  1. 一种GOA电路驱动架构，包括：数个提供数据信号的数据线，数个提供扫描信号的扫描线，数个像素阵列排布，每一像素电性连接于一条数据线及一条扫描线；奇数级GOA电路依序排列于AA区像素一侧，偶数级GOA电路依序排列于AA区像素另一侧，每一级GOA电路分别输出一栅极信号以扫描对应的扫描线，各级GOA电路分别连接第一低频时钟信号、第二低频时钟信号、直流低电压，奇数级GOA电路连接第一高频时钟信号和第三高频时钟信号其中之一，偶数级GOA电路连接第二高频时钟信号和第四高频时钟信号其中之一，最初两级和最后两级GOA电路分别连接启动信号。
  2. 如权利要求1所述的GOA电路驱动架构，其中，第N级GOA电路包括：
    第一薄膜晶体管，其栅极连接第N-2级启动信号端，源极和漏极分别连接第N-2级栅极信号端和第N级第一电路点；
    第二薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接高频时钟信号和第N级栅极信号端；
    第三薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接高频时钟信号和第N级启动信号端；
    电容其连接于第N级第一电路点和第N级栅极信号端之间；
    第四薄膜晶体管，其栅极连接第N+2级启动信号端，源极和漏极分别连接第N级栅极信号端和直流低电压；
    第五薄膜晶体管，其栅极连接第N+2级启动信号端，源极和漏极分别连接第N级第一电路点和直流低电压；
    第六薄膜晶体管，其栅极连接第N级第二电路点，源极和漏极分别连接第N级栅极信号端和直流低电压；
    第七薄膜晶体管，其栅极连接第N级第二电路点，源极和漏极分别连接第N级第一电路点和直流低电压；
    第八薄膜晶体管，其栅极连接第N级第三电路点，源极和漏极分别连接第N级栅极信号端和直流低电压；
    第九薄膜晶体管，其栅极连接第N级第三电路点，源极和漏极分别连接第N级第一电路点和直流低电压；
    第十薄膜晶体管，其栅极连接第一低频时钟信号，源极和漏极分别连 接第一低频时钟信号和第十一薄膜晶体管的栅极；
    第十一薄膜晶体管，其源极和漏极分别连接第一低频时钟信号和第N级第三电路点；
    第十二薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第N级第三电路点和直流低电压；
    第十三薄膜晶体管，其栅极连接第二低频时钟信号，源极和漏极分别连接第二低频时钟信号和第十四薄膜晶体管的栅极；
    第十四薄膜晶体管，其源极和漏极分别连接第二低频时钟信号和第N级第二电路点；
    第十五薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第N级第二电路点和直流低电压；
    第十六薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第十四薄膜晶体管的栅极和直流低电压；
    第十七薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第十一薄膜晶体管的栅极和直流低电压；
    第十八薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第N-2级栅极信号端和电压下拉电路点。
  3. 如权利要求2所述的GOA电路驱动架构，其中，该电压下拉电路点为高频时钟信号。
  4. 如权利要求2所述的GOA电路驱动架构，其中，该电压下拉电路点为直流低电压。
  5. 如权利要求2所述的GOA电路驱动架构，其中，该电压下拉电路点为第N级启动信号端。
  6. 如权利要求1所述的GOA电路驱动架构，其中，所述第一、第二、第三及第四高频时钟信号的波形相同，相位顺序相差四分之一周期。
  7. 如权利要求1所述的GOA电路驱动架构，其中，所述第一低频时钟信号和第二低频时钟信号波形相同，相位相反。
  8. 一种GOA电路驱动架构，包括：数个提供数据信号的数据线，数个提供扫描信号的扫描线，数个像素阵列排布，每一像素电性连接于一条数据线及一条扫描线；奇数级GOA电路依序排列于AA区像素一侧，偶数级GOA电路依序排列于AA区像素另一侧，每一级GOA电路分别输出一栅极信号以扫描对应的扫描线，各级GOA电路分别连接第一低频时钟信号、第二低频时钟信号、直流低电压，奇数级GOA电路连接第一高频时钟信号和第三高频时钟信号其中之一，偶数级GOA电路连接第二高频时钟信号和 第四高频时钟信号其中之一，最初两级和最后两级GOA电路分别连接启动信号；
    其中，所述第一、第二、第三及第四高频时钟信号的波形相同，相位顺序相差四分之一周期；
    其中，所述第一低频时钟信号和第二低频时钟信号波形相同，相位相反。
  9. 如权利要求8所述的GOA电路驱动架构，其中，第N级GOA电路包括：
    第一薄膜晶体管，其栅极连接第N-2级启动信号端，源极和漏极分别连接第N-2级栅极信号端和第N级第一电路点；
    第二薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接高频时钟信号和第N级栅极信号端；
    第三薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接高频时钟信号和第N级启动信号端；
    电容其连接于第N级第一电路点和第N级栅极信号端之间；
    第四薄膜晶体管，其栅极连接第N+2级启动信号端，源极和漏极分别连接第N级栅极信号端和直流低电压；
    第五薄膜晶体管，其栅极连接第N+2级启动信号端，源极和漏极分别连接第N级第一电路点和直流低电压；
    第六薄膜晶体管，其栅极连接第N级第二电路点，源极和漏极分别连接第N级栅极信号端和直流低电压；
    第七薄膜晶体管，其栅极连接第N级第二电路点，源极和漏极分别连接第N级第一电路点和直流低电压；
    第八薄膜晶体管，其栅极连接第N级第三电路点，源极和漏极分别连接第N级栅极信号端和直流低电压；
    第九薄膜晶体管，其栅极连接第N级第三电路点，源极和漏极分别连接第N级第一电路点和直流低电压；
    第十薄膜晶体管，其栅极连接第一低频时钟信号，源极和漏极分别连接第一低频时钟信号和第十一薄膜晶体管的栅极；
    第十一薄膜晶体管，其源极和漏极分别连接第一低频时钟信号和第N级第三电路点；
    第十二薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第N级第三电路点和直流低电压；
    第十三薄膜晶体管，其栅极连接第二低频时钟信号，源极和漏极分别 连接第二低频时钟信号和第十四薄膜晶体管的栅极；
    第十四薄膜晶体管，其源极和漏极分别连接第二低频时钟信号和第N级第二电路点；
    第十五薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第N级第二电路点和直流低电压；
    第十六薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第十四薄膜晶体管的栅极和直流低电压；
    第十七薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第十一薄膜晶体管的栅极和直流低电压；
    第十八薄膜晶体管，其栅极连接第N级第一电路点，源极和漏极分别连接第N-2级栅极信号端和电压下拉电路点。
  10. 如权利要求9所述的GOA电路驱动架构，其中，该电压下拉电路点为高频时钟信号。
  11. 如权利要求9所述的GOA电路驱动架构，其中，该电压下拉电路点为直流低电压。
  12. 如权利要求9所述的GOA电路驱动架构，其中，该电压下拉电路点为第N级启动信号端。
PCT/CN2017/084969 2017-04-17 2017-05-18 Goa电路驱动架构 WO2018192050A1 (zh)

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