WO2016082340A1 - 充电扫描与电荷共享扫描双输出goa电路 - Google Patents

充电扫描与电荷共享扫描双输出goa电路 Download PDF

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Publication number
WO2016082340A1
WO2016082340A1 PCT/CN2015/072504 CN2015072504W WO2016082340A1 WO 2016082340 A1 WO2016082340 A1 WO 2016082340A1 CN 2015072504 W CN2015072504 W CN 2015072504W WO 2016082340 A1 WO2016082340 A1 WO 2016082340A1
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electrically connected
transistor
signal
gate
frequency clock
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PCT/CN2015/072504
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English (en)
French (fr)
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曹尚操
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深圳市华星光电技术有限公司
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Priority to US14/428,978 priority Critical patent/US9773467B2/en
Publication of WO2016082340A1 publication Critical patent/WO2016082340A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/028—Improving the quality of display appearance by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction

Definitions

  • the present invention relates to the field of display technology, in particular to a dual-output GOA circuit for charge scanning and charge sharing scanning.
  • LCD Liquid Crystal Display
  • PDA personal digital assistant
  • LCD TV mobile phone
  • PDA personal digital assistant
  • digital camera computer screen or notebook computer screen, etc.
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to inject liquid crystal molecules between the thin film transistor substrate (Thin Film Transistor Array Substrate, TFT Array Substrate) and the color filter substrate (Color Filter, CF), and apply driving voltage on the two substrates To control the rotation direction of the liquid crystal molecules to refract the light from the backlight module to produce images.
  • each pixel is electrically connected to a thin film transistor (TFT), the gate is connected to the horizontal scan line, the drain is connected to the vertical data line, and the source is Connect to the pixel electrode.
  • TFT thin film transistor
  • Applying enough voltage on the horizontal scan line will turn on all the TFTs that are electrically connected to the scan line, so that the signal voltage on the data line can be written to the pixel, and the transmittance of different liquid crystals can be controlled to achieve color control. effect.
  • the driving of the horizontal scan line of the active liquid crystal display panel is mainly completed by an external integrated circuit board (Integrated Circuit, IC), and the external IC can control the step-by-step charging and discharging of the horizontal scan lines at all levels.
  • IC integrated circuit board
  • the GOA technology (Gate Driver on Array) is the array substrate row driving technology, which can use the original process of the liquid crystal display panel to fabricate the horizontal scan line driver circuit on the substrate around the display area, so that it can replace the external IC to complete the level. Scan line drive. GOA technology can reduce the bonding process of external ICs, which has the opportunity to increase production capacity and reduce product costs, and it can make LCD panels more suitable for manufacturing display products with narrow bezels or no bezels.
  • each level of GOA circuit passes a To The timing signals output the charge scan signal and the charge & share gate at the same time, which will not only increase the load of the scan line and timing signal line, but also reduce the output quality of the scan signal and increase the pressure on the IC.
  • the charging scan signal and the charge sharing scan signal are output by the same TFT, the waveforms of the two are the same, which is not conducive to the reasonable design of the TFT specifications.
  • the purpose of the present invention is to provide a dual-output GOA circuit for charging scan and charge sharing scan, which can realize that the charging scan signal and the charge sharing scan signal are output by two different high-frequency clock signals through a TFT at the same time.
  • the output waveforms of the charging scan signal and the charge sharing scan signal can be controlled by the specifications of the corresponding TFT, which can reduce the instantaneous current of the IC, reduce the load of the IC, and improve the flexibility of the design for reducing color shift.
  • the present invention provides a dual-output GOA circuit for charge scanning and charge sharing scanning, which includes multiple GOA unit circuits cascaded, first and second low-frequency clock signals, DC Low-voltage signal and four metal wires for high-frequency clock signals;
  • n is a positive integer
  • the n-th GOA unit circuit receives the first and second low-frequency clock signals, DC low-voltage signals, and the Mth and M-2th high Frequency clock signal, the stage transfer signal generated by the n-2th stage GOA unit circuit, the charging scan signal generated by the n-2th stage GOA unit circuit, and the stage transfer signal generated by the n+2th stage GOA unit circuit, through different
  • the TFT respectively outputs the charge scan signal, the charge sharing scan signal of the n-2th stage GOA unit circuit, and the stage transfer signal;
  • the n-th stage GOA unit circuit includes: a downstream module, a stage-transmission voltage stabilizing module, an output module, a fast pull-down module, and a pull-down maintenance module.
  • the output module includes a twentieth transistor, the gate of the twentieth transistor is electrically connected to the first node, the source is electrically connected to the M-2th high-frequency clock signal, and the drain outputs the n-2th The charge sharing scan signal of the first-level GOA unit circuit; the twentieth transistor is used to output the charge sharing scan of the n-2th level GOA unit circuit according to the M-2th high-frequency clock signal when the first node is at a high potential signal;
  • the twenty-first transistor, the gate of the twenty-first transistor is electrically connected to the first node, the source is electrically connected to the M-th high-frequency clock signal, and the drain outputs a charging scan signal;
  • the twenty-first transistor A transistor is used to output a charging scan signal according to the M-th high-frequency clock signal when the first node is at a high potential;
  • the twenty-second transistor, the gate of the twenty-second transistor is electrically connected to the first node, the source is electrically connected to the M-th high-frequency clock signal, and the drain output stage transmits signals; the twentieth The two transistors are used to transmit according to the M-th high-frequency clock signal output stage when the first node is at a high potential. To signal.
  • the output module further includes a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the charging scan signal.
  • the download module includes an eleventh transistor, the gate of the eleventh transistor is electrically connected to the stage transmission signal of the n-2th level GOA unit circuit, and the source is electrically connected to the n-2th level GOA unit For the charging scan signal of the circuit, the drain is electrically connected to the first node;
  • the pull-down maintenance module includes a fifty-fifth transistor, a first pull-down maintenance module, and a second pull-down maintenance module;
  • the gate of the fifty-fifth transistor is electrically connected to the first node, the source is electrically connected to the second node, and the drain is electrically connected to the third node;
  • the first pull-down maintenance module includes a forty-second transistor.
  • the gate of the forty-second transistor is electrically connected to the second node, the source is electrically connected to the first node, and the drain is electrically connected to the DC A low voltage signal; a fifty-first transistor, the gate and source of the fifty-first transistor are electrically connected to the first low-frequency clock signal, and the drain is electrically connected to the gate of the fifty-third transistor; A fifty-third transistor, the gate of the fifty-third transistor is electrically connected to the drain of the fifty-first transistor, the source is electrically connected to the first low-frequency clock signal, and the drain is electrically connected to the second node; A fifty-fourth transistor, the gate of the fifty-fourth transistor is electrically connected to the second low-frequency clock signal, the source is electrically connected to the first low-frequency clock signal, and the drain is electrically connected to the second node; third Twelve transistors, the gate of the thirty-second transistor is electrically connected to the second node, the source is electrically connected to the charging
  • the second pull-down maintenance module includes a forty-third transistor.
  • the gate of the forty-third transistor is electrically connected to the third node, the source is electrically connected to the first node, and the drain is electrically connected to the DC low A voltage signal; a sixty-first transistor, the gate and source of the sixty-first transistor are electrically connected to the second low-frequency clock signal, and the drain is electrically connected to the gate of the sixty-third transistor; sixth A thirteenth transistor, the gate of the 63rd transistor is electrically connected to the drain of the 61st transistor, the source is electrically connected to the second low-frequency clock signal, and the drain is electrically connected to the third node; A sixty-four transistor, the gate of the sixty-fourth transistor is electrically connected to the first low-frequency clock signal, the source is electrically connected to the second low-frequency clock signal, and the drain is electrically connected to the third node; thirtieth Three transistors, the gate of the thirty-third transistor is electrically connected to the third node, the source is electrically
  • the cascade voltage stabilizing module includes a fifty-second transistor, the gate of the fifty-second transistor is electrically connected to the first node, the source is electrically connected to the second node, and the drain is electrically connected to the DC low A voltage signal; a sixty-second transistor, the gate of the sixty-second transistor is electrically connected to the first node, the source is electrically connected to the third node, and the drain is electrically connected to the DC low voltage signal; fifth To A sixteenth transistor, the gate of the fifty-sixth crystal is electrically connected to the stage transmission signal of the n-2th stage GOA unit circuit, the source is electrically connected to the drain of the fifty-first transistor, and the drain is electrically connected Connected to a DC low voltage signal; a 66th transistor, the gate of the 66th crystal is electrically connected to the stage transmission signal of the n-2th GOA unit circuit, and the source is electrically connected to the 61st The drain of the transistor is electrically connected to the DC low voltage signal;
  • the fast pull-down module includes a thirtieth transistor, the gate of the thirtieth transistor is electrically connected to the level transmission signal of the n+2 level GOA unit circuit, and the source is electrically connected to the n-2 level GOA unit
  • the charge sharing scanning signal of the circuit, the drain is electrically connected to the DC low voltage signal
  • the thirty-first transistor, the gate of the thirty-first transistor is electrically connected to the stage transmission signal of the n+2th GOA unit circuit
  • the source is electrically connected to the charging scan signal, and the drain is electrically connected to the DC low voltage signal
  • the forty-first transistor, the gate of the forty-first transistor is electrically connected to the n+2 level GOA unit circuit
  • the source is electrically connected to the first node, and the drain is electrically connected to the DC low-voltage signal.
  • the gate and source of the eleventh transistor are electrically connected to the start signal of the circuit, and only the second The drain of the eleven transistor outputs normally, and the drain of the twentieth transistor outputs a low potential.
  • the gate of the thirtieth transistor, the gate of the thirty-first transistor, and the forty-first transistor All gates are electrically connected to the start signal of the circuit.
  • the output waveform of the charging scan signal is controlled by the specifications of the twenty-first transistor; the output waveform of the charge sharing scan signal of the n-2th stage GOA unit circuit is controlled by the specifications of the twentieth transistor.
  • the four high-frequency clock signals are all divided into a charge scan output part and a charge sharing scan output part within one cycle; the charge scan output part of the M-th high-frequency clock signal is at a high potential for a time width greater than that of the M-2th high The charge-sharing scan output portion of the frequency clock signal is at a high level for the time width.
  • the M-2th high-frequency clock signal is the third high-frequency clock signal; when the M-th high-frequency clock signal When it is the second high-frequency clock signal, the M-2th high-frequency clock signal is the fourth high-frequency clock signal.
  • the potentials of the first and second low-frequency clock signals are inverted once every one or more frames.
  • the present invention also provides a charge scan and charge sharing scan dual-output GOA circuit, which includes a plurality of cascaded GOA unit circuits, first and second low-frequency clock signals, DC low-voltage signals, and first and second low-frequency clock signals, DC low-voltage signals, and peripherals of GOA unit circuits at various levels.
  • the n-th level GOA unit circuit receives the first and second low-frequency clock signals, DC low-voltage signals, the Mth and M-2th high-frequency clock signals, and the stage transfer signal generated by the n-2th level GOA unit circuit ,
  • the charge scan signal generated by the n-2th level GOA unit circuit and the level transfer signal generated by the n+2 level GOA unit circuit respectively output the charge scan signal and the charge of the n-2th level GOA unit circuit through different TFTs Sharing scanning signals and level transmission signals;
  • the n-th stage GOA unit circuit includes: a downstream module, a stage-transmission voltage stabilizing module, an output module, a fast pull-down module, and a pull-down maintenance module;
  • the output module includes a twentieth transistor, the gate of the twentieth transistor is electrically connected to the first node, the source is electrically connected to the M-2th high-frequency clock signal, and the drain outputs the nth The charge sharing scan signal of the -2 level GOA unit circuit; the twentieth transistor is used to output the charge of the n-2 level GOA unit circuit according to the M-2 high-frequency clock signal when the first node is at a high potential Share scan signal;
  • the twenty-first transistor, the gate of the twenty-first transistor is electrically connected to the first node, the source is electrically connected to the M-th high-frequency clock signal, and the drain outputs a charging scan signal;
  • the twenty-first transistor A transistor is used to output a charging scan signal according to the M-th high-frequency clock signal when the first node is at a high potential;
  • the twenty-second transistor, the gate of the twenty-second transistor is electrically connected to the first node, the source is electrically connected to the M-th high-frequency clock signal, and the drain output stage transmits signals; the twentieth The two transistors are used to transmit signals according to the M-th high-frequency clock signal output stage when the first node is at a high potential;
  • the output module further includes a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the charging scan signal;
  • the download module includes an eleventh transistor, the gate of the eleventh transistor is electrically connected to the stage transmission signal of the n-2th stage GOA unit circuit, and the source is electrically connected to the n-2th stage The drain of the charging scan signal of the GOA unit circuit is electrically connected to the first node;
  • the pull-down maintenance module includes a fifty-fifth transistor, a first pull-down maintenance module, and a second pull-down maintenance module;
  • the gate of the fifty-fifth transistor is electrically connected to the first node, the source is electrically connected to the second node, and the drain is electrically connected to the third node;
  • the first pull-down maintenance module includes a forty-second transistor.
  • the gate of the forty-second transistor is electrically connected to the second node, the source is electrically connected to the first node, and the drain is electrically connected to the DC A low voltage signal; a fifty-first transistor, the gate and source of the fifty-first transistor are electrically connected to the first low-frequency clock signal, and the drain is electrically connected to the gate of the fifty-third transistor; Fifty-third transistor, the gate of the fifty-third transistor is electrically connected to the fifty-first transistor To The drain, the source is electrically connected to the first low-frequency clock signal, and the drain is electrically connected to the second node; a fifty-fourth transistor, the gate of the fifty-fourth transistor is electrically connected to the second low-frequency clock signal , The source is electrically connected to the first low-frequency clock signal, and the drain is electrically connected to the second node; the thirty-second transistor, the gate of the thirty-second transistor is electrically connected to the second node, and the source is electrically
  • the second pull-down maintenance module includes a forty-third transistor.
  • the gate of the forty-third transistor is electrically connected to the third node, the source is electrically connected to the first node, and the drain is electrically connected to the DC low A voltage signal; a sixty-first transistor, the gate and source of the sixty-first transistor are electrically connected to the second low-frequency clock signal, and the drain is electrically connected to the gate of the sixty-third transistor; sixth A thirteenth transistor, the gate of the 63rd transistor is electrically connected to the drain of the 61st transistor, the source is electrically connected to the second low-frequency clock signal, and the drain is electrically connected to the third node; A sixty-four transistor, the gate of the sixty-fourth transistor is electrically connected to the first low-frequency clock signal, the source is electrically connected to the second low-frequency clock signal, and the drain is electrically connected to the third node; thirtieth Three transistors, the gate of the thirty-third transistor is electrically connected to the third node, the source is electrically
  • the cascade voltage stabilizing module includes a fifty-second transistor, the gate of the fifty-second transistor is electrically connected to the first node, the source is electrically connected to the second node, and the drain is electrically connected to the DC low A voltage signal; a sixty-second transistor, the gate of the sixty-second transistor is electrically connected to the first node, the source is electrically connected to the third node, and the drain is electrically connected to the DC low voltage signal; fifth A sixteenth transistor, the gate of the fifty-sixth crystal is electrically connected to the stage transmission signal of the n-2th stage GOA unit circuit, the source is electrically connected to the drain of the fifty-first transistor, and the drain is electrically connected Connected to a DC low voltage signal; a 66th transistor, the gate of the 66th crystal is electrically connected to the stage transmission signal of the n-2th GOA unit circuit, and the source is electrically connected to the 61st The drain of the transistor is electrically connected to the DC low voltage signal;
  • the fast pull-down module includes a thirtieth transistor, the gate of the thirtieth transistor is electrically connected to the level transmission signal of the n+2 level GOA unit circuit, and the source is electrically connected to the n-2 level GOA unit
  • the charge sharing scanning signal of the circuit, the drain is electrically connected to the DC low voltage signal
  • the thirty-first transistor, the gate of the thirty-first transistor is electrically connected to the stage transmission signal of the n+2th GOA unit circuit
  • the source is electrically connected to the charging scan signal, and the drain is electrically connected to the DC low voltage signal
  • the forty-first transistor, the gate of the forty-first transistor is electrically connected to the n+2 level GOA unit circuit
  • the four high-frequency clock signals are all divided into a charge scan output part and a charge sharing scan output part within one cycle; the charge scan output part of the M-th high-frequency clock signal is in To The time width of the high potential is greater than the time width of the charge sharing scan output part of the M-2th high-frequency clock signal at the high potential;
  • the potentials of the first and second low-frequency clock signals are inverted once every one or more frames.
  • the present invention provides a dual-output GOA circuit for charging scan and charge sharing scan, which combines timing and circuit to realize that at the same time, the charge scan signal and the charge sharing scan signal each pass through a TFT.
  • Two high-frequency clock signals are outputted, and the output waveforms of the charge scan signal and charge sharing scan signal can be controlled by the corresponding TFT specifications, which can reduce the instantaneous current of the IC, reduce the load of the IC, and improve the flexibility of reducing color shift design .
  • FIG. 1 is a multi-level architecture diagram of the dual-output GOA circuit of charge scanning and charge sharing scanning according to the present invention
  • FIG. 2 is a circuit diagram of the n-th stage GOA unit of the dual-output GOA circuit of charge scanning and charge sharing scanning according to the present invention
  • FIG. 3 is a circuit diagram of the first stage GOA unit of the dual-output GOA circuit of charge scanning and charge sharing scanning according to the present invention
  • FIG. 4 is a circuit diagram of the second stage GOA unit of the dual-output GOA circuit of charge scanning and charge sharing scanning according to the present invention
  • FIG. 5 is a circuit diagram of the second-to-last GOA unit of the dual-output GOA circuit of charge scanning and charge sharing scanning according to the present invention
  • FIG. 6 is a circuit diagram of the last stage GOA unit of the dual-output GOA circuit of charge scanning and charge sharing scanning according to the present invention.
  • FIG. 7 is a timing diagram of the dual-output GOA circuit of charge scanning and charge sharing scanning of the present invention.
  • the present invention provides a dual-output GOA circuit for charge scanning and charge sharing scanning.
  • the charge scan and charge sharing scan dual output GOA circuit includes a cascaded To Multiple GOA unit circuits, first and second low-frequency clock signals LC1, LC2, DC low-voltage signal Vss, and four high-frequency clock signals CK(1), CK(2), CK arranged on the periphery of GOA unit circuits at various levels (3) Metal wire of CK (4).
  • the n-th GOA unit circuit receives the first and second low-frequency clock signals LC1, LC2, the DC low-voltage signal Vss, the Mth and M-2th high-frequency clock signals CK(M), CK( M-2), the stage transfer signal ST(n-2) generated by the n-2th stage GOA unit circuit, the charging scan signal CG(n-2) generated by the n-2th stage GOA unit circuit, and the n+2th stage
  • the stage transfer signal ST(n+2) generated by the stage GOA unit circuit respectively outputs the charge scan signal CG(n), the charge sharing scan signal SG(n-2) of the n-2th stage GOA unit circuit through different TFTs, And the level transmission signal ST(n).
  • This structure can ensure that the GOA signal can be transferred step by step, so that the horizontal scan lines of each level can be charged and discharged step by step.
  • the four high-frequency clock signals CK(1), CK(2), CK(3), and CK(4) are all divided into a charging scan output part represented by a solid line and a dashed line in a cycle.
  • the charge-sharing scan output part of the M-th high-frequency clock signal CK(M) is at a high potential for a longer time than the charge-sharing scan output of the M-2th high-frequency clock signal CK(M-2) The time width during which the part is at a high potential.
  • the M-th high-frequency clock signal CK(M) is the first high-frequency clock signal CK(1)
  • the M-2th high-frequency clock signal CK(M-2) is the third high-frequency clock signal CK(M-2).
  • High-frequency clock signal CK(3) when the M-th high-frequency clock signal CK(M) is the second high-frequency clock signal CK(2), the M-2th high-frequency clock signal CK(M) -2) is the fourth high-frequency clock signal CK(4).
  • one stage receives the first high-frequency clock signal CK(1) and the third high-frequency clock signal CK(3), and the other stage receives the second high-frequency clock signal CK(2) and the fourth high-frequency clock signal CK(4).
  • the delay between the four high-frequency clock signals CK(1), CK(2), CK(3), and CK(4) is uncertain, which can be determined according to the liquid crystal display panel The actual resolution is determined, but the high potential overlap between adjacent high-frequency clock signals must be consistent.
  • the electric potentials of the first and second low-frequency clock signals LC1 and LC2 are inverted every one or more frames.
  • the n-th stage GOA unit circuit includes: a downstream module 100, a stage transmission voltage stabilizing module 200, an output module 300, a fast pull-down module 400, and a pull-down maintenance module 500.
  • the output module 300 includes a twentieth transistor T20, the gate of the twentieth transistor T20 is electrically connected to the first node Q(n), and the source is electrically connected to the M-2th high-frequency clock signal CK (M-2), the drain outputs the charge sharing scan signal SG(n-2) of the GOA unit circuit of the n-2th stage; the twentieth transistor T20 is used when the first node Q(n) is at a high potential , According to the M-2 high-frequency clock signal CK (M-2) to output the charge sharing scan signal of the n-2 level GOA unit circuit To SG(n-2), and the output waveform of the charge sharing scan signal SG(n-2) of the n-2th GOA unit circuit is controlled by the specifications of the twentieth transistor T20;
  • the twenty-first transistor T21, the gate of the twenty-first transistor T21 is electrically connected to the first node Q(n), the source is electrically connected to the M-th high-frequency clock signal CK(M), and the drain is Output the charge scan signal CG(n); the twenty-first transistor T21 is used to output the charge scan signal CG() according to the M-th high-frequency clock signal CK(M) when the first node Q(n) is at a high potential n), and the output waveform of the charging scan signal CG(n) is controlled by the specifications of the twenty-first transistor T21;
  • the twenty-second transistor T22 The gate of the twenty-second transistor T22 is electrically connected to the first node Q(n), the source is electrically connected to the M-th high-frequency clock signal CK(M), and the drain is The output stage transmission signal ST(n); the twenty-second transistor T22 is used to output the stage transmission signal ST( n);
  • the output module 300 further includes a capacitor Cb, one end of the capacitor Cb is electrically connected to the first node Q(n), and the other end is electrically connected to the charging scan signal CG(n).
  • the download module 100 includes an eleventh transistor T11, the gate of the eleventh transistor T11 is electrically connected to the stage transmission signal ST(n-2) of the n-2th stage GOA unit circuit, and the source is electrically connected
  • the charging scan signal CG(n-2) is connected to the GOA unit circuit of the n-2th stage, and the drain is electrically connected to the first node Q(n).
  • the pull-down maintenance module 500 includes a fifty-fifth transistor T55, a first pull-down maintenance module 501, and a second pull-down maintenance module 502.
  • the gate of the fifty-fifth transistor T55 is electrically connected to the first node Q(n)
  • the source is electrically connected to the second node P(n)
  • the drain is electrically connected to the third node K(n) .
  • the first pull-down maintenance module 501 includes a forty-second transistor T42, the gate of the forty-second transistor T42 is electrically connected to the second node P(n), and the source is electrically connected to the first node Q (n), the drain is electrically connected to the DC low voltage signal Vss; the fifty-first transistor T51, the gate and source of the fifty-first transistor T51 are electrically connected to the first low-frequency clock signal LC1, and the drain
  • the electrode is electrically connected to the gate of the fifty-third transistor T53; the fifty-third transistor T53, the gate of the fifty-third transistor T53 is electrically connected to the drain of the fifty-first transistor T51, and the source is electrically connected Is electrically connected to the first low-frequency clock signal LC1, and the drain is electrically connected to the second node P(n); a fifty-fourth transistor T54, and the gate of the fifty-fourth transistor T54 is electrically connected to the second low-frequency clock Signal LC2, the source is electrically connected to the first low-frequency
  • the second pull-down sustaining module 502 includes a forty-third transistor T43.
  • the gate of the forty-third transistor T43 is electrically connected to the third node K(n), and the source is electrically connected to the first node Q( n), the drain is electrically connected to the DC low voltage signal Vss;
  • the 61st crystal To Tube T61, the gate and source of the 61st transistor T61 are electrically connected to the second low-frequency clock signal LC2, and the drain is electrically connected to the gate of the 63rd transistor T63;
  • the 63rd transistor T63 the gate of the 63rd transistor T63 is electrically connected to the drain of the 61st transistor T61, the source is electrically connected to the second low-frequency clock signal LC2, and the drain is electrically connected to the third node K (n);
  • Sixty-fourth transistor T64, the gate of the sixty-fourth transistor T64 is electrically connected to the first low-frequency clock signal LC1, the source is electrically connected
  • the stage-pass voltage stabilization module 200 includes a fifty-second transistor T52.
  • the gate of the fifty-second transistor T52 is electrically connected to the first node Q(n), and the source of the fifty-second transistor T52 is electrically connected to the second node P( n), the drain is electrically connected to the DC low voltage signal Vss;
  • the sixty-second transistor T62 the gate of the sixty-second transistor T62 is electrically connected to the first node Q(n), and the source is electrically connected At the third node K(n), the drain is electrically connected to the DC low voltage signal Vss;
  • the fifty-sixth transistor T56 the gate of the fifty-sixth transistor T56 is electrically connected to the n-2th GOA unit
  • the stage transmission signal ST(n-2) of the circuit the source is electrically connected to the drain of the fifty-first transistor T51, and the drain is electrically connected to the DC low voltage signal Vss;
  • the sixty-sixth transistor T66 the first The gate of the sixty-s
  • the fast pull-down module 400 includes a thirtieth transistor T30, the gate of the thirtieth transistor T30 is electrically connected to the stage transmission signal ST(n+2) of the n+2 level GOA unit circuit, and the source is electrically connected The charge sharing scan signal SG(n-2) connected to the n-2th GOA unit circuit, the drain is electrically connected to the DC low voltage signal Vss; the thirty-first transistor T31, the thirty-first transistor T31 The gate is electrically connected to the stage transfer signal ST(n+2) of the n+2th GOA unit circuit, the source is electrically connected to the charging scan signal CG(n), and the drain is electrically connected to the DC low voltage signal Vss Forty-first transistor T41, the gate of the forty-first transistor T41 is electrically connected to the stage transfer signal ST(n+2) of the n+2 level GOA unit circuit, and the source is electrically connected to the first
  • the node Q(n) has a drain electrically connected to the DC low voltage signal Vs
  • the gate and source of the eleventh transistor T11 are electrically connected to the start signal STV of the circuit.
  • the drain of the twenty-first transistor T21 normally outputs the charging scan signal CG(1) of the first-stage GOA unit circuit, while the drain of the twenty-first transistor T20 has no output, that is, outputs a low potential.
  • the gate and source of the eleventh transistor T11 are electrically connected to the circuit To Only the drain of the twenty-first transistor T21 normally outputs the charging scan signal CG(2) of the second-stage GOA unit circuit, while the drain of the twentieth transistor T20 has no output, that is, The output is low.
  • the gate of the thirtieth transistor T30 and the thirty-first stage are both electrically connected to the start signal STV of the circuit.
  • FIG. 1, FIG. 2 and FIG. 7 Please refer to FIG. 1, FIG. 2 and FIG. 7 at the same time.
  • the specific working process of the dual-output GOA circuit of charge scanning and charge sharing scanning of the present invention is as follows:
  • the n-th stage GOA unit circuit receives the stage transfer signal ST(n-2) and the charging scan signal CG(n-2) from the n-2th stage GOA unit circuit. Due to the stage transfer signal of the n-2th stage GOA unit circuit The signal ST(n-2) and the charging scan signal CG(n-2) are both signals output according to the same high-frequency clock signal, so the stage transmission signal ST(n-2) of the n-2th stage GOA unit circuit and The charge scan signal CG(n-2) has the same timing and potential. When they are high, the eleventh transistor T11 is turned on and the first node Q(n) is charged.
  • the fifty-sixth transistor T56 and the sixty-sixth transistor T66 is turned on, pulling down the potentials of the second and third nodes P(n) and K(n); then the first node Q(n) is charged to a high potential, and the fiftieth node is controlled by the potential of the first node Q(n).
  • the second transistor T52, the sixty-second transistor T62 and the fifty-fifth transistor T55 are turned on to further lower the potentials of the second and third nodes P(n) and K(n).
  • the thirty-second transistor T32 and the thirty-second transistor The three transistors T33, the forty-second transistor T42, and the forty-third transistor T43 are turned off.
  • the twentieth transistor T20, the twenty-first transistor T21, and the twenty-second transistor T22, which are also controlled by the potential of the first node Q(n), are turned on.
  • the Mth and M-2th high-frequency clock signals CK (M) and CK (M-2) are both low potentials.
  • the n-th GOA unit circuit outputs the charging scan signal CG(n) and the stage transfer signal ST(n) according to the M-th high-frequency clock signal CK(M). ), and the charge sharing scan signal SG(n-2) of the GOA unit circuit of the n-2th stage output according to the M-2th high-frequency clock signal CK(M-2) are also low potentials.
  • the eleventh transistor T11 When the scan start signal ST(n-2) and the charge scan signal CG(n-2) of the n-2th stage GOA unit circuit are at a low level, the eleventh transistor T11 is turned off, and the first node Q(n) remains Is high, the twentieth transistor T20, the twenty-first transistor T21, and the twenty-second transistor T22 are still open; when the M and M-2 high-frequency clock signals CK(M), CK(M-2) When it becomes a high potential, the charge scan signal CG(n) outputted according to the M-th high-frequency clock signal CK(M), the stage transfer signal ST(n), and the M-2th high-frequency clock signal CK(M) -2) The output charge sharing scan signal SG(n-2) of the GOA unit circuit of the n-2th stage smoothly outputs a high potential.
  • the first node Q(n) rises to a higher potential, and the gate-source voltage (threshold voltage) Vgs of the twentieth transistor T20, the twenty-first transistor T21, and the twenty-second transistor T22 are basically constant, To To further maintain the smooth output of the charge scan signal CG(n), the stage transfer signal ST(n), and the charge sharing scan signal SG(n-2) of the n-2th stage GOA unit circuit.
  • the fifty-second transistor T52, the sixty-second transistor T62, the fifty-fifth transistor T55, the fifty-sixth transistor T56, and the sixty-sixth transistor T66 are turned on, pulling down the second node P(n) and the second node P(n).
  • the potential of the three node K(n), the thirty-second transistor T32, the thirty-third transistor T33, the forty-second transistor T42, and the forty-third transistor T43 are turned off to avoid the potential drop of the first node Q(n), It is ensured that the output of the charge scan signal CG(n), the stage transfer signal ST(n), and the charge sharing scan signal SG(n-2) of the n-2th stage GOA unit circuit are not affected.
  • the stage transmission signal ST(n+2) of the n+2th GOA unit circuit When it becomes a high potential, the 41st transistor T41, the 31st transistor T31 and the 30th transistor T30 are turned on, respectively pulling down the first node Q(n), the charging scan signal CG(n), and the stage transfer signal ST (n) and the potential of the charge sharing scan signal SG(n-2) of the GOA unit circuit of the n-2th stage; at the same time, the fifty-second transistor T52, the sixty-second T62 and the fifty-fifth transistor T55 are turned off; A low-frequency clock signal LC1 or a second low-frequency clock signal LC2 charges the second node P(n) or the third node K(n), and the second node P(n) or the third node K(n) is at a high potential.
  • the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 are inverted once, that is, the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 are alternately high, respectively
  • the node P(n) or the third node K(n) is charged
  • the thirty-second transistor T32 and the forty-second transistor T42 are a set
  • the thirty-third transistor T33 and the forty-third transistor T43 are alternately turned on
  • the first node Q(n) and the charging scan signal CG(n) are maintained at a low level.
  • the M-2 high-frequency clock signal CK(M-2) in the n-th stage GOA unit circuit outputs the charge sharing scan signal SG of the n-2th stage GOA unit circuit through the twentieth transistor T20 (n-2), the M-th high-frequency clock signal CK(M) outputs the stage transmission signal ST(n) and the charging scan signal CG(n) through the twenty-first transistor T21 and the twenty-second transistor T22, respectively, and adjust
  • the specifications of the twentieth transistor T20 and the twenty-first transistor T21 can change the output waveforms of the charge sharing scan signal SG(n-2) and the charge scan signal CG(n) of the GOA unit circuit of the n-2th stage.
  • the dual-output GOA circuit of charge scan and charge sharing scan of the present invention realizes that at the same time, the charge scan signal and the charge sharing scan signal are respectively output by two different high-frequency clock signals through a TFT.
  • the dual-output GOA circuit of charge scanning and charge sharing scanning of the present invention combines timing and circuit to realize that the charge scanning signal and the charge sharing scanning signal are each in the same time.
  • To Two different high-frequency clock signals are output through a TFT, and the output waveforms of the charge scan signal and charge sharing scan signal can be controlled by the specifications of the corresponding TFT, which can reduce the instantaneous current of the IC, reduce the load of the IC, and improve the reduction Color cast design flexibility.

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Abstract

一种充电扫描与电荷共享扫描双输出GOA电路，将时序与电路结合，第n级GOA单元电路接收第一、第二低频时钟信号(LC1、LC2)、直流低电压信号(Vss)、第M、第M-2条高频时钟信号(CK(M)、CK(M-2))、第n-2级GOA单元电路产生的级传信号(ST(n-2))、第n-2级GOA单元电路产生的充电扫描信号(CG(n-2))、及第n+2级GOA单元电路产生的级传信号(ST(n+2))、通过不同的TFT分别输出充电扫描信号(CG(n))、第n-2级GOA单元电路的电荷共享扫描信号(SG(n-2))、及级传信号(ST(n))；所述第n级GOA单元电路包括：下传模块(100)、级传稳压模块(200)、输出模块(300)、快速下拉模块(400)、及下拉维持模块(500)。

Description

充电扫描与电荷共享扫描双输出GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种充电扫描与电荷共享扫描双输出GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，其栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩的效果。目前主动式液晶显示面板水平扫描线的驱动主要由外接的集成电路板(Integrated Circuit，IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。而GOA技术(Gate Driver on Array)即阵列基板行驱动技术，可以运用液晶显示面板的原有制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接IC来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
现有的大尺寸LCD中，大视角下会发生严重的色偏现象，尤其在大尺寸的垂直配向(Vertical Alignment，VA)型的LCD中更为明显。为了改善大尺寸VA型液晶显示面板在大视角下出现的色偏现象，现有技术一般会采用电荷共享(Charge Share)的设计来降低色偏，每一级GOA电路通过一 条时序信号在同一时间输出充电扫描信号和电荷共享扫描信号(Charge &Share gate)，这样不仅会增加扫描线和时序信号线的负载，而且会降低扫描信号的输出质量，同时增加IC的压力。另一方面，由于充电扫描信号和电荷共享扫描信号由同一颗TFT输出，两者波形一致，不利于该TFT规格的合理设计。
发明内容
本发明的目的在于提供一种充电扫描与电荷共享扫描双输出GOA电路，能够实现在同一时间内，充电扫描信号和电荷共享扫描信号各通过一个TFT分别由不同的两条高频时钟信号输出，并且充电扫描信号和电荷共享扫描信号的输出波形可由相应的TFT的规格进行控制，能够减小IC瞬间电流，降低IC的负载，提高降低色偏设计的灵活性。
为实现上述目的，本发明提供一种充电扫描与电荷共享扫描双输出GOA电路，包括级联的多个GOA单元电路、设置于各级GOA单元电路外围的第一、第二低频时钟信号、直流低电压信号、以及四条高频时钟信号的金属线；设n为正整数，第n级GOA单元电路接收第一、第二低频时钟信号、直流低电压信号、第M、第M-2条高频时钟信号、第n-2级GOA单元电路产生的级传信号、第n-2级GOA单元电路产生的充电扫描信号、及第n+2级GOA单元电路产生的级传信号，通过不同的TFT分别输出充电扫描信号、第n-2级GOA单元电路的电荷共享扫描信号、及级传信号；
所述第n级GOA单元电路包括：下传模块、级传稳压模块、输出模块、快速下拉模块、及下拉维持模块。
所述输出模块包括第二十晶体管，所述第二十晶体管的栅极电性连接于第一节点，源极电性连接于第M-2条高频时钟信号，漏极输出第n-2级GOA单元电路的电荷共享扫描信号；所述第二十晶体管用于在第一节点处于高电位时，依据第M-2条高频时钟信号输出第n-2级GOA单元电路的电荷共享扫描信号；
第二十一晶体管，所述第二十一晶体管的栅极电性连接于第一节点，源极电性连接于第M条高频时钟信号，漏极输出充电扫描信号；所述第二十一晶体管用于在第一节点处于高电位时，依据第M条高频时钟信号输出充电扫描信号；
第二十二晶体管，所述第二十二晶体管的栅极电性连接于第一节点，源极电性连接于第M条高频时钟信号，漏极输出级传信号；所述第二十二晶体管用于在第一节点处于高电位时，依据第M条高频时钟信号输出级传 信号。
所述输出模块还包括一电容，所述电容的一端电性连接于第一节点，另一端电性连接于充电扫描信号。
所述下传模块包括第十一晶体管，所述第十一晶体管的栅极电性连接于第n-2级GOA单元电路的级传信号，源极电性连接于第n-2级GOA单元电路的充电扫描信号，漏极电性连接于第一节点；
所述下拉维持模块包括第五十五晶体管、第一下拉维持模块、与第二下拉维持模块；
所述第五十五晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第三节点；
所述第一下拉维持模块包括第四十二晶体管，所述第四十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于直流低电压信号；第五十一晶体管，所述第五十一晶体管的栅极与源极均电性连接于第一低频时钟信号，漏极电性连接于第五十三晶体管的栅极；第五十三晶体管，所述第五十三晶体管的栅极电性连接于第五十一晶体管的漏极，源极电性连接于第一低频时钟信号，漏极电性连接于第二节点；第五十四晶体管，所述第五十四晶体管的栅极电性连接于第二低频时钟信号，源极电性连接于第一低频时钟信号，漏极电性连接于第二节点；第三十二晶体管，所述第三十二晶体管的栅极电性连接于第二节点，源极电性连接于充电扫描信号，漏极电性连接于直流低电压信号；
所述第二下拉维持模块包括第四十三晶体管，所述第四十三晶体管的栅极电性连接于第三节点，源极电性连接于第一节点，漏极电性连接于直流低电压信号；第六十一晶体管，所述第六十一晶体管的栅极与源极均电性连接于第二低频时钟信号，漏极电性连接于第六十三晶体管的栅极；第六十三晶体管，所述第六十三晶体管的栅极电性连接于第六十一晶体管的漏极，源极电性连接于第二低频时钟信号，漏极电性连接于第三节点；第六十四晶体管，所述第六十四晶体管的栅极电性连接于第一低频时钟信号，源极电性连接于第二低频时钟信号，漏极电性连接于第三节点；第三十三晶体管，所述第三十三晶体管的栅极电性连接于第三节点，源极电性连接于充电扫描信号，漏极电性连接于直流低电压信号；
所述级传稳压模块包括第五十二晶体管，所述第五十二晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于直流低电压信号；第六十二晶体管，所述第六十二晶体管的栅极电性连接于第一节点，源极电性连接于第三节点，漏极电性连接于直流低电压信号；第五 十六晶体管，所述第五十六晶体的栅极电性连接于第n-2级GOA单元电路的级传信号，源极电性连接于第五十一晶体管的漏极，漏极电性连接于直流低电压信号；第六十六晶体管，所述第六十六晶体的栅极电性连接于第n-2级GOA单元电路的级传信号，源极电性连接于第六十一晶体管的漏极，漏极电性连接于直流低电压信号；
所述快速下拉模块包括第三十晶体管，所述第三十晶体管的栅极电性连接于第n+2级GOA单元电路的级传信号，源极电性连接于第n-2级GOA单元电路的电荷共享扫描信号，漏极电性连接于直流低电压信号；第三十一晶体管，所述第三十一晶体管的栅极电性连接于第n+2级GOA单元电路的级传信号，源极电性连接于充电扫描信号，漏极电性连接于直流低电压信号；第四十一晶体管，所述第四十一晶体管的栅极电性连接于第n+2级GOA单元电路的级传信号，源极电性连接于第一节点，漏极电性连接于直流低电压信号。
该充电扫描与电荷共享扫描双输出GOA电路的第一级及第二级的连接关系中，第十一晶体管的栅极与源极均电性连接于电路的启始信号，仅所述第二十一晶体管的漏极正常输出，所述第二十晶体管的漏极输出低电位。
该充电扫描与电荷共享扫描双输出GOA电路的最后一级及倒数第二级的连接关系中，所述第三十晶体管的栅极、第三十一晶体管的栅极、及第四十一晶体管的栅极均电性连接于电路的启始信号。
所述充电扫描信号的输出波形由第二十一晶体管的规格进行控制；所述第n-2级GOA单元电路的电荷共享扫描信号的输出波形由第二十晶体管的规格进行控制。
所述四条高频时钟信号均在一个周期内分为充电扫描输出部分和电荷共享扫描输出部分；第M条高频时钟信号的充电扫描输出部分处于高电位的时间宽度大于第M-2条高频时钟信号的电荷共享扫描输出部分处于高电位的时间宽度。
当所述第M条高频时钟信号为第一条高频时钟信号时，所述第M-2条高频时钟信号为第三条高频时钟信号；当所述第M条高频时钟信号为第二条高频时钟信号时，所述第M-2条高频时钟信号为第四条高频时钟信号。
所述第一、第二低频时钟信号的电位每隔一帧或多帧反转一次。
本发明还提供一种充电扫描与电荷共享扫描双输出GOA电路，包括级联的多个GOA单元电路、设置于各级GOA单元电路外围的第一、第二低频时钟信号、直流低电压信号、以及四条高频时钟信号的金属线；设n为 正整数，第n级GOA单元电路接收第一、第二低频时钟信号、直流低电压信号、第M、第M-2条高频时钟信号、第n-2级GOA单元电路产生的级传信号、第n-2级GOA单元电路产生的充电扫描信号、及第n+2级GOA单元电路产生的级传信号，通过不同的TFT分别输出充电扫描信号、第n-2级GOA单元电路的电荷共享扫描信号、及级传信号；
所述第n级GOA单元电路包括：下传模块、级传稳压模块、输出模块、快速下拉模块、及下拉维持模块；
其中，所述输出模块包括第二十晶体管，所述第二十晶体管的栅极电性连接于第一节点，源极电性连接于第M-2条高频时钟信号，漏极输出第n-2级GOA单元电路的电荷共享扫描信号；所述第二十晶体管用于在第一节点处于高电位时，依据第M-2条高频时钟信号输出第n-2级GOA单元电路的电荷共享扫描信号；
第二十一晶体管，所述第二十一晶体管的栅极电性连接于第一节点，源极电性连接于第M条高频时钟信号，漏极输出充电扫描信号；所述第二十一晶体管用于在第一节点处于高电位时，依据第M条高频时钟信号输出充电扫描信号；
第二十二晶体管，所述第二十二晶体管的栅极电性连接于第一节点，源极电性连接于第M条高频时钟信号，漏极输出级传信号；所述第二十二晶体管用于在第一节点处于高电位时，依据第M条高频时钟信号输出级传信号；
其中，所述输出模块还包括一电容，所述电容的一端电性连接于第一节点，另一端电性连接于充电扫描信号；
其中，所述下传模块包括第十一晶体管，所述第十一晶体管的栅极电性连接于第n-2级GOA单元电路的级传信号，源极电性连接于第n-2级GOA单元电路的充电扫描信号，漏极电性连接于第一节点；
所述下拉维持模块包括第五十五晶体管、第一下拉维持模块、与第二下拉维持模块；
所述第五十五晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第三节点；
所述第一下拉维持模块包括第四十二晶体管，所述第四十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于直流低电压信号；第五十一晶体管，所述第五十一晶体管的栅极与源极均电性连接于第一低频时钟信号，漏极电性连接于第五十三晶体管的栅极；第五十三晶体管，所述第五十三晶体管的栅极电性连接于第五十一晶体管的 漏极，源极电性连接于第一低频时钟信号，漏极电性连接于第二节点；第五十四晶体管，所述第五十四晶体管的栅极电性连接于第二低频时钟信号，源极电性连接于第一低频时钟信号，漏极电性连接于第二节点；第三十二晶体管，所述第三十二晶体管的栅极电性连接于第二节点，源极电性连接于充电扫描信号，漏极电性连接于直流低电压信号；
所述第二下拉维持模块包括第四十三晶体管，所述第四十三晶体管的栅极电性连接于第三节点，源极电性连接于第一节点，漏极电性连接于直流低电压信号；第六十一晶体管，所述第六十一晶体管的栅极与源极均电性连接于第二低频时钟信号，漏极电性连接于第六十三晶体管的栅极；第六十三晶体管，所述第六十三晶体管的栅极电性连接于第六十一晶体管的漏极，源极电性连接于第二低频时钟信号，漏极电性连接于第三节点；第六十四晶体管，所述第六十四晶体管的栅极电性连接于第一低频时钟信号，源极电性连接于第二低频时钟信号，漏极电性连接于第三节点；第三十三晶体管，所述第三十三晶体管的栅极电性连接于第三节点，源极电性连接于充电扫描信号，漏极电性连接于直流低电压信号；
所述级传稳压模块包括第五十二晶体管，所述第五十二晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于直流低电压信号；第六十二晶体管，所述第六十二晶体管的栅极电性连接于第一节点，源极电性连接于第三节点，漏极电性连接于直流低电压信号；第五十六晶体管，所述第五十六晶体的栅极电性连接于第n-2级GOA单元电路的级传信号，源极电性连接于第五十一晶体管的漏极，漏极电性连接于直流低电压信号；第六十六晶体管，所述第六十六晶体的栅极电性连接于第n-2级GOA单元电路的级传信号，源极电性连接于第六十一晶体管的漏极，漏极电性连接于直流低电压信号；
所述快速下拉模块包括第三十晶体管，所述第三十晶体管的栅极电性连接于第n+2级GOA单元电路的级传信号，源极电性连接于第n-2级GOA单元电路的电荷共享扫描信号，漏极电性连接于直流低电压信号；第三十一晶体管，所述第三十一晶体管的栅极电性连接于第n+2级GOA单元电路的级传信号，源极电性连接于充电扫描信号，漏极电性连接于直流低电压信号；第四十一晶体管，所述第四十一晶体管的栅极电性连接于第n+2级GOA单元电路的级传信号，源极电性连接于第一节点，漏极电性连接于直流低电压信号；
其中，所述四条高频时钟信号均在一个周期内分为充电扫描输出部分和电荷共享扫描输出部分；第M条高频时钟信号的充电扫描输出部分处于 高电位的时间宽度大于第M-2条高频时钟信号的电荷共享扫描输出部分处于高电位的时间宽度；
其中，所述第一、第二低频时钟信号的电位每隔一帧或多帧反转一次。
本发明的有益效果：本发明提供的一种充电扫描与电荷共享扫描双输出GOA电路，将时序和电路结合，实现在同一时间内，充电扫描信号和电荷共享扫描信号各通过一个TFT分别由不同的两条高频时钟信号输出，并且充电扫描信号和电荷共享扫描信号的输出波形可由相应的TFT的规格进行控制，能够减小IC瞬间电流，降低IC的负载，提高降低色偏设计的灵活性。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明充电扫描与电荷共享扫描双输出GOA电路的多级架构图；
图2为本发明充电扫描与电荷共享扫描双输出GOA电路的第n级GOA单元的电路图；
图3为本发明充电扫描与电荷共享扫描双输出GOA电路的第一级GOA单元的电路图；
图4为本发明充电扫描与电荷共享扫描双输出GOA电路的第二级GOA单元的电路图；
图5为本发明充电扫描与电荷共享扫描双输出GOA电路的倒数第二级GOA单元的电路图；
图6为本发明充电扫描与电荷共享扫描双输出GOA电路的最后一级GOA单元的电路图；
图7为本发明充电扫描与电荷共享扫描双输出GOA电路的时序图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图1、图2、图7，本发明提供一种充电扫描与电荷共享扫描双输出GOA电路。
如图1所示，该充电扫描与电荷共享扫描双输出GOA电路包括级联的 多个GOA单元电路、设置于各级GOA单元电路外围的第一、第二低频时钟信号LC1、LC2、直流低电压信号Vss、以及四条高频时钟信号CK(1)、CK(2)、CK(3)、CK(4)的金属线。设n为正整数，第n级GOA单元电路接收第一、第二低频时钟信号LC1、LC2、直流低电压信号Vss、第M、第M-2条高频时钟信号CK(M)、CK(M-2)、第n-2级GOA单元电路产生的级传信号ST(n-2)、第n-2级GOA单元电路产生的充电扫描信号CG(n-2)、及第n+2级GOA单元电路产生的级传信号ST(n+2)，通过不同的TFT分别输出充电扫描信号CG(n)、第n-2级GOA单元电路的电荷共享扫描信号SG(n-2)、及级传信号ST(n)。这种结构方式能够保证GOA信号可以逐级传递，使得各级水平扫描线可以被逐级充电和放电。
结合图7，所述四条高频时钟信号CK(1)、CK(2)、CK(3)、CK(4)均在一个周期内分为由实线表示的充电扫描输出部分和由虚线表示的电荷共享扫描输出部分；第M条高频时钟信号CK(M)的充电扫描输出部分处于高电位的时间宽度大于第M-2条高频时钟信号CK(M-2)的电荷共享扫描输出部分处于高电位的时间宽度。当所述第M条高频时钟信号CK(M)为第一条高频时钟信号CK(1)时，所述第M-2条高频时钟信号CK(M-2)为第三条高频时钟信号CK(3)；当所述第M条高频时钟信号CK(M)为第二条高频时钟信号CK(2)时，所述第M-2条高频时钟信号CK(M-2)为第四条高频时钟信号CK(4)。对于相邻的两级GOA单元电路，其中一级接收第一条高频时钟信号CK(1)与第三条高频时钟信号CK(3)，另一级则接收第二条高频时钟信号CK(2)与第四条高频时钟信号CK(4)。对于不同分辨率的液晶显示面板，所述四条高频时钟信号CK(1)、CK(2)、CK(3)、CK(4)之间的延时是不确定的，可根据液晶显示面板的实际分辨率来确定，但相邻的高频时钟信号间的高电位交叠必须一致。
所述第一、第二低频时钟信号LC1、LC2的电位每隔一帧或多帧反转一次。
进一步的，如图2所示，所述第n级GOA单元电路包括：下传模块100、级传稳压模块200、输出模块300、快速下拉模块400、及下拉维持模块500。
所述输出模块300包括第二十晶体管T20，所述第二十晶体管T20的栅极电性连接于第一节点Q(n)，源极电性连接于第M-2条高频时钟信号CK(M-2)，漏极输出第n-2级GOA单元电路的电荷共享扫描信号SG(n-2)；所述第二十晶体管T20用于在第一节点Q(n)处于高电位时，依据第M-2条高频时钟信号CK(M-2)输出第n-2级GOA单元电路的电荷共享扫描信号 SG(n-2)，且所述第n-2级GOA单元电路的电荷共享扫描信号SG(n-2)的输出波形由第二十晶体管T20的规格进行控制；
第二十一晶体管T21，所述第二十一晶体管T21的栅极电性连接于第一节点Q(n)，源极电性连接于第M条高频时钟信号CK(M)，漏极输出充电扫描信号CG(n)；所述第二十一晶体管T21用于在第一节点Q(n)处于高电位时，依据第M条高频时钟信号CK(M)输出充电扫描信号CG(n)，且所述充电扫描信号CG(n)的输出波形由第二十一晶体管T21的规格进行控制；
第二十二晶体管T22，所述第二十二晶体管T22的栅极电性连接于第一节点Q(n)，源极电性连接于第M条高频时钟信号CK(M)，漏极输出级传信号ST(n)；所述第二十二晶体管T22用于在第一节点Q(n)处于高电位时，依据第M条高频时钟信号CK(M)输出级传信号ST(n)；
所述输出模块300还包括一电容Cb，所述电容Cb的一端电性连接于第一节点Q(n)，另一端电性连接于充电扫描信号CG(n)。
所述下传模块100包括第十一晶体管T11，所述第十一晶体管T11的栅极电性连接于第n-2级GOA单元电路的级传信号ST(n-2)，源极电性连接于第n-2级GOA单元电路的充电扫描信号CG(n-2)，漏极电性连接于第一节点Q(n)。
所述下拉维持模块500包括第五十五晶体管T55、第一下拉维持模块501、与第二下拉维持模块502。所述第五十五晶体管T55的栅极电性连接于第一节点Q(n)，源极电性连接于第二节点P(n)，漏极电性连接于第三节点K(n)。所述第一下拉维持模块501包括第四十二晶体管T42，所述第四十二晶体管T42的栅极电性连接于第二节点P(n)，源极电性连接于第一节点Q(n)，漏极电性连接于直流低电压信号Vss；第五十一晶体管T51，所述第五十一晶体管T51的栅极与源极均电性连接于第一低频时钟信号LC1，漏极电性连接于第五十三晶体管T53的栅极；第五十三晶体管T53，所述第五十三晶体管T53的栅极电性连接于第五十一晶体管T51的漏极，源极电性连接于第一低频时钟信号LC1，漏极电性连接于第二节点P(n)；第五十四晶体管T54，所述第五十四晶体管T54的栅极电性连接于第二低频时钟信号LC2，源极电性连接于第一低频时钟信号LC1，漏极电性连接于第二节点P(n)；第三十二晶体管T32，所述第三十二晶体管T32的栅极电性连接于第二节点P(n)，源极电性连接于充电扫描信号CG(n)，漏极电性连接于直流低电压信号Vss。所述第二下拉维持模块502包括第四十三晶体管T43，所述第四十三晶体管T43的栅极电性连接于第三节点K(n)，源极电性连接于第一节点Q(n)，漏极电性连接于直流低电压信号Vss；第六十一晶体 管T61，所述第六十一晶体管T61的栅极与源极均电性连接于第二低频时钟信号LC2，漏极电性连接于第六十三晶体管T63的栅极；第六十三晶体管T63，所述第六十三晶体管T63的栅极电性连接于第六十一晶体管T61的漏极，源极电性连接于第二低频时钟信号LC2，漏极电性连接于第三节点K(n)；第六十四晶体管T64，所述第六十四晶体管T64的栅极电性连接于第一低频时钟信号LC1，源极电性连接于第二低频时钟信号LC2，漏极电性连接于第三节点K(n)；第三十三晶体管T33，所述第三十三晶体管T33的栅极电性连接于第三节点K(n)，源极电性连接于充电扫描信号CG(n)，漏极电性连接于直流低电压信号Vss。
所述级传稳压模块200包括第五十二晶体管T52，所述第五十二晶体管T52的栅极电性连接于第一节点Q(n)，源极电性连接于第二节点P(n)，漏极电性连接于直流低电压信号Vss；第六十二晶体管T62，所述第六十二晶体管T62的栅极电性连接于第一节点Q(n)，源极电性连接于第三节点K(n)，漏极电性连接于直流低电压信号Vss；第五十六晶体管T56，所述第五十六晶体T56的栅极电性连接于第n-2级GOA单元电路的级传信号ST(n-2)，源极电性连接于第五十一晶体管T51的漏极，漏极电性连接于直流低电压信号Vss；第六十六晶体管T66，所述第六十六晶体T66的栅极电性连接于第n-2级GOA单元电路的级传信号ST(n-2)，源极电性连接于第六十一晶体管T61的漏极，漏极电性连接于直流低电压信号Vss。
所述快速下拉模块400包括第三十晶体管T30，所述第三十晶体管T30的栅极电性连接于第n+2级GOA单元电路的级传信号ST(n+2)，源极电性连接于第n-2级GOA单元电路的电荷共享扫描信号SG(n-2)，漏极电性连接于直流低电压信号Vss；第三十一晶体管T31，所述第三十一晶体管T31的栅极电性连接于第n+2级GOA单元电路的级传信号ST(n+2)，源极电性连接于充电扫描信号CG(n)，漏极电性连接于直流低电压信号Vss；第四十一晶体管T41，所述第四十一晶体管T41的栅极电性连接于第n+2级GOA单元电路的级传信号ST(n+2)，源极电性连接于第一节点Q(n)，漏极电性连接于直流低电压信号Vss。
特别的，如图3所示，该充电扫描与电荷共享扫描双输出GOA电路的第一级连接关系中，第十一晶体管T11的栅极与源极均电性连接于电路的启始信号STV，仅所述第二十一晶体管T21的漏极正常输出第一级GOA单元电路的充电扫描信号CG(1)，而所述第二十晶体管T20的漏极无输出，即输出低电位。如图4所示，该充电扫描与电荷共享扫描双输出GOA电路的第二级连接关系中，第十一晶体管T11的栅极与源极均电性连接于电路 的启始信号STV，仅所述第二十一晶体管T21的漏极正常输出第二级GOA单元电路的充电扫描信号CG(2)，而所述第二十晶体管T20的漏极无输出，即输出低电位。
如图5、图6所示，该充电扫描与电荷共享扫描双输出GOA电路的最后一级及倒数第二级的的连接关系中，所述第三十晶体管T30的栅极、第三十一晶体管T31的栅极、及第四十一晶体管T41的栅极均电性连接于电路的启始信号STV。
请同时参阅图1、图2与图7，本发明的充电扫描与电荷共享扫描双输出GOA电路的具体工作过程为：
第n级GOA单元电路接收来自于第n-2级GOA单元电路的级传信号ST(n-2)和充电扫描信号CG(n-2)，由于第n-2级GOA单元电路的级传信号ST(n-2)和充电扫描信号CG(n-2)均为依据同一条高频时钟信号输出的信号，因此第n-2级GOA单元电路的级传信号ST(n-2)和充电扫描信号CG(n-2)时序和电位相同，当它们为高电位时，第十一晶体管T11打开，第一节点Q(n)充电，同时第五十六晶体管T56和第六十六晶体管T66打开，拉低第二、第三节点P(n)、K(n)的电位；随后第一节点Q(n)充电为高电位，受第一节点Q(n)电位控制的第五十二晶体管T52、第六十二晶体管T62和第五十五晶体管T55打开，进一步拉低第二、第三节点P(n)、K(n)的电位，第三十二晶体管T32、第三十三晶体管T33、第四十二晶体管T42和第四十三晶体管T43关闭。同时，同样受第一节点Q(n)电位控制的第二十晶体管T20、第二十一晶体管T21和第二十二晶体管T22打开，此时第M、第M-2条高频时钟信号CK(M)、CK(M-2)均为低电位，该第n级GOA单元电路依据第M条高频时钟信号CK(M)输出的充电扫描信号CG(n)、级传信号ST(n)、以及依据第M-2条高频时钟信号CK(M-2)输出的第n-2级GOA单元电路的电荷共享扫描信号SG(n-2)也均为低电位。
当第n-2级GOA单元电路的扫描启动信号ST(n-2)和充电扫描信号CG(n-2)为低电位时，第十一晶体管T11关闭，第一节点Q(n)仍保持为高电位，第二十晶体管T20、第二十一晶体管T21和第二十二晶体管T22仍打开；当第M、第M-2条高频时钟信号CK(M)、CK(M-2)变为高电位时，依据第M条高频时钟信号CK(M)输出的充电扫描信号CG(n)、级传信号ST(n)、以及依据第M-2条高频时钟信号CK(M-2)输出的第n-2级GOA单元电路的电荷共享扫描信号SG(n-2)顺利输出高电位。同时在电容Cb耦合下，第一节点Q(n)抬升到更高电位，第二十晶体管T20、第二十一晶体管T21和第二十二晶体管T22的栅源极电压(阈值电压)Vgs基本保持不变， 进一步保持充电扫描信号CG(n)、级传信号ST(n)以及第n-2级GOA单元电路的电荷共享扫描信号SG(n-2)的顺利输出。进一步的，第五十二晶体管T52、第六十二晶体管T62、第五十五晶体T55、第五十六晶体管T56和第六十六晶体管T66打开，拉低第二节点P(n)、第三节点K(n)的电位，第三十二晶体管T32、第三十三晶体管T33、第四十二晶体管T42和第四十三晶体管T43关闭，避免第一节点Q(n)的电位下降，保证充电扫描信号CG(n)、级传信号ST(n)以及第n-2级GOA单元电路的电荷共享扫描信号SG(n-2)的输出不受影响。
接下来，当第M、第M-2条高频时钟信号CK(M)、CK(M-2)变为低电位，第n+2级GOA单元电路的级传信号ST(n+2)变为高电位时，第四十一晶体管T41、第三十一晶体管T31和第三十晶体T30打开，分别拉低第一节点Q(n)、充电扫描信号CG(n)、级传信号ST(n)以及第n-2级GOA单元电路的电荷共享扫描信号SG(n-2)的电位；同时，第五十二晶体管T52、第六十二T62和第五十五晶体管T55关闭；第一低频时钟信号LC1或第二低频时钟信号LC2对第二节点P(n)或第三节点K(n)充电，第二节点P(n)或第三节点K(n)为高电位，第三十二晶体管T32和第四十二晶体管T42或第三十三晶体管T33和第四十三晶体管T43打开，分别拉低第一节点Q(n)和充电扫描信号CG(n)的电位。
当一帧或多帧显示完成后，第一低频时钟信号LC1与第二低频时钟信号LC2反转一次，即第一低频时钟信号LC1与第二低频时钟信号LC2交替为高电位，分别对第二节点P(n)或第三节点K(n)充电，第三十二晶体管T32和第四十二晶体管T42为一组、第三十三晶体管T33和第四十三晶体管T43为一组交替打开，维持第一节点Q(n)和充电扫描信号CG(n)为低电位。
值得一提的是，在第n级GOA单元电路中第M-2条高频时钟信号CK(M-2)通过第二十晶体管T20输出第n-2级GOA单元电路的电荷共享扫描信号SG(n-2)，第M条高频时钟信号CK(M)通过第二十一晶体管T21和第二十二晶体管T22分别输出级传信号ST(n)和充电扫描信号CG(n)，调节第二十晶体管T20和第二十一晶体管T21的规格可以改变第n-2级GOA单元电路的电荷共享扫描信号SG(n-2)和充电扫描信号CG(n)的输出波形。
如图7所示，本发明的充电扫描与电荷共享扫描双输出GOA电路实现了在同一时间内，充电扫描信号和电荷共享扫描信号各通过一个TFT分别由不同的两条高频时钟信号输出。
综上所述，本发明的充电扫描与电荷共享扫描双输出GOA电路，将时序和电路结合，实现在同一时间内，充电扫描信号和电荷共享扫描信号各 通过一个TFT分别由不同的两条高频时钟信号输出，并且充电扫描信号和电荷共享扫描信号的输出波形可由相应的TFT的规格进行控制，能够减小IC瞬间电流，降低IC的负载，提高降低色偏设计的灵活性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (15)

  1. 一种充电扫描与电荷共享扫描双输出GOA电路，包括级联的多个GOA单元电路、设置于各级GOA单元电路外围的第一、第二低频时钟信号、直流低电压信号、以及四条高频时钟信号的金属线；设n为正整数，第n级GOA单元电路接收第一、第二低频时钟信号、直流低电压信号、第M、第M-2条高频时钟信号、第n-2级GOA单元电路产生的级传信号、第n-2级GOA单元电路产生的充电扫描信号、及第n+2级GOA单元电路产生的级传信号，通过不同的TFT分别输出充电扫描信号、第n-2级GOA单元电路的电荷共享扫描信号、及级传信号；
    所述第n级GOA单元电路包括：下传模块、级传稳压模块、输出模块、快速下拉模块、及下拉维持模块。
  2. 如权利要求1所述的充电扫描与电荷共享扫描双输出GOA电路，其中，所述输出模块包括第二十晶体管，所述第二十晶体管的栅极电性连接于第一节点，源极电性连接于第M-2条高频时钟信号，漏极输出第n-2级GOA单元电路的电荷共享扫描信号；所述第二十晶体管用于在第一节点处于高电位时，依据第M-2条高频时钟信号输出第n-2级GOA单元电路的电荷共享扫描信号；
    第二十一晶体管，所述第二十一晶体管的栅极电性连接于第一节点，源极电性连接于第M条高频时钟信号，漏极输出充电扫描信号；所述第二十一晶体管用于在第一节点处于高电位时，依据第M条高频时钟信号输出充电扫描信号；
    第二十二晶体管，所述第二十二晶体管的栅极电性连接于第一节点，源极电性连接于第M条高频时钟信号，漏极输出级传信号；所述第二十二晶体管用于在第一节点处于高电位时，依据第M条高频时钟信号输出级传信号。
  3. 如权利要求2所述的充电扫描与电荷共享扫描双输出GOA电路，其中，所述输出模块还包括一电容，所述电容的一端电性连接于第一节点，另一端电性连接于充电扫描信号。
  4. 如权利要求2所述的充电扫描与电荷共享扫描双输出GOA电路，其中，所述下传模块包括第十一晶体管，所述第十一晶体管的栅极电性连接于第n-2级GOA单元电路的级传信号，源极电性连接于第n-2级GOA单元电路的充电扫描信号，漏极电性连接于第一节点；
    所述下拉维持模块包括第五十五晶体管、第一下拉维持模块、与第二下拉维持模块；
    所述第五十五晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第三节点；
    所述第一下拉维持模块包括第四十二晶体管，所述第四十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于直流低电压信号；第五十一晶体管，所述第五十一晶体管的栅极与源极均电性连接于第一低频时钟信号，漏极电性连接于第五十三晶体管的栅极；第五十三晶体管，所述第五十三晶体管的栅极电性连接于第五十一晶体管的漏极，源极电性连接于第一低频时钟信号，漏极电性连接于第二节点；第五十四晶体管，所述第五十四晶体管的栅极电性连接于第二低频时钟信号，源极电性连接于第一低频时钟信号，漏极电性连接于第二节点；第三十二晶体管，所述第三十二晶体管的栅极电性连接于第二节点，源极电性连接于充电扫描信号，漏极电性连接于直流低电压信号；
    所述第二下拉维持模块包括第四十三晶体管，所述第四十三晶体管的栅极电性连接于第三节点，源极电性连接于第一节点，漏极电性连接于直流低电压信号；第六十一晶体管，所述第六十一晶体管的栅极与源极均电性连接于第二低频时钟信号，漏极电性连接于第六十三晶体管的栅极；第六十三晶体管，所述第六十三晶体管的栅极电性连接于第六十一晶体管的漏极，源极电性连接于第二低频时钟信号，漏极电性连接于第三节点；第六十四晶体管，所述第六十四晶体管的栅极电性连接于第一低频时钟信号，源极电性连接于第二低频时钟信号，漏极电性连接于第三节点；第三十三晶体管，所述第三十三晶体管的栅极电性连接于第三节点，源极电性连接于充电扫描信号，漏极电性连接于直流低电压信号；
    所述级传稳压模块包括第五十二晶体管，所述第五十二晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于直流低电压信号；第六十二晶体管，所述第六十二晶体管的栅极电性连接于第一节点，源极电性连接于第三节点，漏极电性连接于直流低电压信号；第五十六晶体管，所述第五十六晶体的栅极电性连接于第n-2级GOA单元电路的级传信号，源极电性连接于第五十一晶体管的漏极，漏极电性连接于直流低电压信号；第六十六晶体管，所述第六十六晶体的栅极电性连接于第n-2级GOA单元电路的级传信号，源极电性连接于第六十一晶体管的漏极，漏极电性连接于直流低电压信号；
    所述快速下拉模块包括第三十晶体管，所述第三十晶体管的栅极电性 连接于第n+2级GOA单元电路的级传信号，源极电性连接于第n-2级GOA单元电路的电荷共享扫描信号，漏极电性连接于直流低电压信号；第三十一晶体管，所述第三十一晶体管的栅极电性连接于第n+2级GOA单元电路的级传信号，源极电性连接于充电扫描信号，漏极电性连接于直流低电压信号；第四十一晶体管，所述第四十一晶体管的栅极电性连接于第n+2级GOA单元电路的级传信号，源极电性连接于第一节点，漏极电性连接于直流低电压信号。
  5. 如权利要求4所述的充电扫描与电荷共享扫描双输出GOA电路，其中，该充电扫描与电荷共享扫描双输出GOA电路的第一级及第二级的连接关系中，第十一晶体管的栅极与源极均电性连接于电路的启始信号，仅所述第二十一晶体管的漏极正常输出，所述第二十晶体管的漏极输出低电位。
  6. 如权利要求4所述的充电扫描与电荷共享扫描双输出GOA电路，其中，该充电扫描与电荷共享扫描双输出GOA电路的最后一级及倒数第二级的连接关系中，所述第三十晶体管的栅极、第三十一晶体管的栅极、及第四十一晶体管的栅极均电性连接于电路的启始信号。
  7. 如权利要求4所述的充电扫描与电荷共享扫描双输出GOA电路，其中，所述充电扫描信号的输出波形由第二十一晶体管的规格进行控制；所述第n-2级GOA单元电路的电荷共享扫描信号的输出波形由第二十晶体管的规格进行控制。
  8. 如权利要求2所述的充电扫描与电荷共享扫描双输出GOA电路，其中，所述四条高频时钟信号均在一个周期内分为充电扫描输出部分和电荷共享扫描输出部分；第M条高频时钟信号的充电扫描输出部分处于高电位的时间宽度大于第M-2条高频时钟信号的电荷共享扫描输出部分处于高电位的时间宽度。
  9. 如权利要求8所述的充电扫描与电荷共享扫描双输出GOA电路，其中，当所述第M条高频时钟信号为第一条高频时钟信号时，所述第M-2条高频时钟信号为第三条高频时钟信号；当所述第M条高频时钟信号为第二条高频时钟信号时，所述第M-2条高频时钟信号为第四条高频时钟信号。
  10. 如权利要求2所述的充电扫描与电荷共享扫描双输出GOA电路，其中，所述第一、第二低频时钟信号的电位每隔一帧或多帧反转一次。
  11. 一种充电扫描与电荷共享扫描双输出GOA电路，包括级联的多个GOA单元电路、设置于各级GOA单元电路外围的第一、第二低频时钟信号、直流低电压信号、以及四条高频时钟信号的金属线；设n为正整数， 第n级GOA单元电路接收第一、第二低频时钟信号、直流低电压信号、第M、第M-2条高频时钟信号、第n-2级GOA单元电路产生的级传信号、第n-2级GOA单元电路产生的充电扫描信号、及第n+2级GOA单元电路产生的级传信号，通过不同的TFT分别输出充电扫描信号、第n-2级GOA单元电路的电荷共享扫描信号、及级传信号；
    所述第n级GOA单元电路包括：下传模块、级传稳压模块、输出模块、快速下拉模块、及下拉维持模块；
    其中，所述输出模块包括第二十晶体管，所述第二十晶体管的栅极电性连接于第一节点，源极电性连接于第M-2条高频时钟信号，漏极输出第n-2级GOA单元电路的电荷共享扫描信号；所述第二十晶体管用于在第一节点处于高电位时，依据第M-2条高频时钟信号输出第n-2级GOA单元电路的电荷共享扫描信号；
    第二十一晶体管，所述第二十一晶体管的栅极电性连接于第一节点，源极电性连接于第M条高频时钟信号，漏极输出充电扫描信号；所述第二十一晶体管用于在第一节点处于高电位时，依据第M条高频时钟信号输出充电扫描信号；
    第二十二晶体管，所述第二十二晶体管的栅极电性连接于第一节点，源极电性连接于第M条高频时钟信号，漏极输出级传信号；所述第二十二晶体管用于在第一节点处于高电位时，依据第M条高频时钟信号输出级传信号；
    其中，所述输出模块还包括一电容，所述电容的一端电性连接于第一节点，另一端电性连接于充电扫描信号；
    其中，所述下传模块包括第十一晶体管，所述第十一晶体管的栅极电性连接于第n-2级GOA单元电路的级传信号，源极电性连接于第n-2级GOA单元电路的充电扫描信号，漏极电性连接于第一节点；
    所述下拉维持模块包括第五十五晶体管、第一下拉维持模块、与第二下拉维持模块；
    所述第五十五晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第三节点；
    所述第一下拉维持模块包括第四十二晶体管，所述第四十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于直流低电压信号；第五十一晶体管，所述第五十一晶体管的栅极与源极均电性连接于第一低频时钟信号，漏极电性连接于第五十三晶体管的栅极；第五十三晶体管，所述第五十三晶体管的栅极电性连接于第五十一晶体管的 漏极，源极电性连接于第一低频时钟信号，漏极电性连接于第二节点；第五十四晶体管，所述第五十四晶体管的栅极电性连接于第二低频时钟信号，源极电性连接于第一低频时钟信号，漏极电性连接于第二节点；第三十二晶体管，所述第三十二晶体管的栅极电性连接于第二节点，源极电性连接于充电扫描信号，漏极电性连接于直流低电压信号；
    所述第二下拉维持模块包括第四十三晶体管，所述第四十三晶体管的栅极电性连接于第三节点，源极电性连接于第一节点，漏极电性连接于直流低电压信号；第六十一晶体管，所述第六十一晶体管的栅极与源极均电性连接于第二低频时钟信号，漏极电性连接于第六十三晶体管的栅极；第六十三晶体管，所述第六十三晶体管的栅极电性连接于第六十一晶体管的漏极，源极电性连接于第二低频时钟信号，漏极电性连接于第三节点；第六十四晶体管，所述第六十四晶体管的栅极电性连接于第一低频时钟信号，源极电性连接于第二低频时钟信号，漏极电性连接于第三节点；第三十三晶体管，所述第三十三晶体管的栅极电性连接于第三节点，源极电性连接于充电扫描信号，漏极电性连接于直流低电压信号；
    所述级传稳压模块包括第五十二晶体管，所述第五十二晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于直流低电压信号；第六十二晶体管，所述第六十二晶体管的栅极电性连接于第一节点，源极电性连接于第三节点，漏极电性连接于直流低电压信号；第五十六晶体管，所述第五十六晶体的栅极电性连接于第n-2级GOA单元电路的级传信号，源极电性连接于第五十一晶体管的漏极，漏极电性连接于直流低电压信号；第六十六晶体管，所述第六十六晶体的栅极电性连接于第n-2级GOA单元电路的级传信号，源极电性连接于第六十一晶体管的漏极，漏极电性连接于直流低电压信号；
    所述快速下拉模块包括第三十晶体管，所述第三十晶体管的栅极电性连接于第n+2级GOA单元电路的级传信号，源极电性连接于第n-2级GOA单元电路的电荷共享扫描信号，漏极电性连接于直流低电压信号；第三十一晶体管，所述第三十一晶体管的栅极电性连接于第n+2级GOA单元电路的级传信号，源极电性连接于充电扫描信号，漏极电性连接于直流低电压信号；第四十一晶体管，所述第四十一晶体管的栅极电性连接于第n+2级GOA单元电路的级传信号，源极电性连接于第一节点，漏极电性连接于直流低电压信号；
    其中，所述四条高频时钟信号均在一个周期内分为充电扫描输出部分和电荷共享扫描输出部分；第M条高频时钟信号的充电扫描输出部分处于 高电位的时间宽度大于第M-2条高频时钟信号的电荷共享扫描输出部分处于高电位的时间宽度；
    其中，所述第一、第二低频时钟信号的电位每隔一帧或多帧反转一次。
  12. 如权利要求11所述的充电扫描与电荷共享扫描双输出GOA电路，其中，该充电扫描与电荷共享扫描双输出GOA电路的第一级及第二级的连接关系中，第十一晶体管的栅极与源极均电性连接于电路的启始信号，仅所述第二十一晶体管的漏极正常输出，所述第二十晶体管的漏极输出低电位。
  13. 如权利要求11所述的充电扫描与电荷共享扫描双输出GOA电路，其中，该充电扫描与电荷共享扫描双输出GOA电路的最后一级及倒数第二级的连接关系中，所述第三十晶体管的栅极、第三十一晶体管的栅极、及第四十一晶体管的栅极均电性连接于电路的启始信号。
  14. 如权利要求11所述的充电扫描与电荷共享扫描双输出GOA电路，其中，所述充电扫描信号的输出波形由第二十一晶体管的规格进行控制；所述第n-2级GOA单元电路的电荷共享扫描信号的输出波形由第二十晶体管的规格进行控制。
  15. 如权利要求11所述的充电扫描与电荷共享扫描双输出GOA电路，其中，当所述第M条高频时钟信号为第一条高频时钟信号时，所述第M-2条高频时钟信号为第三条高频时钟信号；当所述第M条高频时钟信号为第二条高频时钟信号时，所述第M-2条高频时钟信号为第四条高频时钟信号。
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CN104537987B (zh) 2017-02-22
US9773467B2 (en) 2017-09-26
CN104537987A (zh) 2015-04-22
US20170243556A1 (en) 2017-08-24
US9818362B2 (en) 2017-11-14
US20170243555A1 (en) 2017-08-24

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