WO2020177243A1 - Goa电路 - Google Patents

Goa电路 Download PDF

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Publication number
WO2020177243A1
WO2020177243A1 PCT/CN2019/092476 CN2019092476W WO2020177243A1 WO 2020177243 A1 WO2020177243 A1 WO 2020177243A1 CN 2019092476 W CN2019092476 W CN 2019092476W WO 2020177243 A1 WO2020177243 A1 WO 2020177243A1
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WIPO (PCT)
Prior art keywords
clock signal
module
pull
node
signal
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PCT/CN2019/092476
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English (en)
French (fr)
Inventor
陈帅
Original Assignee
深圳市华星光电技术有限公司
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Publication of WO2020177243A1 publication Critical patent/WO2020177243A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of display technology, in particular to a GOA circuit.
  • liquid crystal display Liquid Crystal Display, LCD
  • cathode ray tubes Cathode ray tubes
  • Ray Tube, CRT Ray Tube
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is based on the thin film transistor substrate (Thin Film Transistor Array Substrate, TFT Array Substrate) and the color filter (Color Filter, CF) liquid crystal molecules are poured between the substrates, and pixel voltage and common voltage are applied to the two substrates respectively.
  • the rotation direction of the liquid crystal molecules is controlled by the electric field formed between the pixel voltage and the common voltage to reduce the backlight module The light is refracted to produce a picture.
  • each pixel is electrically connected to a thin film transistor (TFT), the gate of the thin film transistor is connected to the horizontal scan line, the drain is connected to the vertical data line, and the source (Source) ) Is connected to the pixel electrode.
  • TFT thin film transistor
  • Source Source
  • Applying enough voltage on the horizontal scan line will turn on all the TFTs that are electrically connected to the horizontal scan line, so that the signal voltage on the data line can be written to the pixel, and the transmittance of different liquid crystals can be controlled to achieve color control With the effect of brightness.
  • the horizontal scanning line of the active liquid crystal display panel is mainly driven by an external integrated circuit board (Integrated Circuit, IC) to complete, the external IC can control the step-by-step charging and discharging of the horizontal scan lines at all levels.
  • IC integrated circuit board
  • GOA technology Gate Driver on Array is the row driving technology of the array substrate, which can use the array process of the liquid crystal display panel to fabricate the gate driving circuit on the TFT array substrate to realize the driving mode of the gate progressive scan.
  • GOA technology can reduce the bonding process of external ICs, which has the opportunity to increase production capacity and reduce product costs, and it can make LCD panels more suitable for manufacturing narrow or borderless display products.
  • the GOA circuit generally includes multi-level GOA units, and each level of GOA unit includes a pull-up control unit for precharging the first node, and a pull-up control unit for outputting scan signals under the control of the potential of the first node.
  • the pull-down unit the downstream unit used to control the output stage transmission signal by the potential of the first node, the pull-down module used to pull down the first node potential and the scan signal potential, and maintain the first node potential and the scan signal potential at Low potential pull-down sustain unit.
  • the common GOA circuit has the problems of excessively long fall time of the scanning signal waveform and abnormal potential caused by the leakage of the first node, which greatly reduces the reliability and stability of the GOA circuit.
  • the purpose of the present invention is to provide a GOA circuit, which can shorten the falling time of the scanning signal waveform, solve the leakage problem of the first node, and has high reliability and stability.
  • the present invention first provides a GOA circuit including a plurality of cascaded GOA units, each level of GOA unit includes a pull-up control module, a pull-up module, a downstream module, and a pull-down module;
  • N be a positive integer, except for the first and last level GOA units, in the Nth level GOA unit,
  • the pull-up control module is electrically connected to the first node and connected to the level transmission signal of the N-1 level GOA unit, for pulling up the potential of the first node according to the level transmission signal of the N-1 level GOA unit;
  • the pull-up module is electrically connected to the first node and connected to the first clock signal or the second clock signal, and is used for outputting the scan signal by using the first clock signal or the second clock signal under the control of the first node;
  • the download module is electrically connected to the first node and connected to the third clock signal or the fourth clock signal, and is used to output the stage transmission signal by using the third clock signal or the fourth clock signal under the control of the first node;
  • the pull-down module is electrically connected to the first node and connected to the scan signal, the scan signal of the N+1th level GOA unit and the constant voltage low potential, and is used to control the first node under the control of the scan signal of the N+1th level GOA unit The potential of a node and the scan signal is pulled down to a constant voltage low potential.
  • the third clock signal and the fourth clock signal are inverted and have a duty cycle of 0.5; the first clock signal and the second clock signal have the same duty cycle and are both less than 0.5 and greater than 0;
  • the rising edge is generated simultaneously with the rising edge of the first clock signal, and the rising edge of the fourth clock signal is generated simultaneously with the rising edge of the second clock signal;
  • the pull-up module of the Nth level GOA unit When the pull-up module of the Nth level GOA unit is connected to the first clock signal, the pull-up module of the N-1 level GOA unit is connected to the second clock signal; when the pull-up module of the Nth level GOA unit is connected to the second clock When the signal is signaled, the pull-up module of the N-1 level GOA unit is connected to the first clock signal.
  • the duty ratios of the first clock signal and the second clock signal are both 0.4.
  • the pull-up control module includes an eleventh thin film transistor; the gate and source of the eleventh thin film transistor are both connected to the stage transmission signal of the N-1 level GOA unit, and the drain is electrically connected to the first node;
  • the pull-down module includes a thirty-first thin film transistor and a forty-first thin film transistor; the gate of the thirty-first thin film transistor is connected to the scan signal of the N+1th level GOA unit, and the source is connected to the scan signal, The drain is connected to a constant voltage and low potential; the gate of the forty-first thin film transistor is connected to the scanning signal of the N+1 level GOA unit, the source is electrically connected to the first node, and the drain is connected to the constant voltage and low potential .
  • the gate and source of the eleventh thin film transistor are both connected to the start signal
  • the gates of the 31st thin film transistor and the 41st thin film transistor are connected to the start signal.
  • the pull-up module includes a twenty-first thin film transistor; the gate of the twenty-first thin film transistor is electrically connected to the first node, the source is connected to the first clock signal or the second clock signal, and the drain outputs the scan signal .
  • the download module includes a twenty-second thin film transistor, the gate of the twenty-second thin film transistor is electrically connected to the first node, the source is connected to the third clock signal or the fourth clock signal, and the drain output stage transmits signal.
  • Each level of GOA unit also includes pull-down maintenance module
  • the pull-down maintenance module is electrically connected to the first node and connected to the scan signal and the constant voltage low potential, and is used to maintain the potential of the first node and the scan signal at the constant voltage low potential.
  • the pull-down maintenance module includes a thirty-second thin film transistor, a forty-second thin film transistor, and an inverter; the gate of the thirty-second thin film transistor is electrically connected to the output terminal of the inverter, and the source is connected to the scan Signal, the drain is connected to the constant voltage low potential; the gate of the forty-second thin film transistor is electrically connected to the output terminal of the inverter, the source is electrically connected to the first node, and the drain is connected to the constant voltage low potential; The input terminal of the inverter is electrically connected to the first node.
  • Each level of GOA unit also includes a bootstrap module; the bootstrap module includes a capacitor; one end of the capacitor is electrically connected to the first node, and the other end is connected to a scan signal.
  • the pull-up control module pulls up the connection point with the pull-up module and the downstream module, that is, the potential of the first node according to the level transmission signal of the upper-level GOA unit.
  • the waveform of the first node is controlled.
  • the pull-up module and the downstream module use two different clock signals to control the waveforms of the scan signal and the stage transmission signal, so as to improve the leakage problem of the first node while reducing the scan
  • the drop time of the signal waveform has high reliability and stability.
  • FIG. 1 is a circuit diagram of the GOA circuit of the present invention.
  • FIG. 2 is a timing diagram of the GOA circuit of the present invention.
  • Fig. 3 is a circuit diagram of the first-stage GOA unit of the GOA circuit of the present invention.
  • FIG. 4 is a circuit diagram of the last stage GOA unit of the GOA circuit of the present invention.
  • the present invention provides a GOA circuit including a plurality of cascaded GOA units, each level of GOA unit includes a pull-up control module 100, a pull-up module 200, a download module 300, and a pull-down module 400.
  • N be a positive integer, except for the first and last level GOA units, in the Nth level GOA unit,
  • the pull-up control module 100 is electrically connected to the first node Q(N) and is connected to the stage transmission signal ST(N-1) of the N-1th level GOA unit, and is used to perform according to the stage of the N-1th level GOA unit
  • the transmission signal ST(N-1) pulls up the potential of the first node Q(N).
  • the pull-up module 200 is electrically connected to the first node Q(N) and is connected to the first clock signal CK or the second clock signal XCK for using the first clock signal CK under the control of the first node Q(N) Or the second clock signal XCK outputs the scan signal G(N).
  • the download module 300 is electrically connected to the first node Q(N) and connected to the third clock signal QCK or the fourth clock signal XQCK, for using the third clock signal QCK under the control of the first node Q(N) Or the fourth clock signal XQCK outputs the stage transmission signal ST(N).
  • the pull-down module 400 is electrically connected to the first node Q(N) and is connected to the scan signal G(N), the scan signal G(N+1) of the N+1th level GOA unit, and the constant voltage low potential VSS for Under the control of the scan signal G(N+1) of the N+1th GOA unit, the potentials of the first node Q(N) and the scan signal G(N) are pulled down to a constant voltage low potential VSS.
  • the third clock signal QCK and the fourth clock signal XQCK are inverted and have a duty ratio of 0.5.
  • the duty ratios of the first clock signal CK and the second clock signal XCK are the same and both are less than 0.5 and greater than zero.
  • the rising edge of the third clock signal QCK is generated simultaneously with the rising edge of the first clock signal CK, and the rising edge of the fourth clock signal XQCK is generated simultaneously with the rising edge of the second clock signal XCK.
  • the pull-up module 200 of the Nth level GOA unit When the pull-up module 200 of the Nth level GOA unit is connected to the first clock signal CK, its download module 300 is connected to the third clock signal QCK, and when the pull-up module 200 of the Nth level GOA unit is connected to the second clock signal XCK At that time, its downloading module 300 accesses the fourth clock signal XQCK.
  • the pull-up module 200 of the N-th level GOA unit is connected to the first clock signal CK
  • the pull-up module 200 of the N-1th level GOA unit is connected to the second clock signal XCK.
  • the pull-up module 200 of the N-1th level GOA unit When the pull-up module 200 of the N-th level GOA unit is connected to the second clock signal XCK, the pull-up module 200 of the N-1th level GOA unit is connected to the first clock signal CK.
  • the duty ratios of the first clock signal CK and the second clock signal XCK are both 0.4.
  • the pull-up control module 100 includes an eleventh thin film transistor T11.
  • the gate and source of the eleventh thin film transistor T11 are both connected to the stage transmission signal ST(N-1) of the N-1 level GOA unit, and the drain is electrically connected to the first node Q(N).
  • the pull-down module 400 includes a thirty-first thin film transistor T31 and a forty-first thin film transistor T41.
  • the gate of the thirty-first thin film transistor T31 is connected to the scanning signal G(N+1) of the N+1th level GOA unit, the source is connected to the scanning signal G(N), and the drain is connected to the constant voltage low potential VSS.
  • the gate of the forty-first thin film transistor T41 is connected to the scanning signal G(N+1) of the N+1th level GOA unit, the source is electrically connected to the first node Q(N), and the drain is connected to a constant voltage Low potential VSS.
  • the gate and source of the eleventh thin film transistor T11 are both connected to the start signal STV.
  • the gates of the thirty-first thin film transistor T31 and the 41st thin film transistor T41 are both connected to the start signal STV.
  • the pull-up module 200 includes a twenty-first thin film transistor T21.
  • the gate of the twenty-first thin film transistor T21 is electrically connected to the first node Q(N), the source is connected to the first clock signal CK or the second clock signal XCK, and the drain outputs the scan signal G(N).
  • the download module 300 includes a twenty-second thin film transistor T22, the gate of the twenty-second thin film transistor T22 is electrically connected to the first node Q(N), and the source is connected to the third clock signal QCK Or the fourth clock signal XQCK, the drain output stage transfer signal ST(N).
  • each level of GOA unit further includes a pull-down maintenance module 500.
  • the pull-down maintenance module 500 is electrically connected to the first node Q(N) and is connected to the scan signal G(N) and the constant voltage low potential VSS for connecting the first node Q(N) and the scan signal G(N) The potential is maintained at a constant voltage and low potential.
  • the pull-down maintenance module 500 includes a thirty-second thin film transistor T32, a forty-second thin film transistor T42, and an inverter 510.
  • the gate of the thirty-second thin film transistor T32 is electrically connected to the output terminal of the inverter 510, the source is connected to the scan signal G(N), and the drain is connected to the constant voltage low potential VSS.
  • the gate of the forty-second thin film transistor T42 is electrically connected to the output terminal of the inverter 510, the source is electrically connected to the first node Q(N), and the drain is connected to the constant voltage low potential VSS.
  • the input terminal of the inverter 510 is electrically connected to the first node Q(N).
  • the inverter 510 includes a fifty-first thin film transistor T51, a fifty-second thin film transistor T52, a fifty-third thin film transistor T53, and a fifty-fourth thin film transistor T54.
  • the gate and source of the fifty-first thin film transistor T51 are both connected to a high-level pull-down sustain signal LC, and the drain is electrically connected to the source of the fifty-second thin film transistor T52.
  • the gate of the fifty-second thin film transistor T52 is the input terminal of the inverter 510, and the drain is connected to the constant voltage low potential VSS.
  • the gate of the fifty-third thin film transistor is electrically connected to the drain of the fifty-first thin film transistor T51, the source is connected to the pull-down sustain signal LC, and the drain is the output terminal of the inverter 510.
  • the gate of the fifty-fourth thin film transistor T54 is electrically connected to the gate of the fifty-second thin film transistor T52, the source is electrically connected to the drain of the fifty-third thin film transistor T53, and the drain is connected to the constant voltage low potential VSS.
  • each level of GOA unit also includes a bootstrap module 600.
  • the bootstrap module 600 includes a capacitor C1. One end of the capacitor C1 is electrically connected to the first node Q(N), and the other end is connected to the scanning signal G(N).
  • the working process of the GOA circuit of the present invention is as follows: First, the stage transfer signal ST(N-1) of the N-1th GOA unit is at a high potential, the eleventh thin film transistor T11 is turned on, and the N-th The level transmission signal ST(N-1) of the level 1 GOA unit is written into the first node Q(N), so that the first node Q(N) is at a high potential, and the twenty-first thin film transistor T21 and the twenty-second thin film transistor T22 is turned on.
  • the second clock signal XCK and the fourth clock signal XQCK are both low, the scanning signal G(N) and the stage transfer signal ST(N) are both low, and then the N-1 level GOA unit
  • the level transmission signal ST(N-1) is low potential to turn off the eleventh thin film transistor T11. Due to the storage effect of the capacitor C1, the first node Q(N) maintains a high potential so that the twenty-first thin film transistor T21 and the second The twelve thin film transistor T22 remains on. At this time, the second clock signal XCK and the fourth clock signal XQCK both become high, so that the scan signal G(N) and the stage transfer signal ST(N) are high.
  • the second clock signal XCK changes to a low level
  • the fourth clock signal XQCK is still at a high level
  • the first node Q(N) still maintains a high level so that the twenty-first thin film transistor T21 and the twenty-second thin film transistor T22 are kept on
  • the second clock signal XCK pulls down the scan signal G(N) through the twenty-first thin film transistor T1, and the stage transfer signal ST(N) is still high.
  • the fourth clock signal XQCK is low, and the first clock signal CK is a high potential, the scan signal G(N+1) of the N+1th GOA unit is a high potential, turning on the thirty-first thin film transistor T31 and the 41st thin film transistor T41, and the constant voltage low potential VSS passes through the first
  • the thirty-first thin film transistor T31 pulls down the potential of the scan signal G(N)
  • the constant-voltage low potential VSS pulls down the potential of the first node Q(N) through the 41st thin film transistor T41, and at the first node Q( N)
  • the output terminal of the inverter 510 outputs a high potential to turn on the thirty-second thin film transistor T32 and the forty-second thin film transistor T42, and turn on the first node Q(N) and the scan signal G(N ) Is maintained at a constant voltage low potential VSS.
  • the downstream module 300 of the N-1 level GOA unit uses the fourth clock signal XQCK or the third clock signal QCK to control the level transmission signal ST(N-1) of the N-1 level GOA unit.
  • the pull-up control module 100 of the N-th GOA unit pulls up the potential of the first node Q(N) according to the stage transmission signal ST(N-1) of the N-1th GOA unit, and at the same time it pulls up the module 200 uses the first clock signal CK or the second clock signal XCK to control the waveform of the scan signal G(N)
  • its downstream module 300 uses the third clock signal QCK or the fourth clock signal XQCK to control the waveform of the stage transmission signal ST(N)
  • the third clock signal QCK is inverted from the fourth clock signal XQCK and the duty cycle is both 0.5, the duty cycle of the first clock signal CK and the second clock signal XCK are the same and both are less than 0.5 and greater than 0, the third clock
  • the fourth clock signal XQCK or the third clock signal The stage transfer signal ST(N-1) of the N-1th stage GOA unit generated by QCK can maintain a high potential for a long time so that the eleventh thin film transistor T11 can be continuously turned on to charge the first node Q(N), and compensate The potential of the first node Q(N) drops due to leakage, and the high potential of the first node Q(N) can be maintained until the pull-down time of the scan signal G(N), so that the pull-down of the scan signal G(N)
  • the twenty-first thin-film transistor T21 remains on and uses the clock signal connected to its source to pull down the potential of the scanning signal G(N), and the thirty-first thin film is turned on by the constant voltage low potential VSS.
  • the crystal T31 pulls down the potential of the scan signal G(N), which can significantly reduce the fall time of the scan signal waveform, and effectively improve the reliability and stability of the GOA circuit.
  • the pull-up control module pulls up its connection point with the pull-up module and the downstream module, that is, the potential of the first node, according to the level transmission signal of the upper-level GOA unit
  • the waveform of a node is controlled, and the pull-up module and the downlink module use two different clock signals to control the waveforms of the scan signal and the stage transmission signal respectively, thereby reducing the scan signal while improving the leakage problem of the first node.
  • the drop time of the waveform has high reliability and stability.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Computer Hardware Design (AREA)
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Abstract

提供一种GOA电路，该电路中，上拉控制模块（100）根据上一级GOA单元的级传信号上拉其与上拉模块（200）及下传模块（300）的连接点也即第一节点（Q(N)）的电位以对第一节点（Q(N)）的波形进行控制，同时上拉模块（200）及下传模块（300）分别利用两组不同的时钟信号分别控制扫描信号及级传信号的波形，从而能够在改善第一节点的漏电问题的同时，降低扫描信号波形的下降时长，具有较高的可靠性及稳定性。

Description

GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路。
 背景技术
在显示技术领域，液晶显示装置(Liquid Crystal Display，LCD)等平板显示装置已经逐步取代阴极射线管(Cathode Ray Tube，CRT)显示装置。液晶显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片(Color Filter，CF)基板之间灌入液晶分子，并在两片基板上分别施加像素电压和公共电压，通过像素电压和公共电压之间形成的电场控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
主动式液晶显示器中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。目前主动式液晶显示面板水平扫描线的驱动主要由外接的集成电路板(Integrated Circuit，IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。
而GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是可以运用液晶显示面板的阵列制程将栅极驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
现有技术中，GOA电路一般包括多级GOA单元，每一级GOA单元均包括用于为第一节点进行预充电的上拉控制单元、用于受第一节点的电位控制输出扫描信号的上拉单元、用于受第一节点的电位控制输出级传信号的下传单元、用于将第一节点电位及扫描信号电位下拉的下拉模块、用于将第一节点电位及扫描信号电位维持在低电位的下拉维持单元。常见的GOA电路中存在扫描信号波形的下降时长过长以及第一节点漏电导致的电位异常的问题，使得GOA电路的可靠性和稳定性大大降低。
 技术问题
本发明的目的在于提供一种GOA电路，能够缩短扫描信号波形的下降时长，并解决第一节点的漏电问题，具有较高的可靠性及稳定性。
 技术解决方案
为实现上述目的，本发明首先提供一种GOA电路，包括多个级联的GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下传模块、下拉模块；
设N为正整数，除了第一级及最后一级GOA单元外，在第N级GOA单元中，
所述上拉控制模块电性连接第一节点并接入第N-1级GOA单元的级传信号，用于根据第N-1级GOA单元的级传信号上拉第一节点的电位；
所述上拉模块电性连接第一节点并接入第一时钟信号或第二时钟信号，用于在第一节点的控制下利用第一时钟信号或第二时钟信号输出扫描信号；
所述下传模块电性连接第一节点并接入第三时钟信号或第四时钟信号，用于在第一节点的控制下利用第三时钟信号或第四时钟信号输出级传信号；
所述下拉模块电性连接第一节点并接入扫描信号、第N+1级GOA单元的扫描信号及恒压低电位，用于在第N+1级GOA单元的扫描信号的控制下将第一节点及扫描信号的电位下拉至恒压低电位。
所述第三时钟信号与第四时钟信号反相且占空比均为0.5；所述第一时钟信号与第二时钟信号的占空比相同且均小于0.5并大于0；第三时钟信号的上升沿与第一时钟信号的上升沿同时产生，第四时钟信号的上升沿与第二时钟信号的上升沿同时产生；
当第N级GOA单元的上拉模块接入第一时钟信号时其下传模块接入第三时钟信号，当第N级GOA单元的上拉模块接入第二时钟信号时其下传模块接入第四时钟信号；
当第N级GOA单元的上拉模块接入第一时钟信号时第N-1级GOA单元的上拉模块接入第二时钟信号；当第N级GOA单元的上拉模块接入第二时钟信号时第N-1级GOA单元的上拉模块接入第一时钟信号。
所述第一时钟信号与第二时钟信号的占空比均为0.4。
所述上拉控制模块包括第十一薄膜晶体管；所述第十一薄膜晶体管的栅极及源极均接入N-1级GOA单元的级传信号，漏极电性连接第一节点；
所述下拉模块包括第三十一薄膜晶体管及第四十一薄膜晶体管；所述第三十一薄膜晶体管的栅极接入第N+1级GOA单元的扫描信号，源极接入扫描信号，漏极接入恒压低电位；所述第四十一薄膜晶体管的栅极接入第N+1级GOA单元的扫描信号，源极电性连接第一节点，漏极接入恒压低电位。
在第一级GOA单元中，第十一薄膜晶体管的栅极及源极均接入起始信号；
在最后一级GOA单元中，第三十一薄膜晶体管及第四十一薄膜晶体管的栅极均接入起始信号。
所述上拉模块包括第二十一薄膜晶体管；所述第二十一薄膜晶体管的栅极电性连接第一节点，源极接入第一时钟信号或第二时钟信号，漏极输出扫描信号。
所述下传模块包括第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接第一节点，源极接入第三时钟信号或第四时钟信号，漏极输出级传信号。
每一级GOA单元还包括下拉维持模块；
所述下拉维持模块电性连接第一节点并接入扫描信号及恒压低电位，用于将第一节点及扫描信号的电位维持在恒压低电位。
所述下拉维持模块包括第三十二薄膜晶体管、第四十二薄膜晶体管及反相器；所述第三十二薄膜晶体管的栅极电性连接反相器的输出端，源极接入扫描信号，漏极接入恒压低电位；所述第四十二薄膜晶体管的栅极电性连接反相器的输出端，源极电性连接第一节点，漏极接入恒压低电位；所述反相器的输入端电性连接第一节点。
每一级GOA单元还包括自举模块；所述自举模块包括电容；所述电容的一端电性连接第一节点，另一端接入扫描信号。
 有益效果
本发明的有益效果：本发明的GOA电路中，上拉控制模块根据上一级GOA单元的级传信号上拉其与上拉模块及下传模块的连接点也即第一节点的电位以对第一节点的波形进行控制，同时上拉模块及下传模块分别利用两组不同的时钟信号分别控制扫描信号及级传信号的波形，从而能够在改善第一节点的漏电问题的同时，降低扫描信号波形的下降时长，具有较高的可靠性及稳定性。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的GOA电路的电路图；
图2为本发明的GOA电路的时序图；
图3为本发明的GOA电路的第一级GOA单元的电路图；
图4为本发明的GOA电路的最后一级GOA单元的电路图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种GOA电路，包括多个级联的GOA单元，每一级GOA单元均包括上拉控制模块100、上拉模块200、下传模块300、下拉模块400。
设N为正整数，除了第一级及最后一级GOA单元外，在第N级GOA单元中，
所述上拉控制模块100电性连接第一节点Q(N)并接入第N-1级GOA单元的级传信号ST(N-1)，用于根据第N-1级GOA单元的级传信号ST(N-1)上拉第一节点Q(N)的电位。
所述上拉模块200电性连接第一节点Q(N)并接入第一时钟信号CK或第二时钟信号XCK，用于在第一节点Q(N)的控制下利用第一时钟信号CK或第二时钟信号XCK输出扫描信号G(N)。
所述下传模块300电性连接第一节点Q(N)并接入第三时钟信号QCK或第四时钟信号XQCK，用于在第一节点Q(N)的控制下利用第三时钟信号QCK或第四时钟信号XQCK输出级传信号ST(N)。
所述下拉模块400电性连接第一节点Q(N)并接入扫描信号G(N)、第N+1级GOA单元的扫描信号G(N+1)及恒压低电位VSS，用于在第N+1级GOA单元的扫描信号G(N+1)的控制下将第一节点Q(N)及扫描信号G(N)的电位下拉至恒压低电位VSS。
具体地，请参阅图2，所述第三时钟信号QCK与第四时钟信号XQCK反相且占空比均为0.5。所述第一时钟信号CK与第二时钟信号XCK的占空比相同且均小于0.5并大于0。第三时钟信号QCK的上升沿与第一时钟信号CK的上升沿同时产生，第四时钟信号XQCK的上升沿与第二时钟信号XCK的上升沿同时产生。当第N级GOA单元的上拉模块200接入第一时钟信号CK时其下传模块300接入第三时钟信号QCK，当第N级GOA单元的上拉模块200接入第二时钟信号XCK时其下传模块300接入第四时钟信号XQCK。当第N级GOA单元的上拉模块200接入第一时钟信号CK时第N-1级GOA单元的上拉模块200接入第二时钟信号XCK。当第N级GOA单元的上拉模块200接入第二时钟信号XCK时第N-1级GOA单元的上拉模块200接入第一时钟信号CK。
优选地，所述第一时钟信号CK与第二时钟信号XCK的占空比均为0.4。
具体地，所述上拉控制模块100包括第十一薄膜晶体管T11。所述第十一薄膜晶体管T11的栅极及源极均接入N-1级GOA单元的级传信号ST(N-1)，漏极电性连接第一节点Q(N)。
具体地，所述下拉模块400包括第三十一薄膜晶体管T31及第四十一薄膜晶体管T41。所述第三十一薄膜晶体管T31的栅极接入第N+1级GOA单元的扫描信号G(N+1)，源极接入扫描信号G(N)，漏极接入恒压低电位VSS。所述第四十一薄膜晶体管T41的栅极接入第N+1级GOA单元的扫描信号G(N+1)，源极电性连接第一节点Q(N)，漏极接入恒压低电位VSS。
具体地，请参阅图3，在第一级GOA单元中，第十一薄膜晶体管T11的栅极及源极均接入起始信号STV。
具体地，请参阅图4，在最后一级GOA单元中，第三十一薄膜晶体管T31及第四十一薄膜晶体管T41的栅极均接入起始信号STV。
具体地，所述上拉模块200包括第二十一薄膜晶体管T21。所述第二十一薄膜晶体管T21的栅极电性连接第一节点Q(N)，源极接入第一时钟信号CK或第二时钟信号XCK，漏极输出扫描信号G(N)。
具体地，所述下传模块300包括第二十二薄膜晶体管T22，所述第二十二薄膜晶体管T22的栅极电性连接第一节点Q(N)，源极接入第三时钟信号QCK或第四时钟信号XQCK，漏极输出级传信号ST(N)。
具体地，每一级GOA单元还包括下拉维持模块500。所述下拉维持模块500电性连接第一节点Q(N)并接入扫描信号G(N)及恒压低电位VSS，用于将第一节点Q(N)及扫描信号G(N)的电位维持在恒压低电位。
进一步地，所述下拉维持模块500包括第三十二薄膜晶体管T32、第四十二薄膜晶体管T42及反相器510。所述第三十二薄膜晶体管T32的栅极电性连接反相器510的输出端，源极接入扫描信号G(N)，漏极接入恒压低电位VSS。所述第四十二薄膜晶体管T42的栅极电性连接反相器510的输出端，源极电性连接第一节点Q(N)，漏极接入恒压低电位VSS。所述反相器510的输入端电性连接第一节点Q(N)。
更进一步地，所述反相器510包括第五十一薄膜晶体管T51、第五十二薄膜晶体管T52、第五十三薄膜晶体管T53及第五十四薄膜晶体管T54。第五十一薄膜晶体管T51的栅极及源极均接入高电平的下拉维持信号LC，漏极电性连接第五十二薄膜晶体管T52的源极。第五十二薄膜晶体管T52的栅极为反相器510的输入端，漏极接入恒压低电位VSS。第五十三薄膜晶体管的栅极电性连接第五十一薄膜晶体管T51的漏极，源极接入下拉维持信号LC，漏极为反相器510的输出端。第五十四薄膜晶体管T54的栅极电性连接第五十二薄膜晶体管T52的栅极，源极电性连接第五十三薄膜晶体管T53的漏极，漏极接入恒压低电位VSS。
具体地，每一级GOA单元还包括自举模块600。所述自举模块600包括电容C1。所述电容C1的一端电性连接第一节点Q(N)，另一端接入扫描信号G(N)。
请结合图1及图2，以第N级GOA单元的上拉模块200及下传模块300分别接入第二时钟信号XCK及第四时钟信号XQCK，第N-1级GOA单元的上拉模块200及下传模块300分别接入第一时钟信号CK及第三时钟信号QCK，第N+1级GOA单元的上拉模块200及下传模块300分别接入第一时钟信号CK及第三时钟信号QCK为例，本发明的GOA电路的工作过程如下：首先，第N-1级GOA单元的级传信号ST(N-1)为高电位，第十一薄膜晶体管T11导通，第N-1级GOA单元的级传信号ST(N-1)写入第一节点Q(N)，使第一节点Q(N)为高电位将第二十一薄膜晶体管T21及第二十二薄膜晶体管T22导通，此时由于第二时钟信号XCK及第四时钟信号XQCK均为低电位，扫描信号G(N)及级传信号ST(N)均为低电位，而后第N-1级GOA单元的级传信号ST(N-1)为低电位使第十一薄膜晶体管T11截止，由于电容C1的存储作用，第一节点Q(N)保持高电位使第二十一薄膜晶体管T21及第二十二薄膜晶体管T22保持导通，此时第二时钟信号XCK及第四时钟信号XQCK均变为高电位，使得扫描信号G(N)及级传信号ST(N)为高电位，随后，第二时钟信号XCK变为低电位，第四时钟信号XQCK仍为高电位，而第一节点Q(N)仍保持高电位使得第二十一薄膜晶体管T21及第二十二薄膜晶体管T22保持导通，第二时钟信号XCK经第二十一薄膜晶体管T1将扫描信号G(N)下拉，级传信号ST(N)仍为高电位，接着，第四时钟信号XQCK为低电位，第一时钟信号CK为高电位，第N+1级GOA单元的扫描信号G(N+1)为高电位将第三十一薄膜晶体管T31及第四十一薄膜晶体管T41导通，恒压低电位VSS经第三十一薄膜晶体管T31对扫描信号G(N)的电位进行下拉，恒压低电位VSS经第四十一薄膜晶体管T41对第一节点Q(N)的电位进行下拉，在第一节点Q(N)电位被下拉后，反相器510的输出端输出高电位将第三十二薄膜晶体管T32及第四十二薄膜晶体管T42导通，将第一节点Q(N)及扫描信号G(N)的电位维持在恒压低电位VSS。
需要说明的是，本发明中，第N-1级GOA单元的下传模块300利用第四时钟信号XQCK或第三时钟信号QCK控制第N-1级GOA单元的级传信号ST(N-1)的波形，第N级GOA单元的上拉控制模块100根据第N-1级GOA单元的级传信号ST(N-1)上拉第一节点Q(N)的电位，同时其上拉模块200利用第一时钟信号CK或第二时钟信号XCK控制扫描信号G(N)的波形，其下传模块300利用第三时钟信号QCK或第四时钟信号XQCK控制级传信号ST(N)的波形，并且第三时钟信号QCK与第四时钟信号XQCK反相且占空比均为0.5，第一时钟信号CK与第二时钟信号XCK的占空比相同且均小于0.5并大于0，第三时钟信号QCK的上升沿与第一时钟信号CK的上升沿同时产生，第四时钟信号XQCK的上升沿与第二时钟信号XCK的上升沿同时产生，因此，利用第四时钟信号XQCK或第三时钟信号QCK产生的第N-1级GOA单元的级传信号ST(N-1)能够维持较长时间的高电位以使得第十一薄膜晶体管T11能够持续打开为第一节点Q(N)充电，补偿第一节点Q(N)因漏电造成的电位下降，而第一节点Q(N)的高电位时长能够维持至扫描信号G(N)的下拉时刻之后，使得在扫描信号G(N)的下拉时刻，第二十一薄膜晶体管T21保持导通状态并利用其源极接入的时钟信号对扫描信号G(N)的电位进行下拉，配合恒压低电位VSS经导通的第三十一薄膜晶体T31对扫描信号G(N)的电位进行下拉，能够显著降低扫描信号波形的下降时间，有效的提升GOA电路的可靠性及稳定性。
综上所述，本发明的GOA电路中，上拉控制模块根据上一级GOA单元的级传信号上拉其与上拉模块及下传模块的连接点也即第一节点的电位以对第一节点的波形进行控制，同时上拉模块及下传模块分别利用两组不同的时钟信号分别控制扫描信号及级传信号的波形，从而能够在改善第一节点的漏电问题的同时，降低扫描信号波形的下降时长，具有较高的可靠性及稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种GOA电路，包括多个级联的GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下传模块、下拉模块；
    设N为正整数，除了第一级及最后一级GOA单元外，在第N级GOA单元中，
    所述上拉控制模块电性连接第一节点并接入第N-1级GOA单元的级传信号，用于根据第N-1级GOA单元的级传信号上拉第一节点的电位；
    所述上拉模块电性连接第一节点并接入第一时钟信号或第二时钟信号，用于在第一节点的控制下利用第一时钟信号或第二时钟信号输出扫描信号；
    所述下传模块电性连接第一节点并接入第三时钟信号或第四时钟信号，用于在第一节点的控制下利用第三时钟信号或第四时钟信号输出级传信号；
    所述下拉模块电性连接第一节点并接入扫描信号、第N+1级GOA单元的扫描信号及恒压低电位，用于在第N+1级GOA单元的扫描信号的控制下将第一节点及扫描信号的电位下拉至恒压低电位。
  2. 如权利要求1所述的GOA电路，其中，所述第三时钟信号与第四时钟信号反相且占空比均为0.5；所述第一时钟信号与第二时钟信号的占空比相同且均小于0.5并大于0；第三时钟信号的上升沿与第一时钟信号的上升沿同时产生，第四时钟信号的上升沿与第二时钟信号的上升沿同时产生；
    当第N级GOA单元的上拉模块接入第一时钟信号时其下传模块接入第三时钟信号，当第N级GOA单元的上拉模块接入第二时钟信号时其下传模块接入第四时钟信号；
    当第N级GOA单元的上拉模块接入第一时钟信号时第N-1级GOA单元的上拉模块接入第二时钟信号；当第N级GOA单元的上拉模块接入第二时钟信号时第N-1级GOA单元的上拉模块接入第一时钟信号。
  3. 如权利要求2所述的GOA电路，其中，所述第一时钟信号与第二时钟信号的占空比均为0.4。
  4. 如权利要求1所述的GOA电路，其中，所述上拉控制模块包括第十一薄膜晶体管；所述第十一薄膜晶体管的栅极及源极均接入N-1级GOA单元的级传信号，漏极电性连接第一节点；
    所述下拉模块包括第三十一薄膜晶体管及第四十一薄膜晶体管；所述第三十一薄膜晶体管的栅极接入第N+1级GOA单元的扫描信号，源极接入扫描信号，漏极接入恒压低电位；所述第四十一薄膜晶体管的栅极接入第N+1级GOA单元的扫描信号，源极电性连接第一节点，漏极接入恒压低电位。
  5. 如权利要求4所述的GOA电路，其中，在第一级GOA单元中，第十一薄膜晶体管的栅极及源极均接入起始信号；
    在最后一级GOA单元中，第三十一薄膜晶体管及第四十一薄膜晶体管的栅极均接入起始信号。
  6. 如权利要求1所述的GOA电路，其中，所述上拉模块包括第二十一薄膜晶体管；所述第二十一薄膜晶体管的栅极电性连接第一节点，源极接入第一时钟信号或第二时钟信号，漏极输出扫描信号。
  7. 如权利要求1所述的GOA电路，其中，所述下传模块包括第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接第一节点，源极接入第三时钟信号或第四时钟信号，漏极输出级传信号。
  8. 如权利要求1所述的GOA电路，其中，每一级GOA单元还包括下拉维持模块；
    所述下拉维持模块电性连接第一节点并接入扫描信号及恒压低电位，用于将第一节点及扫描信号的电位维持在恒压低电位。
  9. 如权利要求8所述的GOA电路，其中，所述下拉维持模块包括第三十二薄膜晶体管、第四十二薄膜晶体管及反相器；所述第三十二薄膜晶体管的栅极电性连接反相器的输出端，源极接入扫描信号，漏极接入恒压低电位；所述第四十二薄膜晶体管的栅极电性连接反相器的输出端，源极电性连接第一节点，漏极接入恒压低电位；所述反相器的输入端电性连接第一节点。
  10. 如权利要求1所述的GOA电路，其中，每一级GOA单元还包括自举模块；所述自举模块包括电容；所述电容的一端电性连接第一节点，另一端接入扫描信号。
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