WO2019010757A1 - 阵列基板及其制造方法、液晶显示面板 - Google Patents

阵列基板及其制造方法、液晶显示面板 Download PDF

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WO2019010757A1
WO2019010757A1 PCT/CN2017/098439 CN2017098439W WO2019010757A1 WO 2019010757 A1 WO2019010757 A1 WO 2019010757A1 CN 2017098439 W CN2017098439 W CN 2017098439W WO 2019010757 A1 WO2019010757 A1 WO 2019010757A1
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layer
pattern
photoresist region
silicon layer
photoresist
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PCT/CN2017/098439
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English (en)
French (fr)
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石龙强
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/557,096 priority Critical patent/US20190019893A1/en
Publication of WO2019010757A1 publication Critical patent/WO2019010757A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the same, and a liquid crystal display panel.
  • IGZO Indium Gallium Zinc Oxide
  • the active layer is located in a portion of the source pattern and the drain pattern to form a channel of the TFT, since IGZO is A material that is extremely sensitive to electrical properties, so that the channel is susceptible to damage during the manufacturing process of the LCD. For example, in etching the source pattern and the drain pattern of the TFT, the etching liquid is liable to damage the channel. Affect the electrical properties of the channel.
  • the present invention provides an array substrate, a method of manufacturing the same, and a liquid crystal display panel, which can avoid damage to the channel and ensure electrical properties of the channel.
  • An electrode pattern is formed on the flat layer such that the electrode pattern can be electrically connected to the drain pattern through the contact hole.
  • a flat layer formed on the insulating layer and covering the source pattern and the drain pattern, the flat layer having a contact hole exposing a surface of the drain pattern;
  • a flat layer formed on the insulating layer and covering the source pattern and the drain pattern, the flat layer having a contact hole exposing a surface of the drain pattern;
  • the present invention is designed to form an amorphous silicon layer on an active layer of a TFT, which is equivalent to forming a protective layer on the channel, and the amorphous silicon is formed during etching to form a source pattern and a drain pattern.
  • the layer can block the etching liquid from contacting the active layer, thereby preventing the etching liquid from damaging the channel, thereby ensuring the electrical properties of the channel.
  • FIG. 1 is a schematic flow chart showing a method of manufacturing an array substrate according to a first embodiment of the present invention
  • FIG. 2 is a schematic diagram of a scene for manufacturing an array substrate based on the method shown in FIG. 1;
  • FIG. 3 is a schematic flow chart of a method of manufacturing an array substrate according to a second embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a process for manufacturing an array substrate based on the method shown in FIG. 3;
  • FIG. 5 is a schematic flow chart of a method of manufacturing an array substrate according to a third embodiment of the present invention.
  • Fig. 6 is a cross-sectional view showing the structure of a liquid crystal display panel according to an embodiment of the present invention.
  • the main object of the present invention is to form an amorphous silicon layer on the active layer of the TFT, and the amorphous silicon layer can block the contact of the etching liquid with the active layer during etching to form the source pattern and the drain pattern. In order to avoid the etchant damage the channel and ensure the electrical properties of the channel.
  • FIG. 1 is a flow chart showing a method of manufacturing an array substrate according to a first embodiment of the present invention. As shown in FIG. 1, the manufacturing method of this embodiment may include steps S11 to S19.
  • S11 sequentially forming a gate pattern and an insulating layer on the substrate.
  • the substrate 21 may be a light-transmitting substrate such as a glass substrate, a transparent plastic substrate, or a flexible substrate.
  • the substrate 21 of the embodiment may also be provided with a passivation protective layer.
  • the substrate 21 may include a substrate substrate and a passivation protective layer formed on the substrate substrate, and the substrate substrate may be a glass substrate.
  • the material of the passivation protective layer includes, but not limited to, silicon nitride, such as Si 3 N 4 (tetrazinc silicon nitride, referred to as silicon nitride), to protect Structural stability of the surface of the substrate 21.
  • the gate pattern 221 having a predetermined pattern can be formed on the substrate 21 by a mask process.
  • a full surface metal layer may be formed on the substrate 21 by a PVD (Physical Vapor Deposition) method, and then a full surface photoresist layer is coated on the metal layer, and then the photomask is used for the light.
  • the resist layer is sequentially subjected to exposure processing and development processing, and the photoresist of the fully exposed portion can be removed by the developer, and the photoresist of the unexposed portion is not removed by the developer, and then the metal layer not covered by the photoresist layer is removed by etching and removed.
  • the photoresist layer, the finally remaining metal layer can be formed as the gate pattern 221 of the TFT.
  • a CVD (Chemical Vapor Deposition) method can be used to form a gate insulating layer (Gate Insulation Layer, GI, also referred to as a gate insulating layer) 23 on the gate pattern 221, and the insulating layer 23 covers the gate.
  • the material of the insulating layer 23 may be silicon oxide (SiO x ).
  • the gate insulating layer 23 may also include a silicon oxide compound layer and a silicon nitride compound, such as SiO 2 (silicon dioxide) and Si 3 N 4 (silicon nitride), which are sequentially formed on the gate pattern 221, thereby being able to The wear resistance and insulation properties of the gate insulating layer 23 are further improved.
  • S12 an active layer, an amorphous silicon layer, a metal layer, and a photoresist layer are sequentially formed on the insulating layer.
  • the active layer 24 may be made of IGZO.
  • the active layer 24, the amorphous silicon (a-Si) layer 25, the metal layer 26, and the photoresist layer 27 formed in this step are all a single-sided structure.
  • the film formation method for forming these structures is not limited in this embodiment.
  • S13 exposing and developing the photoresist layer by using a Half-tone mask to form a first photoresist region and a second photoresist region on both sides of the first photoresist region, wherein the thickness of the first photoresist region is smaller than the first The thickness of the two photoresist regions.
  • the photoresist layer 27 is exposed and developed by a Half-tone mask, and the photoresist of the unexposed portion cannot be removed by the developer, and the photoresist of the half exposed portion can be partially removed by the developer, and is completely exposed. Part of the photoresist can be removed by the developer.
  • the remaining photoresist layer 27 includes a first photoresist region 271 and a second photoresist region 272 located on both sides of the first photoresist region 271.
  • the first photoresist region 271 has the smallest thickness and is located.
  • the thickness of the second photoresist region 272 on both sides of the first photoresist region 271 may be the same.
  • S14 etching removes the active layer, the amorphous silicon layer and the metal layer not covered by the first photoresist region and the second photoresist region.
  • the metal layer 26 may be wet etched, that is, the first photoresist region 271 and the second photoresist region 272 are flooded by the etchant, and the first photoresist region 271 and the second photoresist region 272 are not.
  • the covered metal layer 26 is chemically reacted with the etching solution to be dissolved in the etching liquid, and the metal layer 26 covered by the first photoresist region 271 and the second photoresist region 272 does not undergo chemistry due to the blocking of the photoresist. The reaction is thus retained.
  • the amorphous silicon layer 25 may be dry etched, and the active layer 24 may be wet etched.
  • S15 Perform ashing treatment on the first photoresist region and the second photoresist region to remove the first photoresist region and retain part of the second photoresist region.
  • the first photoresist region 271 and the second photoresist region 272 are subjected to ashing treatment to remove the first photoresist region 271.
  • the second The thickness of the photoresist region 272 becomes small, but is retained.
  • S16 etching removes a metal layer not covered by a portion of the second photoresist region to form a source pattern and a drain pattern.
  • the metal layer 26 can continue to be wet etched, and the metal layer 26 covered by the second photoresist region 272 does not react with the etching solution due to the blocking of the photoresist, thereby being retained, and forming a source of the spacer.
  • the flat layer 28 covering the source pattern 222 and the drain pattern 223 can be formed by a mask process. Specifically, first, a full-surface silicon oxide layer can be formed by a CVD method, and then a full-surface photoresist layer is coated on the silicon oxide compound layer, and then the photoresist layer is sequentially exposed and developed by a photomask. The photoresist of the fully exposed portion may be removed by the developer, the photoresist of the unexposed portion is not removed by the developer, and then the silicon oxide layer not covered by the photoresist layer is etched away to form the surface of the exposed drain pattern 223. The hole 281 is contacted, and then the photoresist layer is removed, and the finally remaining silicon oxide layer is the flat layer 28.
  • the electrode pattern 29 having a predetermined pattern can be formed by a mask process.
  • the principle and process of the mask process can be referred to the prior art.
  • the electrode pattern 29 is a pixel electrode forming an array substrate, and the material thereof may be ITO (Indium Tin Oxide).
  • the present embodiment is designed to form an amorphous silicon layer 25 on the active layer 24, which is equivalent to forming a protective layer on the channel of the TFT, in the process of etching to form the source pattern 222 and the drain pattern 223.
  • the amorphous silicon layer 25 can block the etching liquid from contacting the active layer 24, thereby preventing the etching liquid from damaging the channel, thereby ensuring the electrical properties of the channel.
  • FIG. 3 is a schematic flow chart of a method for fabricating an array substrate according to a second embodiment of the present invention
  • FIG. 4 is a schematic view showing a process for fabricating an array substrate based on the method shown in FIG.
  • the present embodiment is identified by the same reference numerals as those shown in FIG. 2 for the same structural elements.
  • the manufacturing method of this embodiment may include steps S31 to S39.
  • S31 sequentially forming a gate pattern and an insulating layer on the substrate.
  • S32 forming an active layer, an amorphous silicon layer, a heavily doped silicon layer, a metal layer, and a photoresist layer in this order on the insulating layer.
  • S33 exposing and developing the photoresist layer by using a Half-tone mask to form a first photoresist region and a second photoresist region on both sides of the first photoresist region, wherein the thickness of the first photoresist region is smaller than the first The thickness of the two photoresist regions.
  • S34 etching removes the active layer, the amorphous silicon layer, the heavily doped silicon layer, and the metal layer that are not covered by the first photoresist region and the second photoresist region.
  • S35 Perform ashing treatment on the first photoresist region and the second photoresist region to remove the first photoresist region and retain part of the second photoresist region.
  • S36 etching and removing the heavily doped silicon layer and the metal layer not covered by the portion of the second photoresist region to form a source pattern and a drain pattern.
  • step S32 of the embodiment further forms a heavily doped silicon layer 30 between the amorphous silicon layer 25 and the metal layer 26, and the heavily doped silicon layer 30 can be Doped with n+ type impurity ions, for example, heavily doped silicon layer 30 includes n+Si.
  • the heavily doped silicon layer 30 not covered by the first photoresist region 271 and the second photoresist region 272 is etched and removed.
  • the heavily doped silicon layer 30 not covered by the second photoresist region 272 is etched and removed.
  • a heavily doped silicon layer 30 is disposed between the amorphous silicon layer 25 and the drain pattern 223, and between the amorphous silicon layer 25 and the source pattern 222, heavily doped.
  • the silicon layer 30 can improve the electrical contact of the amorphous silicon layer 25 with the source pattern 222 and the drain pattern 223 to ensure electrical properties of the TFT.
  • FIG. 5 is a schematic flow chart of a method of manufacturing an array substrate according to a third embodiment of the present invention.
  • the same structural elements are denoted by the same reference numerals as those shown in FIG. 4 for the same structural elements.
  • the manufacturing method of this embodiment may include steps S51 to S61.
  • S51 sequentially forming a gate pattern and an insulating layer on the substrate.
  • S52 forming an active layer, an amorphous silicon layer, and a heavily doped silicon layer in this order on the insulating layer.
  • S53 annealing the heavily doped silicon layer, so that silicon atoms in the heavily doped silicon layer enter the active layer, and the active layer is doped.
  • S54 sequentially forming a metal layer and a photoresist layer on the annealed heavily doped silicon layer.
  • S55 exposing and developing the photoresist layer by using a Half-tone mask to form a first photoresist region and a second photoresist region on both sides of the first photoresist region, wherein the thickness of the first photoresist region is smaller than the first The thickness of the two photoresist regions.
  • S56 etching removes the active layer, the amorphous silicon layer, the heavily doped silicon layer, and the metal layer that are not covered by the first photoresist region and the second photoresist region.
  • S57 Perform ashing treatment on the first photoresist region and the second photoresist region to remove the first photoresist region and retain a portion of the second photoresist region.
  • S58 etching and removing the heavily doped silicon layer and the metal layer not covered by the portion of the second photoresist region to form a source pattern and a drain pattern.
  • S60 forming a planar layer covering the source pattern and the drain pattern on the insulating layer, the flat layer being provided with a contact hole exposing a surface of the drain pattern.
  • Si atoms in the heavily doped silicon layer 30 are diffused into the active layer 24, thereby forming a doped active layer 24, such as an n + IGZO layer, since the Si-doped IGZO ratio is undoped.
  • the hybrid IGZO has better resistance to negative bias and light resistance, so this embodiment can improve the electrical stability of the TFT.
  • the present invention can produce the desired array substrate.
  • the present invention further provides a liquid crystal display panel according to an embodiment.
  • the liquid crystal display panel 60 includes an array substrate 61 and a color filter substrate 62.
  • the array substrate 61 can be fabricated by the method of any of the above embodiments.
  • the array substrate, and thus the liquid crystal display panel 60 also has the above-described advantageous effects.

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Abstract

一种阵列基板及其制造方法、液晶显示面板。通过在TFT的有源层（24）上形成一非晶硅层（25），相当于在沟道上形成一保护层，在刻蚀形成源极图案(222)和漏极图案(223)的过程中，该非晶硅层(25)能够阻挡刻蚀液与有源层(24)接触，从而能够避免损伤沟道，确保沟道的电学性能。

Description

阵列基板及其制造方法、液晶显示面板 【技术领域】
本发明涉及显示技术领域，具体而言涉及一种阵列基板及其制造方法、液晶显示面板。
【背景技术】
随着液晶显示器(Liquid Crystal Display，LCD)尺寸和清晰度的增加，具有较大电子迁移率的TFT(Thin Film Transistor，薄膜晶体管)结构已崭露头角并表现出巨大的市场应用前景。当前，业界普遍采用IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)来制备TFT的有源层，并且该有源层位于源极图案和漏极图案的部分形成TFT的沟道，由于IGZO是一种电学性能极其敏感的材料，因此在LCD的制造过程中沟道容易受到损伤，例如在刻蚀形成TFT的源极图案和漏极图案的过程中，刻蚀液极易损伤沟道，从而影响沟道的电学性能。
【发明内容】
有鉴于此，本发明提供一种阵列基板及其制造方法、液晶显示面板，能够避免损伤沟道，确保沟道的电学性能。
本发明一实施例的阵列基板的制造方法，包括：
在基板上依次形成栅极图案和绝缘层；
在绝缘层上依次形成有源层、非晶硅层、金属层及光阻层；
采用Half-tone光罩对光阻层曝光显影，形成第一光阻区域和位于第一光阻区域两侧的第二光阻区域，所述第一光阻区域的厚度小于所述第二光阻区域的厚度；
刻蚀去除未被第一光阻区域和第二光阻区域遮盖的有源层、非晶硅层及金属层；
对第一光阻区域和第二光阻区域进行灰化处理，以去除第一光阻区域，并保留部分第二光阻区域；
刻蚀去除未被所述部分第二光阻区域覆盖的金属层，形成源极图案和 漏极图案；
去除所述部分第二光阻区域；
在绝缘层上形成覆盖源极图案和漏极图案的平坦层，所述平坦层开设有暴露漏极图案表面的接触孔；
在平坦层上形成电极图案，使得所述电极图案可通过接触孔与漏极图案电连接。
本发明一实施例的阵列基板，包括：
基板；
依次形成于基板上的栅极图案和绝缘层；
依次形成于绝缘层上的有源层、非晶硅层、源极图案和漏极图案；
形成于绝缘层上且覆盖源极图案和漏极图案的平坦层，所述平坦层开设有暴露漏极图案表面的接触孔；
形成于平坦层上的电极图案，所述电极图案可通过接触孔与漏极图案电连接。
本发明一实施例的液晶显示面板的阵列基板包括：
基板；
依次形成于基板上的栅极图案和绝缘层；
依次形成于绝缘层上的有源层、非晶硅层、源极图案和漏极图案；
形成于绝缘层上且覆盖源极图案和漏极图案的平坦层，所述平坦层开设有暴露漏极图案表面的接触孔；
形成于平坦层上的电极图案，所述电极图案可通过接触孔与漏极图案电连接。
有益效果：本发明设计在TFT的有源层上形成一非晶硅层，相当于在沟道上形成了一保护层，在刻蚀形成源极图案和漏极图案的过程中，该非晶硅层能够阻挡刻蚀液与有源层接触，从而能够避免刻蚀液损伤沟道，以此确保沟道的电学性能。
【附图说明】
图1是本发明第一实施例的阵列基板的制造方法的流程示意图；
图2是基于图1所示方法制造阵列基板的场景示意图；
图3是本发明第二实施例的阵列基板的制造方法的流程示意图；
图4是基于图3所示方法制造阵列基板的场景示意图；
图5是本发明第三实施例的阵列基板的制造方法的流程示意图；
图6是本发明一实施例的液晶显示面板的结构剖视图。
【具体实施方式】
本发明的主要目的是在TFT的有源层上形成一非晶硅层，在刻蚀形成源极图案和漏极图案的过程中，该非晶硅层能够阻挡刻蚀液与有源层接触，以此避免刻蚀液损伤沟道，确保沟道的电学性能。
下面结合本发明实施例中的附图，对本发明所提供的示例性的实施例的技术方案进行清楚、完整地描述。在不冲突的情况下，下述各个实施例及实施例中的技术特征可以相互组合。
图1是本发明第一实施例的阵列基板的制造方法的流程示意图。如图1所示，本实施例的制造方法可以包括步骤S11～S19。
S11：在基板上依次形成栅极图案和绝缘层。
如图2所示，基板21可以为玻璃基材、透明塑料基材、可挠式基材等透光基材。当然，本实施例的基板21也可以设置有钝化保护层，例如基板21可以包括衬底基材和形成于衬底基材上的钝化保护层，衬底基材可以为玻璃基材、透明塑料基材、可挠式基材等透光基材，钝化保护层的材料包括但不限于硅氮化合物，例如Si3N4(四氮化三硅，简称氮化硅)，以保护基板21表面的结构稳定性。
本实施例可以通过光罩制程在基板21上形成具有预定图案的栅极图案221。具体而言，首先可以采用PVD(Physical Vapor Deposition，物理气相沉积)方法在基板21上形成一整面金属层，然后在该金属层上涂布一整面光阻层，再采用光罩对光阻层依次进行曝光处理和显影处理，完全曝光部分的光阻可以被显影液去除，未曝光部分的光阻未被显影液去除，接着刻蚀去除未被光阻层遮盖的金属层，并去除光阻层，最终保留的金属层即可形成为TFT的栅极图案221。
本实施例可以采用CVD(Chemical Vapor Deposition，化学气相沉积)方法在栅极图案221上形成一绝缘层(Gate Insulation Layer，GI，又称栅极 绝缘层)23，该绝缘层23为覆盖栅极图案221的一整面结构。其中，所述绝缘层23的材质可以为硅氧化物(SiOx)。当然，栅极绝缘层23也可以包括依次形成于栅极图案221上的硅氧化合物层和硅氮化合物，例如SiO2(二氧化硅)和Si3N4(三氮化硅)，从而能够进一步提高栅极绝缘层23的耐磨损能力和绝缘性能。
S12：在绝缘层上依次形成有源层、非晶硅层、金属层及光阻层。
继续参阅图2，有源层24的材质可以为IGZO，本步骤形成的有源层24、非晶硅(a-Si)层25、金属层26以及光阻层27均为一整面结构，形成这些结构的成膜方式，本实施例并不予以限制。
S13：采用Half-tone光罩对光阻层曝光显影，形成第一光阻区域和位于第一光阻区域两侧的第二光阻区域，所述第一光阻区域的厚度小于所述第二光阻区域的厚度。
结合图2所示，采用Half-tone光罩对光阻层27进行曝光和显影处理，未曝光部分的光阻无法被显影液去除，半曝光部分的光阻可以被显影液部分去除，完全曝光部分的光阻可以被显影液去除。基于此，经过显影处理后，剩余的光阻层27包括第一光阻区域271和位于第一光阻区域271两侧的第二光阻区域272，第一光阻区域271的厚度最小，位于第一光阻区域271两侧的第二光阻区域272的厚度可以相同。
S14：刻蚀去除未被第一光阻区域和第二光阻区域遮盖的有源层、非晶硅层及金属层。
本实施例可以对金属层26采用湿法刻蚀，即，通过刻蚀液淹没第一光阻区域271和第二光阻区域272，未被第一光阻区域271和第二光阻区域272遮盖的金属层26会与刻蚀液发生化学反应而溶解于刻蚀液中，被第一光阻区域271和第二光阻区域272遮盖的金属层26由于光阻的阻挡而不会发生化学反应，从而得以保留。进一步地，本实施例可以对非晶硅层25采用干法刻蚀，以及对有源层24采用湿法刻蚀。
S15：对第一光阻区域和第二光阻区域进行灰化处理，以去除第一光阻区域，并保留部分第二光阻区域。
对第一光阻区域271和第二光阻区域272进行灰化处理，以去除第一光阻区域271。相比较于曝光显影后的光阻层27，经过灰化处理后，第二 光阻区域272的厚度变小，但被保留。
S16：刻蚀去除未被部分第二光阻区域覆盖的金属层，形成源极图案和漏极图案。
本实施例可以对金属层26继续采用湿法刻蚀，被第二光阻区域272覆盖的金属层26由于光阻的遮挡而未与刻蚀液发生反应，从而得以保留，并形成间隔的源极图案222和漏极图案223。至此，位于源极图案222、漏极图案223以及有源层24之间的部分即可视为TFT的沟道，位于两个第二光阻区域272之间的有源层24的上表面为沟道层。
S17：去除所述部分第二光阻区域。
S18：在绝缘层上形成覆盖源极图案和漏极图案的平坦层，所述平坦层开设有暴露漏极图案表面的接触孔。
本实施例可以通过光罩制程形成覆盖源极图案222和漏极图案223的平坦层28。具体而言，首先可以采用CVD方法形成一整面硅氧化合物层，然后在该硅氧化合物层上涂布一整面光阻层，再采用光罩对光阻层依次进行曝光处理和显影处理，完全曝光部分的光阻可以被显影液去除，未曝光部分的光阻未被显影液去除，接着刻蚀去除未被光阻层遮盖的硅氧化合物层，以形成暴露漏极图案223表面的接触孔281，而后去除光阻层，最终保留的硅氧化合物层即为平坦层28。
S19：在平坦层上形成电极图案，使得所述电极图案可通过接触孔与漏极图案电连接。
本实施例可以通过光罩制程形成具有预定图案的电极图案29，本次光罩制程的原理及过程可参阅现有技术。该电极图案29为形成阵列基板的像素电极，其材料可以为ITO(Indium Tin Oxide，氧化铟锡)。
基于上述，本实施例设计在有源层24上形成一非晶硅层25，相当于在TFT的沟道上形成了一保护层，在刻蚀形成源极图案222和漏极图案223的过程中，该非晶硅层25能够阻挡刻蚀液与有源层24接触，从而能够避免刻蚀液损伤沟道，以此确保沟道的电学性能。
图3是本发明第二实施例的阵列基板的制造方法的流程示意图，图4为基于图3所示方法制造阵列基板的场景示意图。为便于描述，对于相同结构元件，本实施例采用与图2所示相同的标号进行标识。如图3所示， 本实施例的制造方法可以包括步骤S31～S39。
S31：在基板上依次形成栅极图案和绝缘层。
S32：在绝缘层上依次形成有源层、非晶硅层、重掺杂硅层、金属层及光阻层。
S33：采用Half-tone光罩对光阻层曝光显影，形成第一光阻区域和位于第一光阻区域两侧的第二光阻区域，所述第一光阻区域的厚度小于所述第二光阻区域的厚度。
S34：刻蚀去除未被第一光阻区域和第二光阻区域遮盖的有源层、非晶硅层、重掺杂硅层及金属层。
S35：对第一光阻区域和第二光阻区域进行灰化处理，以去除第一光阻区域，并保留部分第二光阻区域。
S36：刻蚀去除未被所述部分第二光阻区域覆盖的重掺杂硅层及金属层，形成源极图案和漏极图案。
S37：去除所述部分第二光阻区域。
S38：在绝缘层上形成覆盖源极图案和漏极图案的平坦层，所述平坦层开设有暴露漏极图案表面的接触孔。
S39：在平坦层上形成电极图案，使得所述电极图案可通过接触孔与漏极图案电连接。
与图1和图2所示实施例的区别在于，本实施例的步骤S32在非晶硅层25和金属层26之间还形成重掺杂硅层30，该重掺杂硅层30中可以掺杂有n+型杂质离子，例如重掺杂硅层30包括n+Si。并且，在步骤S34的刻蚀制程中，对未被第一光阻区域271和第二光阻区域272遮盖的重掺杂硅层30进行刻蚀去除。另外，在步骤S36的刻蚀制程中，将未被第二光阻区域272覆盖的重掺杂硅层30进行刻蚀去除。在本实施例所制得的阵列基板中，非晶硅层25和漏极图案223之间，以及非晶硅层25和源极图案222之间设置有重掺杂硅层30，重掺杂硅层30能够改善非晶硅层25与源极图案222以及漏极图案223的电性接触，确保TFT的电学性能。
图5为本发明第三实施例的阵列基板的制造方法的流程示意图。为便于描述，对于相同结构元件，本实施例采用与图4所示相同的标号进行表述。如图5所示，本实施例的制造方法可以包括步骤S51～S61。
S51：在基板上依次形成栅极图案和绝缘层。
S52：在绝缘层上依次形成有源层、非晶硅层及重掺杂硅层。
S53：对重掺杂硅层进行退火处理，使得重掺杂硅层中的硅原子进入有源层，对有源层进行掺杂。
S54：在经过退火处理的重掺杂硅层上依次形成金属层及光阻层。
S55：采用Half-tone光罩对光阻层曝光显影，形成第一光阻区域和位于第一光阻区域两侧的第二光阻区域，所述第一光阻区域的厚度小于所述第二光阻区域的厚度。
S56：刻蚀去除未被第一光阻区域和第二光阻区域遮盖的有源层、非晶硅层、重掺杂硅层及金属层。
S57：对第一光阻区域和第二光阻区域进行灰化处理，以去除第一光阻区域，并保留部分第二光阻区域。
S58：刻蚀去除未被所述部分第二光阻区域覆盖的重掺杂硅层及金属层，形成源极图案和漏极图案。
S59：去除所述部分第二光阻区域。
S60：在绝缘层上形成覆盖源极图案和漏极图案的平坦层，所述平坦层开设有暴露漏极图案表面的接触孔。
S61：在平坦层上形成电极图案，使得所述电极图案可通过接触孔与漏极图案电连接。
在退火处理过程中，重掺杂硅层30中的Si原子会扩散到有源层24中，从而形成掺杂的有源层24，例如n+IGZO层，由于Si掺杂的IGZO比未掺杂的IGZO有更好的耐负向偏压和耐光照的特性，因此本实施例能够提高TFT的电学稳定性。
通过上述方式，本发明即可制得所需要的阵列基板。
本发明还提供一实施例的液晶显示面板，如图6所示，该液晶显示面板60包括阵列基板61和彩膜基板62，该阵列基板61可以为采用上述任一实施例方法所制得的阵列基板，因此该液晶显示面板60也具有上述有益效果。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各 实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种阵列基板的制造方法，其中，所述方法包括：
    在基板上依次形成栅极图案和绝缘层；
    在所述绝缘层上依次形成有源层、非晶硅层、金属层及光阻层；
    采用Half-tone(半色调)光罩对所述光阻层曝光显影，形成第一光阻区域和位于第一光阻区域两侧的第二光阻区域，所述第一光阻区域的厚度小于所述第二光阻区域的厚度；
    刻蚀去除未被所述第一光阻区域和第二光阻区域遮盖的有源层、非晶硅层及金属层；
    对所述第一光阻区域和第二光阻区域进行灰化处理，以去除所述第一光阻区域，并保留部分第二光阻区域；
    刻蚀去除未被所述部分第二光阻区域覆盖的金属层，形成源极图案和漏极图案；
    去除所述部分第二光阻区域；
    在所述绝缘层上形成覆盖所述源极图案和漏极图案的平坦层，所述平坦层开设有暴露所述漏极图案表面的接触孔；
    在所述平坦层上形成电极图案，使得所述电极图案可通过所述接触孔与所述漏极图案电连接。
  2. 根据权利要求1所述的方法，其中，所述方法还包括：在所述非晶硅层和所述金属层之间形成重掺杂硅层；
    所述刻蚀去除未所述第一光阻区域和第二光阻区域遮盖的有源层、非晶硅层及金属层，包括：刻蚀去除未被所述第一光阻区域和第二光阻区域遮盖的有源层、非晶硅层、重掺杂硅层及金属层；
    所述刻蚀去除未被所述部分第二光阻区域覆盖的金属层，包括：刻蚀去除未被所述部分第二光阻区域覆盖的重掺杂硅层及金属层。
  3. 根据权利要求2所述的方法，其中，在所述绝缘层上依次形成有源层、非晶硅层、金属层及光阻层，包括：
    在所述绝缘层上依次形成有源层、非晶硅层及重掺杂硅层；
    对所述重掺杂硅层进行退火处理，使得所述重掺杂硅层中的硅原子进 入所述有源层，对所述有源层进行掺杂；
    在经过所述退火处理的重掺杂硅层上依次形成金属层及光阻层。
  4. 根据权利要求3所述的方法，其中，所述重掺杂硅层中掺杂有n+型杂质离子。
  5. 根据权利要求2所述的方法，其中，所述刻蚀去除未被所述第一光阻区域和第二光阻区域遮盖的有源层、非晶硅层及金属层，包括：
    对所述金属层采用湿法刻蚀；
    对所述重掺杂硅层和所述非晶硅层采用干法刻蚀；
    对所述有源层采用湿法刻蚀。
  6. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    依次形成于所述基板上的栅极图案和绝缘层；
    依次形成于绝缘层上的有源层、非晶硅层、源极图案和漏极图案；
    形成于所述绝缘层上且覆盖所述源极图案和漏极图案的平坦层，所述平坦层开设有暴露所述漏极图案表面的接触孔；
    形成于所述平坦层上的电极图案，所述电极图案可通过所述接触孔与所述漏极图案电连接。
  7. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括形成于所述非晶硅层和所述漏极图案之间，以及所述非晶硅层和所述源极图案之间的重掺杂硅层。
  8. 根据权利要求7所述的阵列基板，其中，所述有源层中掺杂有所述重掺杂硅层在退火处理时进入的硅原子。
  9. 根据权利要求7所述的阵列基板，其中，所述重掺杂硅层中掺杂有n+型杂质离子。
  10. 一种液晶显示面板，其中，所述液晶显示面板的阵列基板包括：
    基板；
    依次形成于所述基板上的栅极图案和绝缘层；
    依次形成于绝缘层上的有源层、非晶硅层、源极图案和漏极图案；
    形成于所述绝缘层上且覆盖所述源极图案和漏极图案的平坦层，所述平坦层开设有暴露所述漏极图案表面的接触孔；
    形成于所述平坦层上的电极图案，所述电极图案可通过所述接触孔与所述漏极图案电连接。
  11. 根据权利要求10所述的液晶显示面板，其中，所述阵列基板还包括形成于所述非晶硅层和所述漏极图案之间，以及所述非晶硅层和所述源极图案之间的重掺杂硅层。
  12. 根据权利要求11所述的液晶显示面板，其中，所述有源层中掺杂有所述重掺杂硅层在退火处理时进入的硅原子。
  13. 根据权利要求11所述的液晶显示面板，其中，所述重掺杂硅层中掺杂有n+型杂质离子。
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