WO2019007322A1 - 堆叠螺旋电感 - Google Patents

堆叠螺旋电感 Download PDF

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Publication number
WO2019007322A1
WO2019007322A1 PCT/CN2018/094241 CN2018094241W WO2019007322A1 WO 2019007322 A1 WO2019007322 A1 WO 2019007322A1 CN 2018094241 W CN2018094241 W CN 2018094241W WO 2019007322 A1 WO2019007322 A1 WO 2019007322A1
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metal layer
layer
metal
inductive
inductor
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PCT/CN2018/094241
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English (en)
French (fr)
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董聪颖
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无锡华润上华科技有限公司
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Priority to US16/481,600 priority Critical patent/US20200005980A1/en
Publication of WO2019007322A1 publication Critical patent/WO2019007322A1/zh
Priority to US18/308,399 priority patent/US12009129B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0013—Printed inductances with stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F2017/0073—Printed inductances with a special conductive pattern, e.g. flat spiral
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F2017/008—Electric or magnetic shielding of printed inductances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F2017/0086—Printed inductances on semiconductor substrate

Definitions

  • the present invention relates to the field of semiconductor technology, and more particularly to stacked spiral inductors.
  • the conventional stacked spiral inductor is a stacked spiral inductor that is connected to each other by forming a planar spiral inductor on each metal layer and then connecting the adjacent two layers of spiral inductors through metal through holes. .
  • the shape and size of the planar spiral inductors in the first metal layer, the second metal layer, and the third metal layer are the same.
  • the parasitic capacitance of the planar spiral inductor between the metal layer and the metal layer is large, and the parasitic coupling capacitance with the silicon-based substrate also becomes large, which seriously affects the performance of the stacked spiral inductor.
  • a stacked spiral inductor comprising a substrate and a plurality of layers of an insulating layer and an inductive metal layer formed on the substrate by a semiconductor process; the inductive metal layer comprising a conductive coil having a spiral shape and for connecting adjacent two a through-hole region of the layer of the inductive metal layer, the wire coil of each of the inductive metal layers has a common coil center, and the conductive coil of the lower inductive metal layer is opposite to the conductive coil of the upper inductive metal layer in the adjacent two layers of the inductive metal layer The coil center is retracted.
  • FIG. 1 is a schematic structural view of a conventional stacked spiral inductor
  • FIG. 2 is a top plan view of a stacked spiral inductor in one embodiment
  • FIG. 3 is another top view of a stacked spiral inductor in one embodiment
  • FIG. 4 is a partially enlarged schematic view showing an open end of a stacked spiral inductor in an embodiment
  • Figure 5 is a top plan view of a stacked spiral inductor in another embodiment
  • FIG. 6 is a top plan view of a grounding shield layer in a stacked spiral inductor in one embodiment
  • Figure 7 is a top plan view of a stacked spiral inductor in another embodiment.
  • a stacked spiral inductor includes a substrate and a plurality of layers of an insulating layer and an inductive metal layer formed on the substrate by a semiconductor process on the substrate.
  • the substrate may be a silicon substrate, or may be gallium arsenide, germanium silicide or other semiconductor substrate.
  • the insulating layer may be formed by depositing or epitaxially forming on the substrate, and the insulating layer may be a silicon dioxide layer or a silicon nitride layer or other insulating oxide layer.
  • the insulating layer is etched to form a via hole, and an insulating metal layer is sputter-deposited on the insulating layer, and the semiconductor process is repeated to form a multilayer stacked insulating layer and an inductive metal layer on the substrate.
  • the inductive metal layer is formed by a selective etching to form a conductive coil having a spiral shape and a via hole region for connecting adjacent two layers of the inductor metal layer, and a via hole region and an insulating layer of the inductor metal layer.
  • Figure 2 shows a top view of the stacked spiral inductor.
  • the conductive coils formed by etching in each layer of the inductive metal layer have the same shape, have a common coil center O, and have different sizes.
  • the conductive coil L2 of the lower inductive metal layer is indented toward the coil center O with respect to the conductive coil L1 of the upper inductive metal layer, that is, the distance of the conductive coil L2 of the lower inductive metal layer
  • the pitch of the coil center O is smaller than the pitch of the conductive coil L1 of the upper inductor metal layer from the coil center O.
  • the spiral inductor on the conventional stacked sheet is directly translated to the lower layer, that is, the shape and size of the planar spiral inductor in the first metal layer m1, the second metal layer m2, and the third metal layer m3. All the same.
  • a parasitic capacitance like a flat capacitor is generated between adjacent two layers of inductive metal layers, which seriously affects the performance of the on-chip spiral inductor.
  • the wire coil in the lower inductive metal layer is indented toward the center with respect to the conductive coil in the upper inductive metal layer, without changing the conditions of the prior art technology.
  • the parasitic capacitance between the adjacent two layers of the inductor metal layer can be reduced, the resonance frequency of the two layers can be improved, and the quality factor Q of the spiral inductor can be improved, and the performance of the spiral inductor can be improved.
  • the stacked spiral inductor includes two layers of inductive metal layers, namely a top inductor metal layer M1, that is, a first inductor metal layer M1, and a second top inductor metal layer M2, that is, a second inductor metal.
  • Layer M2 The pitch of the conductive coil L2 of the second inductive metal layer M2 with respect to the conductive coil L1 of the first inductive metal layer M1 to the center O of the conductive coil ranges from 2 micrometers to 3 micrometers.
  • the pitch D2 of the conductive coil L2 of the second inductive metal layer M2 from the coil center O is smaller than the pitch D1 of the conductive coil L1 of the first inductive metal layer M1 from the coil center O, and the conductive coil L2 of the second inductive metal layer M2
  • the stacked spiral inductor comprises an n (n>2) layer of an inductive metal layer, and the first inductive metal layer, the second inductive metal layer, ..., the nth are sequentially included from the top inductive metal layer to the underlying metal layer. Inductive metal layer.
  • the distance from the top inductive metal layer to the conductive layer in the underlying metal layer from the center of the coil is D1, D2, ..., Dn.
  • the wire coil of the third inductive metal layer is indented with respect to the wire coil of the second inductive metal layer
  • the pitch ⁇ d2 D2-D3
  • the spacing ⁇ d1, ⁇ d2, ..., ⁇ dn-1 of each indentation is equal, which may be equal to any value from 2 microns to 3 microns.
  • the spacing ⁇ d1, ⁇ d2, ..., ⁇ dn-1 of each indentation is arranged in an arithmetic progression.
  • ⁇ d1 ⁇ d2 ⁇ ... ⁇ dn-1 may be ⁇ d1> ⁇ d2>...> ⁇ dn-1.
  • the spacing of each indentation can be set according to actual needs, and the spacing of each indentation is not limited to the indentation range enumerated in the above embodiment.
  • the conductive coils of the same layer of inductive metal have the same linewidth, and the conductive coils have a line width ranging from 6 microns to 15 microns.
  • the line widths of the conductive coils from the top inductive metal layer to the underlying metal layer may be the same, or may be in an increasing trend, or may be in a decreasing trend, and may of course be alternated.
  • the line width of the conductive coil of each layer of the inductive metal layer can be set according to actual needs.
  • the conductive coils in each layer of inductive metal include a lead end and an open termination disposed opposite the lead end.
  • the inductive metal layer includes an inductive metal layer M1 (first inductive metal layer) and a sub-top inductive metal layer M2 (second inductive metal layer) on the top layer.
  • the conductive coil L1 of the first inductive metal layer M1 includes a lead terminal 10 and an opening terminal 20 disposed opposite the lead terminal 10, and the lead terminal 10 is a lead terminal of the spiral inductor, and the opening terminal The portion 20 is provided with the through hole area (not shown).
  • the opening terminal 20 includes a first extension portion 210 and a second extension portion 220 that are oppositely and spaced apart, and the through hole region 201 is respectively disposed at the first extension portion 210 and the second extension portion.
  • the terminal of the department 220 The sum of the line widths of the first extension portion 210 and the second extension portion 220 is smaller than the line width of the conductive coil L1 (not shown).
  • the line widths of the first extension portion 210 and the second extension portion 220 are equal, and the line widths of the first extension portion 210 and the second extension portion 220 are 1/3 of the line width of the conductive coil L1.
  • the through hole regions are disposed in the opposite and spaced first and second extension portions, and no corner points are required in the through hole region, which simplifies the process complexity of etching the conductive coils, improves efficiency, and reduces costs.
  • the conductive coils of the first inductive metal layer and the second inductive metal layer may be electrically connected through the via region.
  • the stacked spiral inductor comprises an n (n>2) layer of an inductive metal layer, and the first inductive metal layer, the second inductive metal layer, ..., the nth are sequentially included from the top inductive metal layer to the underlying metal layer.
  • the conductive coil of the first inductive metal layer includes a lead end and an opening terminal disposed opposite the lead end, the lead end is a lead terminal of the spiral inductor, and the through end is provided at the opening end Hole area.
  • a via region (not labeled) for connecting the lower adjacent third metal layer M3 in the second inductive metal layer M2 is disposed on the same side as the lead terminal 10 of the first inductive metal layer M1. .
  • the via hole region of the third inductive metal layer M3 for connecting the lower adjacent fourth metal layer is disposed on the same side as the lead terminal of the second inductive metal layer.
  • the via hole region of the n-1th inductor metal layer for connecting the adjacent nth metal layer is disposed on the same side as the lead terminal of the first inductor metal layer.
  • the via hole region of the n-1th inductor metal layer for connecting the adjacent nth metal layer is disposed on the same side as the lead terminal of the second inductor metal layer.
  • the hexagonal spiral inductor is described.
  • the shape of the spiral inductor is not limited thereto, and other types of spirals may be used.
  • a quadrangle, an octagon or a circle may be applied to the present invention. invention.
  • the stacked spiral inductor further includes a grounded shield (PGS) disposed between the substrate and the bottommost inductive metal layer, and the ground shield is used to interrupt the inductor to the silicon substrate.
  • PPS grounded shield
  • the grounding shielding layer (not shown) is provided with a plurality of concentric metal rings (Q1, Q2), and (Q1, Q2) are respectively provided with a plurality of metal strips T disposed perpendicularly to the metal ring. Wherein the length of the metal strip T is smaller than the spacing of the adjacent two metal rings.
  • the plurality of metal strips are not connected to each other in the plane, and are kept at a fixed pitch, and are connected and grounded only through the metal ring at the outermost edge of the plane, thereby reducing electromagnetic loss to the silicon substrate.
  • the number of the metal rings is the same as the number of layers of the inductive metal layer, and the shape of the metal ring is the same as the shape of the conductive coil.
  • the grounding shielding layer is provided with two concentric metal rings, wherein, in space, the metal strip on the outermost metal ring Q1 and the first The conductive coil L1 of an inductive metal layer is disposed vertically; the metal strip on the innermost metal ring Q2 is disposed perpendicular to the conductive coil L2 of the second inductive metal layer.
  • the conductive coil L2 of the second inductive metal layer and the conductive coil L1 of the first inductive metal layer are projected to the ground shield layer, the innermost metal ring Q2, the conductive coil L2 of the second inductive metal layer, and the outermost layer
  • the metal coil Q1 and the conductive coil L1 of the first inductor metal layer are sequentially disposed concentrically from the inside to the outside.
  • the ground shield layer is provided with n-circle concentric metal rings.
  • the metal strips corresponding to the metal rings from the outermost layer to the innermost layer are respectively disposed vertically corresponding to the conductive coils from the top inductive metal layer to the underlying inductive metal layer.
  • the metal strip on the outermost metal ring is disposed perpendicular to the conductive coil of the top inductor metal layer.
  • the metal strip on the innermost metal ring is disposed perpendicular to the conductive coil of the bottom inductor metal layer.
  • the conductive coil from the top inductor metal layer to the bottom inductor metal layer is projected to the ground shield layer, the conductive coils from the top inductor metal layer to the bottom inductor metal layer are respectively disposed on the ground shield layer.
  • the outside of the concentric metal ring from the outside to the inside.
  • the conductive coil of the top inductor metal layer is disposed outside the outermost metal coil of the ground shield layer, and the conductive coil of the bottom inductor metal layer is disposed between the innermost metal ring of the ground shield layer and the inner inner metal ring.
  • a plurality of concentric metal rings are disposed on the grounding shielding layer, and a plurality of metal strips disposed perpendicular to the metal ring are disposed on each of the metal rings.
  • the metal strip is disposed perpendicular to the conductance coils in the inductive metal layers of each layer, which can shield most of the eddy current effect of the silicon-based substrate which occurs with high-frequency electromagnetic waves, thereby reducing the parasitic capacitance between the spiral inductor and the substrate. Improve the quality factor Q of the spiral inductor, thereby improving the performance of the spiral inductor.
  • the hexagonal spiral inductor is formed on the silicon substrate, but in practical applications, the shape of the spiral inductor is not limited thereto, and may be other kinds of spirals, such as a quadrangle, an octagon, or Circular shapes can be applied to the present invention.

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Abstract

一种堆叠螺旋电感，包括衬底以及通过半导体工艺在衬底上形成多层堆叠的绝缘层和电感金属层；电感金属层包括具有螺旋状的导电线圈以及用于连接相邻两层电感金属层的通孔区域，各个电感金属层的导线线圈具有公共的线圈中心，相邻两层电感金属层中，下层电感金属层的导电线圈相对于上层电感金属层的导电线圈向线圈中心缩进。

Description

堆叠螺旋电感 技术领域
本发明涉及半导体技术领域，特别是涉及堆叠螺旋电感。
背景技术
传统的堆叠螺旋电感是通过在每一层金属层上制备一个平面螺旋电感，然后通过金属通孔将相邻两层的螺旋电感连接起来，即可变成三层金属层相互连接的堆叠螺旋电感。其中，第一金属层、第二金属层、第三金属层中平面螺旋电感的形状、大小均相同。传统的堆叠螺旋电感中，金属层与金属层之间平面螺旋电感的寄生电容较大，而且与硅基衬底之间的寄生耦合电容也会变大，严重的影响了堆叠螺旋电感的性能。
发明内容
基于此，有必要提供一种无需改变现有工艺技术的条件下，在同等衬底面积上，能够提高螺旋电感性能的堆叠螺旋电感。
一种堆叠螺旋电感，包括衬底以及通过半导体工艺在所述衬底上形成多层堆叠的绝缘层和电感金属层；所述电感金属层包括具有螺旋状的导电线圈以及用于连接相邻两层电感金属层的通孔区域，各个所述电感金属层的导线线圈具有公共的线圈中心，相邻两层电感金属层中，下层电感金属层的导电线圈相对于上层电感金属层的导电线圈向所述线圈中心缩进。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参 考一副或多副附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为传统堆叠螺旋电感的结构示意图；
图2为一个实施例中堆叠螺旋电感的俯视图；
图3为一个实施例中堆叠螺旋电感的另一俯视图；
图4为一个实施例中堆叠螺旋电感中开口端的局部放大示意图；
图5为另一个实施例中堆叠螺旋电感的俯视图；
图6为一个实施例中堆叠螺旋电感中接地屏蔽层的俯视图；
图7为另一个实施例中堆叠螺旋电感的俯视图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
一种堆叠螺旋电感，包括衬底以及在所述衬底上通过半导体工艺在所述衬底上形成多层堆叠的绝缘层和电感金属层。
其中，衬底可以为硅衬底，也可以为砷化镓、硅化锗或者其他半导体衬底。通过在所述衬底上沉积或外延生成形成绝缘层，其绝缘层可以为二氧化硅层，也可以为氮化硅层或其他绝缘的氧化物层。刻蚀绝缘层形成通孔，在所述绝缘层上溅射形成电感金属层，重复上述半导体工艺在所述衬底上形成 多层堆叠的绝缘层和电感金属层。
在一个实施例中，所述电感金属层通过选择性的刻蚀形成具有螺旋状的导电线圈以及用于连接相邻两层电感金属层的通孔区域，电感金属层的通孔区域与绝缘层中的通孔对应设置。如图2所示的为堆叠螺旋电感的俯视图。每一层电感金属层中通过刻蚀形成的导电线圈的形状都相同，具有公共的线圈中心O，尺寸不同。在相邻两层电感金属层中，其下层电感金属层的导电线圈L2相对于上层电感金属层的导电线圈L1向所述线圈中心O缩进，也即，下层电感金属层的导电线圈L2距离线圈中心O的间距小于上层电感金属层的导电线圈L1距离线圈中心O的间距。
在同等面积的情况下，如图1所示，传统堆叠片上螺旋电感是直接向下层平移，即第一金属层m1、第二金属层m2、第三金属层m3中平面螺旋电感的形状、大小均相同。在高频工作时，相邻两层电感金属层之间会产生类似平板电容的寄生电容，严重影响了片上螺旋电感的性能。而本发明实施例中的，相邻两层电感金属层中，其下层电感金属层中的导线线圈相对于上层电感金属层中得导电线圈向中心缩进，在无需改变现有工艺技术的条件且在同等衬底面积的情况下，可以减少相邻两层电感金属层之间的寄生电容，提高自身的谐振频率，继而可以提高螺旋电感品质因数Q值，提高螺旋电感的性能。
在一个实施例中，参考图2，堆叠螺旋电感包括两层电感金属层，分别为顶层电感金属层M1，也即第一电感金属层M1；次顶层电感金属层M2，也即第二电感金属层M2。其中，第二电感金属层M2的导电线圈L2相对于第一电感金属层M1的导电线圈L1向所述导电线圈的中心O缩进的间距范围为2微米～3微米。也即，第二电感金属层M2的导电线圈L2距离线圈中心O的间距D2小于第一电感金属层M1的导电线圈L1距离线圈中心O的间距D1，而且第二电感金属层M2的导电线圈L2相对于第一电感金属层M1的导电线圈L1向中心O缩进的间距范围δd＝D1-D2为2微米～3微米。
在一个实施例中，堆叠螺旋电感包括n(n＞2)层的电感金属层，从顶 层电感金属层向底层金属层依次包括有第一电感金属层、第二电感金属层、…、第n电感金属层。其中，从顶层电感金属层到底层金属层中的导电线圈距离线圈中心的间距依次为D1、D2、…、Dn。其中，第二电感金属层的导线线圈相对于第一电感金属层的导线线圈缩进的间距Δd1＝D1-D2，第三电感金属层的导线线圈相对于第二电感金属层的导线线圈缩进的间距Δd2＝D2-D3，第n-1电感金属层的导线线圈相对于第n电感金属层的导线线圈缩进的间距Δdn-1＝Dn-1-Dn。
在一个实施例中，每一次缩进的间距Δd1、Δd2、…、Δdn-1均相等，其可以等于2微米～3微米中的任意数值。
在一个实施例中，每一次缩进的间距Δd1、Δd2、…、Δdn-1呈等差数列排布。其中，可以为Δd1<Δd2<…<Δdn-1，还可以为Δd1>Δd2>…>Δdn-1。在实际应用中，可以根据实际需求来设定每一次缩进的间距，其每一次缩进的间距不限于上述实施例所列举的缩进范围。
在一个实施例中，同一层电感金属层的导电线圈的线宽相同，其导电线圈的线宽范围为6微米～15微米。
具体地，从顶层电感金属层到底层金属层中的导电线圈的线宽可以均相同，也可以呈递增的趋势变化，亦可以呈递减的趋势变化，当然也可以交替变化。其每一层电感金属层的导电线圈的线宽可以根据实际需求来设定。
在一个实施例中，每一层电感金属层中的导电线圈包括引线端以及与引线端相对设置的开口终端。参考图3，电感金属层包括位于顶层的电感金属层M1(第一电感金属层)和次顶层电感金属层M2(第二电感金属层)。其中，所述第一电感金属层M1的导电线圈L1包括引线端10以及与所述引线端10相对设置的开口终端20，所述引线端10为所述螺旋电感的引出端子，所述开口终端处20设有所述通孔区域(图未标)。
具体地，参考图4，所述开口终端20包括相对且间隔设置的第一延伸部210和第二延伸部220，所述通孔区域201分别设置在所述第一延伸部210、第二延伸部220的终端。所述第一延伸部210与第二延伸部220的线宽之和 小于所述导电线圈L1(图未标)的线宽。在一个实施例中，第一延伸部210与第二延伸部220的线宽相等，且第一延伸部210与第二延伸部220的线宽为导电线圈L1的线宽的1/3。
将通孔区域设置在相对且间隔设置的第一延伸部和第二延伸部中，不需要在通孔区域设置拐角点，简化了刻蚀导电线圈的工艺复杂度，提高了效率，降低了成本。通过通孔区域，可以电连接第一电感金属层与第二电感金属层的导电线圈。
在一个实施例中，堆叠螺旋电感包括n(n＞2)层的电感金属层，从顶层电感金属层向底层金属层依次包括有第一电感金属层、第二电感金属层、…、第n电感金属层。其中，所述第一电感金属层的导电线圈包括引线端以及与所述引线端相对设置的开口终端，所述引线端为所述螺旋电感的引出端子，所述开口终端处设有所述通孔区域。参考图5，第二电感金属层M2中用于连接下方相邻的第三金属层M3的通孔区域(图未标)与所述第一电感金属层M1的引线端10设置在相同一侧。第三电感金属层M3中用于连接下方相邻的第四金属层的通孔区域与所述第二电感金属层的引线端设置在相同一侧。相应的，若n为奇数，则第n-1电感金属层中用于连接下方相邻的第n金属层的通孔区域与所述第一电感金属层的引线端设置在相同一侧。若n为偶数，则第n-1电感金属层中用于连接下方相邻的第n金属层的通孔区域与所述第二电感金属层的引线端设置在相同一侧。
上述实施例中六边形螺旋电感作说明，但在实际应用中，螺旋电感的形状并不限于此，还可以为其他种类的螺旋状，例如四边形、八边形或者圆形皆可以应用于本发明。
在一个实施例中，堆叠螺旋电感还包括设置在衬底和最底层所述电感金属层之间的接地屏蔽层(Patterned Ground Shield，PGS)，接地屏蔽层用于中断电感到硅片衬底的磁场，减少由于衬底引起的电磁损耗，从而提高Q值。
参考图6，所述接地屏蔽层(图未标)上设有多个同心金属圈(Q1、Q2)，(Q1、Q2)上均设有与所述金属圈垂直设置的多个金属条T，其中，所述金 属条T的长度小于所述相邻两金属圈的间距。多个金属条在平面内部是互不相连，保持固定间距，只在平面最外侧边沿通过金属圈连接并接地，实现降低对硅衬底电磁损耗。
在一个实施例中，所述金属圈的数量与所述电感金属层的层数相同，所述金属圈的形状与所述导电线圈的形状相同。
具体地，参考图7，若电感导电金属层的层数为两层，则接地屏蔽层上设有两圈同心金属圈，其中，在空间上，最外层金属圈Q1上的金属条与第一电感金属层的导电线圈L1对应垂直设置；最内层金属圈Q2上的金属条与第二电感金属层的导电线圈L2对应垂直设置。也即，若第二电感金属层的导电线圈L2、第一电感金属层的导电线圈L1投影至接地屏蔽层时，最内层金属圈Q2、第二电感金属层的导电线圈L2、最外层金属圈Q1、第一电感金属层的导电线圈L1依次由内之外同心设置。
具体地，若电感导电金属层的层数为n(n＞2)层，接地屏蔽层上设有n圈同心金属圈。在空间上，从最外层到最内层的金属圈所对应的金属条分别依次与从顶层电感金属层到底层电感金属层的导电线圈对应垂直设置。其中，最外层金属圈上的金属条与顶层电感金属层的导电线圈对应垂直设置，相应的，所述最内层金属圈上的金属条与底层电感金属层的导电线圈对应垂直设置。也可以理解为，若从顶层电感金属层到底层电感金属层的导电线圈均投影至接地屏蔽层时，则从顶层电感金属层到底层电感金属层的导电线圈分别依次设置在接地屏蔽层上的由外至内的同心金属圈的外侧。其中，顶层电感金属层的导电线圈设置在接地屏蔽层最外层金属圈的外侧，底层电感金属层的导电线圈设置在接地屏蔽层最内层金属圈与次内层金属圈之间。
通过在接地屏蔽层上设置的设有多个同心金属圈，以及在每个金属圈上均设有与所述金属圈垂直设置的多个金属条。其中，金属条与各层电感金属层内的电导线圈垂直设置，可以屏蔽大部分随着高频电磁波而出现的硅基衬底涡流效应，从而减小了螺旋电感与衬底之间的寄生电容，提高螺旋电感品质因数Q值，进而提高螺旋电感的性能。
上述实施例中以在硅衬底上形成六边形螺旋电感作说明，但在实际应用中，螺旋电感的形状并不限于此，还可以为其他种类的螺旋状，例如四边形、八边形或者圆形皆可以应用于本发明。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种堆叠螺旋电感，包括衬底以及通过半导体工艺在所述衬底上形成多层堆叠的绝缘层和电感金属层；
    所述电感金属层包括具有螺旋状的导电线圈以及用于连接相邻两层电感金属层的通孔区域，各个所述电感金属层的导线线圈具有公共的线圈中心；
    相邻两层电感金属层中，下层电感金属层的导电线圈相对于上层电感金属层的导电线圈向所述线圈中心缩进。
  2. 根据权利要求1所述的堆叠螺旋电感，其中，每一层缩进的间距相等或每一层缩进的间距呈等差数列排布。
  3. 根据权利要求1所述的堆叠螺旋电感，其中，每一层缩进的间距范围为2微米～3微米。
  4. 根据权利要求1所述的堆叠螺旋电感，其中，各所述电感金属层中的导电线圈包括引线端以及与所述引线端相对设置的开口终端；
    位于顶层的电感金属层为第一电感金属层，与所述第一电感金属层相邻设置的为第二电感金属层，与所述第二电感金属层下方相邻的为第三电感金属层；
    所述第一电感金属层中用于连接所述第二金属层的通孔区域设置在所述所述第一电感金属层的开口终端处，所述第一层电感金属层的引线端为所述螺旋电感的引出端子；
    所述第二电感金属层中用于连接所述第三金属层的通孔区域与所述第一电感金属层的引线端设置在相同一侧。
  5. 根据权利要求4所述的堆叠螺旋电感，其中，所述开口终端包括相对且间隔设置的第一延伸部和第二延伸部，所述通孔区域分别设置在所述第一延伸部、第二延伸部的终端。
  6. 根据权利要求5所述的堆叠螺旋电感，其中，所述第一延伸部与第二延伸部的线宽之和小于所述导电线圈的线宽。
  7. 根据权利要求1所述的堆叠螺旋电感，其中，所述导电线圈的线宽范 围为6微米～15微米。
  8. 根据权利要求1所述的堆叠螺旋电感，其中，所述导电线圈的形状为六边形、八边形、四边形或圆形。
  9. 根据权利要求1所述的堆叠螺旋电感，其中，还包括设置在衬底和最底层所述电感金属层之间的接地屏蔽层。
  10. 根据权利要求9所述的堆叠螺旋电感，其中，所述接地屏蔽层上设有多个同心金属圈，以及在每个金属圈上均设有与所述金属圈垂直设置的多个金属条，其中，所述金属条的长度小于所述相邻两金属圈的间距。
  11. 根据权利要求10所述的堆叠螺旋电感，其中，各所述金属条保持固定间距，且各金属条的一端与所述金属圈相连以通过所述金属圈接地。
  12. 根据权利要求10所述的堆叠螺旋电感，其中，所述金属圈的数量与所述电感金属层的层数相同。
  13. 根据权利要求10所述的堆叠螺旋电感，其中，所述金属圈的形状与所述导电线圈的形状相同。
  14. 根据权利要求12所述的堆叠螺旋电感，其中，从最外层到最内层的金属圈所对应的金属条分别依次与从顶层电感金属层到底层电感金属层的导电线圈对应垂直设置，其中，最外层金属圈上的金属条与顶层电感金属层的导电线圈对应垂直设置，所述最内层金属圈上的金属条与底层电感金属层的导电线圈对应垂直设置。
  15. 根据权利要求1所述的堆叠螺旋电感，其中，所述绝缘层为氧化物层。
  16. 根据权利要求1所述的堆叠螺旋电感，其中，各所述电感金属层中的导电线圈的形状相同。
  17. 根据权利要求1所述的堆叠螺旋电感，其中，处于同一层所述电感金属层的导电线圈的线宽相同。
  18. 根据权利要求1所述的堆叠螺旋电感，其中，从顶层电感金属层到底层电感金属层中的导电线圈的线宽均相同。
  19. 根据权利要求1所述的堆叠螺旋电感，其中，从顶层电感层到底层电感金属层中的导电线圈的线宽呈递增或递减趋势变化。
  20. 根据权利要求5所述的堆叠螺旋电感，其中，所述第一延伸部的线宽与第二延伸部的线宽相等，且所述第一延伸部的线宽与第二延伸部的线宽为所述导电线圈的线宽的1/3。
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Publication number Priority date Publication date Assignee Title
CN112768607A (zh) * 2020-12-31 2021-05-07 上海交通大学 一种高密度mom电容器结构及其设计方法
CN112768607B (zh) * 2020-12-31 2022-08-09 上海交通大学 一种高密度mom电容器结构及其设计方法

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