WO2019007320A1 - Jfet器件及其制造方法 - Google Patents

Jfet器件及其制造方法 Download PDF

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WO2019007320A1
WO2019007320A1 PCT/CN2018/094229 CN2018094229W WO2019007320A1 WO 2019007320 A1 WO2019007320 A1 WO 2019007320A1 CN 2018094229 W CN2018094229 W CN 2018094229W WO 2019007320 A1 WO2019007320 A1 WO 2019007320A1
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region
jfet device
doping
channel
well
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王琼
孙贵鹏
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/328—Channel regions of field-effect devices of FETs having PN junction gates

Definitions

  • the present solution relates to the field of semiconductor technology, and in particular to a JFET device and a method of fabricating the same.
  • High-voltage JFET (Junction Field-Effect Transistor) devices have a wide range of applications in power management chips, helping to achieve high-efficiency, low-power applications.
  • the problem often encountered is that the conventional high-voltage JFET structure uses the same high-voltage well to form the channel region and the drift region of the device, and it is difficult to simultaneously satisfy the withstand voltage and the pitch-off voltage.
  • Design requirements In order to achieve the design goal of the cutoff voltage, it is necessary to add a Mask (mask) to adjust the doping concentration of the channel region by means of impurity implantation, which increases the cost and complexity of the process.
  • a JFET device that includes:
  • a first well region formed on the substrate and having a first doping type
  • the second well region is provided with a source region, a channel region and a drift region which are sequentially arranged;
  • the channel region is provided with a spacer region belonging to the first well region; the spacer region is spaced apart by at least two segments of the channel extending from the source region to the drift region, and the width of the channel
  • the pinch-off voltage of the JFET device can be adjusted
  • the spacer is taken as the gate of the JFET device, the source region is taken as the source of the JFET device, and the drift region surface also forms a drain region and is drawn as the drain of the JFET device.
  • a method of fabricating a JFET device comprising:
  • first well region Forming a first well region on the substrate, the first well region having a first doping type; and the first well region being provided with a spacer region;
  • the second well region Forming a second well region on the substrate, the second well region having a second doping type; the second well region is provided with a source region, a channel region and a drift region which are sequentially arranged;
  • the spacer region spaces the channel region into at least two spaced apart channels extending from the source region to the drift region, the width of the channel adjusting the pinch-off voltage of the JFET device.
  • a method of fabricating a JFET device comprising a channel region and a drift region, the method comprising:
  • FIG. 1 is a top plan view of a JFET device layout of an embodiment
  • Figure 2 is a cross-sectional view taken along line B-B' of Figure 1;
  • Figure 3 is a cross-sectional view taken along line A-A' of Figure 1;
  • 4a is a schematic diagram showing one arrangement of a channel region spacer of a JFET device of an embodiment
  • FIG. 4b is a schematic view showing another arrangement of a channel region spacer of a JFET device according to an embodiment
  • FIG. 5 is a flow chart of a method of fabricating a JFET device according to an embodiment
  • FIG. 6 is a flow chart of a method of fabricating a JFET device of another embodiment.
  • the JFET device includes a first well region 100 and a second well region 200.
  • the first well region 100 has a first doping type and the second well region 200 has a second doping type.
  • the second well region 200 is provided with a source region 230, a channel region 210, and a drift region 220 which are sequentially arranged.
  • the channel region 210 is provided with a spacer 300.
  • the spacer 300 has a first doping type, and the spacer 300 spaces the channel region 210 into at least two mutually spaced channels extending from the source region 230 to the drift region 220, and the width of the channel can be adjusted.
  • the pinch-off voltage of a JFET device is taken as the gate of the JFET device, the source region 230 is taken as the source of the JFET device, and the surface of the drift region 220 further forms the drain region 240 and is taken out as the JFET device.
  • the drain is taken as the gate of the JFET device.
  • a plurality of spacers 300 extend in a first direction from the channel region 210 toward the drift region 220, and have a fixed width x1 in a second direction perpendicular to the first direction,
  • the corresponding channel region 210 is divided into a plurality of mutually spaced channels having a second doping type and having a width x2.
  • the channel region 210 is a channel for transporting holes or electrons
  • the gate region 300 is formed with a gate for controlling the opening and closing of the channel.
  • Figure 2 is a cross-sectional view taken along line B-B' of Figure 1. As can be seen from Figure 2, channel region 210 is in communication with drift region 220, and holes or electrons can pass through the channel into drift region 220 when the well region of channel region 210 is not depleted.
  • a plurality of spaced N-wells form a channel for transporting electrons
  • a P-well gate controls the opening and closing of the channel.
  • the gate voltage Vgs ⁇ 0V the N/P well junction is reverse biased, and the depletion layer is developed until the N well is fully depleted, the channel is turned off, and the gate voltage at this time is the JFET cutoff voltage; if the gate voltage Vgs>0V, the channel N/P well junction is positively biased, and the source electrons are transmitted to the drift region through the channel, and finally reach the drain under the action of the drain electric field, and the device is in an on state.
  • the width of the N-well determines the cut-off voltage of the JFET device.
  • the purpose of adjusting the cutoff voltage can be achieved by adjusting the width of the N well.
  • this adjustment is not achieved by adjusting the doping concentration by the additional impurity implantation of the channel region 210, so that it is not necessary to add an additional channel region impurity implantation mask, which reduces the process cost and complexity.
  • the width of the spacer 300 is uniform and the width of the spaced N-wells is also uniform. This makes it easier to control and adjust when forming the spacer 300.
  • the number of the spacers 300 is plural and spaced apart from each other. In other embodiments, the number of spacers 300 can also be two.
  • Fig. 3 is a cross-sectional view taken along line A-A' of Fig. 1, and in conjunction with Fig. 3, two or more spacers 300 are spaced apart from each other in parallel. In other embodiments, non-parallel spacing may also be used.
  • the length direction of the spacer 300 is substantially perpendicular to the edge of the drift region, which is more convenient to manufacture.
  • the arrangement of the spacers 300 is not limited thereto, and in other embodiments, other arrangements are also possible.
  • the spacers 300 are arranged in an oblique parallel arrangement; as shown in Figure 4b, the spacers 300 are all arranged obliquely but not parallel to each other. These arrangements are capable of adjusting the cutoff voltage.
  • the first doping type is N-type doping and the second doping type is P-type doping; then the JFET device is a P-channel JFET.
  • the first doping type is P-type doping and the second doping type is N-type doping; then the JFET device is an N-channel JFET.
  • FIG. 5 is a flow chart of a method of fabricating a JFET device of an embodiment. The method includes the following steps S110-S130 in conjunction with FIGS. 1 to 4b.
  • Step S110 forming a first well region 100 on the substrate, the first well region 100 having a first doping type.
  • the first well region 100 includes a spacer 300.
  • Step S120 forming a second well region 200 on the substrate, the second well region 200 having a second doping type; the second well region 200 is provided with a source region 230, a channel region 210, and a sequentially arranged source region Drift zone 220.
  • the spacer 300 spaces the channel region 210 into at least two spaced apart channels extending from the source region 230 to the drift region, the width of the channel adjusting the pinch-off voltage of the JFET device. .
  • a plurality of spacers 300 extend in a first direction from the channel region 210 toward the drift region 220, and have a fixed width x1 in a second direction perpendicular to the first direction, corresponding to the trench
  • the track zone 210 is divided into a plurality of mutually spaced channels and has a width x2.
  • the channel region 210 is a channel for transporting holes or electrons
  • the gate region 300 is formed with a gate for controlling the opening and closing of the channel.
  • Figure 2 is a cross-sectional view taken along line B-B' of Figure 1. As can be seen from FIG. 2, the channel region 210 is in communication with the drift region 220, and holes or electrons can enter the drift region 220 through the channel when the well region of the channel region 210 is not depleted.
  • a plurality of spaced N-type wells form a channel for transporting electrons
  • a P-type gate controls the opening and closing of the channel.
  • the gate voltage Vgs ⁇ 0V the N/P well junction is reverse biased, and the depletion layer is developed until the N well is fully depleted, the channel is turned off, and the gate voltage at this time is the JFET cutoff voltage; if the gate voltage Vgs>0V, the channel N/P well junction is positively biased, and the source electrons are transmitted to the drift region through the channel, and finally reach the drain under the action of the drain electric field, and the device is in an on state.
  • the width of the N-well determines the cut-off voltage of the JFET device.
  • the purpose of adjusting the cutoff voltage can be achieved by adjusting the width of the N well.
  • this adjustment is not achieved by adjusting the doping concentration by additional impurity implantation into the channel region 210, thereby reducing one process and eliminating the need for an additional mask to complete the process.
  • the width of the spacer 300 is uniform and the width of the spaced N-wells is also uniform. This makes it easier to control and adjust when forming the spacer 300.
  • the number of the spacers 300 is plural and spaced apart from each other. In other embodiments, the number of spacers 300 can also be one or two.
  • step S130 two or more spacers are spaced apart from each other in parallel. More specifically, Fig. 3 is a cross-sectional view taken along line A-A' of Fig. 1, and in conjunction with Fig. 3, two or more spacers 300 are spaced apart from each other in parallel. In other embodiments, non-parallel spacing may also be used.
  • the spacer region is extended in a first direction from the channel region toward the drift region, and has a fixed width in a second direction perpendicular to the first direction.
  • the length direction of the spacer 300 is substantially perpendicular to the edge of the drift region, which is more convenient to manufacture.
  • the arrangement of the spacers 300 is not limited thereto, and in other embodiments, other arrangements are also possible.
  • the spacers 300 are arranged in an oblique parallel arrangement; as shown in Figure 4b, the spacers 300 are all arranged obliquely but not parallel to each other. These arrangements are capable of adjusting the cutoff voltage.
  • the first doping type is N-type doping and the second doping type is P-type doping; then the JFET device is a P-channel JFET.
  • the first doping type is P-type doping and the second doping type is N-type doping; then the JFET device is an N-channel JFET.
  • the JFET device includes a channel region 210 and a drift region 220.
  • the method includes:
  • the first well region 100 has a first doping type.
  • Photolithography is performed using a second well region mask, then etched and doped to form a second well region 200 in the first region.
  • the second well region mask defines a pattern of the second well region 200 in the first region.
  • the doping process in this step turns it into the first Two well regions 200.
  • the second well region 200 includes a drift region second well located in the drift region 220 and at least two segments spaced apart from each other in the channel region 210, and a spacer 300 belonging to the first well region 100 between adjacent channels .
  • the second well region 200 has a second doping type.
  • the second well region forms a channel of the device, and the spacer region is subsequently taken out as a gate of the device; the width of the second well region is increased, the impurity in the channel region of the device is increased, and the gate voltage needs to be increased. It can be completely depleted, that is, the channel is closed; therefore, adjusting the width of the second well region can achieve the purpose of adjusting the cutoff voltage. At the same time, this adjustment is not achieved by adjusting the doping concentration by additional impurity implantation into the channel region, thus reducing one process.
  • the second well region of the channel region and the drift region share a mask (ie, the second well region mask), that is, an additional mask is not required to complete the process. The cost and complexity of the process are correspondingly reduced.
  • step S230 the method further includes the following steps:
  • a drain region 240 and a source region 230 are formed, and a second well region is connected to the drain region 240 and the source region 230.
  • Drain region 240 is taken as the drain of the JFET device
  • source region 230 is taken as the source of the JFET device
  • spacer 300 is taken out as the gate of the JFET device.
  • the JFET device is an N-channel JFET, the first doping type is P-type, and the second doping type is N-type.
  • the number of spacers 300 is two or more and are spaced apart from one another.
  • each of the spacers 300 are spaced apart from each other in parallel.
  • the spacer extends in a direction from the channel region 210 to the drift region 220.
  • the first well region 100 is a high voltage P-well and the second well region 200 is a high voltage N-well.
  • step S230 is to form the second well region 200 by ion implantation after etching.

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  • Junction Field-Effect Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种JFET器件及其制造方法。该JFET器件包括：第一阱区（100），形成于衬底上，具有第一掺杂类型；第二阱区（200），形成于衬底上，并具有第二掺杂类型；所述第二阱区(200)设有依次排列的源极区(230)、沟道区(210)和漂移区(220)；其中，所述沟道区(210)设有属于第一阱区（100）的间隔区（300）；所述间隔区(300)将沟道区(210)间隔为至少两段相互间隔的自源极区(230)向漂移区(220)延伸的沟道，沟道的宽度可调整所述JFET器件的夹断电压；所述间隔区(300)引出为所述JFET器件的栅极，所述源极区(230)引出为所述JFET器件的源极，所述漂移区(220)表面还形成漏极区(240)并引出为所述JFET器件的漏极。该制造方法用于制造该JFET器件。

Description

JFET器件及其制造方法 技术领域
本方案涉及半导体技术领域，特别是涉及一种JFET器件及其制造方法。
背景技术
高压JFET(Junction Field-Effect Transistor，结型场效应晶体管)器件在电源管理芯片中有着广泛的应用，有助于电路实现高效率、低功耗的应用需求。在高压BCD工艺生产过程中，经常遇到的问题是：常规高压JFET结构，用同一块高压阱形成器件的沟道区和漂移区，难以同时满足耐压和截止电压(pitch-off voltage)的设计需求。为了达到截止电压的设计目标，需要专门增加一块Mask(掩膜板)，通过杂质注入的方式调整沟道区掺杂浓度来实现，增加了工艺的成本及复杂度。
发明内容
基于此，有必要提供一种JFET器件及其制造方法。
一种JFET器件，包括：
第一阱区，形成于衬底上，具有第一掺杂类型；
第二阱区，形成于衬底上，并具有第二掺杂类型；所述第二阱区设有依次排列的源极区、沟道区和漂移区；
其中，所述沟道区设有属于第一阱区的间隔区；所述间隔区将沟道区间隔为至少两段相互间隔的自源极区向漂移区延伸的沟道，沟道的宽度可调整所述JFET器件的夹断电压；
所述间隔区引出为所述JFET器件的栅极，所述源极区引出为所述JFET器件的源极，所述漂移区表面还形成漏极区并引出为所述JFET器件的漏极。
一种JFET器件的制造方法，包括：
在衬底上形成第一阱区，所述第一阱区具有第一掺杂类型；所述第一阱区内设有间隔区；
在衬底上形成第二阱区，所述第二阱区具有第二掺杂类型；所述第二阱区设有依次排列的源极区、沟道区和漂移区；
所述间隔区将沟道区间隔为至少两段相互间隔的自源极区向漂移区延伸的沟道，沟道的宽度可调整所述JFET器件的夹断电压。
一种JFET器件的制造方法，所述JFET器件包括沟道区和漂移区，所述方法包括：
获取衬底；
在所述衬底上的第一区域形成第一阱区，所述第一阱区具有第一掺杂类型；
使用第二阱区掩膜板光刻，然后刻蚀并掺杂，以在所述第一区域内形成第二阱区，所述第二阱区包括位于所述漂移区的漂移区第二阱和位于所述沟道区的至少两段相互间隔的沟道，相邻的沟道之间为属于所述第一阱区的间隔区；所述第二阱区具有第二掺杂类型。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为一实施例的JFET器件布局的俯视图；
图2为图1中的B-B’截面图；
图3为图1中的A-A’截面图；
图4a为一实施例的JFET器件的沟道区间隔区的其中一种布置方式示意图；
图4b为一实施例的JFET器件的沟道区间隔区的其中另一种布置方式示意图；
图5为一实施例的JFET器件制造方法流程图；
图6为另一实施例的JFET器件制造方法流程图。
具体实施方式
为了使本方案的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本方案进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本方案，并不用于限定本方案。
图1为一实施例的JFET器件布局的俯视图。该JFET器件包括第一阱区100和第二阱区200。第一阱区100具有第一掺杂类型，第二阱区200具有第二掺杂类型。所述第二阱区200设有依次排列的源极区230、沟道区210和漂移区220。其中，所述沟道区210设有间隔区300。所述间隔区300具有第一掺杂类型，间隔区300将沟道区210间隔为至少两段相互间隔的自源极区230向漂移区220延伸的沟道，沟道的宽度可调整所述JFET器件的夹断电压。所述间隔区300引出为所述JFET器件的栅极，所述源极区230引出为所述JFET器件的源极，所述漂移区220表面还形成漏极区240并引出为所述JFET器件的漏极。
具体地，如图1所示，多个间隔区300在自沟道区210指向漂移区220的第一方向上延伸，且在与所述第一方向垂直的第二方向上具有固定宽度x1，对应沟道区210被划分为多个相互间隔的、具有第二掺杂类型的沟道，并具有宽度x2。
沟道区210是运送空穴或电子的通道，间隔区300形成的栅极用于控制沟道的开启和截止。图2为图1中的B-B’截面图。从图2可以看出，沟道区210与漂移区220连通，在沟道区210的阱区未被耗尽时，空穴或电子能够 通过沟道进入漂移区220。
以沟道区210为N型掺杂为例，多个间隔的N阱形成运送电子的通道，P阱栅极控制沟道的开启和截止。工作时，若栅极电压Vgs<0V，N/P阱结反偏，耗尽层展开至N阱全耗尽时，沟道关闭，此时的栅极电压为JFET截止电压；若栅极电压Vgs>0V，沟道N/P阱结正偏，源极电子通过沟道传输到漂移区，在漏极电场作用下最终到达漏极，此时器件处于导通状态。
当N型阱区的宽度较大时，沟道杂质增多，需要更大的栅极电压来耗尽沟道区杂质来关断沟道，截止电压更大。因此，N阱的宽度决定了JFET器件的截止电压。通过调整N阱的宽度即可达到调整截止电压的目的。
同时，这种调整不是通过对沟道区210的额外杂质注入调整掺杂浓度来实现的，因此不需要增加额外的沟道区杂质注入掩膜板，降低了工艺成本和复杂度。
在一个实施例中，间隔区300的宽度是均匀的，且间隔出的N型阱的宽度也是均匀的。这样在形成间隔区300时更加容易控制和调整。
在本实施例中，所述间隔区300的数量为多个，且相互间隔。在其他实施例中，间隔区300的数量也可以是两个。
更具体地，图3为图1中A-A’截面图，结合图3，两个以上的间隔区300相互平行间隔。在其他实施例中，也可以为非平行间隔。
在图1所示实施例中，间隔区300的长度方向基本与漂移区的边缘相互垂直，这样可以更加方便制作。但间隔区300的布置方式并不仅限于此，在其他实施例中，还可以是其他布置方式。如图4a所示，间隔区300为斜向的平行布置；如图4b所示，间隔区300均为斜向布置，但相互之间不不平行。这些布置方式都能够起到调整截止电压的目的。
在具体实施例中，所述第一掺杂类型为N型掺杂，所述第二掺杂类型为P型掺杂；则所述JFET器件为P沟道JFET。或者所述第一掺杂类型为P型掺杂，所述第二掺杂类型为N型掺杂；则所述JFET器件为N沟道JFET。
图5为一实施例的JFET器件的制造方法流程图。结合图1～图4b该方法包括以下步骤S110～S130。
步骤S110：在衬底上形成第一阱区100，所述第一阱区100具有第一掺杂类型。所述第一阱区100包括间隔区300。
步骤S120：在衬底上形成第二阱区200，所述第二阱区200具有第二掺杂类型；所述第二阱区200设有依次排列的源极区230、沟道区210和漂移区220。
所述间隔区300将沟道区210间隔为至少两段相互间隔的自源极区230向漂移区延伸的沟道，沟道的宽度可调整所述JFET器件的夹断电压。。
具体地，参照图1，多个间隔区300在自沟道区210指向漂移区220的第一方向上延伸，且在与所述第一方向垂直的第二方向上具有固定宽度x1，对应沟道区210被划分为多个相互间隔的沟道，并具有宽度x2。
沟道区210是运送空穴或电子的通道，间隔区300形成的栅极用于控制沟道的开启和截止。图2为图1中的B-B’截面图。从图2可以看出，沟道区210与漂移区220连通，在沟道区210的阱区未被耗尽时，空穴或电子能够通过沟道进入漂移区220。
以沟道区210为N型掺杂为例，多个间隔的N型阱形成运送电子的通道，P型的栅极控制沟道的开启和截止。工作时，若栅极电压Vgs<0V，N/P阱结反偏，耗尽层展开至N阱全耗尽时，沟道关闭，此时的栅极电压为JFET截止电压；若栅极电压Vgs>0V，沟道N/P阱结正偏，源极电子通过沟道传输到漂移区，在漏极电场作用下最终到达漏极，此时器件处于导通状态。
当N型阱区的宽度较大时，沟道杂质增多，需要更大的栅极电压来耗尽沟道区杂质来关断沟道，截止电压更大。因此，N阱的宽度决定了JFET器件的截止电压。通过调整N阱的宽度即可达到调整截止电压的目的。
同时，这种调整不是通过对沟道区210的额外杂质注入调整掺杂浓度来实现的，因此减少了一道工序，也不需要额外的掩膜板来配合完成该工序。
在一个实施例中，间隔区300的宽度是均匀的，且间隔出的N型阱的宽 度也是均匀的。这样在形成间隔区300时更加容易控制和调整。
在本实施例中，所述间隔区300的数量为多个，且相互间隔。在其他实施例中，间隔区300的数量也可以是一个或两个。
在步骤S130中，两个以上的间隔区相互平行间隔。更具体地，图3为图1中A-A’截面图，结合图3，两个以上的间隔区300相互平行间隔。在其他实施例中，也可以为非平行间隔。
在步骤S130中，使所述间隔区在自沟道区指向漂移区的第一方向上延伸，且在与所述第一方向垂直的第二方向上具有固定宽度。在图1所示实施例中，间隔区300的长度方向基本与漂移区的边缘相互垂直，这样可以更加方便制作。但间隔区300的布置方式并不仅限于此，在其他实施例中，还可以是其他布置方式。如图4a所示，间隔区300为斜向的平行布置；如图4b所示，间隔区300均为斜向布置，但相互之间不不平行。这些布置方式都能够起到调整截止电压的目的。
在具体实施例中，所述第一掺杂类型为N型掺杂，所述第二掺杂类型为P型掺杂；则所述JFET器件为P沟道JFET。或者所述第一掺杂类型为P型掺杂，所述第二掺杂类型为N型掺杂；则所述JFET器件为N沟道JFET。
还提供另一种JFET器件的制造方法。JFET器件包括沟道区210和漂移区220，结合图1～图4b，所述方法包括：
S210，获取衬底。
S220，在衬底上的第一区域形成第一阱区。
第一阱区100具有第一掺杂类型。
S230，使用第二阱区掩膜板光刻，然后刻蚀并掺杂，以在第一区域内形成第二阱区。
使用第二阱区掩膜板光刻，然后刻蚀并掺杂，以在第一区域内形成第二阱区200。第二阱区掩膜板在第一区域定义出了第二阱区200的图案，对于第一区域内已经形成第一阱区100的区域，本步骤中的掺杂工艺会将其变为第二阱区200。第二阱区200包括位于漂移区220的漂移区第二阱和位于沟 道区210的至少两段相互间隔的沟道，相邻的沟道之间为属于第一阱区100的间隔区300。第二阱区200具有第二掺杂类型。
上述JFET器件的制造方法，第二阱区形成了器件的沟道，间隔区后续引出作为器件的栅极；第二阱区的宽度增大，器件沟道区域杂质增多，需要增大栅极电压才能将其完全耗尽，即沟道关闭；所以，调整第二阱区的宽度即可达到调整截止电压的目的。同时，这种调整不是通过对沟道区的额外杂质注入调整掺杂浓度来实现的，因此减少了一道工序。沟道区和漂移区的第二阱区共用一块掩膜版(即第二阱区掩膜板)，也即不需要额外的掩膜板来配合完成该工序。工艺的成本和复杂度均有相应降低。
在一个实施例中，步骤S230之后还包括以下步骤：
形成漏极区240和源极区230，第二阱区连接漏极区240和源极区230。
将漏极区240引出为JFET器件的漏极，将源极区230引出为JFET器件的源极，将间隔区300引出为JFET器件的栅极。
在一个实施例中，JFET器件是N沟道JFET，第一掺杂类型为P型，第二掺杂类型为N型。
在一个实施例中，间隔区300的数量为两个以上，且相互间隔。
在一个实施例中，各间隔区300相互平行间隔。
在一个实施例中，间隔区在自沟道区210指向漂移区220的方向上延伸。
在一个实施例中，第一阱区100为高压P阱，第二阱区200为高压N阱。
在一个实施例中，步骤S230是刻蚀后通过离子注入形成第二阱区200。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本方案的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本方案构思的前提下，还可以做出若干变形和改进，这些都属于本方案的保护范围。因此，本方案专利的保护范围 应以所附权利要求为准。

Claims (18)

  1. 一种JFET器件，包括：
    第一阱区，形成于衬底上，具有第一掺杂类型；
    第二阱区，形成于衬底上，并具有第二掺杂类型；所述第二阱区设有依次排列的源极区、沟道区和漂移区；
    其中，所述沟道区设有属于第一阱区的间隔区；所述间隔区将沟道区间隔为至少两段相互间隔的自源极区向漂移区延伸的沟道，沟道的宽度可调整所述JFET器件的夹断电压；
    所述间隔区引出为所述JFET器件的栅极，所述源极区引出为所述JFET器件的源极，所述漂移区表面还形成漏极区并引出为所述JFET器件的漏极。
  2. 根据权利要求1所述的JFET器件，其特征在于，所述间隔区的数量为两个以上，且相互间隔。
  3. 根据权利要求2所述的JFET器件，其特征在于，两个以上的间隔区相互平行间隔。
  4. 根据权利要求1～3任一项所述的JFET器件，其特征在于，所述间隔区在自沟道区指向漂移区的第一方向上延伸，且在与所述第一方向垂直的第二方向上具有固定宽度。
  5. 根据权利要求1所述的JFET器件，其特征在于，所述第一掺杂类型为N型掺杂，所述第二掺杂类型为P型掺杂；或者所述第一掺杂类型为P型掺杂，所述第二掺杂类型为N型掺杂。
  6. 一种JFET器件的制造方法，包括：
    在衬底上形成第一阱区，所述第一阱区具有第一掺杂类型；所述第一阱区内设有间隔区；
    在衬底上形成第二阱区，所述第二阱区具有第二掺杂类型；所述第二阱区设有依次排列的源极区、沟道区和漂移区；
    所述间隔区将沟道区间隔为至少两段相互间隔的自源极区向漂移区延伸 的沟道，沟道的宽度可调整所述JFET器件的夹断电压。
  7. 根据权利要求6所述的JFET器件的制造方法，其特征在于，所述间隔区的数量为两个以上，且相互间隔。
  8. 根据权利要求7所述的JFET器件的制造方法，其特征在于，两个以上的间隔区相互平行间隔。
  9. 根据权利要求6～8任一项所述的JFET器件的制造方法，其特征在于，所述间隔区在自沟道区指向漂移区的第一方向上延伸，且在与所述第一方向垂直的第二方向上具有固定宽度。
  10. 根据权利要求6所述的JFET器件的制造方法，其特征在于，所述第一掺杂类型为N型掺杂，所述第二掺杂类型为P型掺杂；或者所述第一掺杂类型为P型掺杂，所述第二掺杂类型为N型掺杂。
  11. 一种JFET器件的制造方法，所述JFET器件包括沟道区和漂移区，所述方法包括：
    获取衬底；
    在所述衬底上的第一区域形成第一阱区，所述第一阱区具有第一掺杂类型；
    使用第二阱区掩膜板光刻，然后刻蚀并掺杂，以在所述第一区域内形成第二阱区，所述第二阱区包括位于所述漂移区的漂移区第二阱和位于所述沟道区的至少两段相互间隔的沟道，相邻的沟道之间为属于所述第一阱区的间隔区；所述第二阱区具有第二掺杂类型，所述第二掺杂类型与第一掺杂类型的导电类型相反。
  12. 根据权利要求11所述的制造方法，其中，还包括：
    形成漏极区和源极区，所述第二阱区连接所述漏极区和源极区；
    将所述漏极区引出为所述JFET器件的漏极，将所述源极区引出为所述JFET器件的源极，将所述间隔区引出为所述JFET器件的栅极。
  13. 根据权利要求11所述的制造方法，其中，所述JFET器件是N沟道JFET，所述第一掺杂类型为P型，所述第二掺杂类型为N型。
  14. 根据权利要求11所述的制造方法，其中，所述间隔区的数量为两个以上，且相互间隔。
  15. 根据权利要求14所述的制造方法，其中，各所述间隔区相互平行间隔。
  16. 根据权利要求11所述的制造方法，其中，所述间隔区在自沟道区指向漂移区的方向上延伸。
  17. 根据权利要求13所述的制造方法，其中，所述第一阱区为高压P阱，所述第二阱区为高压N阱。
  18. 根据权利要求11所述的制造方法，其中，所述使用第二阱区掩膜板光刻，然后刻蚀并掺杂，以在所述第一区域内形成第二阱区的步骤，是刻蚀后通过离子注入形成第二阱区。
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