WO2019000650A1 - 像素电路及其控制方法、显示面板 - Google Patents

像素电路及其控制方法、显示面板 Download PDF

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Publication number
WO2019000650A1
WO2019000650A1 PCT/CN2017/101670 CN2017101670W WO2019000650A1 WO 2019000650 A1 WO2019000650 A1 WO 2019000650A1 CN 2017101670 W CN2017101670 W CN 2017101670W WO 2019000650 A1 WO2019000650 A1 WO 2019000650A1
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Prior art keywords
switch tube
timing signal
tube
voltage
switching
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Ceased
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PCT/CN2017/101670
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English (en)
French (fr)
Inventor
张娣
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/577,238 priority Critical patent/US10262595B2/en
Publication of WO2019000650A1 publication Critical patent/WO2019000650A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel circuit, a control method thereof, and a display panel.
  • IGZO indium gallium zinc oxide
  • amorphous IGZO material is used as a channel layer material in the new generation of thin film transistor technology, and is a kind of metal oxide (Oxide) panel technology
  • AMOLED Active-matrix organic light emitting diode
  • AMOLED Active-matrix organic light emitting diode
  • active matrix organic light emitting diode which has a relatively simple process technology and high electrons. The advantages of mobility and transparency are at the same time.
  • the AMOLED pixel circuit is sensitive and affects the user experience, there are various compensation circuits for the AMOLED circuit, such as voltage compensation, current compensation, hybrid compensation, and external compensation. Due to the double channel effect of the IGZO material, the driving thin film transistor of the pixel circuit has a double gate structure. For the pixel circuit of the current double gate structure, the compensation of the threshold voltage and the change of the IGZO mobility of the driving thin film transistor has a complicated circuit structure or compensation. The problem is not good.
  • the technical problem to be solved by the present invention is to provide a pixel circuit, a control method thereof, and a display panel, which can compensate for variations in threshold voltage and electron mobility of the switching tube while ensuring a simple pixel circuit structure.
  • a technical solution adopted by the present invention is to provide a pixel circuit including an electroluminescent element, a first switching tube, a second switching tube, a third switching tube, and a fourth switching tube.
  • a fifth switch tube, a first capacitor and a second capacitor the first end of the first switch tube is connected to the fourth open
  • the second end of the first switch tube is connected to the first end of the electroluminescent element, the first control end of the first switch tube is connected to the second end of the second switch tube;
  • the second switch tube is connected to the second end of the second switch tube
  • One end is used for inputting the first timing signal, and the control end of the second switch tube is for inputting the second timing signal;
  • the first end of the first capacitor is connected to the first control end of the first switch tube, and the second end of the first switch is Connecting a first voltage;
  • a first end of the third switch tube is connected to the second voltage, a second end of the third switch tube is connected to the second control end of the first switch tube, and
  • the control end of the fourth switch tube is configured to input a fourth timing signal; the first end of the fifth switch tube is connected to the second end of the second capacitor, and the second end of the fifth switch tube is connected to the fourth voltage, the fifth switch tube is The control terminal is configured to input a fifth timing signal, the second end of the electroluminescent element Connected to the fifth voltage, wherein the first control end of the first switch tube is a bottom gate, and the second control end of the first switch tube is a top gate, a first switch tube, a second switch tube, a third switch tube, and a fourth Both the switching transistor and the fifth switching transistor are N-type thin film transistors.
  • another technical solution adopted by the present invention is to provide a display panel, the display panel includes a pixel circuit, and the pixel circuit includes an electroluminescent element, a first switching tube, a second switching tube, and a third switching tube.
  • a fourth switch tube, a fifth switch tube, a first capacitor and a second capacitor the first end of the first switch tube is connected to the second end of the fourth switch tube, and the second end of the first switch tube is connected to the electroluminescent element
  • the first end of the first switch tube is connected to the second end of the second switch tube; the first end of the second switch tube is for inputting the first timing signal, and the control end of the second switch tube is for inputting a second timing signal;
  • the first end of the first capacitor is connected to the first control end of the first switch tube, the second end of the first capacitor is connected to the first voltage;
  • the first end of the third switch tube is connected to the second voltage, and the third
  • the second end of the switch tube is connected to the second control end of the first switch tube, and the control end of the third switch tube is used to input a third timing signal;
  • the first end of the second capacitor is connected to the second control end of the first switch tube,
  • the second end of the second capacitor is connected a first end of the light
  • another technical solution adopted by the present invention is to provide a method for controlling a pixel circuit, the pixel circuit comprising an electroluminescent element, a first switching tube, a second switching tube, a third switching tube, and a fourth a switch tube, a fifth switch tube, a first capacitor and a second capacitor, the first end of the first switch tube is connected to the second end of the fourth switch tube, and the second end of the first switch tube is connected to the first end of the electroluminescent element
  • the first control end of the first switch tube is connected to the second end of the second switch tube; the first end of the second switch tube is used to input the first timing signal, and the control end of the second switch tube is used to input the second timing
  • the first end of the first capacitor is connected to the first control end of the first switch tube, the second end of the first capacitor is connected to the first voltage; the first end of the third switch tube is connected to the second voltage, and the third switch tube is connected to the second voltage
  • the second end is connected to the second control end of the second control
  • the invention has the beneficial effects that the first control terminal of the first switch tube writes the data signal, and the second control end of the first switch tube captures the threshold voltage, thereby realizing the difference between the prior art and the state of the art.
  • the pixel circuit compensates for the function of threshold voltage and electron mobility.
  • FIG. 1 is a schematic structural view of a pixel circuit according to a first embodiment of the present invention
  • FIG. 2 is a timing chart of respective timing signals of the pixel circuit of the first embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a pixel circuit according to a second embodiment of the present invention.
  • FIG. 5 is a flow chart showing a method of controlling a pixel circuit according to a third embodiment of the present invention.
  • FIG. 6 is a flow chart showing a method of controlling a pixel circuit according to a fourth embodiment of the present invention.
  • Fig. 7 is a schematic structural view of a display panel according to a fifth embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to a first embodiment of the present invention.
  • the pixel circuit includes: an electroluminescent element D, a first switching tube T1, a second switching tube T2, a third switching tube T3, a fourth switching tube T4, a fifth switching tube T5, and a first capacitor C1. And a second capacitor C2.
  • the first end d of the first switch tube T1 is connected to the second end of the fourth switch tube T4, and the second end s of the first switch tube T1 is connected to the first end of the electroluminescent element D1, and the first end of the first switch tube T1
  • the control end is connected to the second end of the second switch tube T2.
  • the first end of the second switch T2 is used to input the first timing signal Data, and the control end of the second switch T2 is used to input the second timing signal SCAN1.
  • the first end of the first capacitor C1 is connected to the first control end g1 of the first switch tube T1, and the second end of the first capacitor C1 is connected to the first voltage V1.
  • the first end of the third switch tube T3 is connected to the second voltage V2, the second end of the third switch tube T2 is connected to the second control end g2 of the first switch tube T1, and the control end of the third switch tube T3 is used for inputting the third end.
  • Timing signal SCAN2 is used for inputting the third end.
  • the first end of the second capacitor C2 is connected to the second control end of the first switch tube T1, and the second end of the second capacitor C2 is connected to the first end of the electroluminescent element D.
  • the first end of the fourth switch T4 is connected to the third voltage VDD, and the control end of the fourth switch T4 is used to input the fourth timing signal EM.
  • the first end of the fifth switch T5 is connected to the second end of the second capacitor C2, the second end of the fifth switch T5 is connected to the fourth voltage V3, and the control end of the fifth switch T5 is used to input the fifth timing signal RESET .
  • the second end of the electroluminescent element D is connected to a fifth voltage VSS.
  • the first switching transistor T1 is a double gate thin film transistor, the first control terminal g1 of the first switching transistor T1 is a bottom gate, and the second control terminal g2 of the first switching transistor T1 is a top gate.
  • the first end d of the first switching transistor T1 is a drain, and the second end s of the first switching transistor T1 is a source.
  • the first switching transistor T1, the second switching transistor T2, the third switching transistor T3, the fourth switching transistor T4, and the fifth switching transistor T5 are all N-type thin film transistors.
  • the electroluminescent element D is an OLED light emitting element.
  • the fourth voltage V3 is a constant voltage, and the fourth voltage V3 is smaller than a difference between the lowest voltage MIN (Vdata) of the first timing signal Data and the threshold voltage Vth of the first switching transistor T1, that is, V3 ⁇ MIN(Vdata)- Vth.
  • the second voltage V2 is also a constant voltage.
  • FIG. 2 is a timing chart of respective timing signals of the pixel circuit of the first embodiment of the present invention.
  • the second timing signal SCAN1, the third timing signal SCAN2, the fifth timing signal RESET are at a high level, and the fourth timing signal EM is at a low level.
  • the second switching transistor T2 is controlled to be turned on by the second timing signal SCAN1
  • the third switching transistor T3 is controlled to be turned on by the third timing signal SCAN2
  • the fifth switching transistor T5 is controlled to be turned on by the fifth timing signal RESET.
  • the voltage value of the first timing signal Data in the first phase is the reference constant voltage Vref, and the reference constant voltage Vref is written into the first control terminal of the first switching transistor T1 in the first stage because V3 ⁇ MIN(Vdata) - Vth
  • the two electrodes of the first capacitor C1 and the second capacitor C2 are reset to prepare for subsequent compensation and writing of data.
  • the second timing signal SCAN1, the third timing signal SCAN2, the fourth timing signal EM are at a high level, and the fifth timing signal RESET is at a low level.
  • the second switching transistor T2 is controlled to be turned on by the second timing signal SCAN1
  • the third switching transistor T3 is controlled to be turned on by the third timing signal SCAN2
  • the fourth switching transistor T4 is controlled to be turned on by the fourth timing signal EM
  • the fifth timing signal RESET is controlled by the fifth timing signal SCAN1.
  • the five switch tube T5 is closed.
  • the potential at point A rises to Vref-Vth
  • the second capacitor C2 stores the threshold voltage Vth of the first switching transistor T1.
  • the second timing signal SCAN1 and the fourth timing signal EM are at a high level, and the third timing signal SCAN2 and the fifth timing signal RESET are at a low level.
  • Controlling the second switching transistor to open T2 by using the second timing signal SCAN1 controlling the fourth switching transistor T4 to be turned on by using the fourth timing signal EM, controlling the fifth switching transistor T5 to be turned off by using the fifth timing signal RESET, and controlling the third switching signal SCAN2 by using the third timing signal SCAN1
  • the three switch tubes T3 are closed.
  • the first timing signal Data is a data signal, and the data signal is written from the data line to the first control terminal g1 of the first switching transistor T1, and the potential of the second terminal s of the first switching transistor T1 is charged to Voled, Voled
  • the size is determined by the voltage difference of the light-emitting phase of the electroluminescent element D and the fifth voltage VSS.
  • the potential of the second control terminal g2 of the first switching transistor T1 becomes V2-Vref+Vth+Voled under the action of the coupling of the second capacitor C2.
  • the fourth timing signal EM is at a high level
  • the second timing signal SCAN1, the third timing signal SCAN2, and the fifth timing signal RESET are at a low level.
  • the second switching transistor T2 is controlled to be turned off by the second timing signal SCAN1
  • the fourth switching transistor T4 is controlled to be turned on by the fourth timing signal EM
  • the fifth switching transistor T5 is controlled to be turned off by the fifth timing signal RESET
  • the third timing signal SCAN2 is used to control the second switching transistor T4.
  • the three switch tubes T3 are closed.
  • the voltage between the second control terminal g2 of the first switching transistor T1 and the second terminal s of the first switching transistor T1 is still in the third stage.
  • the pixel circuit of the present embodiment compensates for the fluctuation of the threshold voltage Vth of the first switching transistor T1.
  • the effect is that the voltage of the first end of the electroluminescent element D (ie, its anode) can be negatively fed back into the working process when the electroluminescent element D emits light, thereby preventing the influence of the electron mobility change of the first switching tube T1 during the illuminating process. .
  • the first phase is a reset phase
  • the second phase is a compensation phase
  • the third phase is a writing phase
  • the fourth phase is a lighting phase.
  • FIG. 3 is a schematic structural diagram of a pixel circuit according to a second embodiment of the present invention.
  • the pixel circuit further includes a sixth switch tube T6.
  • the first end of the sixth switch tube T6 is connected to the fifth voltage V4, and the second end of the sixth switch tube T6 is connected to the first switch.
  • the first control end g1 of the tube T1 and the control end of the sixth switch tube T6 are used to input the third timing signal SCAN2.
  • the fifth voltage V4 is a constant voltage and is equal in magnitude to the reference constant voltage Vref.
  • FIG. 4 is a timing diagram of respective timing signals of the pixel circuit according to the second embodiment of the present invention.
  • the reference constant voltage Vref of the first stage is provided by the fifth voltage V4, and the reference constant voltage Vref different from the first embodiment is provided by the first timing signal Data, so that the first timing signal Data can be avoided.
  • the first phase and the second phase are interleaved to write the reference constant voltage Vref and the data signal, respectively.
  • the second timing signal SCAN1, the third timing signal SCAN2, the fifth timing signal RESET are at a high level
  • the fourth timing signal EM is at a low level.
  • the second switch tube T2 is opened, the third switch tube T3 is controlled to be turned on by the third timing signal SCAN2, the fifth switch tube T5 is controlled to be turned on by the fifth timing signal RESET, and the sixth switch tube T6 is controlled to be turned on by the third timing signal SCAN2. Since V3 ⁇ MIN(Vdata)-Vth, the reference constant voltage Vref provided by the fifth voltage V4 is written into the first control terminal of the first switching transistor T1 in the first stage, and two of the first capacitor C1 and the second capacitor C2. The electrodes are reset to prepare for subsequent compensation and data writing.
  • the second timing signal SCAN1, the third timing signal SCAN2, the fourth timing signal EM are at a high level, and the fifth timing signal RESET is at a low level.
  • the second switching transistor T2 is controlled to be turned on by the second timing signal SCAN1
  • the third switching transistor T3 is controlled to be turned on by the third timing signal SCAN2
  • the fourth switching transistor T4 is controlled to be turned on by the fourth timing signal EM
  • the fifth timing signal RESET is controlled by the fifth timing signal SCAN1.
  • the fifth switch tube T5 is turned off, and the sixth switch tube T6 is controlled to be turned on by the third timing signal SCAN2.
  • the potential at point A rises to Vref-Vth
  • the second capacitor C2 stores the threshold voltage Vth of the first switching transistor T1.
  • the second timing signal SCAN1 and the fourth timing signal EM are at a high level, and the third timing signal SCAN2 and the fifth timing signal RESET are at a low level.
  • Controlling the second switching transistor to open T2 by using the second timing signal SCAN1 controlling the fourth switching transistor T4 to be turned on by using the fourth timing signal EM, controlling the fifth switching transistor T5 to be turned off by using the fifth timing signal RESET, and controlling the third switching signal SCAN2 by using the third timing signal SCAN1
  • the three-switching tube T3 is turned off, and the sixth switching transistor T6 is controlled to be turned off by the third timing signal SCAN2.
  • the first timing signal Data is a data signal, and the data signal is written from the data line to the first control terminal g1 of the first switching transistor T1, and the potential of the second terminal s of the first switching transistor T1 is charged to Voled, Voled
  • the size is determined by the voltage difference of the light-emitting phase of the electroluminescent element D and the fifth voltage VSS.
  • the potential of the second control terminal g2 of the first switching transistor T1 becomes V2-Vref+Vth+Voled under the action of the coupling of the second capacitor C2.
  • the fourth timing signal EM is at a high level
  • the second timing signal SCAN1, the third timing signal SCAN2, and the fifth timing signal RESET are at a low level.
  • the second switch tube T2 is turned off
  • the fourth switch tube T4 is controlled to be turned on by the fourth timing signal EM
  • the fifth switch tube T5 is controlled to be turned off by the fifth timing signal RESET
  • the third switch tube T3 is controlled to be turned off by the third timing signal SCAN2.
  • the sixth switching transistor T6 is controlled to be turned off by the third timing signal SCAN2.
  • the voltage between the second control terminal g2 of the first switching transistor T1 and the second terminal s of the first switching transistor T1 is still in the third stage.
  • the pixel circuit of the present embodiment compensates for the fluctuation of the threshold voltage Vth of the first switching transistor T1.
  • the effect is that the voltage of the first end of the electroluminescent element D (ie, its anode) can be negatively fed back into the working process when the electroluminescent element D emits light, thereby preventing the influence of the electron mobility change of the first switching tube T1 during the illuminating process. .
  • FIG. 5 is a flowchart of a method for controlling a pixel circuit according to a third embodiment of the present invention.
  • the control method of the pixel circuit is used to control the pixel circuit of the first embodiment of the present invention.
  • the control method of the pixel circuit includes:
  • Step S11 In the first stage, the second timing switch is used to control the opening of the second switching tube, the third timing signal is used to control the opening of the third switching tube, and the fifth timing signal is used to control the opening of the fifth switching tube, and the fourth timing signal is used to control The fourth switch is closed.
  • Step S12 In the second stage, using the second timing signal to control the second switch tube to open, using the third The timing signal controls the third switch to be turned on, the fourth switch is controlled to open by the fourth timing signal, and the fifth switch is controlled to be closed by the fifth timing signal.
  • Step S13 In the third stage, the second switching tube is controlled to be turned on by using the second timing signal, the fourth switching tube is controlled to be turned on by using the fourth timing signal, and the fifth switching tube is controlled to be closed by the fifth timing signal, and is controlled by the third timing signal.
  • the third switch is closed.
  • Step S14 In the fourth stage, the second timing switch is used to control the second switch to be closed, the fourth timing signal is used to control the fourth switch to be turned on, the fifth timing signal is used to control the fifth switch to be closed, and the third timing signal is used to control The third switch is closed.
  • FIG. 6 is a flowchart of a method for controlling a pixel circuit according to a fourth embodiment of the present invention.
  • the control method of the pixel circuit is used to control the pixel circuit of the second embodiment of the present invention.
  • the control method of the pixel circuit includes:
  • Step S21 In the first stage, the second timing switch is used to control the opening of the second switching tube, the third timing signal is used to control the opening of the third switching tube, and the fifth timing signal is used to control the opening of the fifth switching tube, and the fourth timing signal is used to control The fourth switch is closed, and the sixth switch is controlled to open by using the third timing signal.
  • Step S22 In the second stage, the second switching tube is controlled to be turned on by using the second timing signal, the third switching tube is controlled to be turned on by using the third timing signal, and the fourth switching tube is controlled to be turned on by using the fourth timing signal, and is controlled by the fifth timing signal.
  • the fifth switch is closed, and the sixth switch is controlled to open by using the third timing signal.
  • Step S23 In the third stage, the second switching tube is controlled to be turned on by using the second timing signal, the fourth switching tube is controlled to be turned on by using the fourth timing signal, and the fifth switching tube is controlled to be closed by using the fifth timing signal, and is controlled by the third timing signal.
  • the third switch is closed, and the sixth switch is controlled to be closed by the third timing signal.
  • Step S24 In the fourth stage, using the second timing signal to control the second switch to be closed, using the fourth The timing signal controls the fourth switch to be turned on, the fifth switch is controlled to be closed by the fifth timing signal, the third switch is controlled to be closed by the third timing signal, and the sixth switch is controlled to be closed by the third timing signal.
  • FIG. 7 is a schematic structural diagram of a display panel according to a fifth embodiment of the present invention.
  • the display panel includes a plurality of parallelly disposed data lines 11, a plurality of scan lines 12 disposed in parallel and perpendicular to the data lines, and disposed between the adjacent two data lines 11 and the adjacent two scan lines 12.
  • Pixel circuit 13 may be a pixel circuit in any one of the above embodiments.
  • the first timing signal Data may be provided by the corresponding data line 11, and the second timing signal SCAN1 and the third timing signal SCAN2 may be corresponding.
  • the scan line 12 is provided.
  • the present invention uses the first control end of the first switch tube to write the data signal, and the second control end of the first switch tube captures the threshold voltage to realize the pixel circuit compensation threshold voltage and electron mobility. The function.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素电路，包括电致发光元件（D）、第一至第五开关管（T1~T5）、第一和第二电容（C1、C2），第一开关管（T1）的第一端（d）连接第四开关管（T4）的第二端，第二端（s）连接电致发光元件（D）的第一端，第一控制端（g1）连接第二开关管（T2）的第二端；第二开关管（T2）的第一端输入第一时序信号（Data），控制端输入第二时序信号（SCAN1）；第一电容（C1）的第一端连接第一开关管（T1）的第一控制端（g1）；第三开关管（T3）的第二端连接第一开关管（T1）的第二控制端（g2），控制端输入第三时序信号（SCAN2）；第二电容（C2）的第一端连接第一开关管（T1）的第二控制端（g2），第二端连接电致发光元件（D）的第一端；第四开关管（T4）的控制端输入第四时序信号（EM）。

Description

像素电路及其控制方法、显示面板 【技术领域】
本发明涉及显示技术领域，特别是涉及一种像素电路及其控制方法、显示面板。
【背景技术】
随着显示面板的发展，人们追求更大屏幕，更高的分辨率，更刺激的视觉效果，这无疑对面板制程、材料以及工艺提出了更高的要求。IGZO(indium gallium zinc oxide，铟镓锌氧化物)材料，非晶IGZO材料是用于新一代薄膜晶体管技术中的沟道层材料，是金属氧化物(Oxide)面板技术的一种)被认为是一种AMOLED(Active-matrix organic light emitting diode，有源矩阵有机发光二极体或主动矩阵有机发光二极体)像素设计中最有前景的材料之一，它具有相对简单的制程工艺、高电子迁移率、透明性好等优点，同时。由于AMOLED像素电路很敏感，从而影响到用户体验，因此针对AMOLED电路的具有多种补偿电路，例如：电压补偿、电流补偿、混合型补偿、外部补偿等多种方式。由于IGZO材料的双沟道效应，其像素电路的驱动薄膜晶体管具有双栅结构，针对目前的双栅结构的像素电路，驱动薄膜晶体管的阈值电压和IGZO迁移率变化的补偿具有电路结构复杂或者补偿效果不好的问题。
【发明内容】
本发明主要解决的技术问题是提供一种像素电路及其控制方法、显示面板，能够在保证像素电路结构简单的情况下补偿开关管的阈值电压和电子迁移率变化。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种像素电路，像素电路包括电致发光元件、第一开关管、第二开关管、第三开关管、第四开关管、第五开关管、第一电容以及第二电容，第一开关管的第一端连接第四开 关管的第二端，第一开关管的第二端连接电致发光元件的第一端，第一开关管的第一控制端连接第二开关管的第二端；第二开关管的第一端用于输入第一时序信号，第二开关管的控制端用于输入第二时序信号；第一电容的第一端连接第一开关管的第一控制端，第一电容的第二端连接第一电压；第三开关管的第一端连接第二电压，第三开关管的第二端连接第一开关管的第二控制端，第三开关管的控制端用于输入第三时序信号；第二电容的第一端连接第一开关管的第二控制端，第二电容的第二端连接电致发光元件的第一端；第四开关管的第一端连接第三电压，第四开关管的控制端用于输入第四时序信号；第五开关管的第一端连接第二电容的第二端，第五开关管的第二端连接第四电压，第五开关管的控制端用于输入第五时序信号，电致发光元件的第二端连接第五电压，其中，第一开关管的第一控制端为底栅，第一开关管的第二控制端为顶栅，第一开关管、第二开关管、第三开关管、第四开关管以及第五开关管均为N型薄膜晶体管。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示面板，显示面板包括像素电路，像素电路包括电致发光元件、第一开关管、第二开关管、第三开关管、第四开关管、第五开关管、第一电容以及第二电容，第一开关管的第一端连接第四开关管的第二端，第一开关管的第二端连接电致发光元件的第一端，第一开关管的第一控制端连接第二开关管的第二端；第二开关管的第一端用于输入第一时序信号，第二开关管的控制端用于输入第二时序信号；第一电容的第一端连接第一开关管的第一控制端，第一电容的第二端连接第一电压；第三开关管的第一端连接第二电压，第三开关管的第二端连接第一开关管的第二控制端，第三开关管的控制端用于输入第三时序信号；第二电容的第一端连接第一开关管的第二控制端，第二电容的第二端连接电致发光元件的第一端；第四开关管的第一端连接第三电压，第四开关管的控制端用于输入第四时序信号；第五开关管的第一端连接第二电容的第二端，第五开关管的第二端连接第四电压，第五开关管的控制端用于输入第五时序信号，电致发光 元件的第二端连接第五电压。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种像素电路的控制方法，像素电路包括电致发光元件、第一开关管、第二开关管、第三开关管、第四开关管、第五开关管、第一电容以及第二电容，第一开关管的第一端连接第四开关管的第二端，第一开关管的第二端连接电致发光元件的第一端，第一开关管的第一控制端连接第二开关管的第二端；第二开关管的第一端用于输入第一时序信号，第二开关管的控制端用于输入第二时序信号；第一电容的第一端连接第一开关管的第一控制端，第一电容的第二端连接第一电压；第三开关管的第一端连接第二电压，第三开关管的第二端连接第一开关管的第二控制端，第三开关管的控制端用于输入第三时序信号；第二电容的第一端连接第一开关管的第二控制端，第二电容的第二端连接电致发光元件的第一端；第四开关管的第一端连接第三电压，第四开关管的控制端用于输入第四时序信号；第五开关管的第一端连接第二电容的第二端，第五开关管的第二端连接第四电压，第五开关管的控制端用于输入第五时序信号，电致发光元件的第二端连接第五电压；控制方法包括：在第一阶段，利用第二时序信号控制第二开关管打开，利用第三时序信号控制第三开关管打开，利用第五时序信号控制第五开关管打开，利用第四时序信号控制第四开关管关闭；在第二阶段，利用第二时序信号控制第二开关管打开，利用第三时序信号控制第三开关管打开，利用第四时序信号控制第四开关管打开，利用第五时序信号控制第五开关管关闭；在第三阶段，利用第二时序信号控制第二开关管打开，利用第四时序信号控制第四开关管打开，利用第五时序信号控制第五开关管关闭，利用第三时序信号控制第三开关管关闭；在第四阶段，利用第二时序信号控制第二开关管关闭，利用第四时序信号控制第四开关管打开，利用第五时序信号控制第五开关管关闭，利用第三时序信号控制第三开关管关闭。
本发明的有益效果是：区别于现有技术的情况，本发明利用第一开关管的第一控制端写入数据信号，通过第一开关管的第二控制端抓取阈值电压，实现 像素电路补偿阈值电压和电子迁移率的功能。
【附图说明】
图1是本发明第一实施例的像素电路的结构示意图；
图2是本发明第一实施例的像素电路各个时序信号的时序图；
图3是本发明第二实施例的像素电路的结构示意图；
图4是本发明第二实施例的像素电路各个时序信号的时序图；
图5是本发明第三实施例像素电路的控制方法的流程图；
图6是本发明第四实施例像素电路的控制方法的流程图；
图7是本发明第五实施例的显示面板的结构示意图。
【具体实施方式】
下面结合附图和实施例对本发明进行详细的说明。
请参阅图1，图1是本发明第一实施例的像素电路的结构示意图。在本实施例中，像素电路包括：电致发光元件D、第一开关管T1、第二开关管T2、第三开关管T3、第四开关管T4、第五开关管T5、第一电容C1以及第二电容C2。
第一开关管T1的第一端d连接第四开关管T4的第二端，第一开关管T1的第二端s连接电致发光元件D1的第一端，第一开关管T1的第一控制端连接第二开关管T2的第二端。
第二开关管T2的第一端用于输入第一时序信号Data，第二开关管T2的控制端用于输入第二时序信号SCAN1。
第一电容C1的第一端连接第一开关管T1的第一控制端g1，第一电容C1的第二端连接第一电压V1。
第三开关管T3的第一端连接第二电压V2，第三开关管T2的第二端连接第一开关管T1的第二控制端g2，第三开关管T3的控制端用于输入第三时序信号SCAN2。
第二电容C2的第一端连接第一开关管T1的第二控制端，第二电容C2的第二端连接电致发光元件D的第一端。
第四开关管T4的第一端连接第三电压VDD，第四开关管T4的控制端用于输入第四时序信号EM。
第五开关管T5的第一端连接第二电容C2的第二端，第五开关管T5的第二端连接第四电压V3，第五开关管T5的控制端用于输入第五时序信号RESET。
电致发光元件D的第二端连接第五电压VSS。
优选地，第一开关管T1为双栅薄膜晶体管，第一开关管T1的第一控制端g1为底栅，第一开关管T1的第二控制端g2为顶栅。第一开关管T1的第一端d为漏极，第一开关管T1的第二端s为源极。
优选地，第一开关管T1、第二开关管T2、第三开关管T3、第四开关管T4以及第五开关管T5均为N型薄膜晶体管。
优选地，电致发光元件D为OLED发光元件。
优选地，第四电压V3为恒定电压，第四电压V3小于第一时序信号Data的最低电压MIN(Vdata)与第一开关管T1的阈值电压Vth的差值，即V3＜MIN(Vdata)-Vth。
优选地，第二电压V2也为恒定电压。
请参阅图2，图2是本发明第一实施例的像素电路各个时序信号的时序图。
下面结合图1和图2对本发明第一实施例的像素电路的工作原理进行说明。
在第一阶段，第二时序信号SCAN1、第三时序信号SCAN2、第五时序信号RESET为高电平，第四时序信号EM为低电平。利用第二时序信号SCAN1控制第二开关管T2打开，利用第三时序信号SCAN2控制第三开关管T3打开，利用第五时序信号RESET控制第五开关管T5打开。第一时序信号Data在第一阶段的电压值为参考恒定电压Vref，由于V3＜MIN(Vdata)-Vth，该参考恒定电压Vref在第一阶段被写入第一开关管T1的第一控制端，第一电容C1和第二电容C2的两个电极被复位，为后续的补偿以及写入数据做准备。
在第二阶段，第二时序信号SCAN1、第三时序信号SCAN2、第四时序信号EM为高电平，第五时序信号RESET为低电平。利用第二时序信号SCAN1控制第二开关管T2打开，利用第三时序信号SCAN2控制第三开关管T3打开，利用第四时序信号EM控制第四开关管T4打开，利用第五时序信号RESET控制第五开关管T5关闭。在第二阶段，A点电位升高至Vref-Vth，第二电容C2存储了第一开关管T1的阈值电压Vth。
在第三阶段，第二时序信号SCAN1、第四时序信号EM为高电平，第三时序信号SCAN2、第五时序信号RESET为低电平。利用第二时序信号SCAN1控制第二开关管打开T2，利用第四时序信号EM控制第四开关管T4打开，利用第五时序信号RESET控制第五开关管T5关闭，利用第三时序信号SCAN2控制第三开关管T3关闭。在第三阶段，第一时序信号Data为数据信号，数据信号从数据线写入第一开关管T1的第一控制端g1，第一开关管T1的第二端s电位充电为Voled，Voled的大小由电致发光元件D发光阶段的压差以及第五电压VSS决定。第一开关管T1的第二控制端g2的电位在第二电容C2耦合的作用下变为V2-Vref+Vth+Voled，因此，在第三阶段，第一开关管T1的第二控制端g2与第一开关管T1的第二端s之间的电压为Vgs2＝V2-Vref+Vth，第一开关管T1的第一控制端g1与第一开关管T1的第二端s之间的电压为Vgs1＝Vdata-Voled。
在第四阶段，第四时序信号EM为高电平，第二时序信号SCAN1、第三时序信号SCAN2、第五时序信号RESET为低电平。利用第二时序信号SCAN1控制第二开关管T2关闭，利用第四时序信号EM控制第四开关管T4打开，利用第五时序信号RESET控制第五开关管T5关闭，利用第三时序信号SCAN2控制第三开关管T3关闭。由于第一电容C1和第二电容C2的保持作用，在第四阶段，第一开关管T1的第二控制端g2与第一开关管T1的第二端s之间的电压仍然为第三阶段的数值即为Vgs2＝V2-Vref+Vth，第一开关管T1的第一控制端g1与第一开关管T1的第二端s之间的电压仍然为第三阶段的数值即为Vgs1＝Vdata-Voled，因此，在第四阶段通过电致发光元件D的电流Ioled为：
Ioled＝k(Vgs-Vth)^2         (公式1-1)
Ioled＝k[Vgs1+(1/Etop)*Vgs2-Vth]^2    (公式1-2)
其中，Etop是第一开关管T1的第二控制端，即其顶栅的系数，定义为Etop＝ΔVth/ΔVge2，这里Etop默认为1。
所以带入Vgs1和Vgs2的表达式可以得到
Ioled＝k(Vdata-Voled+V2-Vref)^2        (公式1-3)
由公式1-3可知，该电致发光元件D的发光电流Ioled与第二电压V2和参考恒定电压Vref有关，因此，本实施例的像素电路补偿了第一开关管T1的阈值电压Vth波动的影响，同时可以将电致发光元件D发光时电致发光元件D的第一端(即其阳极)的电压负反馈到工作过程中，防止发光过程中受到第一开关管T1电子迁移率变化影响。
优选地，第一阶段为复位阶段，第二阶段为补偿阶段，第三阶段为写入阶段，第四阶段为发光阶段。
请参阅图3，图3是本发明第二实施例的像素电路的结构示意图。本实施例与第一实施例的区别在于，像素电路进一步包括第六开关管T6，第六开关管T6的第一端连接第五电压V4，第六开关管T6的第二端连接第一开关管T1的第一控制端g1，第六开关管T6的控制端用于输入第三时序信号SCAN2。
第五电压V4为恒定电压，且大小等于参考恒定电压Vref。
请参阅图4，图4是本发明第二实施例的像素电路各个时序信号的时序图。
下面结合图3和图4对本发明第二实施例的像素电路的工作原理进行说明。
本实施例中，第一阶段的参考恒定电压Vref由第五电压V4提供，而不同于第一实施例中的参考恒定电压Vref由第一时序信号Data提供，从而可以避免第一时序信号Data在第一阶段和第二阶段分别交错写入参考恒定电压Vref和数据信号。
在第一阶段，第二时序信号SCAN1、第三时序信号SCAN2、第五时序信号RESET为高电平，第四时序信号EM为低电平。利用第二时序信号SCAN1控 制第二开关管T2打开，利用第三时序信号SCAN2控制第三开关管T3打开，利用第五时序信号RESET控制第五开关管T5打开，利用第三时序信号SCAN2控制第六开关管T6打开。由于V3＜MIN(Vdata)-Vth，第五电压V4提供的参考恒定电压Vref在第一阶段被写入第一开关管T1的第一控制端，第一电容C1和第二电容C2的两个电极被复位，为后续的补偿以及写入数据做准备。
在第二阶段，第二时序信号SCAN1、第三时序信号SCAN2、第四时序信号EM为高电平，第五时序信号RESET为低电平。利用第二时序信号SCAN1控制第二开关管T2打开，利用第三时序信号SCAN2控制第三开关管T3打开，利用第四时序信号EM控制第四开关管T4打开，利用第五时序信号RESET控制第五开关管T5关闭，利用第三时序信号SCAN2控制第六开关管T6打开。在第二阶段，A点电位升高至Vref-Vth，第二电容C2存储了第一开关管T1的阈值电压Vth。
在第三阶段，第二时序信号SCAN1、第四时序信号EM为高电平，第三时序信号SCAN2、第五时序信号RESET为低电平。利用第二时序信号SCAN1控制第二开关管打开T2，利用第四时序信号EM控制第四开关管T4打开，利用第五时序信号RESET控制第五开关管T5关闭，利用第三时序信号SCAN2控制第三开关管T3关闭，利用第三时序信号SCAN2控制第六开关管T6关闭。在第三阶段，第一时序信号Data为数据信号，数据信号从数据线写入第一开关管T1的第一控制端g1，第一开关管T1的第二端s电位充电为Voled，Voled的大小由电致发光元件D发光阶段的压差以及第五电压VSS决定。第一开关管T1的第二控制端g2的电位在第二电容C2耦合的作用下变为V2-Vref+Vth+Voled，因此，在第三阶段，第一开关管T1的第二控制端g2与第一开关管T1的第二端s之间的电压为Vgs2＝V2-Vref+Vth，第一开关管T1的第一控制端g1与第一开关管T1的第二端s之间的电压为Vgs1＝Vdata-Voled。
在第四阶段，第四时序信号EM为高电平，第二时序信号SCAN1、第三时序信号SCAN2、第五时序信号RESET为低电平。利用第二时序信号SCAN1控 制第二开关管T2关闭，利用第四时序信号EM控制第四开关管T4打开，利用第五时序信号RESET控制第五开关管T5关闭，利用第三时序信号SCAN2控制第三开关管T3关闭，利用第三时序信号SCAN2控制第六开关管T6关闭。由于第一电容C1和第二电容C2的保持作用，在第四阶段，第一开关管T1的第二控制端g2与第一开关管T1的第二端s之间的电压仍然为第三阶段的数值即为Vgs2＝V2-Vref+Vth，第一开关管T1的第一控制端g1与第一开关管T1的第二端s之间的电压仍然为第三阶段的数值即为Vgs1＝Vdata-Voled，因此，在第四阶段通过电致发光元件D的电流Ioled为：
Ioled＝k(Vgs-Vth)^2         (公式1-1)
Ioled＝k[Vgs1+(1/Etop)*Vgs2-Vth]^2     (公式1-2)
其中，Etop是第一开关管T1的第二控制端，即其顶栅的系数，定义为Etop＝ΔVth/ΔVge2，这里Etop默认为1。
所以带入Vgs1和Vgs2的表达式可以得到
Ioled＝k(Vdata-Voled+V2-Vref)^2      (公式1-3)
由公式1-3可知，该电致发光元件D的发光电流Ioled与第二电压V2和参考恒定电压Vref有关，因此，本实施例的像素电路补偿了第一开关管T1的阈值电压Vth波动的影响，同时可以将电致发光元件D发光时电致发光元件D的第一端(即其阳极)的电压负反馈到工作过程中，防止发光过程中受到第一开关管T1电子迁移率变化影响。
请参阅图5，图5是本发明第三实施例像素电路的控制方法的流程图。在本实施例中，像素电路的控制方法用于控制本发明第一实施例的像素电路。像素电路的控制方法包括：
步骤S11：在第一阶段，利用第二时序信号控制第二开关管打开，利用第三时序信号控制第三开关管打开，利用第五时序信号控制第五开关管打开，利用第四时序信号控制第四开关管关闭。
步骤S12：在第二阶段，利用第二时序信号控制第二开关管打开，利用第三 时序信号控制第三开关管打开，利用第四时序信号控制第四开关管打开，利用第五时序信号控制第五开关管关闭。
步骤S13：在第三阶段，利用第二时序信号控制第二开关管打开，利用第四时序信号控制第四开关管打开，利用第五时序信号控制第五开关管关闭，利用第三时序信号控制第三开关管关闭。
步骤S14：在第四阶段，利用第二时序信号控制第二开关管关闭，利用第四时序信号控制第四开关管打开，利用第五时序信号控制第五开关管关闭，利用第三时序信号控制第三开关管关闭。
关于上述各个步骤的说明请参见上文中本发明第一实施例的像素电路的说明，此处不再赘述。
请参阅图6，图6是本发明第四实施例像素电路的控制方法的流程图。在本实施例中，像素电路的控制方法用于控制本发明第二实施例的像素电路。像素电路的控制方法包括：
步骤S21：在第一阶段，利用第二时序信号控制第二开关管打开，利用第三时序信号控制第三开关管打开，利用第五时序信号控制第五开关管打开，利用第四时序信号控制第四开关管关闭，利用所述第三时序信号控制所述第六开关管打开。
步骤S22：在第二阶段，利用第二时序信号控制第二开关管打开，利用第三时序信号控制第三开关管打开，利用第四时序信号控制第四开关管打开，利用第五时序信号控制第五开关管关闭，利用所述第三时序信号控制所述第六开关管打开。
步骤S23：在第三阶段，利用第二时序信号控制第二开关管打开，利用第四时序信号控制第四开关管打开，利用第五时序信号控制第五开关管关闭，利用第三时序信号控制第三开关管关闭，利用所述第三时序信号控制所述第六开关管关闭。
步骤S24：在第四阶段，利用第二时序信号控制第二开关管关闭，利用第四 时序信号控制第四开关管打开，利用第五时序信号控制第五开关管关闭，利用第三时序信号控制第三开关管关闭，利用所述第三时序信号控制所述第六开关管关闭。
关于上述各个步骤的说明请参见上文中本发明第二实施例的像素电路的说明，此处不再赘述。
请参阅图7，图7是本发明第五实施例的显示面板的结构示意图。在本实施例中显示面板包括多条平行设置的数据线11、多条平行设置的且与数据线垂直的扫描线12、设置在相邻两数据线11和相邻两扫描线12之间的像素电路13。像素电路13可以为上述任意一实施例中的像素电路，上述各个实施例的像素电路中，第一时序信号Data可由对应的数据线11提供，第二时序信号SCAN1和第三时序信号SCAN2可由对应的扫描线12提供。
区别于现有技术的情况，本发明利用第一开关管的第一控制端写入数据信号，通过第一开关管的第二控制端抓取阈值电压，实现像素电路补偿阈值电压和电子迁移率的功能。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种像素电路，其中，所述像素电路包括电致发光元件、第一开关管、第二开关管、第三开关管、第四开关管、第五开关管、第一电容以及第二电容，
    所述第一开关管的第一端连接所述第四开关管的第二端，所述第一开关管的第二端连接所述电致发光元件的第一端，所述第一开关管的第一控制端连接所述第二开关管的第二端；
    所述第二开关管的第一端用于输入第一时序信号，所述第二开关管的控制端用于输入第二时序信号；
    所述第一电容的第一端连接所述第一开关管的第一控制端，所述第一电容的第二端连接第一电压；
    所述第三开关管的第一端连接第二电压，所述第三开关管的第二端连接所述第一开关管的第二控制端，所述第三开关管的控制端用于输入第三时序信号；
    所述第二电容的第一端连接所述第一开关管的第二控制端，所述第二电容的第二端连接所述电致发光元件的第一端；
    所述第四开关管的第一端连接第三电压，所述第四开关管的控制端用于输入第四时序信号；
    所述第五开关管的第一端连接所述第二电容的第二端，所述第五开关管的第二端连接第四电压，所述第五开关管的控制端用于输入第五时序信号；
    所述电致发光元件的第二端连接第五电压，
    其中，所述第一开关管的第一控制端为底栅，所述第一开关管的第二控制端为顶栅，所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管以及所述第五开关管均为N型薄膜晶体管。
  2. 根据权利要求1所述的像素电路，其中，所述像素电路进一步包括第六开关管，所述第六开关管的第一端连接第五电压，所述第六开关管的第二端连接所述第一开关管的第一控制端，所述第六开关管的控制端用于输入所述第三时序信号。
  3. 根据权利要求2所述的像素电路，其中，所述第六开关管为N型薄膜晶体管。
  4. 根据权利要求1所述的像素电路，其中，所述电致发光元件为OLED发光元件。
  5. 根据权利要求1所述的像素电路，其中，所述第四电压为恒定电压，所述第四电压小于所述第一时序信号的最低电压与所述第一开关管的阈值电压的差值。
  6. 根据权利要求1所述的像素电路，其中，所述第二电压为恒定电压。
  7. 一种显示面板，其中，所述显示面板包括像素电路，所述像素电路包括：电致发光元件、第一开关管、第二开关管、第三开关管、第四开关管、第五开关管、第一电容以及第二电容，
    所述第一开关管的第一端连接所述第四开关管的第二端，所述第一开关管的第二端连接所述电致发光元件的第一端，所述第一开关管的第一控制端连接所述第二开关管的第二端；
    所述第二开关管的第一端用于输入第一时序信号，所述第二开关管的控制端用于输入第二时序信号；
    所述第一电容的第一端连接所述第一开关管的第一控制端，所述第一电容的第二端连接第一电压；
    所述第三开关管的第一端连接第二电压，所述第三开关管的第二端连接所述第一开关管的第二控制端，所述第三开关管的控制端用于输入第三时序信号；
    所述第二电容的第一端连接所述第一开关管的第二控制端，所述第二电容的第二端连接所述电致发光元件的第一端；
    所述第四开关管的第一端连接第三电压，所述第四开关管的控制端用于输入第四时序信号；
    所述第五开关管的第一端连接所述第二电容的第二端，所述第五开关管的第二端连接第四电压，所述第五开关管的控制端用于输入第五时序信号；
    所述电致发光元件的第二端连接第五电压。
  8. 根据权利要求7所述的显示面板，其中，所述第一开关管为双栅薄膜晶体管，所述第一开关管的第一控制端为底栅，所述第一开关管的第二控制端为顶栅。
  9. 根据权利要求7所述的显示面板，其中，所述第一开关管、所述第二开关管、所述第三开关管、所述第四开关管以及所述第五开关管均为N型薄膜晶体管。
  10. 根据权利要求7所述的显示面板，其中，所述像素电路进一步包括第六开关管，所述第六开关管的第一端连接第五电压，所述第六开关管的第二端连接所述第一开关管的第一控制端，所述第六开关管的控制端用于输入所述第三时序信号。
  11. 根据权利要求8所述的显示面板，其中，所述第六开关管为N型薄膜晶体管。
  12. 根据权利要求7所述的显示面板，其中，所述电致发光元件为OLED发光元件。
  13. 根据权利要求7所述的显示面板，其中，所述第四电压为恒定电压，所述第四电压小于所述第一时序信号的最低电压与所述第一开关管的阈值电压的差值。
  14. 根据权利要求7所述的显示面板，其中，所述第二电压为恒定电压。
  15. 一种像素电路的控制方法，其中，所述像素电路包括电致发光元件、第一开关管、第二开关管、第三开关管、第四开关管、第五开关管、第一电容以及第二电容，
    所述第一开关管的第一端连接所述第四开关管的第二端，所述第一开关管的第二端连接所述电致发光元件的第一端，所述第一开关管的第一控制端连接所述第二开关管的第二端；
    所述第二开关管的第一端用于输入第一时序信号，所述第二开关管的控制 端用于输入第二时序信号；
    所述第一电容的第一端连接所述第一开关管的第一控制端，所述第一电容的第二端连接第一电压；
    所述第三开关管的第一端连接第二电压，所述第三开关管的第二端连接所述第一开关管的第二控制端，所述第三开关管的控制端用于输入第三时序信号；
    所述第二电容的第一端连接所述第一开关管的第二控制端，所述第二电容的第二端连接所述电致发光元件的第一端；
    所述第四开关管的第一端连接第三电压，所述第四开关管的控制端用于输入第四时序信号；
    所述第五开关管的第一端连接所述第二电容的第二端，所述第五开关管的第二端连接第四电压，所述第五开关管的控制端用于输入第五时序信号；
    所述电致发光元件的第二端连接第五电压；
    所述控制方法包括：
    在第一阶段，利用所述第二时序信号控制所述第二开关管打开，利用所述第三时序信号控制所述第三开关管打开，利用所述第五时序信号控制所述第五开关管打开，利用所述第四时序信号控制所述第四开关管关闭；
    在第二阶段，利用所述第二时序信号控制所述第二开关管打开，利用所述第三时序信号控制所述第三开关管打开，利用所述第四时序信号控制所述第四开关管打开，利用所述第五时序信号控制所述第五开关管关闭；
    在第三阶段，利用所述第二时序信号控制所述第二开关管打开，利用所述第四时序信号控制所述第四开关管打开，利用所述第五时序信号控制所述第五开关管关闭，利用所述第三时序信号控制所述第三开关管关闭；
    在第四阶段，利用所述第二时序信号控制所述第二开关管关闭，利用所述第四时序信号控制所述第四开关管打开，利用所述第五时序信号控制所述第五开关管关闭，利用所述第三时序信号控制所述第三开关管关闭。
  16. 根据权利要求15所述的控制方法，其中，所述像素电路进一步包括第 六开关管，所述第六开关管的第一端连接第五电压，所述第六开关管的第二端连接所述第一开关管的第一控制端，所述第六开关管的控制端用于输入所述第三时序信号，
    所述控制方法进一步包括：
    在所述第一阶段，利用所述第三时序信号控制所述第六开关管打开；
    在所述第二阶段，利用所述第三时序信号控制所述第六开关管打开；
    在所述第三阶段，利用所述第三时序信号控制所述第六开关管关闭；
    在所述第四阶段，利用所述第三时序信号控制所述第六开关管关闭。
  17. 根据权利要求15所述的控制方法，其中，所述第一开关管为双栅薄膜晶体管，所述第一开关管的第一控制端为底栅，所述第一开关管的第二控制端为顶栅。
  18. 根据权利要求15所述的控制方法，其中，所述第一开关管为双栅薄膜晶体管，所述第一开关管的第一控制端为底栅，所述第一开关管的第二控制端为顶栅。
  19. 根据权利要求15所述的控制方法，其中，所述第四电压为恒定电压，所述第四电压小于所述第一时序信号的最低电压与所述第一开关管的阈值电压的差值。
  20. 根据权利要求15所述的控制方法，其中，所述第一阶段为复位阶段，所述第二阶段为补偿阶段，所述第三阶段为写入阶段，所述第四阶段为发光阶段。
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