WO2018233067A1 - 显示面板的测试电路及测试方法 - Google Patents

显示面板的测试电路及测试方法 Download PDF

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Publication number
WO2018233067A1
WO2018233067A1 PCT/CN2017/100252 CN2017100252W WO2018233067A1 WO 2018233067 A1 WO2018233067 A1 WO 2018233067A1 CN 2017100252 W CN2017100252 W CN 2017100252W WO 2018233067 A1 WO2018233067 A1 WO 2018233067A1
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Prior art keywords
test
pad
test pad
display panel
electrically connected
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Ceased
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PCT/CN2017/100252
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English (en)
French (fr)
Inventor
陈猷仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US16/623,269 priority Critical patent/US11183090B2/en
Publication of WO2018233067A1 publication Critical patent/WO2018233067A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2825—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere in household appliances or professional audio/video equipment
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to display technologies, such as test circuits and test methods for a display panel.
  • the liquid crystal molecular orientation of the display panel is required in the process of fabricating the display panel.
  • the liquid crystal molecular orientation process may be performed by applying a voltage signal or a current signal between the array substrate and the color filter substrate, at least one of the array substrate and the color filter substrate. Having an alignment film thereon, the alignment film forms a polymer protrusion under the action of the above voltage or current, and the polymer protrusion forms a pretilt angle, and the pretilt angle can align the liquid crystal molecules between the array substrate and the color filter substrate in a specific direction. Can improve the display quality of the display panel.
  • each display panel When performing liquid crystal molecular orientation, each display panel requires a separate lead and a pad connected to the lead. This results in a large number of lines, and one solution in the related art is to connect one lead to a plurality of display panels.
  • the present disclosure provides a test circuit and a test method for a display panel, which can respectively test each display panel when performing array test, and simultaneously test a plurality of display panels when performing liquid crystal molecular orientation.
  • a test circuit for a display panel comprising:
  • each of the first test leads is disposed to be electrically connected to a corresponding one of the display panels; each of the first test pads is electrically connected to an output end of the corresponding switch unit, and each of the first test pads Electrically connecting with the corresponding first test lead; the second test pad and the second test lead are electrically connected to inputs of the plurality of switch units; the third test pad and the switch control The wires are electrically connected to the control terminals of the plurality of switch units.
  • test method for a display panel comprising: connecting a display panel to a test circuit, wherein the test circuit comprises:
  • each of the first test leads is disposed to be electrically connected to a corresponding one of the display panels; each of the first The test pad is electrically connected to the output end of the corresponding switch unit, and each of the first test pads is electrically connected to the corresponding first test lead; the second test pad and the second test lead are both Electrically connecting with the input ends of the plurality of switch units; the third test pad and the switch control line are electrically connected to the control ends of the plurality of switch units;
  • a plurality of the switching units are controlled to be turned on by the third test pad, and a second test signal is applied to the plurality of display panels through the second test pad.
  • a test circuit for a display panel comprising:
  • each of the first test leads is disposed to be electrically connected to a corresponding one of the display panels; each of the first a test pad electrically connected to an output of the corresponding switch unit, and each of the first test pads and pairs
  • the first test lead is electrically connected; the second test pad and the second test lead are electrically connected to the input ends of the plurality of switch units; the third test pad and the switch control line Each is electrically connected to a plurality of control terminals of the switch unit;
  • the second test pad and the third test pad are disposed adjacent to each other; the second test lead and the switch control line are disposed in parallel; and the plurality of first test pads are along the second test lead
  • the extension direction array is arranged.
  • FIG. 1 is a test circuit of a display panel according to an embodiment of the present invention
  • FIG. 2 is a test circuit of another display panel according to the embodiment.
  • FIG. 1 is a test circuit of a display panel according to the embodiment of the present invention.
  • the test circuit of the display panel provided in this embodiment includes a plurality of switch units 60 , a plurality of first test leads 20 , and a plurality of A test pad 30, a second test pad 40, a second test lead 50, a third test pad 80, and a switch control line 70.
  • the number of the switch unit 60, the first test lead 20, and the first test pad 30 are the same, and each of the first test leads 20 is disposed to be electrically connected to a corresponding one of the display panels 10, and the plurality of display panels 10 are formed in a mother.
  • each first test pad 30 is electrically connected to an output end of a corresponding switch unit 60, and each first test pad 30 is electrically connected to a corresponding first test lead 20, and a second test pad 40 and a second
  • the test leads 50 are electrically connected to the input ends of the plurality of switch units 60, and the third test pad 80 and the switch control line 70 are electrically connected to the control ends of the plurality of switch units 60 for simultaneously controlling the plurality of switch units 60 to be turned on. Or close.
  • the switch unit 60 is exemplarily configured as a triode in FIG. 1 and is not limited to the embodiment.
  • the switch unit may also have other control terminals, input terminals, and output terminals, and can achieve control through A device that controls the signal transfer relationship between the input and output.
  • the triode can be an electron triode, a field effect transistor, a thin film transistor, or the like.
  • the input can be the source or the drain
  • the output can be the drain or the source
  • the control can be the gate.
  • the second test pad 40 and the third test pad 80 are disposed adjacent to each other, and the benefit of the setting is that The distance between the second test lead 50 electrically connected to the second test pad 40 and the switch control line 70 electrically connected to the third test pad 80 is minimized, saving design space. And the second test pad 40 and the third test pad 80 are disposed adjacent to each other, so that when the liquid crystal molecule is oriented to the display panel 10, the signal sent by the signal source is simultaneously loaded on the second test pad 40 and the third test. Pad 80.
  • switch control line 70 is exemplarily electrically connected to the control terminals of the three transistors, and the number of the transistors electrically connected to the switch control line 70 may be two or more.
  • the test circuit of the display panel provided in this embodiment is provided with a plurality of switch units 60, a third test pad 80 and a switch control line 70, and the third test pad 80 and the switch control line 70 are both controlled by the plurality of switch units 60.
  • the terminal is electrically connected, and the plurality of switch units 60 are controlled to be turned off during the array test of the display panel 10, thereby avoiding the problem that the test signals are interfered by the connection of the plurality of display panels 10 by one lead, thereby realizing the array test.
  • Each display panel 10 is tested separately to improve the accuracy of the array test; and the third test pad 80 and the switch control line 70 are used to control the plurality of switch units 60 to be turned on when the liquid crystal molecules are oriented to the display panel 10, It is achieved that a pretilt angle is simultaneously formed on the plurality of display panels 10 when the liquid crystal molecules are aligned, and the efficiency of liquid crystal molecular orientation on the display panel is improved.
  • a chemical monomer may be added to the liquid crystal. During the alignment process, the chemical monomer is polymerized by ultraviolet irradiation to form a polymer bump for fixing the liquid crystal to form a pretilt angle.
  • the liquid crystal molecular orientation process may be: applying a aligning voltage sequence to the display panel, the liquid crystal is poured down in an order under the electric field, and then maintaining the voltage unchanged, and the display panel is irradiated with ultraviolet rays, and the chemical monomer in the display panel is exposed to ultraviolet rays.
  • the polymerization forms an ordered array of polymer bumps to form a pretilt angle of the display panel, so that the liquid crystal molecules are sequentially arranged under the pretilt angle of the display panel.
  • FIG. 2 is a test circuit of another display panel according to the embodiment.
  • the test circuit provided in this embodiment may further include a plurality of fourth test pads 90, as shown in FIG. A fourth test pad 90 corresponds to one display panel 10, and each of the fourth test pads 90 and the triode 60 (for the test circuit when the triode is used as a switch unit in conjunction with the drawings, the triode adopts the same reference numeral as the switch unit
  • the control terminals of "60" are electrically connected, and the first test pad 30 and the fourth test pad 90 corresponding to the same display panel 10 are disposed adjacent to each other.
  • the display panel 10 Due to the array test of the display panel 10, it is required Applying a test signal on the first test pad 30, and ensuring that there is no mutual signal interference between the plurality of display panels, that is, the transistor 60 is required to be in a closed state, so the first test pad 30 and the fourth test pad 90 are adjacent to each other. It is convenient to use the probe to simultaneously load the signal from the signal source on the first test pad 30 and the fourth test pad 90, and the fourth test pad 90 controls the transistor 60 to be turned off, and the test signal is sent through the first test pad 30 to The display panel 10 is displayed.
  • the transistor 60 is an N-type thin film transistor, and the N-type thin film transistor has a lower on-voltage and is easy to manufacture.
  • the plurality of first test pads 30 are arranged in an array along the extending direction of the second test leads 50.
  • a plurality of first test pad arrays are arranged to facilitate application of a test signal to the first test pad using the probe.
  • the second test lead 50 and the switch control line 70 are arranged in parallel to save space for wiring.
  • the display panel can be a liquid crystal display panel, a quantum dot liquid crystal display panel, or other display panel, and the display panel can be applied to, for example, a mobile phone, a tablet computer, or a television.
  • the mother substrate 100 shown in FIG. 1 and FIG. 2 can be fabricated by using a glass substrate.
  • a plurality of display panels 10 are simultaneously formed on the same mother substrate 100, and the production efficiency of the display panel 10 is improved by making only a single display panel 10 at a time.
  • the mother substrate 100 is cut to obtain a separate display panel 10, and the test circuit can be cut during the process of cutting the mother substrate 100.
  • the cutting removal that is, the above-described test circuit may not be included in the independent display panel 10 after the cutting is completed.
  • the embodiment further provides a test method for a display panel.
  • the test circuit of the display panel based on the method includes: a plurality of switch units 60, a plurality of first test leads 20, and a plurality of A test pad 30, a second test pad 40, a second test lead 50, a third test pad 80, and a switch control line 70.
  • the number of the switch unit 60, the first test lead 20, and the first test pad 30 are the same, and each of the first test leads 20 is disposed to be electrically connected to a corresponding one of the display panels 10, and each of the first test pads 30 corresponds to The output terminals of the switch unit 60 are electrically connected, and each of the first test pads 30 is electrically connected to the corresponding first test lead 20, and the second test pad 40 and the second test lead 50 are connected to the input ends of the plurality of switch units 60.
  • the electrical connection, the third test pad 80 and the switch control line 70 are all electrically connected to the control terminals of the plurality of switch units 60.
  • the switch unit has a control terminal, an input terminal and an output terminal, and can realize the control A device that controls the signal transfer relationship between the input terminal and the output terminal, such as a triode.
  • the triode can be an electron triode, a field effect transistor, a thin film transistor, or the like.
  • the input can be the source or the drain
  • the output can be the drain or the source
  • the control can be the gate.
  • the testing method of the display panel provided in this embodiment includes: when performing array testing on the display panel 10, controlling the plurality of switch units 60 to be turned off, and applying the first test signal to the first test pad 30 through the first test pad 30.
  • Corresponding display panel 10 when performing liquid crystal molecular orientation on the display panel 10, the plurality of switch units 60 are controlled to be turned on, and the second test signal is simultaneously applied to the plurality of display panels 10 through the second test 40 pad.
  • the switch unit 60 is a triode.
  • the triode is given the same reference numeral "60" as the switching unit.
  • the plurality of transistors 60 are controlled to be turned off by the third test pad 80.
  • a low level signal is applied to the third test pad 80 to control the plurality of transistors 60 to be turned off and passed.
  • the first test pad 30 applies a first test signal to the display panel 10 corresponding to the first test pad 30; when the display panel 10 is subjected to liquid crystal molecular orientation, the plurality of transistors 60 are controlled to be turned on by the third test pad 80, for example Applying a high level signal on the third test pad 80 controls the plurality of transistors 60 to conduct, and applies a second test signal to the plurality of display panels 10 through the second test pad 40.
  • a control signal is not applied to the control terminal of the transistor 60.
  • the control terminal of the transistor 60 is turned off, and the first test pad 30 is applied.
  • a test signal is applied to the display panel 10 corresponding to the first test pad 30.
  • the test circuit further includes a plurality of fourth test pads 90, each of the fourth test pads 90 corresponding to one display panel 10, and each of the fourth test pads 90 is electrically connected to the control end of the triode 60, and the same display panel
  • the corresponding first test pad 30 and fourth test pad 90 are disposed adjacent to each other.
  • the control signal is input through the fourth test pad 90, the plurality of transistors 60 are controlled to be turned off, and the first test signal is applied to the display corresponding to the first test pad 30 through the first test pad 30.
  • the panel 10 when the liquid crystal molecules are oriented to the display panel 10, the control signal is input through the third test pad 80, the plurality of transistors 60 are controlled to be turned on, and the second test signal is applied to the plurality of display panels through the second test pad 40. 10.
  • the second test pad 40 and the third test pad 80 are disposed adjacent to each other.
  • the advantage of the arrangement is that the second test lead 50 electrically connected to the second test pad 40 is electrically connected to the third test pad 80.
  • the distance between the lines 70 is minimal, saving design space.
  • the second test pad 40 and the third test pad 80 are disposed adjacent to each other, so that when the liquid crystal molecule is oriented to the display panel 10, the signal sent by the signal source is simultaneously loaded on the second test pad 40 and the third test. Pad 80.
  • the transistor 60 is an N-type thin film transistor, and the N-type thin film transistor has a lower on-voltage and is easy to manufacture.
  • the plurality of first test pads 30 are arranged in an array along the extending direction of the second test leads 50.
  • a plurality of first test pad arrays are arranged to facilitate application of a test signal to the first test pad using the probe.
  • the second test lead 50 and the switch control line 70 are arranged in parallel to save wiring space.
  • the test method of the display panel controls the plurality of switch units 60 to be turned off during the array test of the display panel 10, thereby avoiding the problem that the test signals are interfered by the plurality of display panels 10 due to the connection of one lead. It is realized that each display panel 10 is tested separately during the array test, and the accuracy of the array test is improved; and the plurality of switch units 60 are controlled by the third test pad 80 and the switch control line 70 to perform the display panel 10 When the liquid crystal molecules are aligned, the pretilt angle is simultaneously formed on the plurality of display panels 10 when the alignment of the liquid crystal molecules is performed, and the efficiency of alignment of the liquid crystal molecules of the display panel 10 is improved.

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Abstract

一种显示面板的测试电路及测试方法，该测试电路包括：多个开关单元（60）、多条第一测试引线（20）、多个第一测试垫（30）、第二测试垫（40）、第二测试引线（50）、第三测试垫（80）和开关控制线（70）。其中，开关单元（60）、第一测试引线（20）以及第一测试垫（30）的数量相同，且每一第一测试引线（20）设置为与对应的一个显示面板（10）电连接，多个显示面板（10）形成在一母基板（100）上，每一第一测试垫（30）与对应的开关单元（60）的输出端电连接，以及每一第一测试垫（30）与对应的第一测试引线（20）电连接，第二测试垫（40）和第二测试引线（50）均与多个开关单元（60）的输入端电连接，第三测试垫（80）和开关控制线（70）均与多个开关单元（60）的控制端电连接。

Description

显示面板的测试电路及测试方法 技术领域
本公开涉及显示技术，例如涉及一种显示面板的测试电路及测试方法。
背景技术
制作显示面板的过程中需要对显示面板液晶分子取向，液晶分子取向过程可以采用如下步骤：在阵列基板和彩膜基板之间施加一电压信号或电流信号，阵列基板和彩膜基板中的至少一个上具有配向膜，配向膜在上述电压或电流作用下形成聚合物凸起，该聚合物凸起形成预倾角，预倾角能够使位于阵列基板和彩膜基板之间的液晶分子按照特定方向排列，可以提高显示面板的显示品质。
在进行液晶分子取向时，每个显示面板都需要一个单独的引线以及与该引线相连接的焊盘。这样就造成线路繁多，相关技术中的一种解决方式是将一条引线连接多个显示面板。
但是采用将一条引线连接多个显示面板的方式存在如下问题：在对显示面板进行阵列测试时，多个显示面板之间由于由一条引线相连接因而存在测试信号干扰的问题。
发明内容
本公开提供一种显示面板的测试电路及测试方法，可以实现在进行阵列测试时分别对每个显示面板进行测试，在进行液晶分子取向时同时对多个显示面板进行测试。
一种显示面板的测试电路，包括：
多个开关单元；
多条第一测试引线；
多个第一测试垫；
第二测试垫、第二测试引线、第三测试垫和开关控制线；
其中，所述开关单元、所述第一测试引线以及所述第一测试垫的数量相同； 且每一所述第一测试引线设置为与对应的一个显示面板电连接；每一所述第一测试垫与对应的所述开关单元的输出端电连接，以及每一所述第一测试垫与对应的所述第一测试引线电连接；所述第二测试垫和所述第二测试引线均与多个所述开关单元的输入端电连接；所述第三测试垫和所述开关控制线均与多个所述开关单元的控制端电连接。
一种显示面板的测试方法，包括：将显示面板与测试电路连接，其中，所述测试电路包括：
多个开关单元；
多条第一测试引线；
多个第一测试垫；
第二测试垫、第二测试引线、第三测试垫和开关控制线；
其中，所述开关单元、所述第一测试引线以及所述第一测试垫的数量相同；且每一所述第一测试引线设置为与对应的一个显示面板电连接；每一所述第一测试垫与对应的所述开关单元的输出端电连接，以及每一所述第一测试垫与对应的所述第一测试引线电连接；所述第二测试垫和所述第二测试引线均与多个所述开关单元的输入端电连接；所述第三测试垫和所述开关控制线均与多个所述开关单元的控制端电连接；
通过所第三测试垫控制多个所述开关单元关闭，并通过所述第一测试垫施加第一测试信号到与所述第一测试垫相对应的所述显示面板；
通过所第三测试垫控制多个所述开关单元导通，并通过所述第二测试垫将第二测试信号施加到多个所述显示面板。
一种显示面板的测试电路，包括：
多个开关单元；
多条第一测试引线；
多个第一测试垫；
第二测试垫、第二测试引线、第三测试垫和开关控制线；
其中，所述开关单元、所述第一测试引线以及所述第一测试垫的数量相同；且每一所述第一测试引线设置为与对应的一个显示面板电连接；每一所述第一测试垫与对应的所述开关单元的输出端电连接，以及每一所述第一测试垫与对 应的所述第一测试引线电连接；所述第二测试垫和所述第二测试引线均与多个所述开关单元的输入端电连接；所述第三测试垫和所述开关控制线均与多个所述开关单元的控制端电连接；
其中，所述第二测试垫和所述第三测试垫相邻设置；所述第二测试引线和所述开关控制线平行设置；所述多个第一测试垫沿所述第二测试引线的延伸方向阵列排布。
附图说明
图1为本实施例提供的一种显示面板的测试电路；
图2为本实施例提供的另一种显示面板的测试电路。
具体实施方式
下面结合附图和实施例对本公开作详细说明。
图1为本实施例提供的一种显示面板的测试电路，如图1所示，本实施例提供的显示面板的测试电路包括多个开关单元60、多条第一测试引线20、多个第一测试垫30、第二测试垫40、第二测试引线50、第三测试垫80和开关控制线70。其中，开关单元60、第一测试引线20以及第一测试垫30的数量相同，且每一第一测试引线20设置为与对应的一个显示面板10电连接，多个显示面板10形成在一母基板100上，每一第一测试垫30与对应的开关单元60的输出端电连接，以及每一第一测试垫30与对应的第一测试引线20电连接，第二测试垫40和第二测试引线50均与多个开关单元60的输入端电连接，第三测试垫80和开关控制线70均与多个开关单元60的控制端电连接，用于同时控制多个开关单元60导通或关闭。图1中示例性地将开关单元60设置为三极管进行说明，并非对本实施例的限定，在其他实施方式中，开关单元还可以为其他具有控制端、输入端和输出端，并能实现通过控制端控制输入端和输出端之间信号传递关系的器件。三极管可以采用电子三极管、场效应管、薄膜晶体管等。对于场效应管和薄膜晶体管来说，输入端可以是源极或漏极，输出端可以是漏极或源极，控制端可以是栅极。
可选地，第二测试垫40和第三测试垫80相邻设置，这样设置的好处是， 与第二测试垫40电连接的第二测试引线50和与第三测试垫80电连接的开关控制线70之间的距离最小，节约了设计空间。且将第二测试垫40和第三测试垫80相邻设置，便于在对显示面板10进行液晶分子取向时，使用探针将信号源发出的信号同时加载在第二测试垫40和第三测试垫80上。
图1中仅示例性地设置开关控制线70与三个三极管的控制端电连接，与开关控制线70电连接的三极管的数量还可以是两个或者多个。
本实施例提供的显示面板的测试电路中设置有多个开关单元60、第三测试垫80和开关控制线70，且第三测试垫80和开关控制线70均与多个开关单元60的控制端电连接，控制多个开关单元60在对显示面板10进行阵列测试时关闭，避免了多个显示面板10之间由于由一条引线相连接因而存在测试信号干扰的问题，实现了在进行阵列测试时分别对每个显示面板10进行测试，提高了阵列测试的精准度；通过第三测试垫80和开关控制线70，控制多个开关单元60在对显示面板10进行液晶分子取向时导通，实现了在进行液晶分子取向时同时对多个显示面板10形成预倾角，提高了对显示面板进行液晶分子取向的效率。
另外，本实施例中仅仅设置一个第三测试垫80和一条开关控制线70，相对于相关技术中每一显示面板10均需要设置一开关控制线70和一第三测试垫80的情况来说，简化了线路，节约了成本。其中，对显示面板液晶分子取向，例如可以在液晶中加入化学单体，在配向过程中，化学单体受到紫外线照射聚合形成聚合物凸点，用于固定液晶形成预倾角。液晶分子取向过程可以为：对显示面板施加配向电压序列，液晶在电场作用下有序倾倒，接着保持电压不变，同时使用紫外线照射显示面板，显示面板中的化学单体在紫外线照射的条件下聚合，形成有序排列的聚合物凸点，使显示面板形成预倾角，使液晶分子在显示面板的预倾角作用下有序排列。
图2为本实施例提供的另一种显示面板的测试电路，如图2所示，在上述实施例的基础上，本实施例提供的测试电路还可以包括多个第四测试垫90，每一第四测试垫90对应一个显示面板10，且每一第四测试垫90与三极管60(为了结合附图描述将三极管作为开关单元时的测试电路，将三极管采用与开关单元相同的附图标记“60”)的控制端电连接，与同一显示面板10对应的第一测试垫30和第四测试垫90相邻设置。由于对显示面板10进行阵列测试时，需要 在第一测试垫30上施加测试信号，且需要保证多个显示面板之间不能有相互的信号干扰，即需要三极管60处于关闭状态，因此将第一测试垫30和第四测试垫90相邻设置，方便使用探针将信号源发出的信号同时加载在第一测试垫30和第四测试垫90上，通过第四测试垫90控制三极管60关闭，同时通过第一测试垫30发送测试信号到显示面板10。
在上述实施例的基础上，可选地，三极管60为N型薄膜晶体管，N型薄膜晶体管具有更低的导通电压，且容易制造。
在上述实施例的基础上，可选地，多个第一测试垫30沿第二测试引线50的延伸方向阵列排布。将多个第一测试垫阵列排布，方便使用探针对第一测试垫施加测试信号。
在上述实施例的基础上，可选地，所述第二测试引线50和所述开关控制线70平行设置，以实现节约布线空间。
在一些实施例中，显示面板可以为液晶显示面板、量子点液晶显示面板或其他显示面板，显示面板可以应用在例如手机、平板电脑或电视上。
图1、图2中所示母基板100可以采用玻璃基板来制作，在同一母基板100上同时制作多个显示面板10，相对于一次只制作单个显示面板10提高了显示面板10的制作效率，在对母基板100上的多个显示面板10进行阵列测试和液晶分子取向后，将母基板100进行切割以便得到独立的显示面板10，上述测试电路在对母基板100进行切割的过程中可以被切割去除，即切割完成后独立的显示面板10中可以不包含上述测试电路。
本实施例还提供了一种显示面板的测试方法，请参照图1、图2，该方法基于的显示面板的测试电路包括：多个开关单元60、多条第一测试引线20、多个第一测试垫30、第二测试垫40、第二测试引线50、第三测试垫80和开关控制线70。其中，开关单元60、第一测试引线20以及第一测试垫30的数量相同，且每一第一测试引线20设置为与对应的一个显示面板10电连接，每一第一测试垫30与对应的开关单元60的输出端电连接，以及每一第一测试垫30与对应的第一测试引线20电连接，第二测试垫40和第二测试引线50均与多个开关单元60的输入端电连接，第三测试垫80和开关控制线70均与多个开关单元60的控制端电连接。开关单元为具有控制端、输入端和输出端，并能实现通过控 制端控制输入端和输出端之间信号传递关系的器件，例如三极管等。三极管可以采用电子三极管、场效应管、薄膜晶体管等。对于场效应管和薄膜晶体管来说，输入端可以是源极或漏极，输出端可以是漏极或源极，控制端可以是栅极。
本实施例提供的显示面板的测试方法包括：在对显示面板10进行阵列测试时，控制多个开关单元60关闭，并通过第一测试垫30施加第一测试信号到与第一测试垫30相对应的显示面板10；在对显示面板10进行液晶分子取向时，控制多个开关单元60导通，并通过第二测试40垫将第二测试信号同时施加到多个显示面板10。
可选地，开关单元60为三极管。为了结合附图描述将三极管作为开关单元时的测试方法，将三极管采用与开关单元相同的附图标记“60”。
可选地，在对显示面板10进行阵列测试时，通过第三测试垫80控制多个三极管60关闭，例如在第三测试垫80上施加一低电平信号控制多个三极管60关闭，并通过第一测试垫30施加第一测试信号到与第一测试垫30相对应的显示面板10；在对显示面板10进行液晶分子取向时，通过第三测试垫80控制多个三极管60导通，例如在第三测试垫80上施加一高电平信号控制多个三极管60导通，并通过第二测试垫40将第二测试信号施加到多个显示面板10。在其他实施方式中还可以为，在对显示面板10进行阵列测试时，并没有在三极管60的控制端施加控制信号，此时三极管60的控制端是关闭的，通过第一测试垫30施加第一测试信号到与第一测试垫30相对应的显示面板10。
可选地，测试电路还包括多个第四测试垫90，每一第四测试垫90对应一个显示面板10，且每一第四测试垫90与三极管60的控制端电连接，与同一显示面板10对应的第一测试垫30和第四测试垫90相邻设置。在对显示面板10进行阵列测试时，通过第四测试垫90输入控制信号，控制多个三极管60关闭，并通过第一测试垫30施加第一测试信号到与第一测试垫30相对应的显示面板10；在对显示面板10进行液晶分子取向时，通过第三测试垫80输入控制信号，控制多个三极管60导通，并通过第二测试垫40将第二测试信号施加到多个显示面板10。
可选地，第二测试垫40和第三测试垫80相邻设置，这样设置的好处是，与第二测试垫40电连接的第二测试引线50与第三测试垫80电连接的开关控制 线70之间的距离最小，节约了设计空间。且将第二测试垫40和第三测试垫80相邻设置，便于在对显示面板10进行液晶分子取向时，使用探针将信号源发出的信号同时加载在第二测试垫40和第三测试垫80上。
在上述实施例的基础上，可选地，三极管60为N型薄膜晶体管，N型薄膜晶体管具有更低的导通电压，且容易制造。
在上述实施例的基础上，可选地，多个第一测试垫30沿第二测试引线50的延伸方向阵列排布。将多个第一测试垫阵列排布，方便使用探针对第一测试垫施加测试信号。
在上述实施例的基础上，可选地，所述第二测试引线50和所述开关控制线70平行设置，以节约布线空间。
本实施例提供的显示面板的测试方法，控制多个开关单元60在对显示面板10进行阵列测试时关闭，避免了多个显示面板10之间由于由一条引线相连接因而存在测试信号干扰的问题，实现了在进行阵列测试时分别对每个显示面板10进行测试，提高了阵列测试的精准度；通过第三测试垫80和开关控制线70，控制多个开关单元60在对显示面板10进行液晶分子取向时导通，实现了在进行液晶分子取向时同时对多个显示面板10形成预倾角，提高了对显示面板10液晶分子取向的效率。

Claims (20)

  1. 一种显示面板的测试电路，包括：
    多个开关单元；
    多条第一测试引线；
    多个第一测试垫；
    第二测试垫、第二测试引线、第三测试垫和开关控制线；
    其中，所述开关单元、所述第一测试引线以及所述第一测试垫的数量相同；且每一所述第一测试引线设置为与对应的一个显示面板电连接；每一所述第一测试垫与对应的所述开关单元的输出端电连接，以及每一所述第一测试垫与对应的所述第一测试引线电连接；所述第二测试垫和所述第二测试引线均与多个所述开关单元的输入端电连接；所述第三测试垫和所述开关控制线均与多个所述开关单元的控制端电连接。
  2. 根据权利要求1所述的测试电路，其中，所述开关单元为三极管。
  3. 根据权利要求2所述的测试电路，其中，所述测试电路还包括多个第四测试垫，每个第四测试垫对应一个显示面板，且每一所述第四测试垫与所述三极管的控制端电连接；
    与同一个显示面板对应的所述第一测试垫和所述第四测试垫相邻设置。
  4. 根据权利要求2所述的测试电路，其中，所述第二测试垫和所述第三测试垫相邻设置。
  5. 根据权利要求2所述的测试电路，其中，所述三极管为N型薄膜晶体管。
  6. 根据权利要求2所述的测试电路，其中，所述三极管的输入端为源极或漏极，所述三极管的输出端为漏极或源极，所述三极管的控制端为栅极。
  7. 根据权利要求1所述的测试电路，其中，所述多个第一测试垫沿所述第二测试引线的延伸方向阵列排布。
  8. 根据权利要求1所述的测试电路，其中，所述第二测试引线和所述开关控制线平行设置。
  9. 一种显示面板的测试方法，包括：将显示面板与测试电路连接，其中所述测试电路包括：
    多个开关单元；
    多条第一测试引线；
    多个第一测试垫；
    第二测试垫、第二测试引线、第三测试垫和开关控制线；
    其中，所述开关单元、所述第一测试引线以及所述第一测试垫的数量相同；且每一所述第一测试引线设置为与对应的一个显示面板电连接；每一所述第一测试垫与对应的所述开关单元的输出端电连接，以及每一所述第一测试垫与对应的所述第一测试引线电连接；所述第二测试垫和所述第二测试引线均与多个所述开关单元的输入端电连接；所述第三测试垫和所述开关控制线均与多个所述开关单元的控制端电连接；
    通过所述第三测试垫控制多个所述开关单元关闭，并通过所述第一测试垫施加第一测试信号到与所述第一测试垫相对应的所述显示面板；
    通过所第三测试垫控制多个所述开关单元导通，并通过所述第二测试垫将第二测试信号施加到多个所述显示面板。
  10. 根据权利要求9所述的测试方法，其中，所述开关单元为三极管。
  11. 根据权利要求10所述的测试方法，其中，所述测试电路还包括多个第四测试垫，每个所述第四测试垫对应一个显示面板，且每一所述第四测试垫与所述三极管的控制端电连接；与同一个显示面板对应的所述第一测试垫和所述第四测试垫相邻设置；
    通过所述第四测试垫输入控制信号，控制多个所述三极管关闭，并通过所述第一测试垫施加第一测试信号到与所述第一测试垫相对应的所述显示面板。
  12. 根据权利要求10所述的测试方法，其中，所述通过所述第三测试垫控制多个所述三极管关闭，包括：
    在所述第三测试垫上施加一低电平信号控制多个所述三极管关闭；
    所述通过所第三测试垫控制多个所述三极管导通，包括：
    在所述第三测试垫上施加一高电平信号控制多个所述三极管导通。
  13. 根据权利要求10所述的测试方法，其中，所述通过所述第三测试垫控制多个所述三极管关闭，包括：
    在所述第三测试垫上不施加控制信号，以使多个所述三极管关闭。
  14. 根据权利要求11所述的测试方法，其中，所述通过所述第四测试垫输入控制信号，控制多个所述三极管关闭，包括：
    在所述第四测试垫上施加一低电平信号，控制多个所述三极管关闭。
  15. 根据权利要求9所述的测试方法，其中，所述第二测试垫和所述第三测试垫相邻设置。
  16. 根据权利要求10所述的测试方法，其中，所述三极管为N型薄膜晶体管。
  17. 根据权利要求10所述的测试方法，其中，所述三极管的输入端为源极或漏极，所述三极管的输出端为漏极或源极，所述三极管的控制端为栅极。
  18. 根据权利要求9所述的测试方法，其中，所述多个第一测试垫沿所述第二测试引线的延伸方向阵列排布。
  19. 根据权利要求9所述的测试方法，其中，所述第二测试引线和所述开关控制线平行设置。
  20. 一种显示面板的测试电路，包括：
    多个开关单元；
    多条第一测试引线；
    多个第一测试垫；
    第二测试垫、第二测试引线、第三测试垫和开关控制线；
    其中，所述开关单元、所述第一测试引线以及所述第一测试垫的数量相同；且每一所述第一测试引线设置为与对应的一个显示面板电连接；每一所述第一测试垫与对应的所述开关单元的输出端电连接，以及每一所述第一测试垫与对应的所述第一测试引线电连接；所述第二测试垫和所述第二测试引线均与多个所述开关单元的输入端电连接；所述第三测试垫和所述开关控制线均与多个所述开关单元的控制端电连接；
    其中，所述第二测试垫和所述第三测试垫相邻设置；所述第二测试引线和所述开关控制线平行设置；所述多个第一测试垫沿所述第二测试引线的延伸方向阵列排布。
PCT/CN2017/100252 2017-06-20 2017-09-01 显示面板的测试电路及测试方法 Ceased WO2018233067A1 (zh)

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