WO2018223799A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2018223799A1
WO2018223799A1 PCT/CN2018/086137 CN2018086137W WO2018223799A1 WO 2018223799 A1 WO2018223799 A1 WO 2018223799A1 CN 2018086137 W CN2018086137 W CN 2018086137W WO 2018223799 A1 WO2018223799 A1 WO 2018223799A1
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Prior art keywords
unit
scan line
data signal
control
pixel circuit
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PCT/CN2018/086137
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English (en)
French (fr)
Inventor
徐映嵩
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US16/329,503 priority Critical patent/US10714007B2/en
Publication of WO2018223799A1 publication Critical patent/WO2018223799A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • ELA Excimer Laser Annealing
  • Doping doping
  • Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display device, which can improve brightness unevenness of a display device caused by effects of threshold voltage and mobility, and compensate for a problem of brightness reduction caused by aging of an OLED.
  • a pixel circuit including: a data writing unit, a driving unit, a resetting unit, a lighting control unit, a lighting unit, and a storage unit, wherein the data writing unit is connected to the data signal line, and the first a scan line and a first node, configured to write a data signal input by the data signal line to the first node under control of a first scan signal of the first scan line; the reset unit, a connection station a data signal line, the first scan line, and an output end of the driving unit, configured to reset a data signal input by the data signal line and write the data signal under control of the first scan signal An input end of the driving unit; one end of the storage unit is connected to the control end of the driving unit, and the other end is connected to the input end of the driving unit and the first power voltage terminal for storing the data signal And translating the information to the control end of the driving unit; the lighting control unit is connected to the output end of the driving unit, the lighting unit, the second scanning line, and the third
  • the pixel circuit further includes a compensation unit that connects the first node, a control end of the driving unit, and a fourth scan line for a fourth scan signal on the fourth scan line And writing the voltage of the first node to the control end of the driving unit and compensating for the illuminating current.
  • the compensation unit is further connected to an input of the lighting unit.
  • the first scan line and the second scan line are the same signal line or two different signal lines.
  • a second aspect the method for driving a pixel circuit according to the first aspect, comprising: a first stage of writing information about a data signal input by the data signal line to the driving unit; The input end of the light emitting unit is reset; in the third stage, a light emitting current is supplied to the light emitting unit to control its light emission.
  • the pixel circuit further includes a compensation unit, the driving method further comprising: resetting the data signal line input while resetting an input end of the light emitting unit in the second phase Data signal; in the third phase, the illuminating current is compensated.
  • a driving circuit comprising the pixel circuit of the first aspect, wherein the plurality of pixel circuits form a matrix, wherein a third scan line of the pixel circuit of the row in the matrix and a pixel circuit of the previous row The fourth scan line is the same scan line.
  • a display device comprising the drive circuit of the third aspect.
  • FIG. 1(a) shows an example circuit configuration diagram of a pixel circuit according to a first embodiment of the present disclosure
  • FIG. 1(b) is a timing chart showing an operation of an example circuit of the pixel circuit in FIG. 1(a);
  • FIG. 2(a) is a diagram showing an example circuit configuration of a pixel circuit according to a second embodiment of the present disclosure
  • FIG. 2(b) is a timing chart showing an operation of an example circuit of the pixel circuit in FIG. 2(a);
  • FIG. 3 shows an example circuit configuration diagram of a pixel circuit according to a third embodiment of the present disclosure
  • FIG. 4 shows an example circuit configuration diagram of a pixel circuit according to a fourth embodiment of the present disclosure
  • FIG. 5(a) shows an example circuit configuration diagram of a pixel circuit according to a fifth embodiment of the present disclosure
  • FIG. 5(b) is a timing chart showing an operation of an example circuit of the pixel circuit in FIG. 5(a);
  • FIG. 6(a) is a diagram showing an example circuit configuration of a pixel circuit according to a sixth embodiment of the present disclosure
  • FIG. 6(b) is a timing chart showing an operation of an example circuit of the pixel circuit in FIG. 6(a);
  • FIG. 7 shows an example circuit configuration diagram of a pixel circuit according to a seventh embodiment of the present disclosure
  • FIG. 8 shows an example circuit configuration diagram of a pixel circuit according to an eighth embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the second pole and the first pole of each transistor are interchanged. Therefore, the second pole and the first pole of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • one of the second and first poles of the transistor is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor.
  • Embodiments of the present disclosure provide a pixel circuit including: a data writing unit, a driving unit, a resetting unit, a lighting control unit, a lighting unit, and a storage unit.
  • the data writing unit connects the data signal line, the first scan line, and the first node, and is configured to write the data signal input by the data signal line to the first node under the control of the first scan signal of the first scan line.
  • the reset unit is connected to the data signal line, the first scan line and the output end of the driving unit for resetting the data signal input by the data signal line under the control of the first scan signal and writing the data signal to the output end of the driving unit .
  • the storage unit has one end connected to the control end of the driving unit, and the other end connected to the input end of the driving unit and the first power voltage terminal for storing information about the data signal and translating it to the control end of the driving unit.
  • the light emission control unit is connected to the output end of the driving unit, the light emitting unit, the second scan line, the third scan line and the second power voltage terminal for the second scan signal of the second scan line and the third scan of the third scan line Under the control of the signal, the second power voltage of the second power voltage terminal is written to the reset unit and the light emitting current is supplied to the light emitting unit to control its light emission.
  • the output end of the light emitting unit is connected to the second power voltage terminal.
  • the pixel circuit further includes a compensation unit that connects the first node, the control end of the driving unit, and the fourth scan line for using the first node under the control of the fourth scan signal of the fourth scan line
  • the voltage is written to the control terminal of the drive unit and compensates for the illuminating current.
  • the compensation unit is further connected to an input end of the light unit.
  • the first scan line and the second scan line are the same signal line or two different signal lines.
  • 1(a) and 2(a) respectively show example circuit configuration diagrams of pixel circuits according to the first embodiment and the second embodiment of the present disclosure.
  • the pixel circuits shown in FIGS. 1(a) and 2(a) each include: a data writing unit 11, a compensation unit 12, a driving unit 13, a reset unit 14, an emission control unit 15, a storage unit 16, and a light-emitting unit 17. .
  • the data writing unit 11 connects the data signal line Idata, the first scanning line CL1 and the first node A
  • the compensation unit 12 connects the first node A and the second.
  • a node B and a fourth scan line EMn a driving unit 13, connected to the first power voltage terminal Vdd, the second node B and the third node C
  • a reset unit 14 connecting the data signal line Idata, the first scan line CL1 and the third a node C
  • an illumination control unit 15 connecting the third node C, the third scan line EMn-1, the second scan line CL2, and the input terminal D of the light-emitting unit 17 and the output terminal E of the light-emitting unit 17
  • the output end of the light-emitting unit 17 E is connected to the second power voltage terminal Vss
  • the second end of the storage unit 16 is connected to the first power voltage terminal Vdd, and the first end is connected to the second node B.
  • the data writing unit 11 includes a first switching transistor T1.
  • the gate of the first switching transistor T1 is connected to the first scan line CL1, the first pole is connected to the data signal line Idata, and the second pole is connected to the first node A.
  • the compensation unit 12 includes a second switching transistor T2.
  • the gate of the second switching transistor T2 is connected to the fourth scan line EMn, the first pole is connected to the first node A, and the second pole is connected to the second node B.
  • the driving unit 13 includes a third switching transistor T3.
  • the gate of the third switching transistor T3 is connected to the second node B.
  • the first pole serves as an input terminal of the driving unit 13 and is connected to the first power supply voltage terminal Vdd
  • the second electrode serves as an output terminal of the driving unit 13 and is connected to the third node C.
  • the reset unit 14 includes a fourth switching transistor T4.
  • the gate of the fourth switching transistor T4 is connected to the first scan line CL1, the first pole is connected to the data signal line Idata, and the second pole is connected to the third node C.
  • the illumination control unit 15 includes a fifth switching transistor T5 and a sixth switching transistor T6.
  • the gate of the fifth switching transistor T5 is connected to the third scan line EMn-1, the first pole is connected to the third node C, and the second pole is connected to the input terminal D of the light emitting unit 17.
  • the gate of the sixth switching transistor T6 is connected to the second scan line CL2, the first electrode is connected to the input terminal D of the light-emitting unit 17, and the second electrode is connected to the output terminal E of the light-emitting unit 17.
  • memory unit 16 includes a first capacitor C1.
  • the first end of the first capacitor C1 is connected to the second node B, and the second end is connected to the first power voltage terminal Vdd.
  • the light emitting unit 17 includes a light emitting diode.
  • the anode of the light-emitting diode serves as the input terminal D of the light-emitting unit 17, and the cathode serves as the output terminal E of the light-emitting unit 17.
  • FIG. 1(b) will be described by taking the same timing of the first scanning line CL1 and the second scanning line CL2 as an example.
  • the present invention is not limited thereto, and the timings of the first scan line CL1 and the second scan line CL2 may be different.
  • the switching transistors in FIG. 1(a) are all P-type transistors as an example. As is well known to those skilled in the art, the P-type transistor is turned on when the gate input is high.
  • the first scanning line CL1, the second scanning line CL2, and the fourth scanning line EMn are at a low level, and the third scanning line EMn-1 is at a high level.
  • the first switching transistor T1 is turned on under the signal control of the first scanning line CL1, and the data signal input from the data signal line Idata is written to the first node A.
  • the second switching transistor T2 is turned on under the signal control of the fourth scan line EMn, and writes the data signal of the first node A to the second node B.
  • the first capacitor C1 at this time stores the voltage difference between the data signal and the first power supply voltage terminal Vdd.
  • the fourth switching transistor T4 is turned on under the control of the first scanning line CL1, and writes the data signal input from the data signal line Idata to the third node C.
  • the fifth switching transistor T5 is turned off under the control of the third scanning line EMn-1.
  • the sixth switching transistor T6 is turned on under the control of the second scanning line CL2, and connects the input terminal D of the light emitting unit 17 to the second power supply voltage terminal Vss.
  • the first scan line CL1, the second scan line CL2, and the third scan line EMn-1 are at a low level, and the fourth scan line EMn is at a high level.
  • the sixth switching transistor T6 is turned on under the control of the second scanning line CL2, and pulls the potential of the input terminal D of the light emitting unit 17 to the second power supply voltage of the second power supply voltage terminal Vss.
  • the fifth switching transistor T5 is turned on under the control of the third scan line EMn-1, and further pulls the potential of the third node C to the second power supply voltage.
  • the fourth switching transistor T4 is turned on under the control of the first scan line CL1, and the potential of the data signal line Idata is also pulled down to the second power supply voltage through the third node C to achieve voltage on the data signal line Idata.
  • the parasitic capacitance is reset. In this way, when the next frame comes, the data signal of the previous frame is not acquired due to the parasitic capacitance on the data signal line Idata, thereby affecting the display effect.
  • the second switching transistor T2 is turned off under the control of the signal of the fourth scanning line EMn.
  • the first switching transistor T1 is turned on under the signal control of the first scanning line CL1, and writes the reset data signal line Idata to the first node.
  • the potential of the second node B can be pulled down by the second switching transistor T2 in the S1 phase of the next frame, thereby ensuring that the third switching transistor T3 can be turned on in the next frame, thereby ensuring The second node B can acquire a voltage corresponding to the current on the data signal line Idata.
  • the first scan line CL1 and the second scan line CL2 are at a high level, and the third scan line EMn-1 and the fourth scan line EMn are at a low level.
  • the first switching transistor T1 is turned off under the control of the signal of the first scanning line CL1.
  • the fourth switching transistor T4 is turned off under the control of the first scanning line CL1.
  • the sixth switching transistor T6 is turned off under the control of the second scanning line CL2.
  • the fifth switching transistor T5 is turned on under the control of the third scanning line EMn-1, and supplies the light-emission current output from the driving unit 13 to the input terminal of the light-emitting unit 17 to cause it to emit light.
  • the second switching transistor T2 supplies the voltage of the first node A to the second node B under the control of the signal of the fourth scan line EMn.
  • the first capacitor C1 stores the potential of the second node B at this time.
  • the driving electrode 13 obtains a voltage value Vg.
  • the data writing phase that is, the S1 phase, the voltage value Vg satisfies:
  • I is the current written by the data signal line Idata
  • Vth is the threshold voltage of the driving electrode 13
  • Idata is written to the data signal line 17, and therefore, regardless of the [mu] and Vth, i.e., a light-emitting unit
  • the current of the 17 illuminating is not affected by the threshold voltage and mobility.
  • the pixel circuit of the second embodiment shown in FIG. 2(a) is substantially the same as the circuit structure of the pixel circuit of the first embodiment shown in FIG. 1(a), and details are not described herein again.
  • the only difference between the first embodiment and the second embodiment is that in the first embodiment, the first scan line and the second scan line are separate two different signal lines, namely CL1 and CL2, respectively, wherein CL2
  • CL1 and CL2 respectively, wherein CL2
  • the timing may be different or the same as CL1; and in the second embodiment, the first scan line and the second scan line are the same signal line, that is, CL1.
  • the first embodiment has an advantage that it is possible to individually control whether the light-emitting unit 17 emits light by controlling the gate potential of the second scan line CL2, even if the fifth switching transistor T5 is in an on state at this time, Moreover, the pixel circuit is in the light emitting phase, and the second scan line CL2 can also be controlled to adjust the light emission of the light emitting unit, thereby modulating brightness and contrast.
  • the second embodiment has the advantage of eliminating one scanning line and, therefore, has a simplified design.
  • the operation timing of the pixel circuit in the first embodiment shown in FIG. 1(a) in the case where the timings of the first scan line CL1 and the second scan line CL2 are the same is as shown in FIG. 2(a).
  • the operation timings of the pixel circuits in the second embodiment are the same. Therefore, the operation timing of the pixel circuit of the second embodiment shown in FIG. 2(b) can be specifically referred to the S1-S3 described above for FIG. 1(b). stage.
  • 3 and 4 respectively show example circuit configuration diagrams of pixel circuits according to third and fourth embodiments of the present disclosure.
  • a second capacitor C2 is added to the compensation unit 12 based on the pixel circuit shown in FIG. 1(a). As shown in FIG. 4, the pixel shown in FIG. 2(a) is shown. On the basis of the circuit, a second capacitor C2 is added to the compensation unit 12. The first end of the second capacitor C2 is connected to the first node A, and the second end is connected to the input terminal D of the light-emitting unit 17.
  • the circuit shown in FIG. 3 is in the S1 phase in FIG. 1(b), the circuit shown in FIG. 4 is in the S1 phase in FIG. 2(b), and the second capacitor C2 is used to store the first node A and the input terminal D of the light-emitting unit 17.
  • the circuit shown in FIG. 3 is in the S2 phase in FIG. 1(b), the circuit shown in FIG. 4 is in the S2 phase in FIG. 2(b), and the second capacitor C2 is also used to pass the data signal line Idata with the second power supply voltage.
  • the Vss connection is discharged when reset.
  • the circuit shown in FIG. 3 is in the S3 phase in FIG. 1(b), the circuit shown in FIG. 4 is in the S3 phase in FIG. 2(b), and the second capacitor C2 is also used to be used by the first power supply voltage when the light-emitting unit 17 emits light.
  • the terminal Vdd is charged by the first capacitor C1.
  • the third and fourth embodiments it is possible to compensate for the decrease in luminance caused by the aging of the light-emitting unit 17 by adding the second capacitor C2.
  • the illuminating phase that is, in the S3 phase, since the illuminating unit 17 ages with the use time, the internal resistance of the illuminating unit 17 increases, and the voltage of the input terminal D of the illuminating unit 17 increases, and is used to store the first node A and the input end of the illuminating unit 17.
  • the voltage difference stored by the second capacitor C2 between the voltage differences between D does not change. Therefore, in the case where the second switching transistor T2 is turned on, the voltage values of the first node A and the first node B also increase. As a result, the drive current value that the drive unit 13 outputs to the light-emitting unit 17 through the fifth switching transistor T5 increases.
  • the voltage value of the input terminal D of the light-emitting unit 17 is increased by Voled, and the voltage value of the second node B is increased by Vx, which is obtained by the conservation of the charge:
  • C1 is the capacitance of the first capacitor
  • C2 is the capacitance of the second capacitor, which is derived from the formula:
  • the value of the actual current Ioled flowing through the driving unit 13 still contains the K value
  • the main determinant of the Ioled is the current value I of the writing phase
  • the value of the K value has very little influence on the Ioled, therefore, when When the pixel circuit is applied to a display device, the cause of instability of the threshold voltage or mobility can be improved to some extent, resulting in uneven brightness of the display device.
  • the value of the driving current output from the driving unit 13 to the light emitting unit 17 through the fifth switching transistor T5 is increased, thereby increasing the brightness of the light emitted from the light emitting unit 17, as compared with the prior art.
  • the light emitted by the illuminating unit 17 after the aging can improve the display brightness, and the illuminating efficiency is lowered due to aging of the illuminating unit 17 with the use time, thereby affecting the illuminating effect.
  • the pixel circuit of the third embodiment shown in FIG. 3 is substantially the same as the circuit structure of the pixel circuit of the fourth embodiment shown in FIG. 4, the only difference being: in the third embodiment, the first scan line and the second The scan lines are two separate signal lines, namely CL1 and CL2, respectively, wherein the timing of CL2 may be different or the same as CL1; and in the fourth embodiment, the first scan line and the second scan line are the same Signal line, CL1.
  • the third embodiment has an advantage that it is possible to individually control whether or not the light-emitting unit 17 emits light by controlling the gate potential of the second scan line CL2, even if the fifth switching transistor T5 is in an on state at this time, Moreover, the pixel circuit is in the light emitting phase, and the second scan line CL2 can also be controlled to adjust the light emission of the light emitting unit, thereby modulating brightness and contrast.
  • the fourth embodiment has the advantage of eliminating one scanning line and, therefore, has a simplified design.
  • 5(a) and 6(a) respectively show an example circuit configuration diagram of a pixel circuit according to a fifth embodiment and a sixth embodiment of the present disclosure.
  • the pixel circuits shown in FIGS. 5(a) and 6(a) each include a data writing unit 11, a driving unit 13, a reset unit 14, an emission control unit 15, a storage unit 16, and a light-emitting unit 17.
  • the pixel circuit of the fifth embodiment shown in FIG. 5(a) reduces the compensation unit 12 as compared with the pixel circuit of the first embodiment shown in FIG. 1(a).
  • the pixel circuit of the sixth embodiment shown in FIG. 6(a) reduces the compensation unit 12 as compared with the pixel circuit of the second embodiment shown in FIG. 2(a). Therefore, the data writing unit 11, the driving unit 13, the reset unit 14, the light emission control unit 15, the storage unit 16, and the light included in the pixel circuits in FIGS. 5(a) and 6(a) are not described herein again.
  • the switching transistor in FIG. 5(a) is a P-type transistor as an example. As is well known to those skilled in the art, the P-type transistor is turned on when the gate input is high.
  • the first scan line CL1 and the second scan line CL2 are at a low level, and the fourth scan line EMn is at a high level.
  • the first switching transistor T1 is turned on under the signal control of the first scanning line CL1, and the data signal input from the data signal line Idata is written in the first node A.
  • the first capacitor C1 at this time stores the voltage difference between the data signal and the first power supply voltage terminal Vdd.
  • the fourth switching transistor T4 is turned on under the control of the first scanning line CL1, and the data signal input from the data signal line Idata is written in the third node C.
  • the fifth switching transistor T5 is turned off under the control of the third scanning line EMn-1.
  • the sixth switching transistor T6 is turned on under the control of the second scanning line CL2, and connects the input terminal D of the light emitting unit 17 to the second power supply voltage terminal Vss.
  • the second scan line CL2 is at a low level, and the first scan line CL1 and the fourth scan line EMn are at a high level.
  • the first switching transistor T1 is turned off under the control of the first scanning line CL1.
  • the fourth switching transistor T4 is turned off under the control of the first scanning line CL1.
  • the fifth switching transistor T5 is turned off under the control of the third scanning line EMn-1.
  • the sixth switching transistor T6 is turned on under the control of the second scanning line CL2, and connects the input terminal D of the light emitting unit 17 to the second power supply voltage terminal Vss.
  • the first scan line CL1 and the second scan line CL2 are at a high level, and the fourth scan line EMn is at a low level.
  • the first switching transistor T1 is turned off under the control of the first scanning line CL1.
  • the fourth switching transistor T4 is turned off under the control of the first scanning line CL1.
  • the sixth switching transistor T6 is turned off under the control of the second scanning line CL2.
  • the fifth switching transistor T5 is turned on under the control of the third scanning line EMn-1, and supplies the light-emission current output from the driving unit 13 to the input terminal D of the light-emitting unit 17 to cause it to emit light.
  • the above S2' phase acts as a buffering phase after the writing phase, ie after the S1 phase and before the lighting phase, ie the S3 phase. If there is no such buffering stage, that is, after the writing phase S1, directly making EMn low and causing CL1 and CL2 to go directly to the high level, the Vss potential may be directly immersed due to possible competition in timing.
  • the S2' phase causes the first switching transistor T1 and the fourth switching transistor T4 to be turned off before the sixth switching transistor T6 is turned off, so as not to affect the Idata signal line.
  • this S2' phase there is a reset of the anode of the light-emitting unit 17. Since the difference between the current type and the voltage type signal writing is that the gate potential of the driving unit is written again, since the current driving IC driving capability is stronger than the voltage driving capability, it does not affect the next frame.
  • the pixel circuit of the sixth embodiment shown in FIG. 6(a) is substantially the same as the circuit structure of the pixel circuit of the fifth embodiment shown in FIG. 5(a), and details are not described herein again.
  • the only difference between the fifth embodiment and the sixth embodiment is that in the fifth embodiment, the first scan line and the second scan line are two separate signal lines, namely, CL1 and CL2, respectively; In the sixth embodiment, the first scan line and the second scan line are the same signal line, that is, CL1.
  • the fifth embodiment has an advantage that it is possible to individually control whether or not the light-emitting unit 17 emits light by controlling the gate potential of the second scan line CL2, even if the fifth switching transistor T5 is in an on state at this time, Moreover, the pixel circuit is in the light emitting phase, and the second scan line CL2 can also be controlled to adjust the light emission of the light emitting unit, thereby modulating brightness and contrast.
  • the sixth embodiment has the advantage of eliminating one scanning line and, therefore, has a simplified design.
  • 7 and 8 respectively show example circuit configuration diagrams of pixel circuits according to seventh and eighth embodiments of the present disclosure.
  • a compensation unit 12 is added to the pixel circuit shown in FIG. 5(a).
  • a compensation is added to the pixel circuit shown in FIG. 6(a).
  • the compensation unit 12 described above includes a second capacitor C2.
  • the first end of the second capacitor C2 is connected to the first node A, and the second end is connected to the input end D of the light emitting unit 17.
  • the second capacitor C2 is for storing a voltage difference between the first node A and the input terminal D of the light emitting unit 17; the second capacitor C2 is charged by the first power voltage terminal Vdd through the first memory C1 when the light emitting unit 17 emits light.
  • the first capacitor C1 and the second capacitor C2 can store the voltage of the first node A, therefore,
  • the first capacitor C1 may or may not be included.
  • the pixel circuit includes the first capacitor C1 if the sixth switching transistor T6 is suddenly turned on or suddenly turned off, it is advantageous to reduce the switching error.
  • the pixel circuit does not include the first capacitor C1, it is advantageous to reduce the board design area.
  • the reduction in luminance caused by the aging of the light-emitting unit 17 can be achieved by adding the second capacitor C2.
  • the illuminating phase that is, in the S3 phase, since the illuminating unit 17 ages with the use time, the internal resistance of the illuminating unit 17 increases, and the voltage of the input terminal D of the illuminating unit 17 increases, and is used to store the first node A and the input end of the illuminating unit 17.
  • the voltage difference stored by the second capacitor C2 between the voltage differences between D does not change, so the voltage value of the first node A (first node B) also increases, so that the driving unit 13 passes the fifth switching transistor.
  • the value of the drive current output by T5 to the light-emitting unit 17 is increased.
  • the value of the actual current Ioled flowing through the driving unit 13 still contains the K value
  • the main determinant of the Ioled is the current value I of the writing phase
  • the value of the K value has very little influence on the Ioled, therefore, when When the pixel circuit is applied to a display device, the cause of instability of the threshold voltage or mobility can be improved to some extent, resulting in uneven brightness of the display device.
  • the value of the driving current output from the driving unit 13 to the light emitting unit 17 through the fifth switching transistor T5 is increased, thereby increasing the brightness of the light emitted from the light emitting unit 17, as compared with the prior art.
  • the light emitted by the illuminating unit 17 after the aging can improve the display brightness, and the illuminating efficiency is lowered due to aging of the illuminating unit 17 with the use time, thereby affecting the illuminating effect.
  • the pixel circuit of the seventh embodiment shown in FIG. 7 is substantially the same as the circuit structure of the pixel circuit of the eighth embodiment shown in FIG. 8, the only difference being: in the seventh embodiment, the first scan line and the second The scan lines are two separate signal lines, namely CL1 and CL2, respectively; and in the eighth embodiment, the first scan line and the second scan line are the same signal line, that is, CL1.
  • the seventh embodiment has an advantage that it is possible to individually control whether or not the light-emitting unit 17 emits light by controlling the gate potential of the second scan line CL2, even if the fifth switching transistor T5 is in an on state at this time, Moreover, the pixel circuit is in the light emitting phase, and the second scan line CL2 can also be controlled to adjust the light emission of the light emitting unit, thereby modulating brightness and contrast.
  • the eighth embodiment has the advantage of eliminating one scanning line and, therefore, has a simplified design.
  • Example circuit structures of the pixel circuits of the eight embodiments of the present disclosure and their operational timings are specifically described above with reference to FIGS. 1(a) through 8.
  • the present disclosure also provides a driving method of a pixel circuit including a data writing unit, a driving unit, a reset unit, an emission control unit, a light emitting unit, and a storage unit.
  • the data writing unit connects the data signal line, the first scan line, and the first node, and is configured to write the data signal input by the data signal line to the first node under the control of the first scan signal of the first scan line.
  • the reset unit is connected to the data signal line, the first scan line and the output end of the driving unit for resetting the data signal input by the data signal line under the control of the first scan signal and writing the data signal to the output end of the driving unit .
  • the storage unit has one end connected to the control end of the driving unit, and the other end connected to the input end of the driving unit and the first power voltage terminal for storing information about the data signal and translating it to the control end of the driving unit.
  • the light emission control unit is connected to the output end of the driving unit, the light emitting unit, the second scan line, the third scan line and the second power voltage terminal for the second scan signal of the second scan line and the third scan of the third scan line Under the control of the signal, the second power voltage of the second power voltage terminal is written to the reset unit and the light emitting current is supplied to the light emitting unit to control its light emission.
  • the output end of the light emitting unit is connected to the second power voltage terminal.
  • the driving method includes:
  • a light-emitting current is supplied to the light-emitting unit to control its light emission.
  • the driving method applied to the pixel circuits of the first and second embodiments of the present disclosure includes:
  • the data writing unit writes the data signal input by the data signal line to the first node under the control of the first scan signal of the first scan line;
  • the compensation unit is under the control of the fourth scan signal of the fourth scan line Writing a data signal of the first node to the second node;
  • the storage unit stores a voltage difference between the data signal and the first power voltage terminal;
  • the reset unit inputs the data signal line under the control of the first scan signal of the first scan line
  • the data signal is written into the third node;
  • the illumination control unit disconnects the third node from the input end of the illumination unit under the control of the third scan signal of the third scan line, and the second scan signal on the second scan line Controlling the input end of the light unit to the second power voltage terminal;
  • the light emission control unit connects the input end of the light emitting unit to the second power voltage terminal under the control of the second scan signal of the second scan line, and emits light under the control of the third scan signal of the third scan line
  • the input end of the unit is connected to the third node;
  • the reset unit connects the third node to the data signal line under the control of the first scan signal of the first scan line;
  • the first scan signal of the data write unit on the first scan line The data signal of the reset data signal line is written into the first node under the control of the signal;
  • the compensation unit disconnects the first node from the second node under the control of the fourth scan signal of the fourth scan line;
  • the data writing unit disconnects the data signal line from the first node under the control of the first scan signal of the first scan line; the reset unit will be under the control of the first scan signal of the first scan line
  • the data signal line is disconnected from the third node;
  • the illumination control unit disconnects the input end of the light emitting unit from the second power supply voltage terminal under the control of the second scan signal of the second scan line, and is in the third scan line
  • the input end of the light emitting unit is connected to the third node under the control of the third scan signal;
  • the storage unit stores the potential of the second node;
  • the compensation unit controls the first node and the second under the control of the fourth scan signal of the fourth scan line
  • the node is connected;
  • the driving unit outputs a light-emitting current to the light-emitting unit through the light-emitting control unit under the control of the voltage of the second node.
  • the compensation unit of the pixel circuit according to the third and fourth embodiments of the present disclosure further includes a second capacitor C2.
  • the driving method applied to the pixel circuits of the third and fourth embodiments of the present disclosure further includes: in the first stage, the second capacitor C2 stores the voltage difference between the data signal and the input terminal D of the light emitting unit 17; in the second stage, The data signal line Idata is reset by being connected to the second power supply voltage terminal Vss, and the second capacitor C2 is discharged; in the third stage, the first power supply voltage terminal Vdd charges the second capacitor C2 through the first capacitor C1.
  • the driving method applied to the pixel circuit of the fifth and sixth embodiments of the present disclosure includes:
  • the data writing unit writes the data signal input by the data signal line to the first node under the control of the signal of the first scan signal of the first scan line;
  • the storage unit stores the voltage difference between the data signal and the voltage terminal of the first power supply;
  • the reset unit writes the data signal input by the data signal line to the third node under the control of the first scan signal of the first scan line;
  • the illumination control unit sets the third node under the control of the third scan signal of the third scan line Disconnecting from an input end of the light emitting unit, and connecting the input end of the light emitting unit to the second power voltage terminal under the control of the second scan signal of the second scan line;
  • the data writing unit disconnects the data signal line from the first node under the control of the signal of the first scan signal of the first scan line;
  • the reset unit is under the control of the first scan signal of the first scan line Disconnecting the data signal line from the third node;
  • the illumination control unit disconnects the third node from the input end of the illumination unit under the control of the third scan signal of the third scan line, and in the second scan line The input end of the light emitting unit is pulled down to the second power supply voltage of the second power supply voltage terminal under the control of the two scan signals;
  • the data writing unit disconnects the data signal line from the first node under the control of the first scan signal of the first scan line; the reset unit will be under the control of the first scan signal of the first scan line
  • the data signal line is disconnected from the third node; the illumination control unit disconnects the input end of the light emitting unit from the second power supply voltage terminal under the control of the second scan signal of the second scan line, and is in the third scan line
  • the third node is connected to the input end of the light emitting unit under the control of the third scan signal; the driving unit outputs the light emitting current to the light emitting unit through the light emitting control unit under the control of the voltage of the second node.
  • the compensation unit of the pixel circuit according to the seventh and eighth embodiments of the present disclosure includes the second capacitor C2.
  • the driving method applied to the pixel circuit of the seventh and eighth embodiments of the present disclosure further includes: in the first stage, the second capacitor C2 stores a voltage difference between the data signal and the input terminal D of the light emitting unit 17; in the second stage, The data signal line Idata is reset by being connected to the second power supply voltage terminal Vss, and the second capacitor C2 is discharged; in the third stage, the first power supply voltage terminal Vdd charges the second capacitor C2 through the first capacitor C1.
  • the present disclosure also provides a driving circuit comprising a plurality of pixel circuits according to any one of the first to eighth embodiments, the plurality of pixel circuits constituting a matrix of a plurality of rows and columns, wherein the matrix
  • the third scan line of the row pixel circuit is the same scan line as the fourth scan line of the previous row of pixel circuits, for example, both are EMn-1.
  • the present disclosure provides a display device comprising the pixel circuit of any of the preceding embodiments.
  • the display device includes a display panel, and the display panel may be an OLED display panel, and the OLED display panel includes an array substrate and a package substrate.
  • the array substrate may include a TFT, an anode electrically connected to the second pole of the TFT, a cathode, and an organic material functional layer between the anode and the cathode.

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Abstract

提供了一种像素电路，包括：数据写入单元(11)、驱动单元(13)、重置单元(14)、发光控制单元(15)、存储单元(16)和发光单元(17)，数据写入单元(11)用于在第一扫描线(CL1)的第一扫描信号的控制下将数据信号线(Idata)输入的数据信号写入第一节点(A)；重置单元(14)用于在第一扫描信号的控制下重置数据信号以及将其写入驱动单元(13)的输出端；存储单元(16)用于存储关于数据信号的信息并将其转写至驱动单元(13)；发光控制单元(15)用于在第二扫描线(CL2)的第二扫描信号以及第三扫描线(EMn-1)的第三扫描信号的控制下，将第二电源电压端(Vss)的第二电源电压写入重置单元(14)以及向发光单元(17)提供发光电流以使其发光。

Description

像素电路及其驱动方法、显示装置
本申请要求2017年06月09日提交的申请号为201710433288.5且发明名称为“一种像素电路及其驱动方法、显示装置”的中国优先申请的优先权，通过引用将其全部内容并入于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示装置。
背景技术
近年来，得益于机电致发光二极管(Organic Light Emitting Diode，简称OLED)显示器的优异显示效果，国内外的OLED相关产业迅速发展，各种像素电路相继被开发出来。
而在实际生产制作薄膜晶体管(Thin Film Transistor，简称TFT)过程中，应用到的ELA(Excimer Laser Annealing，准分子激光退火)及掺杂(Doping)工艺并不能保证TFT具有良好的均一性，从而存在阈值电压(Vth)和迁移率偏差现象，其中，迁移率与电流公式中的μ有关，对于最基本的2T1C(两个具有开关功能的TFT、一个具有存储电荷功能的电容)电路来说，当相同的数据(Data)信号写入时，会由于电流公式中存在不同的Vth和μ而导致各像素(pixel)的亮度不均一，从而引起显示不良等问题，影响影响OLED显示器的显示效果。
发明内容
本公开的实施例提供一种像素电路及其驱动方法、显示装置，可改善因阈值电压和迁移率的影响而造成的显示装置亮度不均，并且补偿OLED老化导致的亮度降低问题。
为达到上述目的，本公开的实施例采用如下技术方案：
第一方面，提供一种像素电路，包括：数据写入单元、驱动单元、重置单元、发光控制单元、发光单元和存储单元，其中，所述数据写入单元，连接数据信号线、第一扫描线和第一节点，用于在所述第一扫描线的第一扫描 信号的控制下将所述数据信号线输入的数据信号写入所述第一节点；所述重置单元，连接所述数据信号线、所述第一扫描线和所述驱动单元的输出端，用于在所述第一扫描信号的控制下重置所述数据信号线输入的数据信号以及将所述数据信号写入所述驱动单元的输出端；所述存储单元，其一端连接所述驱动单元的控制端，另一端连接所述驱动单元的输入端和第一电源电压端，用于存储关于所述数据信号的信息并将其转写至所述驱动单元的控制端；所述发光控制单元，连接所述驱动单元的输出端、所述发光单元、第二扫描线、第三扫描线和第二电源电压端，用于在所述第二扫描线的第二扫描信号以及所述第三扫描线的第三扫描信号的控制下，将所述第二电源电压端的第二电源电压写入所述重置单元以及向所述发光单元提供发光电流以控制其发光；所述发光单元的输出端连接所述第二电源电压端。
在一个实施例中，所述像素电路还包括补偿单元，其连接所述第一节点、所述驱动单元的控制端和第四扫描线，用于在所述第四扫描线的第四扫描信号的控制下将所述第一节点的电压写入所述驱动单元的控制端并且补偿所述发光电流。
在一个实施例中，所述补偿单元还连接所述发光单元的输入端。
在一个实施例中，所述第一扫描线和第二扫描线是同一根信号线或者是两根不同的信号线。
第二方面，提供一种如第一方面所述的像素电路的驱动方法，包括：第一阶段，向所述驱动单元写入关于所述数据信号线输入的数据信号的信息；第二阶段，重置所述发光单元的输入端；第三阶段，向所述发光单元提供发光电流以控制其发光。
在一个实施例中，所述像素电路还包括补偿单元，所述驱动方法还包括：在所述第二阶段中，在重置所述发光单元的输入端的同时，重置所述数据信号线输入的数据信号；在所述第三阶段中，补偿所述发光电流。
第三方面，提供一种驱动电路，包括多个第一方面所述的像素电路，所述多个像素电路构成矩阵，其中矩阵中的本行像素电路的第三扫描线与上一行像素电路的第四扫描线为同一条扫描线。
第四方面，提供一种包括如第三方面所述的驱动电路的显示装置。
附图说明
通过结合附图对本公开的优选实施例进行详细描述，本公开的上述和其他目的、特性和优点将会变得更加清楚，其中相同的标号指定相同结构的单元，并且在其中：
图1(a)示出了根据本公开第一实施例的像素电路的一种示例电路结构图；
图1(b)示出了图1(a)中的像素电路的示例电路的操作时序图；
图2(a)示出了根据本公开第二实施例的像素电路的一种示例电路结构图；
图2(b)示出了图2(a)中的像素电路的示例电路的操作时序图；
图3示出了根据本公开第三实施例的像素电路的一种示例电路结构图；
图4示出了根据本公开第四实施例的像素电路的一种示例电路结构图；
图5(a)示出了根据本公开第五实施例的像素电路的一种示例电路结构图；
图5(b)示出了图5(a)中的像素电路的示例电路的操作时序图；
图6(a)示出了根据本公开第六实施例的像素电路的一种示例电路结构图；
图6(b)示出了图6(a)中的像素电路的示例电路的操作时序图；
图7示出了根据本公开第七实施例的像素电路的一种示例电路结构图；
图8示出了根据本公开第八实施例的像素电路的一种示例电路结构图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在所有实施例中，每个晶体管的第二极和第一极的连接方式可以互换，因此，本公开实施例中各晶体管的第二极、第一极实际是没有区别的。这里，为了描述方便，将晶体管的第二极和第一极之一称作晶体管的第一极，而将另一个称作晶体管的第二极。
本公开实施例提供一种像素电路，包括：数据写入单元、驱动单元、重 置单元、发光控制单元、发光单元和存储单元。
数据写入单元连接数据信号线、第一扫描线和第一节点，其用于在第一扫描线的第一扫描信号的控制下将数据信号线输入的数据信号写入第一节点。
重置单元连接数据信号线、第一扫描线和驱动单元的输出端，其用于在第一扫描信号的控制下重置数据信号线输入的数据信号以及将数据信号写入驱动单元的输出端。
存储单元，其一端连接驱动单元的控制端，另一端连接驱动单元的输入端和第一电源电压端，用于存储关于数据信号的信息并将其转写至驱动单元的控制端。
发光控制单元连接驱动单元的输出端、发光单元、第二扫描线、第三扫描线和第二电源电压端，用于在第二扫描线的第二扫描信号以及第三扫描线的第三扫描信号的控制下，将第二电源电压端的第二电源电压写入重置单元以及向发光单元提供发光电流以控制其发光。
发光单元的输出端连接第二电源电压端。
根据本公开实施例，像素电路还包括补偿单元，其连接第一节点、驱动单元的控制端和第四扫描线，用于在第四扫描线的第四扫描信号的控制下将第一节点的电压写入驱动单元的控制端并且补偿发光电流。
根据本公开实施例，补偿单元还连接发光单元的输入端。
根据本公开实施例，第一扫描线和第二扫描线是同一根信号线或者是两根不同的信号线。
第一和第二实施例
图1(a)和图2(a)分别示出了根据本公开第一实施例和第二实施例的像素电路的示例电路结构图。
图1(a)和图2(a)所示的像素电路各自包括：数据写入单元11、补偿单元12、驱动单元13、重置单元14、发光控制单元15、存储单元16和发光单元17。
在图1(a)所示的第一实施例中，数据写入单元11，连接数据信号线Idata、第一扫描线CL1和第一节点A；补偿单元12，连接第一节点A、第二节点B以及第四扫描线EMn；驱动单元13，连接第一电源电压端Vdd、第二节点B和第三节点C；重置单元14，连接数据信号线Idata、第一扫描线CL1和第三 节点C；发光控制单元15，连接第三节点C、第三扫描线EMn-1、第二扫描线CL2以及发光单元17的输入端D和发光单元17的输出端E；发光单元17的输出端E连接第二电源电压端Vss；存储单元16的第二端连接第一电源电压端Vdd、第一端连接第二节点B。
在该实施例中，数据写入单元11包括第一开关晶体管T1。第一开关晶体管T1的栅极连接第一扫描线CL1，第一极连接数据信号线Idata，第二极连接第一节点A。
在该实施例中，补偿单元12包括第二开关晶体管T2。第二开关晶体管T2的栅极连接第四扫描线EMn，第一极连接第一节点A，第二极连接第二节点B。
在该实施例中，驱动单元13包括第三开关晶体管T3。第三开关晶体管T3的栅极连接第二节点B，第一极作为驱动单元13的输入端并且连接第一电源电压端Vdd，第二极作为驱动单元13的输出端并且连接第三节点C。
在该实施例中，重置单元14包括第四开关晶体管T4。第四开关晶体管T4的栅极连接第一扫描线CL1，第一极连接数据信号线Idata，第二极连接第三节点C。
在该实施例中，发光控制单元15包括第五开关晶体管T5和第六开关晶体管T6。第五开关晶体管T5的栅极连接第三扫描线EMn-1，第一极连接第三节点C，第二极连接发光单元17的输入端D。第六开关晶体管T6的栅极连接第二扫描线CL2，第一极连接发光单元17的输入端D，第二极连接发光单元17的输出端E。
在该实施例中，存储单元16包括第一电容C1。第一电容C1的第一端连接第二节点B，第二端连接第一电源电压端Vdd。
在该实施例中，发光单元17包括发光二极管。发光二极管的阳极作为发光单元17的输入端D，阴极作为发光单元17的输出端E。下面，参考图1(b)来描述如图1(a)所示的像素电路的操作时序。在此，图1(b)以第一扫描线CL1和第二扫描线CL2的时序相同为示例来进行说明。然而本发明不限于此，第一扫描线CL1和第二扫描线CL2的时序也可以不同。
另外，下面以图1(a)中的开关晶体管均为P型晶体管为例进行说明。如本领域技术人员所熟知的，P型晶体管在栅极输入高电平时导通。
在图1(b)中S1阶段，第一扫描线CL1、第二扫描线CL2和第四扫描线 EMn为低电平，第三扫描线EMn-1为高电平。第一开关晶体管T1在第一扫描线CL1的信号控制下导通，并且将数据信号线Idata输入的数据信号写入第一节点A。第二开关晶体管T2在第四扫描线EMn的信号控制下导通，并且将第一节点A的数据信号写入第二节点B。第一电容器C1此时存储数据信号与第一电源电压端Vdd的电压差。第四开关晶体管T4在第一扫描线CL1的控制下导通，并且将数据信号线Idata输入的数据信号写入第三节点C。第五开关晶体管T5在第三扫描线EMn-1的控制下截止。第六开关晶体管T6在第二扫描线CL2的控制下导通，并且将发光单元17的输入端D连接到第二电源电压端Vss。
在图1(b)中S2阶段，第一扫描线CL1、第二扫描线CL2和第三扫描线EMn-1为低电平，第四扫描线EMn为高电平。第六开关晶体管T6在第二扫描线CL2的控制下导通，并且将发光单元17的输入端D的电位拉低至第二电源电压端Vss的第二电源电压。第五开关晶体管T5在第三扫描线EMn-1的控制下导通，并且进一步将第三节点C的电位拉低至第二电源电压。第四开关晶体管T4在第一扫描线CL1的控制下导通，并且通过第三节点C将数据信号线Idata的电位也拉低至第二电源电压，以实现对数据信号线Idata上的电压和寄生电容进行重置。这样一来，当下一帧来临时，不会因数据信号线Idata上的寄生电容而获取上一帧的数据信号，进而影响显示效果。第二开关晶体管T2在第四扫描线EMn的信号控制下截止。第一开关晶体管T1在第一扫描线CL1的信号控制下导通，并且将重置后的数据信号线Idata写入第一节点。这样一来，当下一帧来临时，可以在下一帧的S1阶段通过第二开关晶体管T2将第二节点B电位进行拉低，以此保证下一帧时第三开关晶体管T3可以开启，进而保证第二节点B可以获取与数据信号线Idata上的电流对应的电压。
在图1(b)中S3阶段，第一扫描线CL1和第二扫描线CL2为高电平，第三扫描线EMn-1和第四扫描线EMn为低电平。第一开关晶体管T1在第一扫描线CL1的信号控制下截止。第四开关晶体管T4在第一扫描线CL1的控制下截止。第六开关晶体管T6在第二扫描线CL2的控制下截止。第五开关晶体管T5在第三扫描线EMn-1的控制下导通，并且将从驱动单元13输出的发光电流提供至发光单元17的输入端，以使其发光。第二开关晶体管T2在第四扫描线EMn的信号控制下将第一节点A的电压提供至第二节点B。第一电 容器C1此时存储第二节点B的电位。
在实际显示过程中，当数据信号线Idata输入的数据信号写入第二节点B，即，当数据信号线Idata上的电流流过第二节点B时，驱动电极13得到一个电压值Vg，在数据写入阶段即S1阶段该电压值Vg满足：
Figure PCTCN2018086137-appb-000001
其中，I为数据信号线Idata写入的电流、
Figure PCTCN2018086137-appb-000002
可以看作常数K，Vth为驱动电极13的阈值电压，在发光阶段即S3阶段，
Figure PCTCN2018086137-appb-000003
进而推到得出：
Figure PCTCN2018086137-appb-000004
由电流公式I＝K(Vgs-Vth) 2可知，此时，流过发光单元17的电流即为数据信号线Idata写入的电流I，因此，与Vth和μ无关，即，用于发光单元17发光的电流不受阈值电压和迁移率的影响。当所述像素电路应用于显示装置时，可改善因阈值电压或迁移率不稳定的原因，造成显示装置显示时，亮度不均的现象。
图2(a)所示的第二实施例的像素电路与图1(a)所示的第一实施例的像素电路的电路结构基本相同，在此不再赘述。第一实施例和第二实施例的唯一的区别在于：在第一实施例中，第一扫描线和第二扫描线是单独的两根不同的信号线，即分别为CL1和CL2，其中CL2的时序可以与CL1不同或相同；而在第二实施例中，第一扫描线和第二扫描线是同一根信号线，即CL1。
与第二实施例相比，第一实施例的优点是可以通过控制第二扫描线CL2的栅极电位，单独地控制发光单元17是否发光，即使此时第五开关晶体管T5处于导通状态，并且该像素电路处于发光阶段，也可以控制第二扫描线CL2来调节发光单元的发光，起到调制亮度、对比度的目的。与第一实施例相比，第二实施的优点是省去一条扫描线，因此，具有简化设计的作用。
由于如图1(a)所示的第一实施例中的像素电路在第一扫描线CL1和第二扫描线CL2的时序相同的情况下的操作时序与如图2(a)所示的第二实施例中的像素电路的操作时序相同，因此，图2(b)中所示出的第二实施例的像素电路的操作时序具体可以参见上面对于图1(b)所描述的S1-S3阶段。
第三和第四实施例
图3和图4分别示出了根据本公开第三实施例和第四实施例的像素电路的示例电路结构图。
具体地，如图3所示，在图1(a)所示的像素电路基础上在补偿单元12中增加了第二电容器C2，如图4所示，在图2(a)所示的像素电路基础上在补偿单元12中增加了第二电容器C2，所述第二电容器C2的第一端连接第一节 点A，第二端连接发光单元17的输入端D。
图3所示的电路在图1(b)中S1阶段、图4所示的电路在图2(b)中S1阶段，第二电容器C2用于存储第一节点A与发光单元17输入端D之间的电压差。图3所示的电路在图1(b)中S2阶段、图4所示的电路在图2(b)中S2阶段，第二电容器C2还用于在数据信号线Idata通过与第二电源电压端Vss连接进行重置时放电。图3所示的电路在图1(b)中S3阶段、图4所示的电路在图2(b)中S3阶段，第二电容器C2还用于在发光单元17发光时由第一电源电压端Vdd通过第一电容器C1充电。
在第三和第四实施例中，通过增加第二电容器C2能实现补偿发光单元17老化导致的亮度降低。在发光阶段即S3阶段，由于发光单元17随使用时间老化，发光单元17的内阻增加，发光单元17输入端D的电压随之增加，而用于存储第一节点A与发光单元17输入端D之间的电压差的第二电容器C2所存储的电压差不变，因此，在第二开关晶体管T2导通的情况下，第一节点A、第一节点B的电压值也随之增加，这样一来，驱动单元13通过第五开关晶体管T5向发光单元17输出的驱动电流值增加。
具体的，发光单元17输入端D增加后的电压值为Voled，第二节点B增加后的电压值为Vx，由电荷守恒定理得：
(Vx-Vdd)C1+(Vx-Voled-Vss)C2＝(Vg-Vdd)C1+(Vg-Vss)C2，等式左边为发光阶段的总电荷量，等式右边为写入阶段的总电荷量，C1为第一电容器的电容，C2为第二电容器的电容，由该公式推到得出：
Figure PCTCN2018086137-appb-000005
由前述实施例可知
Figure PCTCN2018086137-appb-000006
故
Figure PCTCN2018086137-appb-000007
所以，
Figure PCTCN2018086137-appb-000008
推到得出：
Figure PCTCN2018086137-appb-000009
此时流过驱动单元13的实际电流
Figure PCTCN2018086137-appb-000010
由此可以看出，随着发光单元17的老化，Voled值增加，Vgs'-Vth值增加，进而驱动单元13通过第五开关晶体管T5向发光单元17输出的驱动电流值增加。
此处，虽然流过驱动单元13的实际电流Ioled的公式中仍包含K值，但是Ioled的主要决定因素为写入阶段的电流值I，K值对Ioled的影响非常小，因此，当所述像素电路应用于显示装置时，在一定程度上仍然可以改善因阈值电压或迁移率不稳定的原因，造成显示装置亮度不均。
因此，在第三和第四实施例中，驱动单元13通过第五开关晶体管T5向发光单元17输出的驱动电流值增加，从而增加发光单元17发出的光的亮度，相较于现有技术中老化后的发光单元17所发出的光，本公开实施例可起到提高显示亮度的效果，避免由于发光单元17随着使用时间老化，发光效率降低，影响发光效果。
图3所示的第三实施例的像素电路与图4所示的第四实施例的像素电路的电路结构基本相同，唯一的区别在于：在第三实施例中，第一扫描线和第二扫描线是单独的两根不同的信号线，即分别为CL1和CL2，其中CL2的时序可以与CL1不同或相同；而在第四实施例中，第一扫描线和第二扫描线是同一根信号线，即CL1。
与第四实施例相比，第三实施例的优点是可以通过控制第二扫描线CL2的栅极电位，单独地控制发光单元17是否发光，即使此时第五开关晶体管T5处于导通状态，并且该像素电路处于发光阶段，也可以控制第二扫描线CL2来调节发光单元的发光，起到调制亮度、对比度的目的。与第三实施例相比，第四实施的优点是省去一条扫描线，因此，具有简化设计的作用。
第五和第六实施例
图5(a)和图6(a)分别示出了根据本公开第五实施例和第六实施例的像素电路的示例电路结构图。
图5(a)和图6(a)所示的像素电路各自包括：数据写入单元11、驱动单元13、重置单元14、发光控制单元15、存储单元16和发光单元17。
与图1(a)所示的第一实施例的像素电路相比，图5(a)所示的第五实施例的像素电路减少了补偿单元12。与图2(a)所示的第二实施例的像素电路相比，图6(a)所示的第六实施例的像素电路减少了补偿单元12。因此，在此不再赘述图5(a)和图6(a)中的像素电路所包含的数据写入单元11、驱动单元13、重置单元14、发光控制单元15、存储单元16和发光单元17的具体连接结构。
下面，参考图5(b)来描述如图5(a)所示的像素电路的操作时序。另外，以图5(a)中的开关晶体管均为P型晶体管为例进行说明。如本领域技术人员所熟知的，P型晶体管在栅极输入高电平时导通。
在图5(b)中S1阶段，第一扫描线CL1和第二扫描线CL2为低电平，第四扫描线EMn为高电平。第一开关晶体管T1在第一扫描线CL1的信号控制下导通，将数据信号线Idata输入的数据信号写入第一节点A。第一电容器 C1此时存储数据信号与第一电源电压端Vdd的电压差。第四开关晶体管T4在第一扫描线CL1的控制下导通，将数据信号线Idata输入的数据信号写入第三节点C。第五开关晶体管T5在第三扫描线EMn-1的控制下截止。第六开关晶体管T6在第二扫描线CL2的控制下导通，并且将发光单元17的输入端D连接到第二电源电压端Vss。
在图5(b)中S2'阶段，第二扫描线CL2为低电平，第一扫描线CL1和第四扫描线EMn为高电平。第一开关晶体管T1在第一扫描线CL1的控制下截止。第四开关晶体管T4在第一扫描线CL1的控制下截止。第五开关晶体管T5在第三扫描线EMn-1的控制下截止。第六开关晶体管T6在第二扫描线CL2的控制下导通，并且将发光单元17的输入端D连接到第二电源电压端Vss。
在图5(b)中S3阶段，第一扫描线CL1和第二扫描线CL2为高电平，第四扫描线EMn为低电平。第一开关晶体管T1在第一扫描线CL1的控制下截止。第四开关晶体管T4在第一扫描线CL1的控制下截止。第六开关晶体管T6在第二扫描线CL2的控制下截止。第五开关晶体管T5在第三扫描线EMn-1的控制下导通，并且将从驱动单元13输出的发光电流提供至发光单元17的输入端D，以使其发光。
上述S2'阶段充当在写入阶段即S1阶段之后以及发光阶段即S3阶段之前的一个缓冲阶段。如果没有这样的缓冲阶段，即，在写入阶段S1之后，直接使得EMn变为低电平且使得CL1、CL2直接变为高电平，那么由于时序上可能存在竞争，导致Vss电位可能直接灌入Idata信号线。该S2'阶段使得在第六开关晶体管T6断开之前，先断开第一开关晶体管T1和第四开关晶体管T4，以达到不影响Idata信号线。另外，在该S2'阶段中，存在对发光单元17的阳极的重置。由于电流型与电压型信号写入的区别在于再次写入驱动单元的栅极电位时，由于电流驱动IC驱动能力较电压驱动能力强，所以不会对下一帧产生影响。
在实际显示过程中，当数据信号线Idata输入的数据信号写入第二节点B，即，当数据信号线Idata上的电流流过第二节点B时，驱动电极13得到一个电压值Vg，在数据写入阶段该电压值Vg满足：
Figure PCTCN2018086137-appb-000011
其中，I为数据信号线Idata写入的电流、
Figure PCTCN2018086137-appb-000012
可以看作常数K，Vth为 驱动电极13的阈值电压，在发光阶段，
Figure PCTCN2018086137-appb-000013
进而推到得出：
Figure PCTCN2018086137-appb-000014
由电流公式I＝K(Vgs-Vth) 2可知，此时，流过发光单元17的电流即为数据信号线Idata写入的电流I，因此，与Vth和μ无关，即，用于发光单元17发光的电流不受阈值电压和迁移率的影响。当所述像素电路应用于显示装置时，可改善因阈值电压或迁移率不稳定的原因，造成显示装置显示时，亮度不均的现象。
图6(a)所示的第六实施例的像素电路与图5(a)所示的第五实施例的像素电路的电路结构基本相同，在此不再赘述。第五实施例和第六实施例的唯一的区别在于：在第五实施例中，第一扫描线和第二扫描线是单独的两根不同的信号线，即分别为CL1和CL2；而在第六实施例中，第一扫描线和第二扫描线是同一根信号线，即CL1。
与第六实施例相比，第五实施例的优点是可以通过控制第二扫描线CL2的栅极电位，单独地控制发光单元17是否发光，即使此时第五开关晶体管T5处于导通状态，并且该像素电路处于发光阶段，也可以控制第二扫描线CL2来调节发光单元的发光，起到调制亮度、对比度的目的。与第五实施例相比，第六实施的优点是省去一条扫描线，因此，具有简化设计的作用。
由于图6(a)所示的第六实施例中的像素电路的操作时序与图5(a)所示的第五实施例中的像素电路的操作时序相似，因此，在此不再赘述图6(a)所示的第六实施例中的像素电路的操作时序。
第七和第八实施例
图7和图8分别示出了根据本公开第七实施例和第八实施例的像素电路的示例电路结构图。
具体地，如图7所示，在图5(a)所示的像素电路基础上增加了补偿单元12，如图8所示，在图6(a)所示的像素电路基础上增加了补偿单元12。上述补偿单元12包括第二电容器C2。第二电容器C2的第一端连接第一节点A，第二端连接发光单元17的输入端D。第二电容器C2用于存储第一节点A与发光单元17输入端D之间的电压差；第二电容器C2在发光单元17发光时通过第一存储器C1由第一电源电压端Vdd进行充电。
需要说明的是，考虑到第一节点A与第二节点B始终导通，二者电位始相同，且第一电容器C1和第二电容器C2均可以存储第一节点A的电压， 因此，当所述像素电路包括第二电容器C2时，可以包括或不包括第一电容器C1。当所述像素电路包括第一电容器C1时，若第六开关晶体管T6突然导通或突然截止，则有利于减小开关误差。当所述像素电路不包括第一电容器C1时，有利于减小电路板设计面积。
在第七和第八实施例中，通过增加第二电容器C2能实现补偿发光单元17老化导致的亮度降低。在发光阶段即S3阶段，由于发光单元17随使用时间老化，发光单元17的内阻增加，发光单元17输入端D的电压随之增加，而用于存储第一节点A与发光单元17输入端D之间的电压差的第二电容器C2所存储的电压差不变，因此第一节点A(第一节点B)的电压值也随之增加，这样一来，驱动单元13通过第五开关晶体管T5向发光单元17输出的驱动电流值增加。
具体的，发光单元17输入端D增加后的电压值为Voled，第二节点B增加后的电压值为Vx，Vx＝Vg+Voled，由前述实施例可知，写入的
Figure PCTCN2018086137-appb-000015
进而可以得到
Figure PCTCN2018086137-appb-000016
所以，
Figure PCTCN2018086137-appb-000017
推到得出：
Figure PCTCN2018086137-appb-000018
因此，此时流过驱动单元13的实际电流
Figure PCTCN2018086137-appb-000019
由此可以看出，随着发光单元17的老化，Voled值增加，Vgs'-Vth值增加，进而驱动单元13通过第五开关晶体管T5向发光单元17输出的驱动电流值增加。
此处，虽然流过驱动单元13的实际电流Ioled的公式中仍包含K值，但是Ioled的主要决定因素为写入阶段的电流值I，K值对Ioled的影响非常小，因此，当所述像素电路应用于显示装置时，在一定程度上仍然可以改善因阈值电压或迁移率不稳定的原因，造成显示装置亮度不均。
因此，在第七和第八实施例中，驱动单元13通过第五开关晶体管T5向发光单元17输出的驱动电流值增加，从而增加发光单元17发出的光的亮度，相较于现有技术中老化后的发光单元17所发出的光，本公开实施例可起到提高显示亮度的效果，避免由于发光单元17随着使用时间老化，发光效率降低，影响发光效果。
图7所示的第七实施例的像素电路与图8所示的第八实施例的像素电路的电路结构基本相同，唯一的区别在于：在第七实施例中，第一扫描线和第 二扫描线是单独的两根不同的信号线，即分别为CL1和CL2；而在第八实施例中，第一扫描线和第二扫描线是同一根信号线，即CL1。
与第八实施例相比，第七实施例的优点是可以通过控制第二扫描线CL2的栅极电位，单独地控制发光单元17是否发光，即使此时第五开关晶体管T5处于导通状态，并且该像素电路处于发光阶段，也可以控制第二扫描线CL2来调节发光单元的发光，起到调制亮度、对比度的目的。与第七实施例相比，第八实施的优点是省去一条扫描线，因此，具有简化设计的作用。
上面参考图1(a)至图8具体说明了本公开的八个实施例的像素电路的示例电路结构及其操作时序。
此外，本公开还提供了一种像素电路的驱动方法，所述像素电路包括数据写入单元、驱动单元、重置单元、发光控制单元、发光单元和存储单元。
数据写入单元连接数据信号线、第一扫描线和第一节点，其用于在第一扫描线的第一扫描信号的控制下将数据信号线输入的数据信号写入第一节点。
重置单元连接数据信号线、第一扫描线和驱动单元的输出端，其用于在第一扫描信号的控制下重置数据信号线输入的数据信号以及将数据信号写入驱动单元的输出端。
存储单元，其一端连接驱动单元的控制端，另一端连接驱动单元的输入端和第一电源电压端，用于存储关于数据信号的信息并将其转写至驱动单元的控制端。
发光控制单元连接驱动单元的输出端、发光单元、第二扫描线、第三扫描线和第二电源电压端，用于在第二扫描线的第二扫描信号以及第三扫描线的第三扫描信号的控制下，将第二电源电压端的第二电源电压写入重置单元以及向发光单元提供发光电流以控制其发光。
发光单元的输出端连接第二电源电压端。
所述驱动方法包括：
第一阶段，向所述驱动单元写入关于所述数据信号线输入的数据信号的信息；
第二阶段，重置所述发光单元的输入端；
第三阶段，向所述发光单元提供发光电流以控制其发光。
具体地，应用于本公开第一和第二实施例的像素电路的驱动方法包括：
第一阶段，数据写入单元在第一扫描线的第一扫描信号的控制下将数据信号线输入的数据信号写入第一节点；补偿单元在第四扫描线的第四扫描信号的控制下将第一节点的数据信号写入第二节点；存储单元存储所述数据信号与第一电源电压端的电压差；重置单元在第一扫描线的第一扫描信号的控制下将数据信号线输入的数据信号写入第三节点；发光控制单元在第三扫描线的第三扫描信号的控制下将第三节点与发光单元的输入端断开连接，并且在第二扫描线的第二扫描信号的控制下将发光单元的输入端连接到第二电源电压端；
第二阶段，发光控制单元在第二扫描线的第二扫描信号的控制下将发光单元的输入端连接到第二电源电压端，并且在第三扫描线的第三扫描信号的控制下将发光单元的输入端连接到第三节点；重置单元在第一扫描线的第一扫描信号的控制下将第三节点连接到数据信号线；数据写入单元在第一扫描线的第一扫描信号的信号控制下将重置后的数据信号线的数据信号写入第一节点；补偿单元在第四扫描线的第四扫描信号的控制下将第一节点与第二节点断开连接；
第三阶段，数据写入单元在第一扫描线的第一扫描信号的控制下将数据信号线与第一节点断开连接；重置单元在第一扫描线的第一扫描信号的控制下将数据信号线与第三节点断开连接；发光控制单元在第二扫描线的第二扫描信号的控制下将发光单元的输入端与第二电源电压端断开连接，并且在第三扫描线的第三扫描信号的控制下将发光单元的输入端连接到第三节点；存储单元存储第二节点的电位；补偿单元在第四扫描线的第四扫描信号的控制下将第一节点与第二节点进行连接；驱动单元在第二节点的电压的控制下，通过发光控制单元向发光单元输出发光电流。
进一步地，根据本公开第三和第四实施例的像素电路的补偿单元还包括第二电容器C2。
应用于本公开第三和第四实施例的像素电路的驱动方法还包括：在第一阶段，第二电容器C2存储数据信号与发光单元17输入端D之间的电压差；在第二阶段，数据信号线Idata通过与第二电源电压端Vss连接而重置，第二电容器C2放电；在第三阶段，第一电源电压端Vdd通过第一电容器C1为第二电容器C2充电。
此外，应用于本公开第五和第六实施例的像素电路的驱动方法包括：
第一阶段，数据写入单元在第一扫描线的第一扫描信号的信号控制下将数据信号线输入的数据信号写入第一节点；存储单元存储数据信号与第一电源电压端的电压差；重置单元在第一扫描线的第一扫描信号的控制下将数据信号线输入的数据信号写入第三节点；发光控制单元在第三扫描线的第三扫描信号的控制下将第三节点与发光单元的输入端断开连接，并且在第二扫描线的第二扫描信号的控制下将发光单元的输入端连接到第二电源电压端；
第二阶段，数据写入单元在第一扫描线的第一扫描信号的信号控制下将数据信号线与第一节点断开连接；重置单元在第一扫描线的第一扫描信号的控制下将数据信号线与第三节点断开连接；发光控制单元在第三扫描线的第三扫描信号的控制下将第三节点与发光单元的输入端断开连接，并且在第二扫描线的第二扫描信号的控制下将发光单元的输入端拉低至第二电源电压端的第二电源电压；
第三阶段，数据写入单元在第一扫描线的第一扫描信号的控制下将数据信号线与第一节点断开连接；重置单元在第一扫描线的第一扫描信号的控制下将数据信号线与第三节点断开连接；发光控制单元在第二扫描线的第二扫描信号的控制下将发光单元的输入端与第二电源电压端断开连接，并且在第三扫描线的第三扫描信号的控制下将第三节点连接到发光单元的输入端；驱动单元在第二节点的电压的控制下，通过发光控制单元向发光单元输出发光电流。
进一步地，根据本公开第七和第八实施例的像素电路的补偿单元包括第二电容器C2。
应用于本公开第七和第八实施例的像素电路的驱动方法还包括：在第一阶段，第二电容器C2存储数据信号与发光单元17输入端D之间的电压差；在第二阶段，数据信号线Idata通过与第二电源电压端Vss连接而重置，第二电容器C2放电；在第三阶段，第一电源电压端Vdd通过第一电容器C1为第二电容器C2充电。
本公开还提供了一种驱动电路，包括多个如第一至第八实施例中的任一实施例的像素电路，所述多个像素电路构成多行多列的矩阵，其中矩阵中的本行像素电路的第三扫描线与上一行像素电路的第四扫描线为同一条扫描线，例如均为EMn-1。
此外，本公开还提供一种显示装置，包括前述任一实施例所述的像素电 路。
所述显示装置包括显示面板，所述显示面板可以是OLED显示面板，OLED显示面板包括阵列基板和封装基板。其中，阵列基板可以包括TFT，与TFT的第二极电连接的阳极、阴极、以及位于阳极和阴极之间的有机材料功能层。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种像素电路，包括：数据写入单元、驱动单元、重置单元、发光控制单元、发光单元和存储单元，其中，
    所述数据写入单元，连接数据信号线、第一扫描线和第一节点，用于在所述第一扫描线的第一扫描信号的控制下将所述数据信号线输入的数据信号写入所述第一节点；
    所述重置单元，连接所述数据信号线、所述第一扫描线和所述驱动单元的输出端，用于在所述第一扫描信号的控制下重置所述数据信号线输入的数据信号以及将所述数据信号写入所述驱动单元的输出端；
    所述存储单元，其一端连接所述驱动单元的控制端，另一端连接所述驱动单元的输入端和第一电源电压端，用于存储关于所述数据信号的信息并将其转写至所述驱动单元的控制端；
    所述发光控制单元，连接所述驱动单元的输出端、所述发光单元、第二扫描线、第三扫描线和第二电源电压端，用于在所述第二扫描线的第二扫描信号以及所述第三扫描线的第三扫描信号的控制下，将所述第二电源电压端的第二电源电压写入所述重置单元以及向所述发光单元提供发光电流以控制其发光；以及
    所述发光单元的输出端连接所述第二电源电压端。
  2. 根据权利要求1所述的像素电路，还包括补偿单元，其连接所述第一节点、所述驱动单元的控制端和第四扫描线，用于在所述第四扫描线的第四扫描信号的控制下将所述第一节点的电压写入所述驱动单元的控制端并且补偿所述发光电流。
  3. 根据权利要求1或2所述的像素电路，其中，所述数据写入单元包括第一开关晶体管，其栅极连接所述第一扫描线，第一极连接所述数据信号线，第二极连接所述第一节点。
  4. 根据权利要求1-3中任一项所述的像素电路，其中，所述存储单元包括第一电容器，该第一电容器的第一端连接所述驱动单元的控制端，第二端连接所述驱动单元的输入端和所述第一电源电压端。
  5. 根据权利要求1-4中任一项所述的像素电路，其中，所述驱动单元包括第三开关晶体管，其栅极和第一极分别连接所述存储单元的两端，第二极 连接所述重置单元和所述发光控制单元。
  6. 根据权利要求1-5中任一项所述的像素电路，其中，所述重置单元包括第四开关晶体管，其栅极连接所述第一扫描线，第一极连接所述数据信号线，第二极连接所述驱动单元的输出端。
  7. 根据权利要求1-6中任一项所述的像素电路，其中，所述发光控制单元包括：
    第五开关晶体管，其栅极连接所述第三扫描线，第一极连接所述驱动单元的输出端，第二极连接所述发光单元的输入端；以及
    第六开关晶体管，其栅极连接所述第二扫描线，第一极连接所述发光单元的输入端，第二极连接所述发光单元的输出端。
  8. 根据权利要求2所述的像素电路，其中，所述补偿单元包括第二开关晶体管，其栅极连接所述第四扫描线，第一极连接所述第一节点，第二极连接所述驱动单元的控制端。
  9. 根据权利要求8所述的像素电路，其中，所述补偿单元还连接所述发光单元的输入端，并且还包括第二电容器，所述第二电容器的第一端连接所述第一节点，第二端连接所述发光单元的输入端。
  10. 根据权利要求1或2所述的像素电路，其中，所述第一扫描线和第二扫描线是同一根信号线或者是两根不同的信号线。
  11. 一种如权利要求1所述的像素电路的驱动方法，包括：
    第一阶段，向所述驱动单元写入关于所述数据信号线输入的数据信号的信息；
    第二阶段，重置所述发光单元的输入端；以及
    第三阶段，向所述发光单元提供发光电流以控制其发光。
  12. 根据权利要求11所述的驱动方法，其中，所述像素电路还包括补偿单元，所述驱动方法还包括：在所述第二阶段中，在重置所述发光单元的输入端的同时，重置所述数据信号线输入的数据信号；在所述第三阶段中，补偿所述发光电流。
  13. 一种驱动电路，包括多个如权利要求1-10任一项所述的像素电路，所述多个像素电路构成矩阵，其中矩阵中的本行像素电路的第三扫描线与上一行像素电路的第四扫描线为同一条扫描线。
  14. 一种显示装置，包括权利要求13所述的驱动电路。
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