WO2018205659A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2018205659A1
WO2018205659A1 PCT/CN2018/071376 CN2018071376W WO2018205659A1 WO 2018205659 A1 WO2018205659 A1 WO 2018205659A1 CN 2018071376 W CN2018071376 W CN 2018071376W WO 2018205659 A1 WO2018205659 A1 WO 2018205659A1
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WO
WIPO (PCT)
Prior art keywords
circuit
electrode pattern
layer
display panel
protection structure
Prior art date
Application number
PCT/CN2018/071376
Other languages
English (en)
French (fr)
Inventor
王祖强
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/078,319 priority Critical patent/US10586814B2/en
Priority to EP18752077.0A priority patent/EP3651199A4/en
Publication of WO2018205659A1 publication Critical patent/WO2018205659A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • Embodiments of the present disclosure relate to a display panel.
  • the manufacturing process of the display device includes a binding process of binding a circuit structure of a peripheral area of the display panel to an external circuit.
  • the electrode pattern on the surface of the circuit may be scratched, thereby causing problems such as electrode disconnection.
  • Embodiments of the present disclosure provide a display panel in which one purpose is to prevent a peripheral circuit of the display panel from being scratched.
  • a display panel including: a substrate; a peripheral circuit on the substrate, the peripheral circuit including a first circuit, a second circuit, and a third circuit, the first The circuit, the second circuit, and the third circuit respectively include a first electrode pattern, a second electrode pattern, and a third electrode pattern; and a protection structure located in at least one of the first circuit, the second circuit, and the third circuit, It is used to prevent the electrode pattern located in the at least one circuit from being broken.
  • FIG. 1 is a cross-sectional view of a peripheral circuit of a display panel related to the present disclosure
  • 2-1 is a top plan view of a display panel of an embodiment of the present disclosure
  • Figure 2-2 is a cross-sectional view of the circuit 12A of Figure 2-1;
  • Figure 2-3 is a cross-sectional view of the circuit 12B of Figure 2-1;
  • FIG. 3 is a cross-sectional view of a peripheral circuit of a display panel according to an embodiment of the present disclosure
  • 4-1 is a cross-sectional view of a circuit 12A of another embodiment of the present disclosure.
  • FIG. 4-2 is a cross-sectional view of a circuit 12A in accordance with still another embodiment of the present disclosure.
  • 4-3 is a cross-sectional view of a circuit 12A of still another embodiment of the present disclosure.
  • 5-1 is a cross-sectional view of a circuit 12C in accordance with an embodiment of the present disclosure
  • 5-2 is a cross-sectional view of a circuit 12C of another embodiment of the present disclosure.
  • 5-3 is a cross-sectional view of a circuit 12C according to still another embodiment of the present disclosure.
  • 6-1 is a cross-sectional view of a circuit 12B of another embodiment of the present disclosure.
  • 6-2 is a top plan view of a circuit 12B according to still another embodiment of the present disclosure.
  • 7-1 is a flowchart of a method for binding a display panel according to an embodiment of the present disclosure
  • FIG. 7-2 is a flowchart of a method for binding a display panel according to another embodiment of the present disclosure.
  • FIG. 1 is a schematic structural view of a display panel related to the present disclosure. As shown in FIG. 1, it is a schematic structural view of a flexible printed circuit (FPC) in which a contact electrode 02 is disposed on a substrate structure 01, and a planar layer 03 is formed on a substrate structure 01 on which a contact electrode 02 is formed.
  • FPC flexible printed circuit
  • the electrodes in the external circuit board can be electrically connected to the contact electrode 02.
  • the display panel 10 includes an active area A (ie, a display area) and a peripheral area B.
  • the peripheral area B is provided with a peripheral circuit 12, and the peripheral circuit 12 may include Chip On Glass (COG) circuit 12A, fanout circuit 12B, and FPC 12C.
  • COG Chip On Glass
  • the structure of the FPC 12C can be as shown in FIG.
  • the COG circuit 12A is for binding to an integrated circuit (IC)
  • the fan-out circuit 12B is for connecting to the bonded IC
  • the FPC 12C is for connecting to an external circuit board.
  • 2-2 is a schematic structural view of a COG circuit 12A of the present disclosure.
  • the source/drain contact electrode 1211 is formed on the substrate structure 51, and is easily scratched and broken.
  • 2-3 is a schematic structural view of a fan-out circuit 12B of the present disclosure.
  • the source/drain contact electrode 1211 is formed on the substrate structure 51.
  • a flat layer 126 and a Pixel Definition Layer (PDL) 52 are formed over the source/drain contact electrode 1211.
  • the PDL 52 may be made of polyimide (PI) and flat.
  • the layers 126 and the pixel defining layer 52 are both soft in material, and it is difficult to protect the source/drain contact electrode 1211 from being scratched.
  • An embodiment of the present invention provides a display panel including: a substrate; a peripheral circuit on the substrate; the peripheral circuit includes a first circuit, a second circuit, and a third circuit, the first circuit, The second circuit and the third circuit respectively include a first electrode pattern, a second electrode pattern, and a third electrode pattern; and a protection structure located in at least one of the first circuit, the second circuit, and the third circuit, wherein The protective structure includes at least one of the first, second, and third electrode patterns for preventing an electrode pattern located in the at least one circuit from being broken.
  • the first circuit is a glass-on-chip circuit
  • the second circuit is a flexible printed circuit
  • the third circuit is a fan-out circuit
  • the protective structure is located in at least two circuits of a chip-on-glass circuit, a flexible printed circuit, and a fan-out circuit, or in each of the above circuits.
  • the first, second, and third electrode patterns respectively comprise a plurality of source and drain contact electrodes.
  • the display panel provided by the embodiment of the present disclosure prevents the source/drain contact electrode pattern from being scratched and broken by providing a protection structure, and solves the related art, the circuit structure of the peripheral area is bound, and the source/drain contact electrode pattern may be drawn.
  • the injury which in turn causes the problem of open circuit, achieves the effect that the source-drain contact electrode pattern is not easily scratched.
  • FIG. 3 is a cross-sectional view of a peripheral circuit of a display panel of an embodiment of the present disclosure.
  • the display panel 10 may include a base substrate 11 on which a peripheral circuit 12 is disposed, and an active drain contact electrode pattern 121 is disposed in the peripheral circuit 12.
  • a protective layer 20 is provided in the base substrate 11 provided with the peripheral circuit 12 for preventing the source/drain contact electrode pattern 121 from being broken.
  • Embodiments of the present disclosure describe the protection structures in the three circuits of the chip-on-glass circuit, the flexible printed circuit, and the fan-out circuit, respectively.
  • FIGS. 4-1, 4-2, and 4-3 show only the on-glass chip circuit 12A in the peripheral circuit of the display panel, and the structure of the display region of the display panel will not be discussed here.
  • the peripheral circuit includes a chip-on-glass circuit 12A
  • the protection structure in the chip-on-glass circuit 12A includes a dielectric layer 34, an electrode pattern, and a protective layer sequentially disposed on the substrate substrate 11. 20.
  • the dielectric layer 34 includes at least one first via K1 with at least a portion of the electrode pattern contacting and covering a peripheral edge of the at least one first via K1.
  • the protective layer 20 contacts and covers the at least a portion of the electrode pattern.
  • the electrode pattern includes a source/drain contact electrode pattern 121, and the source/drain contact electrode pattern 121 includes a plurality of source/drain contact electrodes 1211. 4-1 shows a source/drain contact electrode 1211.
  • the source/drain contact electrode pattern 121 may further include more source/drain contact electrodes 1211, which are not specifically shown in the embodiments of the present disclosure.
  • the source/drain contact electrode pattern 121 contacts and covers a peripheral edge of the at least one first via hole K1, in other words, the source/drain contact electrode pattern 121 surrounds the periphery of the first via hole K1.
  • the first protective layer 20 covers the peripheral edge of each of the source/drain contact electrodes 1211 of the plurality of source/drain contact electrodes 1211.
  • the protective layer 20 can be formed in a patterning process with the pixel electrodes of the display panel without increasing the number of patterning processes.
  • the "primary patterning process” refers to patterning using the same mask.
  • the "patterning process” refers to a process of applying a layer of photoresist, exposing and developing with a mask, and then performing etching.
  • the material of the protective layer 20 is a transparent conductive material, and may include, for example, indium tin oxide (ITO). The hardness of the ITO is high, and the source-drain contact electrode can be effectively protected.
  • ITO indium tin oxide
  • a buffer layer 31 may be disposed on the base substrate 11, a gate insulating layer 32 is disposed on the base substrate 11 provided with the buffer layer 31, and a gate electrode is disposed on the base substrate 11 provided with the gate insulating layer 32. 33.
  • the substrate substrate 11 provided with the gate electrode 33 is provided with a dielectric layer 34.
  • the dielectric layer 34 may be provided with a first via hole K1 corresponding to the plurality of source/drain contact electrodes 1211, one for each source drain.
  • the contact electrode 1211 can be in contact with the gate electrode 33 through one of the first via holes K1. At least a portion of the source/drain contact electrode 1211 covers the inner wall of the first via hole K1, and the protective layer 20 also extends into the first via hole K1. That is, the protective layer 20 contacts and covers all surfaces of the source-drain contact electrode 1211 with respect to the surface convex portion of the dielectric layer 34.
  • the glass-on-chip circuit 12A shown in FIG. 4-1 protects the source-drain contact electrode 1211 by the protective layer 20 covering the peripheral edge of the electrode pattern, so that the source-drain contact electrode 1211 is less likely to be scratched, reducing the possibility of disconnection. At the same time, the source/drain contact electrode 1211 is exposed except for the edge, and other regions are exposed, so that when the source/drain contact electrode is bound, the resistance is not excessively large, which reduces the influence of the voltage drop (IR Drop) phenomenon.
  • IR Drop voltage drop
  • the glass-on-chip circuit 12A of another embodiment of the present disclosure includes a source/drain contact electrode pattern 121, a dielectric layer 34, and a gate electrode 33.
  • the dielectric layer 34 includes a plurality of first via holes K1.
  • the source/drain contact electrode pattern 121 includes a plurality of source/drain contact electrodes 1211.
  • Dielectric layer 34 can be an inter-layer Dielectric (ILD).
  • ILD inter-layer Dielectric
  • the gate electrode 33 is disposed on the base substrate 11.
  • the dielectric layer 34 is disposed on the base substrate 11 provided with the gate electrode 33.
  • the source/drain contact electrode pattern 121 is disposed on the base substrate 11 provided with the dielectric layer 34, and is in contact with the gate electrode 33 through the plurality of first via holes K1, and the plurality of source/drain contact electrodes 1211 and the plurality of first via holes K1 corresponds one by one.
  • the source/drain contact electrode 1211 includes a plurality of second via holes K2, for example, at the bottom of the first via hole K1, the gate electrode 33 is exposed at the second via hole K2, and the source/drain contact electrode 1211 passes through the first via hole K1 and the gate electrode. 33 contacts.
  • the gate electrode 33 can be used as the contact electrode at the time of bonding, and the source/drain contact electrode 1211 can be used to protect the gate electrode 33 from being scratched.
  • the protective structure of FIG. 4-2 further includes a protective layer 20 that covers an edge of each of the source and drain contact electrodes of the plurality of source and drain contact electrodes 1211.
  • the protective layer 20 may be formed in the same patterning process as the pixel electrode and composed of ITO.
  • the protective layer 20 can further enhance the scratch resistance of the source/drain contact electrode 1211.
  • the source/drain contact electrode pattern 121 is a stacked structure including a first metal layer C1 in contact with the gate electrode 33 and a first metal layer C1 in contact with the first metal layer C1.
  • the second metal layer C2 and the third metal layer C3 in contact with the second metal layer C2 have a thickness greater than a thickness of the first metal layer C1.
  • the thickness of the third metal layer C3 and the thickness of the first metal layer C1 are generally equal, and the embodiment of the present disclosure increases the scratch resistance of the source/drain contact electrode pattern 121 by increasing the thickness of the top third metal layer C3. Injury ability.
  • the first metal layer C1 and the third metal layer C3 are titanium metal layers, and the titanium metal layer has strong scratch resistance; the conductive metal layer is an aluminum metal layer, and the aluminum metal layer has strong conductivity.
  • FIGS. 5-1, 5-2, and 5-3 show only the flexible printed circuit 12C in the peripheral circuit of the display panel, and the structure of the display area of the display panel will not be discussed here.
  • FIGS. 4-1, 4-2, and 4-3 only show the glass substrate chip circuit 12A in the peripheral circuit of the display panel.
  • Other structures of the display panel may refer to related technologies, and are no longer referred to herein. Narration.
  • the display panel provided by the embodiment of the present invention prevents the source/drain contact electrode pattern from being scratched and broken by providing a protection structure, and solves the related art, the circuit structure of the peripheral area is bound, and the source/drain contact electrode pattern may be Scratches, which in turn cause problems with open circuits. The effect that the source/drain contact electrode pattern is not easily scratched is achieved.
  • the peripheral circuit includes a flexible printed circuit 12C.
  • the protective structure in the flexible printed circuit 12C includes a source/drain contact electrode pattern 121, a flat layer 124, and a protective layer 20.
  • the thickness of the flat layer 124 is greater than the source and drain.
  • an active drain contact electrode pattern 121 is disposed on the base substrate 11, and the source/drain contact electrode pattern 121 includes a plurality of source/drain contact electrodes 1211.
  • the base substrate 11 on which the active drain contact electrode pattern 121 is disposed is provided with a flat layer 124.
  • the flat layer 124 includes a plurality of third via holes K3, and the plurality of third via holes K3 and the plurality of source/drain contact electrodes 1211 are formed one by one. correspond.
  • the source/drain contact electrode 1211 is disposed in the third via hole K3.
  • the protective layer 20 is overlaid on the flat layer 124 and extends to the bottom of the third via K3 to be in contact with the source/drain contact electrode 1211. Since the flat layer 124 is generally soft and easily scratched, the protective layer 20 may be covered on the flat layer 124 to increase the scratch resistance of the flat layer 124. Under the protection of the flat layer 124, the source/drain contact electrode pattern 121 It is also not easy to be scratched.
  • the protective layer 20 covers the entire outer surface of the flat layer 124 as the outermost layer. The material of the protective layer 20 can be seen in the previous embodiment.
  • a buffer layer 31 may be further disposed on the base substrate 11, a gate insulating layer 32 is disposed on the base substrate 11 on which the buffer layer 31 is disposed, and a dielectric layer 34 is disposed on the base substrate 11 on which the gate insulating layer 32 is disposed.
  • the protective layer 20 may also be disposed only on the side of the flat layer 124, which is adjacent to the third via K3, so as to enhance the scratch resistance of the flat layer 124.
  • the effect of injury ability For the meanings of other tags in Figure 5-2, refer to Figure 5-1, and details are not described here.
  • the protection structure of the flexible printed circuit 12C includes a source/drain contact electrode pattern 121 and an interlayer insulating layer 122.
  • the interlayer insulating layer 122 is provided with a plurality of fourth via holes. K4.
  • the interlayer insulating layer 122 may be an intermediate dielectric layer.
  • An active drain contact electrode pattern 121 is disposed on the base substrate 11 provided with the interlayer insulating layer 122.
  • the source/drain contact electrode pattern 121 includes a plurality of source/drain contact electrodes 1211, and the plurality of source/drain contact electrodes 1211 are disposed in a plurality of fourth In the via hole K4, the plurality of source/drain contact electrodes 1211 are in one-to-one correspondence with the plurality of fourth via holes K4.
  • the base substrate 11 on which the active drain contact electrode pattern 121 is disposed is provided with a flat layer 124.
  • the flat layer 124 includes a plurality of third via holes K3, and the plurality of third via holes K3 and the plurality of source/drain contact electrodes 1211 are formed one by one.
  • each of the source/drain contact electrodes 1211 can be exposed from the third via K3.
  • the source/drain contact electrode pattern 121 contacts and covers the peripheral edge of the fourth via hole and extends into the contact region between the flat layer 124 and the interlayer insulating layer 122.
  • the source/drain contact electrode pattern 121 is less likely to be scratched.
  • a protective layer 20 as shown in FIG. 5-1 may also be formed on the flat layer 124 in FIG. 5-3 to further protect the source/drain contact electrode pattern 121.
  • the display panel provided by the embodiment of the present disclosure prevents the source/drain contact electrode pattern from being scratched and broken by providing a protection structure, and solves the related art, the circuit structure of the peripheral area is bound, and the source/drain contact electrode pattern may be Scratches, which in turn cause problems with open circuits. The effect that the source/drain contact electrode pattern is not easily scratched is achieved.
  • FIGS. 6-1 and 6-2 show only the fan-out circuit 12B in the peripheral circuit of the display panel, and the structure of the display area of the display panel will not be discussed here.
  • the peripheral circuit includes a fan-out circuit 12B
  • the protection structure in the fan-out circuit 12B includes a source-drain contact electrode pattern 121, a planarization layer 126, and a protective layer 20.
  • an active drain contact electrode pattern 121 is provided on the base substrate 11, and a flat layer 126 is provided on the base substrate 11 on which the active drain contact electrode pattern 121 is provided.
  • the protective layer 20 is disposed on the base substrate 11 provided with the flat layer 126, and the orthographic projection of the source/drain contact electrode pattern 121 on the base substrate 11 overlaps with the orthographic projection of the protective layer 20 on the base substrate 11, that is, protection The layer 20 is overlaid over the source/drain contact electrode pattern 121 to protect the source and drain contact electrode patterns 121.
  • a pixel defining layer may also be formed on the substrate substrate on which the protective layer 20 is formed, which is not limited in the embodiment of the present disclosure.
  • FIG. 6-2 which is a top view of the fan-out circuit 12B in the display panel shown in FIG. 6-1, wherein the protective layer 20 is composed of a plurality of block structures arranged at intervals. There may be one source/drain contact electrode under each of the block structures in Figure 6-2.
  • the spaced block structure can reduce the cost of materials and can cause problems such as disconnection when the protective layer 20 is made of a conductive material.
  • the display panel includes a pixel electrode pattern in the display area, and the protective layer 20 is disposed in the same layer as the pixel electrode pattern. This makes it possible to provide a protective structure without increasing the patterning process.
  • the protective layer 20 is composed, for example, of indium tin oxide.
  • Indium tin oxide is harder in material and can resist scratching.
  • the display panel provided by the embodiment of the present disclosure prevents the source/drain contact electrode pattern from being scratched and broken by providing a protection structure, and solves the related art, the circuit structure of the peripheral area is bound, and the source/drain contact electrode pattern may be Scratches, which in turn cause problems with open circuits. The effect that the source/drain contact electrode pattern is not easily scratched is achieved.
  • FIG. 7-1 it is a flowchart of a method for binding a display panel according to an embodiment of the present disclosure, which is used in the display panel shown in each embodiment, and the binding method of the display panel includes:
  • Step 701 Acquire a display panel and an external circuit.
  • the external circuit includes an integrated circuit and an external circuit board.
  • Step 702 Bind the external circuit to the peripheral circuit of the display panel.
  • the peripheral circuits may include a chip-on-glass circuit and a flexible printed circuit.
  • the on-glass chip circuit and the flexible printed circuit can be respectively bound.
  • this step can include the following two sub-steps:
  • Sub-step 7021 combines the integrated circuit with the on-glass chip circuit.
  • Binding can be performed by an anisotropic conductive film.
  • Sub-step 7022 the external circuit board is bound to the flexible printed circuit.
  • Binding can be performed by an anisotropic conductive film.
  • the binding method of the display panel provided by the embodiment of the present disclosure prevents the source/drain contact electrode pattern from being scratched and broken during the binding by setting the protection structure, and solves the related problem that the circuit structure of the peripheral area in the related art is bound.
  • the source/drain contact electrode pattern may be scratched, which may cause an open circuit problem. The effect that the source/drain contact electrode pattern is not easily scratched when bound is achieved.

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Abstract

一种显示面板(10)，其包括：衬底基板(11)；位于所述衬底基板(11)上的外围电路(12)，所述外围电路(12)包括第一电路、第二电路和第三电路，所述第一电路、第二电路和第三电路分别包括第一电极图案、第二电极图案和第三电极图案；和保护结构，位于所述第一电路、第二电路和第三电路的至少一个电路中，用于避免所述电极图案断路。通过在上述显示面板(10)中设置保护结构来避免电极图案被划伤断路。

Description

显示面板
相关申请的交叉引用
本申请基于并且要求于2017年5月12日递交的中国专利申请第201710332764.4号的优先权，在此全文引用上述中国专利申请公开的内容。
技术领域
本公开实施例涉及一种显示面板。
背景技术
显示装置的制造过程包括将显示面板外围区域的电路结构与外部电路绑定(Bonding)起来的绑定流程。然而，上述外围区域的电路结构在进行绑定时，位于电路表面的电极图案可能会被划伤，进而造成电极断路等问题。
发明内容
本公开实施例提供了一种显示面板，其中一个目的是避免显示面板的外围电路被划伤。
根据本公开实施例，提供一种显示面板，包括：衬底基板；位于所述衬底基板上的外围电路，所述外围电路包括第一电路、第二电路和第三电路，所述第一电路、第二电路和第三电路分别包括第一电极图案、第二电极图案和第三电极图案；和保护结构，位于所述第一电路、第二电路和第三电路的至少一个电路中，用于避免位于该至少一个电路中的电极图案断路。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，而非对本公开的限制。
图1是本公开相关的一种显示面板周边电路的截面图；
图2-1是本公开实施例的显示面板的俯视图；
图2-2是图2-1中电路12A的截面图；
图2-3是图2-1中电路12B的截面图；
图3是本公开实施例的一种显示面板周边电路的截面图；
图4-1是本公开另一实施例的电路12A的截面图；
图4-2是本公开再一实施例的电路12A的截面图；
图4-3是本公开又一实施例的电路12A的截面图；
图5-1是本公开一实施例的电路12C的截面图；
图5-2是本公开另一实施例的电路12C的截面图；
图5-3是本公开再一实施例的电路12C的截面图；
图6-1是本公开另一实施例的电路12B的截面图；
图6-2是本公开再一实施例的电路12B的俯视图；
图7-1是本公开实施例提供的一种显示面板的绑定方法的流程图；
图7-2是本公开另一实施例提供的一种显示面板的绑定方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1是本公开相关的一种显示面板的结构示意图。如图1所示，其为一种柔性印刷电路(FPC)的结构示意图，其中接触电极02设置在衬底结构01上，形成有接触电极02的衬底结构01上形成有平坦层03。在将该FPC与外部电路板绑定时，可以将外部电路板中的电极与接触电极02电连接。
图2-1是本公开实施例中各个电路的结构示意图，其中，显示面板10包括有效区域A(即显示区域)和外围区域B，外围区域B中设置有外围电路12，外围电路12可以包括玻璃衬底芯片(Chip On Glass，COG)电路12A、扇出(FanOut)电路12B和FPC12C。FPC 12C的结构可以如图1所示。COG电路12A用于与集成电路(integrated circuit，IC)进行绑定，扇出电路12B用于与绑定后的IC连接，FPC12C用于与外部电路板连接。
图2-2是本公开一种COG电路12A的结构示意图。源漏接触电极1211形成于衬底结构51上，容易被划伤而断路。图2-3是本公开一种扇出电路12B的结构示意图。源漏接触电极1211形成于衬底结构51上，源漏接触电极1211上方形成有平坦层126和像素定义层(Pixel Definition Layer，PDL)52，PDL52可以由聚酰亚胺(PI)构成，平坦层126和像素定义层52材质均较软，难以保护源漏接触电极1211不被划伤。
本发明实施例提供一种显示面板，包括：衬底基板；位于所述衬底基板上的外围电路，所述外围电路包括第一电路、第二电路和第三电路，所述第一电路、第二电路和第三电路分别包括第一电极图案、第二电极图案和第三电极图案；和保护结构，位于所述第一电路、第二电路和第三电路的至少一个电路中，其中所述保护结构至少包括第一、第二和第三电极图案中的至少一个，用于避免位于该至少一个电路中的电极图案断路。
至少一些实施例中，所述第一电路为玻璃上芯片电路，所述第二电路为柔性印刷电路，所述第三电路为扇出电路。
至少一些实施例中，所述保护结构位于玻璃上芯片电路、柔性印刷电路和扇出电路的至少两个电路中，或者位于以上每个电路中。
至少一些实施例中，所述第一、第二和第三电极图案分别包括多个源漏接触电极。
本公开实施例提供的显示面板，通过设置保护结构来避免源漏接触电极图案被划伤断路，解决了相关技术中外围区域的电路结构在进行绑定时，源 漏接触电极图案可能会被划伤，进而造成断路的问题，达到了源漏接触电极图案不易被划伤的效果。
例如，图3是本公开实施例的一种显示面板的周边电路的截面图。该显示面板10可以包括：衬底基板11；衬底基板11上设置有外围电路12，外围电路12中设置有源漏接触电极图案121。设置有外围电路12的衬底基板11中设置有保护层20，保护层20用于避免源漏接触电极图案121断路。
本公开实施例下面分别对玻璃上芯片电路、柔性印制电路和扇出电路这三种电路中的保护结构进行说明。
为了便于说明，图4-1、图4-2和图4-3仅示出了显示面板的外围电路中的玻璃上芯片电路12A，显示面板的显示区域的结构在此不做讨论。
参考图4-1，至少一些实施例中，外围电路包括玻璃上芯片电路12A，玻璃上芯片电路12A中的保护结构包括依次设置在衬底基板11上的介电层34、电极图案和保护层20。介电层34包括至少一个第一过孔K1，电极图案的至少一部分接触并且覆盖所述至少一个第一过孔K1的周边边缘。保护层20接触并覆盖所述电极图案的该至少一部分。
至少一些实施例中，电极图案包括源漏接触电极图案121，源漏接触电极图案121包括多个源漏接触电极1211。图4-1示出了一个源漏接触电极1211，源漏接触电极图案121中还可以包括更多的源漏接触电极1211，本公开实施例不再具体画出。
如图4-1所示，源漏接触电极图案121的至少一部分接触并且覆盖所述至少一个第一过孔K1的周边边缘，换言之，源漏接触电极图案121环绕于第一过孔K1的周边设置。第一保护层20覆盖在多个源漏接触电极1211中每个源漏接触电极1211的周边边缘。该保护层20可以与显示面板的像素电极在一次构图工艺中形成，不用增加构图工艺的次数。这里，“一次构图工艺”指的是采用同一掩模板进行图案化，“构图工艺”例如指的是涂覆一层光刻胶，利用掩模板曝光和显影，然后进行刻蚀等工艺。保护层20的材料为透明导电材料，例如可以包括氧化铟锡(Indium tin oxide，ITO)，ITO的硬度较高，能够有效的保护源漏接触电极。
衬底基板11上还可以设置有缓冲(buffer)层31，设置有缓冲层31的衬底基板11上设置有栅绝缘层32，设置有栅绝缘层32的衬底基板11上设 置有栅极33，设置有栅极33的衬底基板11上设置有介电层34，介电层34上可以设置有与多个源漏接触电极1211一一对应的第一过孔K1，每个源漏接触电极1211可以通过其中一个第一过孔K1与栅极33接触。源漏接触电极1211的至少一部分覆盖第一过孔K1的内壁，保护层20也延伸到所述第一过孔K1内。也就是说，保护层20接触并覆盖源漏接触电极1211相对于介电层34的表面凸出部分的所有表面。
图4-1所示的玻璃上芯片电路12A通过覆盖在电极图案的周边边缘的保护层20来保护源漏接触电极1211，使得源漏接触电极1211不易被划伤，减少了断路的可能性。同时源漏接触电极1211除了边缘被保护结构覆盖外，其他区域露出，使得源漏接触电极在进行绑定时，电阻不会过大，减小了电压降(IR Drop)现象造成的影响。
如图4-2所示，本公开另一实施例的玻璃上芯片电路12A包括源漏接触电极图案121、介电层34和栅极33，介电层34包括有多个第一过孔K1，源漏接触电极图案121包括多个源漏接触电极1211。介电层34可以为中间介电层(inter-layer Dielectric，ILD)。图4-2中其他标记的含义可以参考图4-1，在此不再赘述。
栅极33设置在衬底基板11上。介电层34设置在设置有栅极33的衬底基板11上。源漏接触电极图案121设置在设置有介电层34的衬底基板11上，并通过多个第一过孔K1与栅极33接触，多个源漏接触电极1211与多个第一过孔K1一一对应。
源漏接触电极1211包括多个第二过孔K2，例如位于第一过孔K1的底部，栅极33在第二过孔K2处露出，源漏接触电极1211通过第一过孔K1与栅极33接触。这样就能够以栅极33来作为绑定时的接触电极，而源漏接触电极1211可以用于保护保护栅极33，避免栅极33被划伤。
至少一些实施例中，图4-2的保护结构还包括保护层20，其覆盖在多个源漏接触电极1211中每个源漏接触电极的边缘。保护层20可以与像素电极在同一次构图工艺中形成，并由ITO构成。保护层20能够进一步增强源漏接触电极1211的抗划伤能力。
如图4-3所示，至少一些实施例中，源漏接触电极图案121为叠层结构，叠层结构包括与栅极33接触的第一金属层C1、与第一金属层C1接触的第 二金属层C2以及与第二金属层C2接触的第三金属层C3，第三金属层C3的厚度大于第一金属层C1的厚度。相关技术中，第三金属层C3的厚度和第一金属层C1的厚度一般是相等的，本公开实施例通过增加顶部第三金属层C3的厚度，以增加源漏接触电极图案121的抗划伤能力。
至少一些实施例中，第一金属层C1和第三金属层C3为钛金属层，钛金属层的抗划伤能力较强；导电金属层为铝金属层，铝金属层的导电能力较强。
为了便于说明，图5-1、图5-2和图5-3仅示出了显示面板的外围电路中的柔性印制电路12C，显示面板的显示区域的结构在此不做讨论。
为了便于说明，图4-1、图4-2和图4-3仅示出了显示面板的外围电路中的玻璃衬底芯片电路12A，显示面板的其它结构可以参考相关技术，在此不再赘述。
上述本发明实施例提供的显示面板，通过设置保护结构来避免源漏接触电极图案被划伤断路，解决了相关技术中外围区域的电路结构在进行绑定时，源漏接触电极图案可能会被划伤，进而造成断路的问题。达到了源漏接触电极图案不易被划伤的效果。
如图5-1所示，外围电路包括柔性印制电路12C，柔性印制电路12C中的保护结构包括源漏接触电极图案121、平坦层124和保护层20，平坦层124的厚度大于源漏接触电极图案121的厚度。
至少一些实施例中，衬底基板11上设置有源漏接触电极图案121，源漏接触电极图案121包括多个源漏接触电极1211。设置有源漏接触电极图案121的衬底基板11上设置有平坦层124，平坦层124包括有多个第三过孔K3，多个第三过孔K3与多个源漏接触电极1211一一对应。源漏接触电极1211设置在第三过孔K3。
保护层20覆盖在平坦层124上，并且延伸到第三过孔K3的底部以与源漏接触电极1211相接触。由于平坦层124一般较软，易被划伤，因而可以在平坦层124上覆盖保护层20，以增加平坦层124的抗划伤能力，在平坦层124的保护下，源漏接触电极图案121也不易被划伤。保护层20覆盖平坦层124的整个外表面以作为最外层。保护层20的材料可参见前面实施例。
衬底基板11上还可以设置有缓冲层31，设置有缓冲层31的衬底基板11上设置有栅绝缘层32，设置有栅绝缘层32的衬底基板11上设置有介电层34。
如图5-2示出，至少一些实施例中，保护层20还可以仅设置在平坦层124的侧面，该侧面与第三过孔K3邻近，这样也能够起到增强平坦层124的抗划伤能力的效果。图5-2中其他标记的含义可以参考图5-1，在此不再赘述。
如图5-3所示，至少一些实施例中，柔性印制电路12C的保护结构包括源漏接触电极图案121、层间绝缘层122，层间绝缘层122中设置有多个第四过孔K4。层间绝缘层122可以为中间介电层。
设置有层间绝缘层122的衬底基板11上设置有源漏接触电极图案121，源漏接触电极图案121包括多个源漏接触电极1211，多个源漏接触电极1211设置在多个第四过孔K4中，且多个源漏接触电极1211与多个第四过孔K4一一对应。
设置有源漏接触电极图案121的衬底基板11上设置有平坦层124，平坦层124包括有多个第三过孔K3，多个第三过孔K3与多个源漏接触电极1211一一对应，使每个源漏接触电极1211均能够从第三过孔K3中露出。源漏接触电极图案121接触并覆盖第四过孔的周边边缘，并且延伸到平坦层124和层间绝缘层122之间的接触区中。
如5-3中所示，将源漏接触电极图案121埋入层间绝缘层122后，源漏接触电极图案121不易被划伤。
此外，还可以在图5-3中的平坦层124上形成如图5-1中所示的保护层20，以进一步保护源漏接触电极图案121。
图5-3中其他标记的含义可以参考图5-1，在此不再赘述。
上述本公开实施例提供的显示面板，通过设置保护结构来避免源漏接触电极图案被划伤断路，解决了相关技术中外围区域的电路结构在进行绑定时，源漏接触电极图案可能会被划伤，进而造成断路的问题。达到了源漏接触电极图案不易被划伤的效果。
为了便于说明，图6-1和图6-2仅示出了显示面板的外围电路中的扇出电路12B，显示面板的显示区域的结构在此不做讨论。
至少一些实施例中，外围电路包括扇出电路12B，扇出电路12B中的保护结构包括源漏接触电极图案121、平坦层126和保护层20。
例如，衬底基板11上设置有源漏接触电极图案121，设置有源漏接触电 极图案121的衬底基板11上设置有平坦层126。保护层20设置在设置有平坦层126的衬底基板11上，源漏接触电极图案121在衬底基板11上的正投影与保护层20在衬底基板11上的正投影存在重叠，即保护层20覆盖在源漏接触电极图案121的上方以保护源漏接触电极图案121。
此外，形成有保护层20的衬底基板上还可以形成有像素定义层，本公开实施例不作出限制。
至少一些实施例中，如图6-2所示，其为图6-1所示的显示面板中扇出电路12B的俯视图，其中，保护层20由多个间隔排布的块状结构组成，图6-2中的每个块状结构下方可以存在一个源漏接触电极。间隔的块状结构能够减少材料的耗费，并能够在保护层20由导电材料构成时，不会造成断路等问题。
至少一些实施例中，显示面板包括显示区域中的像素电极图案，保护层20与像素电极图案同层设置。这样能够在不增加构图工艺的基础上，设置保护结构。
至少一些实施例中，保护层20例如由氧化铟锡构成。氧化铟锡的材质较硬，能够起到抗划伤的作用。
上述本公开实施例提供的显示面板，通过设置保护结构来避免源漏接触电极图案被划伤断路，解决了相关技术中外围区域的电路结构在进行绑定时，源漏接触电极图案可能会被划伤，进而造成断路的问题。达到了源漏接触电极图案不易被划伤的效果。
如图7-1所示，其为本公开实施例提供的一种显示面板的绑定方法的流程图，用于上述各个实施例所示出的显示面板，该显示面板的绑定方法包括：
步骤701、获取显示面板与外部电路。
外部电路包括集成电路和外部电路板。
步骤702、将外部电路与显示面板的外围电路进行绑定。
外围电路可以包括玻璃上芯片电路和柔性印制电路。
本公开实施例中，可以对玻璃上芯片电路和柔性印制电路分别进行绑定。
如图7-2所示，本步骤可以包括下面两个子步骤：
子步骤7021，将集成电路与玻璃上芯片电路进行绑定。
可以通过异方性导电胶膜来进行绑定。
子步骤7022，将外部电路板与柔性印制电路进行绑定。
可以通过异方性导电胶膜来进行绑定。
上述本公开实施例提供的显示面板的绑定方法，通过设置保护结构来避免源漏接触电极图案在绑定时被划伤断路，解决了相关技术中外围区域的电路结构在进行绑定时，源漏接触电极图案可能会被划伤，进而造成断路的问题。达到了源漏接触电极图案在绑定时不易被划伤的效果。
本文中，有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (17)

  1. 一种显示面板，包括：
    衬底基板；
    位于所述衬底基板上的外围电路，所述外围电路包括第一电路、第二电路和第三电路，所述第一电路、第二电路和第三电路分别包括第一电极图案、第二电极图案和第三电极图案；和
    保护结构，位于所述第一电路、第二电路和第三电路的至少一个电路中，用于避免位于该至少一个电路中的电极图案断路。
  2. 根据权利要求1所述的显示面板，其中，所述保护结构包括位于第一电路中的第一保护结构，第一保护结构包括依次设置在所述衬底基板上的介电层、所述第一电极图案和第一保护层；所述介电层包括至少一个第一过孔，所述第一电极图案的至少一部分接触并且覆盖所述至少一个第一过孔的边缘；所述第一保护层接触并覆盖所述第一电极图案的该至少一部分。
  3. 根据权利要求2所述的显示面板，其中，所述第一电极图案的至少一部分覆盖所述至少一个第一过孔的内壁，所述第一保护层延伸到所述至少一个第一过孔内。
  4. 根据权利要求1所述的显示面板，其中，所述保护结构包括位于第一电路中的第一保护结构，所述第一保护结构包括依次设置在所述衬底基板上的栅极、介电层和所述第一电极图案；所述介电层包括至少一个第一过孔，所述第一电极图案的至少一部分接触并且覆盖所述至少一个第一过孔的边缘；所述第一电极图案包括位于所述第一过孔的底部的第二过孔，所述第一电极图案通过所述第一过孔与所述栅极接触，所述栅极在所述第二过孔处露出。
  5. 根据要求4所述的显示面板，其中，所述第一电极图案包括叠层结构，所述叠层结构包括与所述栅极接触的第一金属层、与所述第一金属层接触的第二金属层以及与所述第二金属层接触的第三金属层，所述第三金属层的厚度大于所述第一金属层的厚度。
  6. 根据权利要求5所述的显示面板，其中，所述第一金属层和所述第三金属层为钛层；所述第二金属层为铝层。
  7. 根据权利要求4所述的显示面板，其中，所述保护结构还包括覆盖在所述第一电极图案上的第一保护层。
  8. 根据权利要求1所述的显示面板，其中，所述保护结构包括位于第二电路中的第二保护结构，所述第二保护结构包括设置在所述衬底基板上的所述第二电极图案、平坦层和第二保护层；所述平坦层包括至少一个第三过孔，所述第二电极图案设置在所述至少一个第三过孔中，所述第二保护层覆盖所述平坦层，并且所述平坦层的厚度大于所述第二电极图案的厚度。
  9. 根据权利要求8所述的显示面板，其中，所述第二保护层延伸到所述至少一个第三过孔的底部以与所述第二电极图案相接触。
  10. 根据权利要求8所述的显示面板，其中，所述第二保护层覆盖所述平坦层的整个外表面。
  11. 根据权利要求1所述的显示面板，其中，所述保护结构包括位于第二电路中的第二保护结构，所述第二保护结构包括设置在所述衬底基板上的层间绝缘层、所述第二电极图案和平坦层；所述层间绝缘层包括至少一个第四过孔，所述第二电极图案位于所述至少一个第四过孔中，接触并覆盖所述至少一个第四过孔的边缘，并且延伸到所述平坦层和所述层间绝缘层之间的接触区中。
  12. 根据权利要求1所述的显示面板，其中，所述保护结构包括位于第三电路中的第三保护结构，所述第三保护结构包括依次设置在衬底基板上的所述第三电极图案、平坦层和第三保护层，所述第三电极图案和所述第三保护层分别位于所述平坦层的相对两侧，所述第三电极图案在所述衬底基板上的正投影与所述第三保护层在所述衬底基板上的正投影重叠。
  13. 根据权利要求1至12中任一项所述的显示面板，其中，所述第一电路为玻璃上芯片电路，所述第二电路为柔性印刷电路，所述第三电路为扇出电路。
  14. 根据权利要求2-3、7-10、12中任一项所述的显示面板，其中，所述第一保护层、第二保护层、第三保护层均由透明导电材料制成。
  15. 根据权利要求14所述的显示面板，其中，所述透明导电材料包括氧化铟锡。
  16. 根据权利要求2-3、7-10、12中任一项所述的显示面板，还包括像 素电极图案，其中，所述第一保护层、第二保护层、第三保护层与所述像素电极图案同层设置。
  17. 根据权利要求1所述的显示面板，其中，所述保护结构位于所述第一电路、第二电路和第三电路的每个电路中。
PCT/CN2018/071376 2017-05-12 2018-01-04 显示面板 WO2018205659A1 (zh)

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