WO2018201721A1 - 增强型hfet - Google Patents

增强型hfet Download PDF

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WO2018201721A1
WO2018201721A1 PCT/CN2017/115427 CN2017115427W WO2018201721A1 WO 2018201721 A1 WO2018201721 A1 WO 2018201721A1 CN 2017115427 W CN2017115427 W CN 2017115427W WO 2018201721 A1 WO2018201721 A1 WO 2018201721A1
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layer
gate
dimensional electron
electron gas
electrode
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PCT/CN2017/115427
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English (en)
French (fr)
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王元刚
冯志红
吕元杰
谭鑫
宋旭波
周幸叶
房玉龙
顾国栋
郭红雨
蔡树军
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中国电子科技集团公司第十三研究所
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Priority to US16/610,207 priority Critical patent/US10854741B2/en
Publication of WO2018201721A1 publication Critical patent/WO2018201721A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors

Definitions

  • the present invention relates to the field of semiconductor switching devices, and in particular, to an enhanced HFET.
  • Reference 1 "High-Performance Enhancement-Mode AlGaN/GaN HFETs Using Fluoride-Based Plasma Treatment. IEEE Electron Device Letters", Yong Cai, Yugang Zhou, Kevin J. Chen , and Kei May Lau., 2005, 26(7) In pp.435-437, F plasma treatment is used to realize the shift of the threshold voltage of the device, and the threshold voltage of the device is increased from -4V to 0.9V, realizing an enhanced device.
  • Literature 2 Development and Characterization of Enhanced AlGaN/GaN Trench HFETs.
  • the -123 uses the under-gate trenching technique to increase the threshold voltage of the device from -2.2V to 0.47V.
  • the III-based nitride material-enhanced HFETs use equal-plane channel layers, which are enhanced by grooving, F-ion implantation, and cascading with Si devices (as shown in Figure 1).
  • the damage at the interface is large, the process without damage is difficult, and the threshold value varies significantly with the groove depth; the F injection is unstable, and the switching characteristics of the cascade structure are limited by the Si device.
  • the technical problem to be solved by the present invention is how to provide an enhanced HFET with a large saturation current and an enhanced threshold controllable.
  • an enhanced HFET including an HFET device body, characterized in that there is no channel layer between the drain electrode and the source electrode of the HFET device body.
  • a two-dimensional electron gas region is disposed on the channel layer between the gate electrode and the source electrode and between the gate electrode and the drain electrode, and the channel layer directly under the gate electrode is in a position portion of the two-dimensional electron gas layer or All exist in two-dimensional electron gas.
  • a further technical solution is that the number of the two-dimensional electronic gas zones is one or more.
  • each of the two-dimensional electron-free gas regions has a width ranging from 1 nm to 10 ⁇ m and less than or equal to 10 ⁇ m.
  • each of the two-dimensional electron-free gas regions has a width ranging from 50 nm or more and 800 nm or less.
  • a further technical solution is that the number of the gate electrodes is an integer number of one or more.
  • a further technical solution is that the number of the gate electrodes is an integer greater than one and the length of each gate electrode is equal or unequal.
  • the gate electrode has a topography, a T gate, a TT gate, a TTT gate, a V gate, a U gate, and a Y gate. .
  • a further technical solution is: when a gate electrode is disposed on the HFET device, an insulating dielectric layer is disposed between the gate root and the barrier layer on the underside of the gate electrode, or there is no insulating dielectric layer; when the HFET When more than two gate electrodes are provided on the device, an insulating dielectric layer is disposed between the gate root and the barrier layer on the lower side of the gate electrode, and there is no insulating dielectric layer between the gate root and the barrier layer on the lower side of the gate electrode. Or an insulating dielectric layer is disposed between the gate root on the lower side of the gate electrode and the barrier layer, or there is no insulating dielectric layer between the gate root and the barrier layer on the lower side of the entire gate electrode.
  • the HFET device body comprises a substrate, an upper surface of the substrate layer is provided with a channel layer, and a left side of the upper surface of the channel layer is provided with a source electrode, and an upper surface of the channel layer a drain electrode is disposed on a right side thereof, and a barrier layer is disposed on an upper surface of the channel layer between the source electrode and the drain electrode, and the upper surface of the barrier layer is provided with one or more gate electrodes, and the gate electrode is not provided
  • the upper surface of the barrier layer is provided with a passivation layer; an insulating dielectric layer is disposed between the gate root and the barrier layer on the lower side of the gate electrode, or there is no insulating dielectric layer.
  • a further technical solution is that a part of the upper surface of the barrier layer is further provided with a P-type cap layer for forming a two-dimensional electronic gas zone.
  • the beneficial effects produced by the above technical solution are that there is no two-dimensional electron gas region on the channel layer between the drain electrode and the source electrode of the HFET device body, and the region is a two-dimensional electron gas barrier region, with the gate As the positive forward voltage increases, the barrier width and height decrease continuously. When the device is turned on, no electron tunneling occurs in the 2DG region, and the saturation current is large. The barrier height of the 2DEG region does not affect the device threshold voltage.
  • threshold controllable expected to be used in power electronic devices and digital circuits to increase speed and reduce energy consumption
  • device turn-on and turn-off only need to control a small amount of electron charging and discharging without 2DEG area, switching speed is fast
  • no 2DEG area width has a great influence on the threshold voltage, and the threshold voltage ultra-wide area can be controlled.
  • FIG. 1 is a schematic perspective view of a prior art Cascode GaN HFET
  • FIG. 2 is a schematic structural view of an enhanced HFET according to Embodiment 1 of the present invention.
  • FIG. 3 is an enhanced single-gate GaN prepared by a fluorine treatment process according to Embodiment 2 of the present invention; Schematic diagram of HFET structure;
  • FIG. 4 is a schematic structural view of a three-groove enhanced double-gate GaN HFET according to an embodiment of the present invention
  • FIG. 5 is a schematic structural view of a four-groove enhanced double-gate GaN HFET according to an embodiment of the present invention
  • FIG. 6 is a schematic structural view of a fifth enhanced triple gate GaN HFET according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a conduction band at a barrier layer/channel layer interface when the enhanced HFET gate voltage is 0 V according to the first embodiment of the present invention
  • FIG. 8 is a schematic diagram of a conduction band at a barrier layer/channel layer interface when the enhancement type HFET gate voltage>threshold voltage>0 V according to the first embodiment of the present invention
  • barrier layer 1, barrier layer; 2, channel layer; 3, substrate; 4, source electrode; 5, gate electrode; 6, drain electrode; 7, passivation layer; 8, two-dimensional electron gas; Dielectric layer; 10, P-type cap layer 11, conduction band 12, electron tunneling.
  • an embodiment of the present invention discloses an enhancement type HFET including a HFET device body.
  • the HFET device body includes a substrate 1 having an upper surface provided with a channel layer 2, and a left side of the upper surface of the channel layer 2 is provided with a source electrode 4, and the upper surface of the channel layer 2
  • the drain electrode 6 is provided on the right side.
  • a barrier layer 1 is provided on the upper surface of the channel layer between the source electrode 4 and the drain electrode 6, and a two-dimensional electron gas (2DEG) layer is formed on the channel layer 2 on the lower side of the barrier layer 1.
  • a channel-free layer 2 between the drain electrode 6 and the source electrode 4 is provided with a two-dimensional electron-free gas region (A to A' region in FIG.
  • a two-dimensional electron gas zone is provided on the channel layer 2 between the four. That is to say, the two-dimensional electron gas layer is discontinuous, and is divided by two-dimensional electron gas to the left and right two two-dimensional electron gas regions (B to A region and A' to B' region in Fig. 2).
  • the upper surface of the barrier layer is provided with a gate electrode 5, and the gate electrode 5 is a T-gate.
  • the upper surface of the barrier layer 1 other than the gate electrode 5 is provided with a passivation layer 7, and the channel layer directly under the gate electrode 5 has two-dimensional electron gas at all positions of the two-dimensional electron gas layer.
  • the region is a two-dimensional electron gas barrier region, and the barrier width increases as the gate forward voltage increases.
  • the height is continuously reduced, the device is turned on, electron tunneling can occur in the 2DG-free region (2DEG), and the saturation current is large; the thickness of the barrier layer without the 2DEG region has little influence on the threshold voltage of the device, and the threshold is controlled; Controllable, it is expected to be used in the field of power electronic devices and digital circuits to increase speed and reduce energy consumption; device turn-on and turn-off only need to control a small amount of electron charging and discharging without 2DEG area, and the switching speed is fast; when the device is turned on, there is no 2DEG area width pair The threshold voltage has a large influence, and the threshold voltage ultra-wide area can be controlled.
  • FIG. 7 is a schematic diagram of a conduction band at a barrier layer/channel layer interface when the enhancement type HFET gate voltage is 0 V according to the first embodiment of the present invention
  • FIG. 8 is an enhanced HFET gate voltage> threshold value according to the first embodiment of the present invention
  • an embodiment of the present invention discloses an enhancement type HFET including a HFET device body.
  • the HFET device body includes a substrate 1 having an upper surface provided with a channel layer 2, and a left side of the upper surface of the channel layer 2 is provided with a source electrode 4, and the upper surface of the channel layer 2
  • the drain electrode 6 is provided on the right side.
  • a barrier layer 1 is provided on the upper surface of the channel layer between the source electrode 4 and the drain electrode 6, and a two-dimensional electron gas (2DEG) layer is formed on the channel layer 2 on the lower side of the barrier layer 1.
  • Two non-two-dimensional electron gas regions are provided on the channel layer 2 between the drain electrode 6 and the source electrode 4 (A 1 to A 1 ' region and A to A' region in FIG. 3 ), and no 2DEG region is composed of fluoride ions Injection formation.
  • a two-dimensional electron gas region is provided on the channel layer 2 between the drain electrode 6 and the source electrode 4 outside the two-dimensional electron gas region. That is two-dimensional electron gas layer is not continuous, non-dimensional electron gas is to distinguish the three-dimensional electron gas region (FIG. 3 B to area A 1, A 1 'to A and region A' to B 'region) .
  • An upper portion of the upper surface of the barrier layer is provided with an insulating dielectric layer 9.
  • the upper surface of the insulating dielectric layer 9 is provided with a T-type gate electrode, and the upper surface of the barrier layer 1 outside the gate electrode 5 is provided.
  • a channel layer directly under the gate electrode 5 has a two-dimensional electron gas at a position portion of the two-dimensional electron gas layer.
  • an embodiment of the present invention discloses an enhancement type HFET including a HFET device body.
  • the HFET device body includes a substrate 1 having an upper surface provided with a channel layer 2, and a left side of the upper surface of the channel layer 2 is provided with a source electrode 4, and the upper surface of the channel layer 2
  • the drain electrode 6 is provided on the right side.
  • a barrier layer 1 is provided on the upper surface of the channel layer between the source electrode 4 and the drain electrode 6, and a two-dimensional electron gas (2DEG) layer is formed on the channel layer 2 on the lower side of the barrier layer 1.
  • a channel-free layer 2 between the drain electrode 6 and the source electrode 4 is provided with a two-dimensional electron-free gas region (A to A' region in FIG. 4), and no 2DEG region is formed by the etching barrier layer 1.
  • a two-dimensional electron gas region is disposed on the channel layer 2 between the drain electrode 6 and the source electrode 4 outside the two-dimensional electron gas region, that is, the two-dimensional electron gas layer is discontinuous, and is distinguished by the two-dimensional electron gas.
  • the two-dimensional electron gas layer is discontinuous, and is distinguished by the two-dimensional electron gas.
  • a part of the upper surface of the barrier layer 1 is provided with two gate electrodes 5, the gate electrodes 5 are straight gates, and the widths of the gate electrodes 5 are not equal.
  • a passivation layer 7 is provided on the upper surface of the barrier layer 1 outside the gate electrode 5, and a passivation layer 7 between the gate electrode 5 and the gate electrode 5 is embedded in the etching trench of the barrier layer 1.
  • the channel layer directly under the gate electrode 5 has two-dimensional electron gas at all positions of the two-dimensional electron gas layer.
  • an embodiment of the present invention discloses an enhancement type HFET including a HFET device body.
  • the HFET device body includes a substrate 1 having an upper surface provided with a channel layer 2, and a left side of the upper surface of the channel layer 2 is provided with a source electrode 4, and the upper surface of the channel layer 2
  • the drain electrode 6 is provided on the right side.
  • a barrier layer 1 is provided on the upper surface of the channel layer between the source electrode 4 and the drain electrode 6, and a two-dimensional electron gas (2DEG) layer is formed on the channel layer 2 on the lower side of the barrier layer 1.
  • a channel-free layer 2 between the drain electrode 6 and the source electrode 4 is provided with a two-dimensional electron-free gas region (A to A' region in FIG. 5), and no 2DEG region is formed by self-depletion of the P-type cap layer 10.
  • a two-dimensional electron gas region is disposed on the channel layer 2 between the drain electrode 6 and the source electrode 4 outside the two-dimensional electron gas region, that is, the two-dimensional electron gas layer is discontinuous, and is distinguished by the two-dimensional electron gas.
  • a part of the upper surface of the barrier layer 1 is provided with two gate electrodes 5, which are T-type gates and Y-type gates.
  • a P-type cap layer 10 is provided on the upper surface of the barrier layer 1 between the two gate electrodes 5, and a passivation layer 7 is provided on the upper surface of the barrier layer 1 other than the two gate electrodes 5.
  • the channel layer directly under one of the gate electrodes 5 has two-dimensional electron gas at the position of the two-dimensional electron gas layer, and the channel layer directly under the other gate electrode 5 exists at the position of the two-dimensional electron gas layer. Two-dimensional electronic gas.
  • an embodiment of the present invention discloses an enhancement type HFET including a HFET device body.
  • the HFET device body includes a substrate 1 having an upper surface provided with a channel layer 2, and a left side of the upper surface of the channel layer 2 is provided with a source electrode 4, and the upper surface of the channel layer 2
  • the drain electrode 6 is provided on the right side.
  • a barrier layer 1 is provided on the upper surface of the channel layer between the source electrode 4 and the drain electrode 6, and a two-dimensional electron gas (2DEG) layer is formed on the channel layer 2 on the lower side of the barrier layer 1. It provided no two-dimensional electron gas region (FIG.
  • a to A 1 'and A to area A' region) 2 4 between the drain electrode and the source electrode 6 channel layer no two-dimensional electron
  • the formation method of the gas zone is different, in which the A to A' region is formed by self-depletion of the P-type cap layer 10, and the A 1 to A 1 ' region is formed by fluoride ion treatment.
  • a two-dimensional electron gas region is disposed on the channel layer 2 between the drain electrode 6 and the source electrode 4 outside the two-dimensional electron gas region, that is, the two-dimensional electron gas layer is discontinuous, and is distinguished by the two-dimensional electron gas.
  • a portion of the upper surface of the barrier layer 1 is provided with two gate electrodes 5 and an insulating dielectric layer 9 and a P-type cap layer 10.
  • the upper surface of the insulating dielectric layer 9 is provided with a gate electrode 5; It is a straight gate, a T-gate and a Y-gate.
  • a passivation layer 7 is provided on the upper surface of the barrier layer 1 other than the gate electrode 5 and the upper surface of the P-type cap layer 10.
  • the channel layer directly under the gate electrode 5 has two-dimensional electron gas at all positions of the two-dimensional electron gas layer.
  • the width of each of the 2DEG-free regions is 1 nm or more and 10 ⁇ m or less, and the preferred range is 50 nm or more and 800 nm or less.
  • the 2DEG-free region is formed by other methods listed in the present invention, and the barrier layer 1 is selected from one or more layers of composite materials, etc.
  • the material of the layer 2 is selected from a multilayer composite material, a back barrier structure, a multilayer buffer layer, etc.
  • the substrate is selected from a substrate such as SiC, Si, diamond, sapphire or GaN, or a multilayer composite substrate is selected, and the epitaxial layer is directly epitaxially grown.
  • the shape of the grid is selected from the other shapes listed in the present invention
  • the insulating medium is a single medium or conforms to the medium, etc., but these changes should fall within the protection scope of the claims of the present invention. .

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Abstract

一种增强型HFET，包括HFET器件本体，所述HFET器件本体的漏电极（6）与源电极（4）之间的沟道层（2）上存在无二维电子气区，且栅电极（5）以外的沟道层（2）上存在无二维电子气区，无二维电子气区之外的漏电极（6）与源电极（4）之间的沟道层（2）上设有二维电子气区，且栅电极（5）与源电极（4）之间以及栅电极（5）与漏电极（6）之间的沟道层（2）上均存在二维电子气区，栅电极（5）正下方的沟道层（2）在二维电子气层的位置部分或全部存在二维电子气（8）。所述HFET具有饱和电流大、阈值电压可控性强、响应速度快以及能耗低等优点。

Description

增强型HFET 技术领域
本发明涉及半导体开关器件技术领域，尤其涉及一种增强型HFET。
 背景技术
文献1：《High-Performance Enhancement-Mode AlGaN/GaN HFETs Using Fluoride-Based Plasma Treatment. IEEE Electron Device Letters》, Yong Cai, Yugang Zhou, Kevin J. Chen , and Kei May Lau.，2005, 26(7), pp.435-437中采用F等离子体处理实现了器件阈值电压的转移，器件的阈值电压由-4V提高到0.9V，实现了增强型器件。
文献2：《增强型AlGaN/GaN 槽栅HFET 研制与特性分析》. 郝跃, 王冲, 倪金玉, 冯倩，张进城，毛维.中国科学E辑，39 (1)，2009，pp.119-123中采用栅下挖槽技术将器件的阈值电压从-2.2V提高到了0.47V。
文献3：《Simulation Model Development and Verification for High Voltage GaN HFET in Cascode Structure. Energy Conversion Congress and Exposition》, Zhengyang Liu, Xiucheng Huang, Fred C. Lee, and Qiang Li. ECCE, IEEE, 2013, pp.3587 – 3594中公开了一种Cascode GaN HFET实现增强型，该结构依靠Si器件控制GaN HFET的阈值。
目前基于III族氮化物材料增强型HFET均采用等平面沟道层，通过刻槽、F离子注入以及与Si器件级联（如图1所示）等方式实现增强型，其中刻槽工艺对栅界面处损伤较大，无损伤刻槽工艺难度大，且阈值随槽深变化明显；F注入不稳定，级联结构的开关特性受Si器件限制。
 技术问题
本发明所要解决的技术问题是如何提供一种饱和电流大、增强阈值可控的增强型HFET。
 技术解决方案
为解决上述技术问题，本发明所采取的技术方案是：一种增强型HFET，包括HFET器件本体，其特征在于：所述HFET器件本体的漏电极与源电极之间的沟道层上存在无二维电子气区，且栅电极下方以外的沟道层存在无二维电子气区，无二维电子气区之外的漏电极与源电极之间的沟道层上设有二维电子气区，且栅电极与源电极之间以及栅电极与漏电极之间的沟道层上均设有二维电子气区， 栅电极正下方的沟道层在二维电子气层的位置部分或全部存在二维电子气。
进一步的技术方案在于：所述无二维电子气区的数量为一个以上。
进一步的技术方案在于：每个所述无二维电子气区的宽度范围为大于等于1nm且小于等于10μm。
进一步的技术方案在于：每个所述无二维电子气区的宽度范围为大于等于50nm且小于等于800nm。
进一步的技术方案在于：所述栅电极数量为大于等于1的整数个。
进一步的技术方案在于：所述栅电极的数量为大于1的整数个且每根栅电极的长度相等或者不相等。
进一步的技术方案在于：所述栅电极的形貌为直栅、T型栅、TT型栅、TTT型栅、V型栅、U型栅和Y型栅中的一种或者多种栅的组合。
进一步的技术方案在于：当所述HFET器件上设有一个栅电极时，所述栅电极下侧的栅根与势垒层之间设有绝缘介质层，或者没有绝缘介质层；当所述HFET器件上设有两个以上的栅电极时，部分栅电极下侧的栅根与势垒层之间设有绝缘介质层，部分栅电极下侧的栅根与势垒层之间没有绝缘介质层，或者全部栅电极下侧的栅根与势垒层之间设有绝缘介质层，或者全部栅电极下侧的栅根与势垒层之间没有绝缘介质层。
进一步的技术方案在于：所述HFET器件本体包括衬底，所述衬底层的上表面设有沟道层，所述沟道层上表面的左侧设有源电极，所述沟道层上表面的右侧设有漏电极，源电极与漏电极之间的沟道层的上表面设有势垒层，所述势垒层的上表面设有一个以上的栅电极，所述栅电极之外的势垒层的上表面设有钝化层；所述栅电极下侧的栅根与势垒层之间设有绝缘介质层，或者没有绝缘介质层。
进一步的技术方案在于：所述势垒层的部分上表面还设有P型帽层，用于形成无二维电子气区。
 有益效果
采用上述技术方案所产生的有益效果在于：所述HFET器件本体的漏电极与源电极之间的沟道层上存在无二维电子气区，该区为二维电子气势垒区，随着栅极正向电压的增大，势垒宽度和高度不断降低，器件开启时，无二维电子气（2DEG）区可发生电子隧穿，饱和电流大；无2DEG区的势垒高度对器件阈值电压影响较小，增强阈值可控性；阈值可控，有望用于电力电子器件和数字电路，提高速度以及降低能耗；器件开启和关断仅需控制无2DEG区少量电子充放电，开关速度快；器件开启时，无2DEG区宽度对阈值电压影响大，可实现阈值电压超宽区域可控。
 附图说明
图1是现有技术中Cascode GaN HFET的立体结构示意图；
图2是本发明实施例一所述增强型HFET的结构示意图；
图3是本发明实施例二通过氟处理工艺制备的增强型单栅GaN HFET结构示意图；
图4是本发明实施例三凹槽增强型双栅GaN HFET结构示意图；
图5是本发明实施例四凹槽增强型双栅GaN HFET结构示意图；
图6是本发明实施例五增强型三栅GaN HFET结构示意图；
图7是本发明实施例一所述增强型HFET栅压=0V时的势垒层/沟道层界面处的导带示意图；
图8是本发明实施例一所述增强型HFET栅压＞阈值电压>0V时的势垒层/沟道层界面处的导带示意图；
其中：1、势垒层；2、沟道层；3、衬底；4、源电极；5、栅电极；6、漏电极；7、钝化层；8、二维电子气；9、绝缘介质层；10、P型帽层 11、导带12、电子隧穿。
 本发明的最佳实施方式
下面结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。
实施例一
如图2所示，本发明实施例公开了一种增强型HFET，包括HFET器件本体。所述HFET器件本体包括衬底1，所述衬底1的上表面设有沟道层2，所述沟道层2上表面的左侧设有源电极4，所述沟道层2上表面的右侧设有漏电极6。源电极4与漏电极6之间的沟道层的上表面设有势垒层1，势垒层1下侧的沟道层2上形成有二维电子气（2DEG）层。漏电极6与源电极4之间的沟道层2上设有一个无二维电子气区（图2中A至A＇区），无二维电子气区之外的漏电极6与源电极4之间的沟道层2上设有二维电子气区。也就是说二维电子气层不连续，被无二维电子气区分为了左右两个二维电子气区（图2中B至A区以及A＇至B＇区）。所述势垒层的上表面设有一个栅电极5，栅电极5为T型栅。所述栅电极5之外的势垒层1的上表面设有钝化层7，所述栅电极5正下方的沟道层在二维电子气层的位置全部存在二维电子气。
所述HFET器件本体的漏电极与源电极之间的沟道层上存在无二维电子气区，该区为二维电子气势垒区，随着栅极正向电压的增大，势垒宽度和高度不断降低，器件开启，无二维电子气（2DEG）区可发生电子隧穿，饱和电流大；无2DEG区的势垒层厚度对器件阈值电压影响较小，增强阈值可控性；阈值可控，有望用于电力电子器件领域以及数字电路，提高速度以及降低能耗；器件开启和关断仅需控制无2DEG区少量电子充放电，开关速度快；器件开启时，无2DEG区宽度对阈值电压影响大，可实现阈值电压超宽区域可控。
图7是本发明实施例一所述增强型HFET栅压=0V时的势垒层/沟道层界面处的导带示意图；图8是本发明实施例一所述增强型HFET栅压＞阈值电压>0V时的势垒层/沟道层界面处的导带示意图；正栅压越大，势垒高度和宽度降低，电子越容易发生隧穿。
实施例二
如图3所示，本发明实施例公开了一种增强型HFET，包括HFET器件本体。所述HFET器件本体包括衬底1，所述衬底1的上表面设有沟道层2，所述沟道层2上表面的左侧设有源电极4，所述沟道层2上表面的右侧设有漏电极6。源电极4与漏电极6之间的沟道层的上表面设有势垒层1，势垒层1下侧的沟道层2上形成有二维电子气（2DEG）层。漏电极6与源电极4之间的沟道层2上设有两个无二维电子气区（图3中A 1至A 1＇区以及A至A＇区），无2DEG区由氟离子注入形成。
无二维电子气区之外的漏电极6与源电极4之间的沟道层2上设有二维电子气区。也就是说二维电子气层不连续，被无二维电子气区分为了三个二维电子气区（图3中B至A 1区、A 1＇至A区以及A＇至B＇区）。所述势垒层的部分上表面设有绝缘介质层9，所述绝缘介质层9的上表面设有一个T型栅电极，所述栅电极5之外的势垒层1的上表面设有钝化层7。所述栅电极5正下方的沟道层在二维电子气层的位置部分存在二维电子气。
实施例三
如图4所示，本发明实施例公开了一种增强型HFET，包括HFET器件本体。所述HFET器件本体包括衬底1，所述衬底1的上表面设有沟道层2，所述沟道层2上表面的左侧设有源电极4，所述沟道层2上表面的右侧设有漏电极6。源电极4与漏电极6之间的沟道层的上表面设有势垒层1，势垒层1下侧的沟道层2上形成有二维电子气（2DEG）层。漏电极6与源电极4之间的沟道层2上设有一个无二维电子气区（图4中A至A＇区），无2DEG区由刻蚀势垒层1形成。
无二维电子气区之外的漏电极6与源电极4之间的沟道层2上设有二维电子气区，也就是说二维电子气层不连续，被无二维电子气区分为了两个二维电子气区（图4中B至A区以及A＇至B＇区）。所述势垒层1的部分上表面设有两个栅电极5，所述栅电极5为直栅，且栅电极5的宽度不相等。所述栅电极5之外的势垒层1的上表面设有钝化层7，且栅电极5与栅电极5之间的钝化层7嵌入到势垒层1的刻蚀槽内。所述栅电极5正下方的沟道层在二维电子气层的位置全部存在二维电子气。
实施例四
如图5所示，本发明实施例公开了一种增强型HFET，包括HFET器件本体。所述HFET器件本体包括衬底1，所述衬底1的上表面设有沟道层2，所述沟道层2上表面的左侧设有源电极4，所述沟道层2上表面的右侧设有漏电极6。源电极4与漏电极6之间的沟道层的上表面设有势垒层1，势垒层1下侧的沟道层2上形成有二维电子气（2DEG）层。漏电极6与源电极4之间的沟道层2上设有一个无二维电子气区（图5中A至A＇区），无2DEG区由P型帽层10自耗尽形成。
无二维电子气区之外的漏电极6与源电极4之间的沟道层2上设有二维电子气区，也就是说二维电子气层不连续，被无二维电子气区分为了两个二维电子气区（图5中B至A区以及A＇至B＇区）。所述势垒层1的部分上表面设有两个栅电极5，所述栅电极5为T型栅和Y型栅。两个栅电极5之间的势垒层1的上表面设有P型帽层10，两个栅电极5以外的势垒层1的上表面设有钝化层7。其中的一个栅电极5的正下方的沟道层在二维电子气层的位置全部存在二维电子气，另一个栅电极5的正下方的沟道层在二维电子气层的位置部分存在二维电子气。
实施例五
如图6所示，本发明实施例公开了一种增强型HFET，包括HFET器件本体。所述HFET器件本体包括衬底1，所述衬底1的上表面设有沟道层2，所述沟道层2上表面的左侧设有源电极4，所述沟道层2上表面的右侧设有漏电极6。源电极4与漏电极6之间的沟道层的上表面设有势垒层1，势垒层1下侧的沟道层2上形成有二维电子气（2DEG）层。漏电极6与源电极4之间的沟道层2上设有两个无二维电子气区（图6中A 1至A 1＇区以及A至A＇区），两个无二维电子气区的形成方法不同，其中A至A＇区由P型帽层10自耗尽形成，A 1至A 1＇区由氟离子处理形成。
无二维电子气区之外的漏电极6与源电极4之间的沟道层2上设有二维电子气区，也就是说二维电子气层不连续，被无二维电子气区分为了三个二维电子气区（图6中的B至A 1区、A 1＇至A区以及A＇至B＇区）。所述势垒层1的部分上表面设有两个栅电极5和绝缘介质层9以及P型帽层10，所述绝缘介质层9的上表面设有一个栅电极5；三个栅电极分别为直栅、T型栅和Y型栅。所述栅电极5之外的势垒层1的上表面以及P型帽层10的上表面设有钝化层7。所述栅电极5正下方的沟道层在二维电子气层的位置全部存在二维电子气。
需要说明的是，实施例一至实施例五中，每个所述无2DEG的区宽度范围为大于等于1nm且小于等于10μm，较优的范围为大于等于50nm且小于等于800nm。此外，根据上述实施例的描述，本领域的技术人员还可做出一些显而易见的改变，例如无2DEG区由本发明列举的以外方法形成，势垒层1选用一种或多层复合材料等，沟道层2材料选用多层复合材料、背势垒结构、多层缓冲层等结构，衬底选用SiC、Si、金刚石、蓝宝石、GaN等衬底，或者选用多层复合衬底，外延层直接外延到衬底上或者转移到其他衬底上，栅形貌选用本发明列举的以外形状，绝缘介质为单一介质或者符合介质等改变，但这些改变均应落入本发明权利要求的保护范围之内。

Claims (10)

  1. 一种增强型HFET，包括HFET器件本体，其特征在于：所述HFET器件本体的漏电极（6）与源电极（4）之间的沟道层（2）上存在无二维电子气区，且栅电极（5）下方以外的沟道层（2）存在无二维电子气区，无二维电子气区之外的漏电极（6）与源电极（4）之间的沟道层上设有二维电子气区，且栅电极（5）与源电极（4）之间以及栅电极（5）与漏电极（6）之间的沟道层（2）上均设有二维电子气区，栅电极（5）正下方的沟道层（2）在二维电子气层的位置部分或全部存在二维电子气（8）。
  2. 如权利要求1所述的增强型HFET，其特征在于：所述无二维电子气区的数量为一个以上。
  3. 如权利要求1所述的增强型HFET，其特征在于：每个所述无二维电子气区的宽度范围为大于等于1nm且小于等于10μm。
  4. 如权利要求3所述的增强型HFET，其特征在于：每个所述无二维电子气区的宽度范围为大于等于50nm且小于等于800nm。
  5. 如权利要求1所述的增强型HFET，其特征在于：所述栅电极（5）的数量为大于等于1的整数个。
  6. 如权利要求1所述的增强型HFET，其特征在于：所述栅电极（5）的数量为大于1的整数个且每根栅电极（5）的长度相等或者不相等。
  7. 如权利要求1所述的增强型HFET，其特征在于：所述栅电极（5）的形貌为直栅、T型栅、TT型栅、TTT型栅、V型栅、U型栅和Y型栅中的一种或者多种栅的组合。
  8. 如权利要求1所述的增强型HFET，其特征在于：当所述HFET器件上设有一个栅电极（5）时，所述栅电极（5）下侧的栅根与势垒层（1）之间设有绝缘介质层（9），或者没有绝缘介质层（9）；当所述HFET器件上设有两个以上的栅电极（5）时，部分栅电极（5）下侧的栅根与势垒层之间设有绝缘介质层（9），部分栅电极（5）下侧的栅根与势垒层（1）之间没有绝缘介质层（9），或者全部栅电极（5）下侧的栅根与势垒层（1）之间设有绝缘介质层（9），或者全部栅电极（5）下侧的栅根与势垒层（1）之间没有绝缘介质层（9）。
  9. 如权利要求1所述的增强型HFET，其特征在于：所述HFET器件本体包括衬底（3），所述衬底层（3）的上表面设有沟道层（2），所述沟道层（2）上表面的左侧设有源电极（4），所述沟道层（2）上表面的右侧设有漏电极（6），源电极（4）与漏电极（6）之间的沟道层（2）的上表面设有势垒层（1），所述势垒层（1）的上表面设有一个以上的栅电极（5），所述栅电极（5）之外的势垒层（1）的上表面设有钝化层（7）；所述栅电极（5）下侧的栅根与势垒层之间设有绝缘介质层（9），或者没有绝缘介质层（9）。
  10. 如权利要求9所述的增强型HFET，其特征在于：所述势垒层（1）的部分上表面还设有P型帽层，用于形成无二维电子气区。
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