WO2018196399A1 - 显示基板及其制造方法和显示装置 - Google Patents

显示基板及其制造方法和显示装置 Download PDF

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WO2018196399A1
WO2018196399A1 PCT/CN2017/116141 CN2017116141W WO2018196399A1 WO 2018196399 A1 WO2018196399 A1 WO 2018196399A1 CN 2017116141 W CN2017116141 W CN 2017116141W WO 2018196399 A1 WO2018196399 A1 WO 2018196399A1
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layer
substrate
light shielding
insulating
amorphous silicon
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PCT/CN2017/116141
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English (en)
French (fr)
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姚琪
曹占锋
张锋
王久石
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京东方科技集团股份有限公司
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Priority to US16/070,271 priority Critical patent/US11201120B2/en
Publication of WO2018196399A1 publication Critical patent/WO2018196399A1/zh

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    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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Definitions

  • Embodiments of the present disclosure generally relate to the field of display technologies, and in particular, to a display substrate, a method of manufacturing the display substrate, and a display device including the display substrate.
  • TFTs Thin Film Transistors
  • the active layer of TFT generally uses amorphous silicon (a-Si) material with good stability and processability, but due to its own defects in amorphous silicon, such as low on-state current, low mobility, and poor stability. Etc., its application in many fields is limited.
  • Low Temperature Poly-Silicon (LTPS) technology emerged.
  • the display device using the LTPS process has a high electron mobility, can effectively reduce the area of the TFT to increase the aperture ratio of the pixel, and can reduce the power consumption and the production cost while enhancing the display brightness, so that it has become a display field.
  • Research hotspots research hotspots.
  • the present disclosure has been made in order to overcome or eliminate at least one of the problems and disadvantages of the prior art.
  • a display substrate including:
  • An active layer of a thin film transistor disposed on the base substrate, the orthographic projection of the active layer on the base substrate along a thickness direction of the base substrate is located along a thickness direction of the base substrate of the light shielding layer Within the orthographic projection on the base substrate, and the light shielding layer includes an amorphous silicon layer having dopant ions.
  • the display substrate further includes:
  • a buffer layer disposed on the base substrate
  • the second insulating layer is disposed on the light shielding layer
  • the light shielding layer is located between the first insulating layer and the second insulating layer, and the second insulating layer is located between the light shielding layer and the active layer.
  • the buffer layer, the active layer, the first insulating layer, the light shielding layer, and the second insulating layer are positive on the substrate substrate along a thickness direction of the substrate substrate.
  • the projections are completely overlapping.
  • the thickness of the light shielding layer is
  • the thickness of the pattern of the light shielding layer is
  • the light shielding layer comprises an amorphous silicon layer doped with boron ions or phosphorus ions.
  • the active layer comprises a polysilicon material.
  • the buffer layer comprises a silicon nitride material.
  • the thickness of the buffer layer is
  • the first insulating layer and the second insulating layer comprise a silicon oxide material.
  • the thickness of the first insulating layer is The thickness of the second insulating layer is
  • a display device comprising the display substrate according to any of the above embodiments.
  • a method of manufacturing a display substrate including:
  • the material layer and the semiconductor material layer are patterned to form a first insulating layer, the light shielding layer, the second insulating layer, and the active layer, respectively.
  • the step of forming a buffer layer, a first insulating material layer, a light shielding layer, a second insulating material layer, and a semiconductor material layer on the base substrate includes:
  • the second amorphous silicon layer is annealed to convert the second amorphous silicon layer into a polysilicon layer to serve as the semiconductor material layer.
  • the steps of forming the first insulating layer, the light shielding layer, the second insulating layer and the active layer using the same mask include:
  • the first insulating material layer, the ion-doped amorphous silicon layer, the second insulating material layer and the semiconductor material layer are etched by an etching process using the pattern of the formed photoresist as a mask to form a first An insulating layer, a light shielding layer, a second insulating layer, and an active layer;
  • the etching rates of the first insulating material layer and the second insulating material layer are approximately the same when etching the first insulating material layer and the second insulating material layer.
  • the step of ion doping the first amorphous silicon layer comprises:
  • Boron ions or phosphorus ions are implanted into the first amorphous silicon layer using ion implantation process parameters including a voltage of 30 KV and an ion implantation dose of 5E14 to 9E14.
  • the first insulating material layer and the second insulating material layer are formed of silicon oxide.
  • FIG. 1 is a partial cross-sectional view of a display substrate in accordance with an embodiment of the present disclosure
  • 2 is a graph showing light shielding properties of light shielding layers having different thicknesses for light of different wavelength ranges
  • 3 is a graph showing the effect of ion doping on the shading characteristics of light shielding layers for light of different wavelength ranges
  • FIG. 4 is a schematic cross-sectional view of a display substrate in accordance with an embodiment of the present disclosure
  • FIG. 5 is a flowchart of a method of manufacturing a display substrate according to an embodiment of the present disclosure
  • FIG. 6 is a flow chart of a method of fabricating a display substrate in accordance with another embodiment of the present disclosure.
  • FIG. 7 is a schematic cross-sectional view showing a structure formed by several steps of a method of manufacturing a display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional view showing a structure formed by another step of a method of manufacturing a display substrate according to an embodiment of the present disclosure.
  • the pattern of the light shielding layer has been formed before the amorphous silicon is converted into polysilicon (p-Si).
  • the pattern of the formed light shielding layer forms a certain slope angle at the edge, so that the thickness of the light shielding layer itself and the slope angle at the edge of the pattern affect the crystallization effect of the subsequent polysilicon.
  • FIG. 1 shows a partial schematic view of a display substrate in accordance with one embodiment of the present disclosure.
  • the display substrate can be an array substrate.
  • the display substrate may include a base substrate 10, a light shielding layer 6 disposed on the base substrate 10, and an active layer 12 of a thin film transistor disposed on the base substrate 10.
  • the position of the light shielding layer 6 and the active layer 12 on the base substrate 10 corresponds to block the irradiation of the active layer from external light.
  • the orthographic projection of the active layer 12 in a direction perpendicular to the main surface of the substrate substrate (ie, the thickness direction of the substrate substrate) on the substrate substrate 10 is located in the substrate along the light shielding layer 6 in the direction Inside the orthographic projection on 10.
  • the orthographic projections of the light shielding layer 6 and the active layer 12 on the base substrate 10 in a direction perpendicular to the main surface of the base substrate ie, the thickness direction of the base substrate
  • the light shielding layer 6 can prevent the light from the backlight from illuminating the back channel region of the TFT located in the active layer, thereby avoiding leakage current generated by the strong light of the backlight directly illuminating the back channel.
  • the display substrate may further include: a buffer layer 2 disposed on the base substrate 10; a first insulating layer 4 disposed on the first insulating layer On the buffer layer 2; and a second insulating layer 8, the second insulating layer is disposed on the light shielding layer 6.
  • the light shielding layer 6 is disposed on the first insulating layer 4, that is, the light shielding layer 6 is located between the first insulating layer 4 and the second insulating layer 8, and the active layer 12 is disposed on the second insulating layer 8, that is, the second The insulating layer 8 is located between the light shielding layer 6 and the active layer 12. That is, the buffer layer 2, the first insulating layer 4, the light shielding layer 6, the second insulating layer 8, and the active layer 12 are stacked in this order from the bottom to the top on the base substrate 10.
  • the light shielding layer 6 is formed of amorphous silicon (a-Si).
  • a-Si amorphous silicon
  • the active layer and the corresponding light shielding layer can be formed by using only the same mask (that is, by one patterning process), and the metal substrate is additionally used under the active layer.
  • the technical solution of forming a light shielding layer by a mask can reduce a mask process, thereby simplifying the manufacturing process of the display substrate. A manufacturing process for forming an active layer and a light shielding layer by one patterning process will be described in detail below.
  • the inventors further studied the light-shielding characteristics of the amorphous silicon material layer from various aspects through experiments.
  • the spectral distribution of visible light is shown in the following table. Since the light emitted by the backlight is mainly visible light, the embodiment shown in FIG. 2 mainly shows the transmission characteristics of the light shielding layer of different thicknesses to visible light.
  • the amorphous silicon is doped by ion implantation or the like, and the impurity level is introduced in the band gap, which is equivalent to reducing the optical band gap of the amorphous silicon, that is, the light having a wavelength greater than 580 nm (the energy is small).
  • the light is easily absorbed, and therefore, the absorption of light having a wavelength of 580 nm or more by the ion-doped amorphous silicon is enhanced, resulting in a decrease in light transmittance.
  • the light shielding effect of the light shielding layer can be further improved, and in particular, the light shielding effect of the light shielding layer on visible light in the medium and long wavelength range can be improved.
  • the active layer 12 may be formed of a polysilicon material (p-Si, especially a low temperature polysilicon (LTPS) material).
  • p-Si polysilicon material
  • LTPS low temperature polysilicon
  • the manufacturing process of LTPS thin film transistors is complicated, and generally requires 9 to 11 patterning processes.
  • TFTs thin film transistors
  • the top gate structure is superior to some basic properties such as mobility, threshold voltage, and S value (sub-threshold slope).
  • the bottom gate structure, so the top gate structure is the mainstream structure of the LTPSTFT.
  • the TFT of the top gate structure it is usually required to provide a light shielding layer to prevent the strong light of the backlight from directly illuminating the back channel to generate a leakage current.
  • a light shielding layer to prevent the strong light of the backlight from directly illuminating the back channel to generate a leakage current.
  • the manufacturing method according to the embodiment of the present disclosure can also improve the polysilicon in the LTPS TFT. Crystallization effect.
  • the buffer layer 2 may be formed of silicon nitride.
  • the buffer layer 2 formed of silicon nitride can block ions (for example, Na+, etc.) in the substrate substrate 10 from entering the layers above the buffer layer 2.
  • the first insulating layer 4 and the second insulating layer 8 may be composed of materials having the same or approximately the same etching rate.
  • the first insulating layer 4 and the second insulating layer 8 may each be formed of silicon oxide.
  • the etching rates of the two layers can be controlled to be the same or approximately the same, so as to adjust the slope angle of one etching, thereby avoiding "falling" Poor structure such as trapezoid.
  • the thickness of the buffer layer 2 can be The thickness of the first insulating layer 4 may be The thickness of the second insulating layer case 8 may be By matching the material and thickness of the buffer layer, the first insulating layer and the second insulating layer, the etching rate of each layer can be matched while minimizing the etching difficulty, thereby avoiding undesirable structures such as "inverted trapezoid", thereby ensuring A good crystallization effect is achieved when the subsequent a-Si is converted to p-Si.
  • the buffer layer 2 may be formed of silicon nitride, and the first insulating layer 4 and the second insulating layer 8 may be formed of silicon oxide, and by such a combination of materials, it is ensured that the subsequent a-Si transition to p- A good crystallization effect is achieved when Si is used.
  • FIG. 4 shows a schematic diagram of a display substrate in accordance with an embodiment of the present disclosure.
  • the display substrate includes: a base substrate 10; a buffer layer 2 disposed on the base substrate 10; a first insulating layer 4 disposed on the buffer layer 2; and a first insulating layer 4 disposed on the first insulating layer 4.
  • a light shielding layer 6 a light shielding layer 6; a second insulating layer 8 disposed on the light shielding layer 6; an active layer 12 disposed on the second insulating layer 8; a gate insulating layer 14 overlying the active layer 12; and a gate insulating layer 14 a gate electrode 18 and a connection sub-electrode 262 electrically connected to the common electrode; an interlayer dielectric layer 16 formed on the base substrate and covering the gate electrode 18 and the connection sub-electrode 262; a source disposed on the interlayer dielectric layer 16
  • the drain 20, the source and the drain 20 are electrically connected to the active layer 12 through vias 202 formed in the interlayer dielectric layer 16, respectively; and the planarization layer 24 is disposed on the source and drain electrodes 20 and the interlayer dielectric layer 16.
  • a common electrode 26 disposed on the planarization layer 24, the common electrode 26 being electrically connected to the connection sub-electrode 262 through a via 161 formed in the interlayer dielectric layer 16; a passivation layer 28 disposed on the common electrode 26; On the pixel electrode 30 on the passivation layer 28, the pixel electrode 30 is electrically connected to the drain electrode 20 through a via hole 281 formed in the passivation layer 28.
  • the active layer 12 may be formed of low temperature polysilicon; in the embodiment illustrated in FIG. 4, one TFT of the display substrate includes two gates 18, ie, forms a dual gate structure.
  • FIG. 4 is only for showing the overall structure of the display substrate according to an embodiment of the present disclosure, and is not intended to limit the present disclosure. It can be understood that the display substrate according to an embodiment of the present disclosure may have other structures.
  • a method of manufacturing a display substrate is also provided, as shown in FIG.
  • a base substrate is provided, which may be, for example, a glass substrate or other transparent substrate.
  • a light shielding layer is formed on the base substrate, and as described above, the light shielding layer may be formed of an ion doped amorphous silicon layer.
  • an active layer is formed on the base substrate, The light shielding layer corresponds to a position of the active layer on the base substrate; for example, an orthographic projection of the active layer on the base substrate is located in an orthographic projection of the light shielding layer on the substrate substrate or coincides with the two
  • the active layer may be formed of polysilicon.
  • a method of manufacturing a display substrate is also provided, as shown in FIG. 6.
  • a base substrate is provided.
  • a buffer layer is formed on the base substrate.
  • a first insulating material layer is formed on the buffer layer.
  • a light shielding material layer is formed on the first insulating layer, and the light shielding material layer may be formed of amorphous silicon or ion doped amorphous silicon.
  • a second insulating material layer is formed on the light shielding material layer.
  • a layer of semiconductor material is formed on the second layer of insulating material, which may be formed of polysilicon transformed by amorphous silicon.
  • the first insulating material layer, the light shielding material layer, the second insulating material layer, and the semiconductor material layer are processed by the same mask to form a first insulating layer, a light shielding layer, a second insulating layer, and an active layer, respectively.
  • the light shielding layer may be formed of amorphous silicon (a-Si).
  • a-Si amorphous silicon
  • the same mask can be used (ie, by one patterning process) to form the active layer and the light shielding layer, and the same mask is used instead of the metal layer as the substrate under the active layer.
  • the technical solution of forming the light shielding layer can reduce one mask process, thereby simplifying the manufacturing process of the display substrate.
  • the light shielding layer is first formed by one patterning process, and then the active layer is formed by another patterning process, and a certain slope is formed at the edge of the pattern of the light shielding layer formed by the previous patterning process.
  • the thickness of the light-shielding layer itself and the slope angle at the edge of the pattern affect the crystallization of the subsequent polysilicon.
  • the light shielding layer and the active layer are formed only by the same mask, and the above-mentioned crystallization effect is not present. Therefore, the manufacturing method according to the embodiment of the present disclosure can further improve the crystal of the polysilicon. Effect.
  • FIG. 7 showing a structure of a display substrate formed in an exemplary step.
  • a buffer layer 2 As shown in FIG. 7, a buffer layer 2, a first insulating material layer 4', a first amorphous silicon layer 6', a second insulating material layer 8', and a second amorphous are sequentially formed on the base substrate 10 from bottom to top. Silicon layer 12'.
  • the buffer layer 2 may be formed of silicon nitride (SiNx), and one or both of the first insulating material layer 4' and the second insulating material layer 8' may be formed of silicon oxide (SiO2).
  • the above layers may be formed on the base substrate 10 by deposition.
  • the light shielding layer can be made better.
  • Ions such as boron ions or phosphorus ions
  • the present disclosure is not limited to using an ion implantation process to form a light shielding layer.
  • other processes such as a CVD doping process, may be employed to dope ions into the first amorphous silicon layer. Thereby, the light shielding layer of the embodiment of the present disclosure is formed.
  • first insulating material layer 4' the first amorphous silicon layer 6' with implanted ions, the second insulating material layer 8, and the second amorphous silicon layer 12' are processed by the same mask to form respectively.
  • the first insulating layer 4, the light shielding layer 6, the second insulating layer 8, and the active layer 12 are shown in FIG.
  • the step of forming the first insulating layer, the light shielding layer, the second insulating layer, and the active layer by using the same mask may include:
  • a pattern of the photoresist 40 is formed on the second amorphous silicon layer 12' through the mask 50 as shown in FIG. 8;
  • the first insulating material layer 4', the first amorphous silicon layer 6', the second insulating material layer 8', and the second amorphous silicon layer 12' are subjected to an etching process. Etching to form the first insulating layer 4, the light shielding layer 6, the second insulating layer 8, and the active layer 12, respectively (as shown in FIG. 1);
  • the photoresist 40 is stripped.
  • the etching process performed on the first insulating material layer, the light shielding material layer or the first amorphous silicon layer, the second insulating material layer, and the semiconductor material layer or the second amorphous silicon layer is
  • the pattern of the formed photoresist is used as a mask or the pattern of the formed photoresist is used as a mask, so that a mask corresponding to the mask for forming the photoresist can be used to complete the A patterning process of an insulating material layer, a light shielding material layer or a first amorphous silicon layer, a second insulating material layer, and a semiconductor material layer or a second amorphous silicon layer.
  • the light shielding layer is formed under the active layer, in other embodiments, the light shielding layer may also be formed over the active layer, for example, the light shielding layer may be It is formed over the TFT structure including the active layer, or the light shielding layer may be simultaneously formed above and below the active layer.
  • the same mask layer (ie, by one patterning process) may be used to form the active layer and the corresponding light shielding layer, with respect to the metal under the active layer
  • a mask process can be reduced, which simplifies the manufacturing process of the display substrate and saves manufacturing costs, and at the same time ensures that the amorphous silicon is converted into a subsequent process. Crystallization effect in polycrystalline silicon.
  • the light shielding effect of the light shielding layer can be further improved.

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Abstract

提供一种显示基板，包括：衬底基板(10)；设置在衬底基板上的遮光层(6)；和设置在衬底基板上的薄膜晶体管的有源层(12)；有源层沿衬底基板的厚度方向在衬底基板上的正投影位于遮光层沿衬底基板的厚度方向在衬底基板上的正投影内，并且遮光层包括具有掺杂离子的非晶硅层。还提供一种显示基板的制造方法和包括该显示基板的显示装置。

Description

显示基板及其制造方法和显示装置
本申请主张在2017年4月28日在中国专利局提交的中国专利申请No.201710299861.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开的实施例一般地涉及显示技术领域，尤其涉及一种显示基板、显示基板的制造方法以及包括该显示基板的显示装置。
背景技术
目前，在各种显示装置的显示基板中，薄膜晶体管(Thin Film Transistor，TFT)被大量使用。TFT的有源层一般使用稳定性和加工性较好的非晶硅(a-Si)材料，但是，由于非晶硅本身自有的缺陷问题，如开态电流低、迁移率低、稳定性差等，使它在很多领域的应用受到了限制。为了弥补非晶硅本身缺陷，扩大在相关领域的应用，低温多晶硅(Low Temperature Poly-Silicon，LTPS)技术应运而生。采用LTPS工艺的显示装置具有较高的电子迁移率、能够有效减小TFT的面积以提升像素的开口率，并且在增强显示亮度的同时能够降低功耗及生产成本，所以，它已成为显示领域的研究热点。
发明内容
为了克服或消除现有技术存在的问题和缺陷中的至少一种，提出了本公开。
根据本公开的一个方面，提供一种显示基板，包括：
衬底基板；
设置在所述衬底基板上的遮光层；和
设置在所述衬底基板上的薄膜晶体管的有源层，所述有源层沿衬底基板的厚度方向在所述衬底基板上的正投影位于所述遮光层沿衬底基板的厚度方向在所述衬底基板上的正投影内，并且，所述遮光层包括具有掺杂离子的非晶硅层。
根据一些实施例，该显示基板还包括：
缓冲层，该缓冲层设置在衬底基板上；
第一绝缘层，该第一绝缘层设置在缓冲层上；和
第二绝缘层，该第二绝缘层设置在遮光层上，
所述遮光层位于所述第一绝缘层和第二绝缘层之间，并且第二绝缘层位于所述遮光层和所述有源层之间。
根据一些实施例，所述缓冲层、所述有源层、所述第一绝缘层、所述遮光层和所述第二绝缘层沿衬底基板的厚度方向在所述衬底基板上的正投影完全重叠。
根据一些实施例，所述缓冲层、第一绝缘层、遮光层、第二绝缘层和有源层从下至上依次堆叠于所述衬底基板上。
根据一些实施例，所述遮光层的厚度为
Figure PCTCN2017116141-appb-000001
根据一些实施例，所述遮光层的图案的厚度为
Figure PCTCN2017116141-appb-000002
根据一些实施例，所述遮光层包括掺杂有硼离子或磷离子的非晶硅层。
根据一些实施例，所述有源层包括多晶硅材料。
根据一些实施例，所述缓冲层包括氮化硅材料。
根据一些实施例，所述缓冲层的厚度为
Figure PCTCN2017116141-appb-000003
根据一些实施例，所述第一绝缘层和所述第二绝缘层包括氧化硅材料。
根据一些实施例，所述第一绝缘层的厚度为
Figure PCTCN2017116141-appb-000004
所述第二绝缘层的厚度为
Figure PCTCN2017116141-appb-000005
根据本公开的另一方面，还提供一种显示装置，包括根据上述任一实施例中所述的显示基板。
根据本公开的又一方面，还提供一种显示基板的制造方法，包括：
提供衬底基板；
提供衬底基板；以及
在衬底基板上形成遮光层和薄膜晶体管的有源层，使得所述有源层沿衬底基板的厚度方向在所述衬底基板上的正投影位于所述遮光层沿衬底基板的厚度方向在所述衬底基板上的正投影内并且，所述遮光层由经离子掺杂的非晶硅层形成。
根据一些实施例，所述方法还包括：
在所述衬底基板上形成缓冲层、第一绝缘材料层、第二绝缘材料层和半导体材料层；和
采用同一个掩模版对第一绝缘材料层、经离子掺杂的非晶硅层、第二绝缘 材料层和半导体材料层进行构图工艺，以分别形成第一绝缘层、所述遮光层、第二绝缘层和所述有源层。
根据一些实施例，在所述衬底基板上形成缓冲层、第一绝缘材料层、遮光层、第二绝缘材料层和半导体材料层的步骤包括：
在衬底基板上形成缓冲层；
在缓冲层上形成第一绝缘材料层；
在第一绝缘材料层上形成第一非晶硅层；
在第一非晶硅层上形成第二绝缘材料层；
在第二绝缘材料层上形成第二非晶硅层；
对第一非晶硅层进行离子掺杂，并对离子掺杂后的第一非晶硅层进行退火处理，以形成遮光层；和
对所述第二非晶硅层进行退火处理，将所述第二非晶硅层转化为多晶硅层，以作为所述半导体材料层。
根据一些实施例，采用同一个掩膜板形成第一绝缘层、遮光层、第二绝缘层和有源层步骤包括：
通过掩膜板在所述半导体材料层上形成光刻胶的图案；
以所形成光刻胶的图案为掩膜，通过刻蚀工艺对第一绝缘材料层、经离子掺杂的非晶硅层、第二绝缘材料层和半导体材料层进行刻蚀，以分别形成第一绝缘层、遮光层、第二绝缘层和有源层；和
剥离光刻胶。
根据一些实施例，在对所述第一绝缘材料层和所述第二绝缘材料层进行刻蚀时，保持第一绝缘材料层和第二绝缘材料层的刻蚀速率近似相同。
根据一些实施例，对第一非晶硅层进行离子掺杂的步骤包括：
采用包括30KV的电压和5E14～9E14的离子注入剂量的离子注入工艺参数将硼离子或磷离子注入所述第一非晶硅层中。
根据一些实施例，所述缓冲层由氮化硅形成。
根据一些实施例，所述第一绝缘材料层和所述第二绝缘材料层由氧化硅形成。
附图说明
通过下文中参照附图对本公开所作的描述，本公开的其它目的和优点将显 而易见，并可帮助对本公开有全面的理解。
图1是根据本公开的一个实施例的显示基板的局部剖面示意图；
图2为示出具有不同厚度的遮光层对不同波长范围的光的遮光特性的曲线图；
图3为示出离子掺杂对遮光层对不同波长范围的光的遮光特性的影响的曲线图；
图4是根据本公开的一个实施例的显示基板的剖面示意图；
图5是根据本公开的一个实施例的显示基板的制造方法的流程图；
图6是根据本公开的另一个实施例的显示基板的制造方法的流程图；
图7是示出根据本公开实施例的显示基板的制造方法的数个步骤形成的结构的剖面示意图；和
图8是示出根据本公开实施例的显示基板的制造方法的另一个步骤形成的结构的剖面示意图。
具体实施方式
下面通过实施例，并结合附图，对本公开的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本公开实施方式的说明旨在对本公开的总体公开构思进行解释，而不应当理解为对本公开的一种限制。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
需要说明的是，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件或层下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。而且，在本文中，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性。
还应指出的是，由于本公开实施例所涉及的各结构尺寸非常微小，为了清 楚起见，本公开实施例的附图中各结构的尺寸和比例均不代表实际的尺寸和比例。
LTPS TFT一般采用顶栅结构，但是，在顶栅结构的TFT中，为了避免背光源的强光直接照射背沟道产生漏电流，一般需要在在有源层之前形成一层遮光层。目前，通常采用金属Mo等金属材料形成遮光层。在制造这类LPTS TFT时，一般使用掩膜板通过单独的一次构图工艺来形成遮光层的图案，然后采用另外的构图工艺来形成TFT的有源层等其它层的图案，增加了构图工艺的次数，从而导致目前的LTPS TFT的制造工艺较为复杂，并且增加了生产成本。同时，在LPTS TFT的制造工艺中，遮光层的图案在非晶硅转变成多晶硅(p-Si)之前已经形成。一般地，由于构图工艺的限制，形成的遮光层的图案在边缘处会形成一定的坡度角，这样，遮光层本身的厚度以及其图案边缘处的坡度角都会影响后续多晶硅的晶化效果。
图1示出了根据本公开的一个实施例的显示基板的局部示意图。在一个示例中，该显示基板可以为阵列基板。该显示基板可以包括：衬底基板10、设置在衬底基板10上的遮光层6和设置在衬底基板10上的薄膜晶体管的有源层12。如图1所示，遮光层6与有源层12在衬底基板10上的位置对应以遮挡来自外部光对有源层的照射。在一个示例中，有源层12沿垂直于衬底基板的主表面的方向(即，衬底基板的厚度方向)在衬底基板10上的正投影位于遮光层6沿该方向在衬底基板10上的正投影内。在另一个示例中，遮光层6和有源层12沿垂直于衬底基板的主表面的方向(即，衬底基板的厚度方向)在衬底基板10上的正投影完全重叠。以此方式，遮光层6能够避免来自背光源的光照射TFT的位于有源层中的背沟道区域，从而避免由于背光源的强光直接照射背沟道而产生的漏电流。
在一些示例性实施例中，如图1所示，所述显示基板还可以包括：缓冲层2，该缓冲层设置在衬底基板10上；第一绝缘层4，该第一绝缘层设置在缓冲层2上；和第二绝缘层8，该第二绝缘层设置在遮光层6上。并且，遮光层6设置在第一绝缘层4上，即，遮光层6位于第一绝缘层4和第二绝缘层8之间，有源层12设置在第二绝缘层8上，即第二绝缘层8位于遮光层6和有源层12之间。也就是说，衬底基板10上从下至上依次堆叠有缓冲层2、第一绝缘层4、遮光层6、第二绝缘层8和有源层12。
根据本公开的一个实施例，遮光层6由非晶硅(a-Si)形成。这样，在本 公开的实施例中，可以只采用同一个掩膜板(即通过一次构图工艺)即可形成有源层和相应的遮光层，相对于在有源层之下以金属为基材额外再通过一个掩膜板来形成遮光层的技术方案，可以减少一道掩膜工艺，从而简化了显示基板的制造流程。关于通过一次构图工艺形成有源层和遮光层的制造工艺，将在下文中详细描述。
对于上述采用非晶硅材料层形成遮光层的方案，发明人进一步通过实验从不同方面研究了非晶硅材料层的遮光特性。
图2示出了具有不同厚度的遮光层的遮光特性。如图2所示，横坐标表示光的波长，纵坐标表示光穿过遮光层6的透过率。在图2示出的实施例中，分别示出了厚度为
Figure PCTCN2017116141-appb-000006
(埃)、
Figure PCTCN2017116141-appb-000007
Figure PCTCN2017116141-appb-000008
和
Figure PCTCN2017116141-appb-000009
的遮光层的透过率曲线。
一般地，可见光的光谱分布如下表所示。由于背光源发出的光主要为可见光，所以图2示出的实施例主要示出了不同厚度的遮光层对可见光的透过特性。
表1可见光的光谱分布
可见光的光谱颜色 波长范围(纳米)
红色(R) 约625～740nm
橙色 约590～625nm
黄色 约565～590nm
绿色(G) 约500～565nm
青色 约485～500nm
蓝色(B) 约440～485nm
紫色 约380～440nm
在显示基板中，通常蓝光为激发光，所以，在本公开的实施例中，在设计遮光层6的厚度时，首先考虑了不同厚度的遮光层对蓝光(即短波长范围内的光)的透过特性。这样，根据图2所示的透过曲线，在本公开的实施例中，遮光层6的厚度可以设置在
Figure PCTCN2017116141-appb-000010
的范围内，更优选地，遮光层6的厚度可以设置在
Figure PCTCN2017116141-appb-000011
的范围内，从而保证遮光层6对背光源发出的光(尤其是蓝光)的低透过率。
根据本公开进一步的实施例，遮光层6可以由经离子掺杂的非晶硅层形成， 即遮光层6可以包括离子掺杂的非晶硅层。在一个示例中，遮光层6可以由掺杂硼离子(B3+)或磷离子(P3+)的非晶硅层形成。图3示出了离子掺杂对遮光层的遮光特性的影响。根据图3可以看出，当遮光层未掺杂离子时，遮光层对中长波长范围内的可见光的透过率较高，即，遮光效果不佳；当遮光层掺杂有不同浓度的离子(例如，掺杂1表示掺杂一定浓度的硼离子，掺杂2表示掺杂一定浓度的磷离子)时，遮光层对中长波长范围内的可见光的透过率得以减小。经实验研究发现，离子掺杂的非晶硅层对580nm～780nm的中长波段的可见光的透光率降低6％～10％左右。其主要原因在于，通过离子注入等方式对非晶硅进行掺杂，在带隙中引入了杂质能级，相当于减小了非晶硅的光学带隙，即波长大于580nm的光(能量小的光)容易被吸收，因此，经离子掺杂后的非晶硅对波长为580nm以上的光的吸收作用被增强，从而导致光的透过率下降。也就是说，当由经离子掺杂的非晶硅层形成遮光层时，可以进一步提高遮光层的遮光效果，特别是提高遮光层对中长波长范围内的可见光的遮光效果。
根据本公开的一个实施例，有源层12可以由多晶硅材料(p-Si，尤其是低温多晶硅(LTPS)材料)形成。一般地，LTPS薄膜晶体管的制造工艺较为复杂，一般需要进行9至11道构图工艺。而且，对于LPTS薄膜晶体管(TFT)，其一般也有底栅和顶栅两种结构，但是，在迁移率、阈值电压、S值(亚阈值斜率)等一些基本性能上，顶栅结构均优于底栅结构，所以顶栅结构是LTPSTFT的主流结构。对于顶栅结构的TFT，通常需要设置遮光层来避免背光源的强光直接照射背沟道产生漏电流。这样，在将根据本公开实施例的上述结构应用于LTPS TFT时，不仅可以简化LTPS TFT的制造流程，还可以更好地提高LTPS TFT的工作性能。而且，在LTPS TFT的制造工艺中，一般是通过一次构图工艺先形成遮光层，然后再通过另一次构图工艺形成有源层，在前一次构图工艺形成的遮光层的边缘处会形成一定的坡度角，这样，遮光层本身的厚度以及其边缘处的坡度角都会影响后续多晶硅的晶化效果。而在本公开的实施例中，遮光层和有源层通过一次构图工艺形成，就不存在上述影响晶化效果的情形，所以，根据本公开实施例的制造方法还能够提高LTPS TFT中的多晶硅的晶化效果。
根据本公开的实施例，缓冲层2可以由氮化硅形成。以此方式，由氮化硅形成的缓冲层2可以阻挡衬底基板10中的离子(例如，Na+等)进入缓冲层2上方的各层中。在一个示例中，第一绝缘层4和第二绝缘层8可以由刻蚀速率 相同或近似相同的材料构成。在一个示例中，第一绝缘层4和第二绝缘层8可以均由氧化硅形成。通过使用刻蚀速率相同或近似相同的材料构成第一绝缘层和第二绝缘层，可以控制这两层的刻蚀速率相同或近似相同，以调整一次刻蚀的坡度角，从而避免出现“倒梯形”等不良的结构。在一个示例中，缓冲层2的厚度可以为
Figure PCTCN2017116141-appb-000012
第一绝缘层4的厚度可以为
Figure PCTCN2017116141-appb-000013
第二绝缘层案8的厚度可以为
Figure PCTCN2017116141-appb-000014
通过匹配缓冲层、第一绝缘层和第二绝缘层的材料和厚度，可以在最小化刻蚀难度的同时使各层的刻蚀速率相匹配，避免出现“倒梯形”等不良结构，从而保证在后续的a-Si转变为p-Si时实现良好的晶化效果。在一个示例中，缓冲层2可以由氮化硅形成，第一绝缘层4和第二绝缘层8可以由氧化硅形成，通过这样的材料组合，可以保证在后续的a-Si转变为p-Si时实现良好的晶化效果。
图4示出了根据本公开的一个实施例的显示基板的示意图。如图4所示，该显示基板包括：衬底基板10；设置在衬底基板10上的缓冲层2；设置在缓冲层2上的第一绝缘层4；设置在第一绝缘层4上的遮光层6；设置在遮光层6上的第二绝缘层8；设置在第二绝缘层8上的有源层12；覆盖在有源层12上的栅绝缘层14；设置在栅绝缘层14上的栅极18和与公共电极电连接的连接子电极262；形成在衬底基板上并覆盖栅极18和连接子电极262的层间介质层16；设置在层间介质层16上的源、漏极20，源、漏极20分别通过层间介质层16中形成的过孔202与有源层12电连接；设置在源、漏极20和层间介质层16上的平坦化层24；设置在平坦化层24上的公共电极26，公共电极26通过层间介质层16中形成的过孔161与连接子电极262电连接；设置在公共电极26上的钝化层28；和设置在钝化层28上的像素电极30，像素电极30通过钝化层28中形成的过孔281与漏极20电连接。
在一些实施例中，有源层12可以由低温多晶硅形成；在图4示出的实施例中，所述显示基板的一个TFT包括2个栅极18，即形成双栅极结构。但是，图4仅为了示出根据本公开实施例的显示基板的总体结构，而不是用于限制本公开。可以理解的是，根据本公开实施例的显示基板还可以具有其它结构。
根据本公开的实施例，还提供一种显示基板的制造方法，如图5所示。在步骤S510中，提供衬底基板，例如，该衬底基板可以为玻璃基板或其它透明基板。在步骤S520中，在衬底基板上形成遮光层，如上所述，所述遮光层可以由经离子掺杂的非晶硅层形成。在步骤S530中，在衬底基板上形成有源层， 所述遮光层与所述有源层在所述衬底基板上的位置对应；例如，有源层在衬底基板上的正投影位于遮光层在衬底基板上的正投影内或二者重合，所述有源层可以由多晶硅形成。
根据本公开的实施例，还提供一种显示基板的制造方法，如图6所示。在步骤S610中，提供衬底基板。在步骤S620中，在衬底基板上形成缓冲层。在步骤S630中，在缓冲层上形成第一绝缘材料层。在步骤S640中，在第一绝缘层上形成遮光材料层，所述遮光材料层可以由非晶硅或经离子掺杂的非晶硅形成。在步骤S650中，在遮光材料层上形成第二绝缘材料层。在步骤S660中，在第二绝缘材料层上形成半导体材料层，所述半导体材料层可以由经非晶硅转化的多晶硅形成。在步骤S670中，采用同一个掩模板对第一绝缘材料层、遮光材料层、第二绝缘材料层、半导体材料层进行处理以分别形成第一绝缘层、遮光层、第二绝缘层和有源层。由于在本公开的实施例中，遮光层可以由非晶硅(a-Si)形成。这样，可以采用同一个掩膜板(即通过一次构图工艺)即可形成有源层和遮光层的图案，相对于在有源层之下以金属为基材额外再采用同一个掩膜板来形成遮光层的技术方案，可以减少一道掩膜工艺，从而简化了显示基板的制造流程。而且，在现有的制造工艺中，通过一次构图工艺先形成遮光层，然后再通过另一次构图工艺形成有源层，在前一次构图工艺形成的遮光层的图案的边缘处会形成一定的坡度角，这样，遮光层本身的厚度以及其图案边缘处的坡度角都会影响后续多晶硅的晶化效果。而在本公开的实施例中，遮光层和有源层只采用同一个掩模板形成，就不存在上述影响晶化效果的情形，所以，根据本公开实施例的制造方法还能够提高多晶硅的晶化效果。
下面，结合示出在示例性步骤中形成的显示基板的结构的图7来详细描述根据本公开的一个实施例的显示基板的制造方法。
如图7所示，在衬底基板10上从下至上依次形成缓冲层2、第一绝缘材料层4’、第一非晶硅层6’、第二绝缘材料层8’和第二非晶硅层12’。其中，缓冲层2可以由氮化硅(SiNx)形成，第一绝缘材料层4’和第二绝缘材料层8’中的一个或二者可以由氧化硅(SiO2)形成。在一个示例中，上述各层可以通过沉积的方式形成在衬底基板10上。
然后，对第一非晶硅层6’进行离子注入，以形成遮光层。在一个示例中，可以通过离子注入设备调整离子注入浓度、能量等参数将硼离子或者磷离子注入第一非晶硅层中或者注入第一非晶硅层与第一绝缘材料层4’的界面处，随后， 例如使用快速退火炉，对带有注入离子的第一非晶硅层的基板进行退火。经实验发现，当离子注入设备的离子注入工艺参数为：电压为30KV、注入浓度/剂量为5E14～9E14(即，5×1014～9×1014)时，可以使得遮光层具有较好的离子(例如硼离子或者磷离子)掺杂浓度，从而实现较好的遮光效果。需要说明的是，本公开不限于使用离子注入工艺来形成遮光层，在其它实施例中，还可以采用其它工艺，例如CVD掺杂工艺，以将离子掺杂进第一非晶硅层中，从而形成本公开实施例的遮光层。
然后，对第二非晶硅层12’进行退火处理，将第二非晶硅层12’转化为多晶硅层，以用于后续形成所述有源层。
最后，采用同一个掩模板对第一绝缘材料层4’、带有注入离子的第一非晶硅层6’、第二绝缘材料层8、第二非晶硅层12’进行处理以分别形成图1所示的第一绝缘层4、遮光层6、第二绝缘层8和有源层12。
在一个实施例中，采用同一个掩模板形成第一绝缘层、遮光层、第二绝缘层和有源层的步骤可以包括：
通过掩膜板50在第二非晶硅层12’上形成光刻胶40的图案，如图8所示；
以光刻胶40的图案为掩膜，通过刻蚀工艺对第一绝缘材料层4’、第一非晶硅层6’、第二绝缘材料层8’和第二非晶硅层12’进行刻蚀，以分别形成第一绝缘层4、遮光层6、第二绝缘层8和有源层12(如图1所示)；和
剥离光刻胶40。
在上述实施例中，由于对第一绝缘材料层、遮光材料层或第一非晶硅层、第二绝缘材料层、和半导体材料层或第二非晶硅层执行的刻蚀工艺都是在所形成的光刻胶的图案的基础上或以所形成的光刻胶的图案为掩膜进行的，因此可以采用与形成光刻胶的掩膜板相对应的一个掩膜板来完成对于第一绝缘材料层、遮光材料层或第一非晶硅层、第二绝缘材料层、和半导体材料层或第二非晶硅层的构图工艺。
根据本公开的实施例，在采用同一个掩模板形成上述第一绝缘层、遮光层、第二绝缘层和有源层之后，还可以采用构图工艺依次形成图4所示的栅极、层间介质层、源极和漏极、平坦化层、公共电极、钝化层和像素电极的图案，形成这些层的图案的工艺可以采用常规的构图工艺，在此不再赘述。
需要说明的是，虽然在上述示例性的实施例中，遮光层形成在有源层下方，但是，在其它实施例中，遮光层也可以形成在有源层上方，例如，遮光层可以 形成在包括有源层的TFT结构的上方，或者遮光层可以同时形成在有源层的上方和下方。
在根据本公开的实施例的显示基板及其制造方法中，可以采用同一个掩膜板(即通过一次构图工艺)形成有源层和相应的遮光层，相对于在有源层之下以金属为基材额外再通过一个掩膜板来形成遮光层的方案，可以减少一道掩膜工艺，从而简化了显示基板的制造流程和节省制造成本，同时，还可以保证后续工艺中非晶硅转变为多晶硅时的晶化效果。并且，采用由经离子掺杂的非晶硅层形成遮光层，可以进一步提高遮光层的遮光效果。
根据本公开的另一实施例，还提出一种显示装置，包括在本公开的任一实施例中描述的显示基板。示例性地，所述显示装置可以为：显示面板、电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
虽然本公开总体构思的一些实施例已被图示和说明，本领域普通技术人员将理解，在不背离本总体公开构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (20)

  1. 一种显示基板，包括：
    衬底基板；
    设置在所述衬底基板上的遮光层；和
    设置在所述衬底基板上的薄膜晶体管的有源层；
    其中，所述有源层沿衬底基板的厚度方向在所述衬底基板上的正投影位于所述遮光层沿衬底基板的厚度方向在所述衬底基板上的正投影内，并且，所述遮光层包括具有掺杂离子的非晶硅层。
  2. 根据权利要求1所述的显示基板，还包括：
    缓冲层，该缓冲层设置在衬底基板上；
    第一绝缘层，该第一绝缘层设置在缓冲层上；和
    第二绝缘层，该第二绝缘层设置在遮光层上，
    其中，所述遮光层位于所述第一绝缘层和第二绝缘层之间，并且第二绝缘层位于所述遮光层和所述有源层之间。
  3. 根据权利要求2所述的显示基板，其中所述缓冲层、所述有源层、所述第一绝缘层、所述遮光层和所述第二绝缘层沿衬底基板的厚度方向在所述衬底基板上的正投影完全重叠。
  4. 根据权利要求2所述的显示基板，其中，所述缓冲层、第一绝缘层、遮光层、第二绝缘层和有源层从下至上依次堆叠于所述衬底基板上。
  5. 根据权利要求1-4中任一项所述的显示基板，其中，所述遮光层的厚度为
    Figure PCTCN2017116141-appb-100001
  6. 根据权利要求1-5中任一项所述的显示基板，其中，所述遮光层包括掺杂有硼离子或磷离子的非晶硅层。
  7. 根据权利要求1-6中任一项所述的显示基板，其中，所述有源层包括多晶硅材料。
  8. 根据权利要求2-4中任一项所述的显示基板，其中，所述缓冲层包括氮化硅材料。
  9. 根据权利要求2-4和8中任一项所述的显示基板，其中，所述缓冲层的厚度为
    Figure PCTCN2017116141-appb-100002
  10. 根据权利要求2-4、8和9中任一项所述的显示基板，其中，所述第一绝缘层和所述第二绝缘层包括氧化硅材料。
  11. 根据权利要求2-4和8-10中任一项所述的显示基板，其中，所述第一绝缘层的厚度为
    Figure PCTCN2017116141-appb-100003
    所述第二绝缘层的厚度为
    Figure PCTCN2017116141-appb-100004
  12. 一种显示装置，包括根据权利要求1-11中任一项所述的显示基板。
  13. 一种显示基板的制造方法，包括：
    提供衬底基板；以及
    在衬底基板上形成遮光层和薄膜晶体管的有源层，使得所述有源层沿衬底基板的厚度方向在所述衬底基板上的正投影位于所述遮光层沿衬底基板的厚度方向在所述衬底基板上的正投影内，并且，所述遮光层由经离子掺杂的非晶硅层形成。
  14. 根据权利要求13所述的方法，还包括：
    在所述衬底基板上形成缓冲层、第一绝缘材料层、第二绝缘材料层和半导体材料层；和
    采用同一个掩膜板对第一绝缘材料层、经离子掺杂的非晶硅层、第二绝缘 材料层和半导体材料层进行构图工艺，以分别形成第一绝缘层、所述遮光层、第二绝缘层和所述有源层。
  15. 根据权利要求14所述的方法，其中，在所述衬底基板上形成缓冲层、第一绝缘材料层、遮光层、第二绝缘材料层和半导体材料层的步骤包括：
    在衬底基板上形成缓冲层；
    在缓冲层上形成第一绝缘材料层；
    在第一绝缘材料层上形成第一非晶硅层；
    在第一非晶硅层上形成第二绝缘材料层；
    在第二绝缘材料层上形成第二非晶硅层；
    对第一非晶硅层进行离子掺杂，并对离子掺杂后的第一非晶硅层进行退火处理，以形成遮光层；和
    对所述第二非晶硅层进行退火处理，将所述第二非晶硅层转化为多晶硅层，以作为所述半导体材料层。
  16. 根据权利要求14或15所述的方法，其中，采用同一个掩膜板形成第一绝缘层、遮光层、第二绝缘层和有源层步骤包括：
    通过所述掩膜板在所述半导体材料层上形成光刻胶的图案；
    以所形成光刻胶的图案为掩膜，通过刻蚀工艺对第一绝缘材料层、经离子掺杂的非晶硅层、第二绝缘材料层和半导体材料层进行刻蚀，以分别形成第一绝缘层、遮光层、第二绝缘层和有源层；和
    剥离光刻胶。
  17. 根据权利要求16所述的方法，其中，在对所述第一绝缘材料层和所述第二绝缘材料层进行刻蚀时，保持第一绝缘材料层和第二绝缘材料层的刻蚀速率近似相同。
  18. 根据权利要求15所述的方法，其中，对第一非晶硅层进行离子掺杂的步骤包括：
    采用包括30KV的电压和5E14～9E14的离子注入剂量的离子注入工艺参数将硼离子或磷离子注入所述第一非晶硅层中。
  19. 根据权利要求14所述的方法，其中，所述缓冲层由氮化硅形成。
  20. 根据权利要求15或19所述的方法，其中，所述第一绝缘材料层和所述第二绝缘材料层由氧化硅形成。
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