WO2018196301A1 - Cmos图像传感器及其像素电路、驱动方法 - Google Patents

Cmos图像传感器及其像素电路、驱动方法 Download PDF

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Publication number
WO2018196301A1
WO2018196301A1 PCT/CN2017/107105 CN2017107105W WO2018196301A1 WO 2018196301 A1 WO2018196301 A1 WO 2018196301A1 CN 2017107105 W CN2017107105 W CN 2017107105W WO 2018196301 A1 WO2018196301 A1 WO 2018196301A1
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Prior art keywords
voltage
transistor
circuit
output
boosting
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PCT/CN2017/107105
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English (en)
French (fr)
Inventor
郑智仁
丁小梁
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京东方科技集团股份有限公司
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Priority to US16/078,626 priority Critical patent/US10805565B2/en
Publication of WO2018196301A1 publication Critical patent/WO2018196301A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/55—Optical parts specially adapted for electronic image sensors; Mounting thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/74—Circuitry for scanning or addressing the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present disclosure relates to the field of image acquisition technologies, and in particular, to a CMOS image sensor, a pixel circuit thereof, and a driving method.
  • CMOS image sensors are classified into Complementary Metal Oxide Semiconductor (CMOS) image sensors and Charge Coupled Device (CCD) image sensors, which are commonly used to convert optical signals into corresponding electrical signals.
  • CCD image sensors are widely used in digital cameras, mobile phones, medical devices, automobiles, etc. because of their simple process, easy integration with other devices, small size, light weight, low power consumption, and low cost. occasion.
  • a pixel circuit composed of a plurality of transistors and a photodiode (PD) is disposed in a pixel unit (Pixel) of the CMOS image sensor.
  • the plurality of transistors may be CMOS transistors or Thin Film Transistors (TFTs).
  • TFTs Thin Film Transistors
  • the mobility of the CMOS transistor is large, usually 1000 cm 2 /VS, so the pixel circuit composed of the CMOS transistor can operate in a relatively low voltage environment, for example, a transistor having a channel length L of 0.35 ⁇ m.
  • the operating voltage range of the above pixel circuit may be 3.3V to 0V (Ground).
  • the mobility of the TFT is 300-600 cm 2 /VS; and when amorphous silicon (anomorphous silicon, In the case of a-Si), the mobility of the TFT is 0.6 to 0.3 cm 2 /VS. Therefore, the mobility of the TFT is much smaller than that of the CMOS transistor. In this case, when the transistor in the above pixel circuit employs a TFT, the operating voltage range of the pixel circuit is larger.
  • LTPS Low Temperature Poly-silicon
  • amorphous silicon anomorphous silicon, In the case of a-Si
  • the mobility of the TFT is much smaller than that of the CMOS transistor.
  • the transistor in the above pixel circuit employs a TFT, the operating voltage range of the pixel circuit is larger.
  • the prior art In order to make the TFT have a good on state, a large voltage difference between the source and the drain of the TFT is required.
  • the prior art generally uses a negative voltage to drive one pole of the TFT, so the above image
  • the output of the prime circuit typically outputs a negative voltage.
  • the operating voltage of the integrated circuit (IC) receiving the output signal of the pixel circuit is a positive voltage
  • an additional interface circuit needs to be added in the IC. This will lead to an increase in the production cost of the IC.
  • Embodiments of the present disclosure provide a CMOS image sensor and a pixel circuit and a driving method thereof, without additionally adding an interface circuit in the IC.
  • An aspect of an embodiment of the present disclosure provides a pixel circuit of a CMOS image sensor for outputting an acquisition signal to an image processor, the pixel circuit including an acquisition circuit, a source follower circuit, and a voltage conversion circuit; Collecting the incident light and converting the collected optical signal into an electrical signal; the source follower circuit is configured to receive an electrical signal from the acquisition circuit, and the source follower circuit is further connected to the output signal output end and the scan line, and configured For outputting the received electrical signal to the output signal output terminal under the control of the scan line; the voltage conversion circuit is configured to be connected to the output signal output end by the read signal line, The voltage at the output of the acquisition signal is converted to an output voltage and output by a voltage output terminal; wherein the output voltage is within an operating voltage range of the image processor.
  • the voltage conversion circuit includes a current mirror and a boosting sub-circuit connected to the current mirror; the current mirror and current source, a first voltage terminal, the read signal line, and The booster sub-circuit is connected, the current mirror is configured to the booster sub-circuit and to the source follower circuit through the read signal line under the action of the current source and the first voltage terminal Providing a bias current; the boost sub-circuit further connecting a second voltage terminal, a voltage output terminal, and the read signal line, the boost sub-circuit being used for a bias current provided by the current mirror, and a second Under the action of the voltage terminal, through the reading
  • the signal line converts the voltage at the output of the acquisition signal to an output voltage and is output by the voltage output terminal; wherein the output voltage is within an operating voltage range of the image processor.
  • the boost sub-circuit includes: a first boost transistor and a second boost transistor; the first boost transistor and the second boost transistor are both N-type transistors; the first boost transistor a gate is connected to the output signal output terminal, a drain is connected to the voltage output terminal, a source is connected to the current mirror, and a gate and a drain of the second boost transistor are connected to a second voltage terminal.
  • the pole is connected to the voltage output.
  • the boost sub-circuit includes: a first boost transistor and a second boost transistor; the first boost transistor and the second boost transistor are both P-type transistors; when the boost sub-circuit When the third voltage terminal is further connected, the gate of the first boosting transistor is connected to the output signal output terminal, the source is connected to the voltage output terminal, and the drain is connected to the current mirror; The gate of the voltage transistor is connected to the third voltage terminal, the source is connected to the second voltage terminal, and the drain is connected to the voltage output terminal.
  • the current mirror includes: a first common gate transistor, a second common gate transistor, and a third common gate transistor; the first common gate transistor, the second common gate transistor, and the third common gate transistor All of which are N-type transistors; a gate and a drain of the first common-gate transistor are connected to the current source, a drain is connected to the first voltage terminal; and a gate of the second common-gate transistor is connected to the a current source, a drain connected to the output signal output terminal, a source connected to the first voltage terminal, a gate of the third common-gate transistor connected to the current source, and a drain connected to the boost sub-circuit The source is connected to the first voltage terminal.
  • the image processor provides the current source.
  • the CMOS image sensor provides the current source.
  • the voltage conversion circuit includes a boost sub-circuit connected to a second voltage terminal, the voltage output terminal, and the read signal line for using the acquisition signal The voltage at the output is converted to the output voltage.
  • the boosting sub-circuit includes: a first boosting transistor and a second boosting transistor; the first boosting transistor and the second boosting transistor are both P-type transistors;
  • the gate of the first boosting transistor is connected to the output signal output terminal, the source is connected to the voltage output terminal, and the drain is connected to the first voltage terminal;
  • a gate of the second boosting transistor is connected to the third voltage terminal, a source is connected to the second voltage terminal, and a drain is connected to the voltage output terminal.
  • the source follower circuit includes a source follower transistor and a switching transistor; a gate of the source follower transistor is connected to the acquisition circuit, and a first pole is connected to the second voltage terminal, and the second pole is connected The first pole of the switching transistor is connected; the gate of the switching transistor is connected to the scan line, and the second pole is connected to the read signal line through the output signal output end.
  • the acquisition circuit is connected to a reset voltage terminal, a reset control signal terminal, a transmission control signal terminal, and a ground terminal;
  • the acquisition circuit includes a transfer transistor, a reset transistor, a photodiode, and a storage capacitor; a gate of the transfer transistor is connected to the transfer control signal terminal, a first electrode is connected to a gate of the source follower transistor, a second electrode is connected to an N-type region of the photodiode; and a P-type region of the photodiode is Connecting the ground terminal;
  • a gate of the reset transistor is connected to the reset control signal end, a first pole is connected to the reset voltage terminal, and a second pole is connected to a gate of the source follower transistor;
  • the first end of the storage capacitor is connected to the gate of the source follower transistor, and the second end is connected to the ground.
  • CMOS image sensor including the pixel circuit of any one of the CMOS image sensors described above is provided.
  • the CMOS image sensor includes an acquisition area and a peripheral area disposed around the collection area; the collection area includes a plurality of scan lines and read signal lines that intersect horizontally and vertically; the scan line Intersecting a plurality of pixel units with the read signal line; wherein each pixel unit is provided with an acquisition circuit and a source follower circuit, The source follower circuit in a column of pixel units is connected to the same read signal line through an acquisition signal output terminal; a voltage conversion circuit is disposed in the peripheral region, each of the read signal lines and one of the voltages The conversion circuits are connected.
  • a method of driving a pixel circuit of any one of the CMOS image sensors as described above comprising: the acquisition circuit converting the received optical signal into an electrical signal and outputting to the source a follower circuit; the source follower circuit outputs the received electrical signal to the output signal output terminal under the control of the scan line; the current mirror of the voltage conversion circuit follows the current source and the first voltage terminal to follow the source
  • the circuit and the boosting sub-circuit provide a bias current; the boosting sub-circuit converts the voltage of the output of the collected signal to an output voltage under the action of the bias current provided by the current mirror and the second voltage end, and The voltage output is output; wherein the output voltage is within an operating voltage range of the image processor.
  • FIG. 1 is a schematic structural diagram of a pixel circuit of a CMOS image sensor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing a specific structure of the source follower circuit and the voltage conversion circuit of FIG. 1;
  • FIG. 3 is another schematic structural view of the voltage conversion circuit of FIG. 1;
  • FIG. 4a is a schematic structural view of the acquisition circuit of FIG. 1;
  • Figure 4b is a timing signal diagram for controlling the circuit structure shown in Figure 4a;
  • FIG. 5 is a schematic structural diagram of a CMOS image sensor according to an embodiment of the present disclosure.
  • FIG. 6 is a diagram of driving a pixel circuit of a CMOS image sensor according to an embodiment of the present disclosure Method flow chart.
  • Embodiments of the present disclosure provide a pixel circuit of a CMOS image sensor for outputting an acquisition signal to an image processor 01 as shown in FIG. 1.
  • the image processor 01 is configured to integrate the collected signals of the respective pixel circuits and output the image data.
  • the pixel circuit includes an acquisition circuit 10, a source follower circuit 20, and a voltage conversion circuit 30.
  • the acquisition circuit 10 is connected to the source follower circuit 20.
  • the acquisition circuit 10 is configured to collect incident light and convert the collected optical signal into an electrical signal output to the source follower circuit 20.
  • the source follower circuit 20 is also connected to the second voltage source VDD, the acquisition signal output terminal A, and the scan line SEL.
  • the source follower circuit 20 is for amplifying and buffering the received electrical signal under the control of the scan line SEL and outputting it to the acquisition signal output terminal A.
  • the voltage conversion circuit 30 is connected to the acquisition signal output terminal A via the read signal line RL.
  • the voltage conversion circuit 30 converts the voltage of the output of the acquisition signal to an output voltage and is output by a voltage output terminal; wherein the output voltage is within an operating voltage range of the image processor.
  • the voltage conversion circuit 30 includes a current mirror 301 and a boost sub-circuit 302 coupled to the current mirror 301.
  • the current mirror 301 is connected to the current source CS, the first voltage terminal VSS, the read signal line RL, and the boosting sub-circuit 302.
  • the current mirror is used to supply a bias current to the boost sub-circuit 302 and to the source follower circuit 20 via the read signal line RL under the action of the current source CS and the first voltage terminal VSS.
  • the boosting sub-circuit 302 is also connected to the second voltage terminal VDD, the voltage output terminal OUTPUT, and the read signal line RL.
  • the boosting sub-circuit 302 is configured to convert the voltage of the output terminal A of the acquisition signal to the output voltage Vout by reading the signal line RL under the action of the bias current provided by the current mirror CS and the second voltage terminal VDD, and by the voltage Output OUTPUT output.
  • the output voltage Vout is located within the operating voltage range of the image processor 01.
  • the output voltage Vout matches the operating voltage of the image processor 01.
  • the first voltage terminal VSS outputs a low level
  • the second voltage terminal VDD outputs a high level as an example.
  • the magnitude of the output voltage of the first voltage terminal VSS for example, -5 V
  • the magnitude of the output voltage of the second voltage terminal VDD for example 5V
  • the maximum value of the operating voltage of the image processor 01 for example 3V.
  • the current mirror 301 can supply a bias current to the source follower circuit 20 under the action of the current source CS and the first voltage terminal VSS, so that a current flows through the read signal line RL, so
  • the read signal line RL can be connected to a negative voltage interface, that is, the first voltage terminal VSS.
  • the transistor in the pixel circuit connected to the read signal line RL through the acquisition signal output terminal A can be driven by the negative voltage outputted by the first voltage terminal VSS, so that the source and the drain of the transistor are Has a large differential pressure to have a good on state.
  • the boost sub-circuit 302 can be operated under the bias current.
  • the output voltage Vout output from the voltage output terminal OUTPUT is within the operating voltage range of the image processor 01 connected to the pixel circuit, the output voltage and image of the source follower circuit 20 can be made by the voltage conversion circuit 30.
  • the operating voltage of processor 01 is matched. In this way, in the above-mentioned step-up process, the present application does not need to modify the internal structure of the image processor 01, so that the problem that the interface circuit is added to the image processor 01 causes an increase in cost. Based on this, for a transistor having a low mobility and a high threshold voltage Vth, for example, a TFT fabricated by an a-Si process, the above-described voltage conversion circuit 30 More applicable.
  • the boosting sub-circuit 302 includes a first boosting transistor M S1 and a second boosting transistor M S2 .
  • the first boosting transistor M S1 and the second boosting transistor M S2 are both N-type transistors.
  • the gate of the first boosting transistor M S1 is connected to the acquisition signal output terminal A, the drain is connected to the voltage output terminal OUTPUT, and the source is connected to the current mirror 301.
  • the gate and the drain of the second boosting transistor M S2 are connected to the second voltage terminal VDD, and the source is connected to the voltage output terminal OUTPUT.
  • the connection manner of the first boosting transistor M S1 and the second boosting transistor M S2 is as follows:
  • the gate of the first boosting transistor M S1 is connected to the acquisition signal output terminal A, the source is connected to the voltage output terminal OUTPUT, and the drain is connected to the current mirror 301.
  • the gate of the second boosting transistor M S2 is connected to the third voltage terminal Vbias, the source is connected to the second voltage terminal VDD, and the drain is connected to the voltage output terminal OUTPUT.
  • the current mirror 301 includes a first common gate transistor M M1 , a second common gate transistor M M2 , and a third common gate transistor M M3 as shown in FIG. 2 .
  • the first common gate transistor M M1 , the second common gate transistor M M2 , and the third common gate transistor M M3 are all N-type transistors.
  • the gate and the drain of the first common-gate transistor M M1 are connected to the current source CS, and the drain is connected to the first voltage terminal VSS.
  • the gate of the second common-gate transistor M M2 is connected to the current source CS, the drain is connected to the output signal terminal A, and the source is connected to the first voltage terminal VSS.
  • the gate of the third common-gate transistor M M3 is connected to the current source CS, the drain is connected to the boosting sub-circuit 302, and the source is connected to the first voltage terminal VSS.
  • the current I01 flowing through the second common-gate transistor M M2 and the current I02 flowing through the third common-gate transistor M M3 can mirror the current Ir flowing through the first common-gate transistor M M1 .
  • (W/L) 1 is the aspect ratio of the first common-gate transistor M M1 ;
  • (W/L) 2 is the aspect ratio of the second common-gate transistor M M2 ;
  • (W/L) 3 is the third common-gate transistor M M3 aspect ratio.
  • the magnitude of the mirror current can be adjusted by adjusting the aspect ratio of the second common gate transistor M M2 and the third common gate transistor M M3 .
  • the current mirror 301 may further include a transistor M M1 ' in series with the first common gate transistor M M1 ; in addition, a transistor M M2 ' may be included in series with the second common gate transistor M M2 .
  • the transistor M M1 ' is connected to the gate of the transistor M M2 '.
  • the drain of the third common-gate transistor M M3 is connected to the source of the first boosting transistor M S1 .
  • the voltage of the second voltage terminal VDD, and the current I 02 flowing through the third common-gate transistor M M3 may be Meet the following formula:
  • Vmin is the minimum value of the operating voltage of the image processor 01, such as 0V
  • Vmax is the maximum value of the operating voltage of the image processor 01, for example, 3V.
  • the second boosting body tube M S2 is in a diode-connected form.
  • the voltages of the gate and the drain of the second boosting transistor M S2 are the same, so that the additional gain due to the uneven characteristics of the transistors in the boosting sub-circuit 302 can be reduced, so that the voltage of the signal output terminal A is collected.
  • the change value and the change value of the output voltage Vout outputted by the voltage output terminal OUTPUT can be synchronized as much as possible, so that the influence of the above gain on the accuracy of the signal collected by the CMOS image sensor can be reduced.
  • Vg + Vth Vs.
  • the gate voltage Vg of the first boosting transistor M S1 that is, the voltage change value of the output terminal A of the above-mentioned acquisition signal and the voltage output terminal OUTPUT
  • the change value of the output voltage Vout is synchronized, so that the influence of the extra gain due to the uneven characteristics of the transistors in the boosting sub-circuit 302 on the accuracy of the signal acquired by the CMOS image sensor can be avoided.
  • the voltage conversion accuracy of the boosting sub-circuit 302 shown in FIG. 3 is higher with respect to the structure shown in FIG. 2.
  • the current mirror 301 can be omitted as an example.
  • the boosting sub-circuit 302 is connected to the second voltage terminal, the voltage output terminal, and the read signal line for converting the voltage of the output terminal of the acquisition signal to the output voltage. As shown in formula (4) above.
  • connection manner of the first boosting transistor M S1 and the second boosting transistor M S2 is as follows:
  • the gate of the first boosting transistor M S1 is connected to the acquisition signal output terminal A, the source is connected to the voltage output terminal OUTPUT, and the drain is connected to the first voltage terminal VSS.
  • the gate of the second boosting transistor M S2 is connected to the third voltage terminal Vbias, the source is connected to the second voltage terminal VDD, and the drain is connected to the voltage output terminal OUTPUT.
  • the current mirror 301 can be connected as shown in FIG.
  • the current I02 flowing through the third common-gate transistor M M3 can finely adjust the output voltage Vout outputted from the voltage output terminal OUTPUT such that the output voltage Vout of the voltage output terminal OUTPUT is better located in the image processor 01. The working voltage range.
  • the voltage output terminal OUTPUT can be input through the boosting sub-circuit 302.
  • the output voltage Vout is converted to the operating voltage range of the image processor 01, thereby solving the problem that the read signal line RL is connected to the negative voltage interface, causing the output voltage of the source follower circuit 20 to not match the operating voltage of the image processor 01. .
  • the current source CS may be provided separately by an external circuit, or may also be provided by an internal circuit of the CMOS image sensor; or, in order to further increase the output voltage of the source follower circuit 20 and the operating voltage of the image processor 01.
  • the degree of matching, the preferred current source CS is provided by the image processor 01.
  • the source follower circuit 20 includes a source follower transistor M SF and a switching transistor M SEL .
  • the gate of the source follower transistor M SF is connected to the acquisition circuit 10 , the first pole is connected to the second voltage terminal VDD, and the second pole is connected to the first pole of the switching transistor M SFL .
  • the gate of the switching transistor M SFL is connected to the scan line SEL, and the second pole is connected to the read signal line RL through the acquisition signal output terminal A.
  • the acquisition circuit 10 when the acquisition circuit 10 is connected to the reset voltage terminal V rst , the reset control signal terminal Reset, the transmission control signal terminal TX, and the ground terminal.
  • the acquisition circuit 10 includes a transfer transistor T1, a reset transistor T2, a photodiode PD, and a storage capacitor Cst as shown in FIG. 4a.
  • the gate of the transfer transistor T1 is connected to the transmission control signal terminal TX, the first pole connection source follows the gate of the transistor M SF , and the second pole is connected to the N-type region of the photodiode PD.
  • the P-type region of the photodiode PD is connected to the ground terminal.
  • the gate of the reset transistor T2 is connected to the reset control signal terminal Reset, the first pole is connected to the reset voltage terminal V rst , and the second pole is connected to the gate of the source follower transistor M SF .
  • a first end of the storage capacitor Cst is connected to the gate of the source follower transistor M SF , and a second end is connected to the ground.
  • the driving process of the above-mentioned acquisition circuit 10 and source follower circuit 20 is specifically as follows:
  • the reset control signal end Reset outputs a high level, and the control reset transistor T2 is turned on to output the voltage of the reset voltage terminal V vst to the gate of the source follower transistor M SF .
  • the pole thus resets the gate voltage of the source follower transistor M SF and releases the charge stored in the storage capacitor Cst.
  • the charge remaining in the gate of the source follower transistor M SF and the storage capacitor Cst from the previous image frame is prevented from affecting the acquisition voltage of the image frame.
  • the transmission control signal terminal TX outputs a high level to turn on the transmission transistor T1 under the control of the transmission control signal terminal TX, thereby causing the photodiode PD to receive the incident light and illuminate the light.
  • Photoelectric conversion is carried out to generate photogenerated carriers.
  • the photo-generated carriers are transferred from the photodiode PD to a floating diffusion (FD).
  • the source follower transistor M SF is turned on by the floating diffusion region.
  • the scan line SEL outputs a high level, so that under the control of the scan line SEL, the switching transistor M SEL is also turned on, so that the photo-generated carriers sequentially pass from the floating diffusion region to the source follower transistor M SF having the amplification buffering effect,
  • the switching transistor M SEL is outputted to the acquisition signal output terminal A and the read signal line RL connected to the acquisition signal output terminal A, thereby completing the acquisition and output of the primary optical signal.
  • the current source CS is activated to turn on the voltage conversion circuit 30 described above.
  • the voltage output from the read signal line RL is received by the voltage conversion circuit 30, and the voltage is converted into the operating voltage range of the image processor 01, and the voltage output from the read signal line RL and the image processor are achieved.
  • the working voltage of 01 matches the purpose.
  • the above-mentioned acquisition circuit 10 includes a transfer transistor T1 and a reset transistor T2.
  • the source follower circuit 20 includes a source follower transistor M SF and a switch transistor M SEL . Therefore, the acquisition circuit 10 and the source follower circuit 20 include a total of four transistors, thereby constituting a 4T-APS (Active Pixel Sensor).
  • the above-mentioned acquisition circuit 10 may further include only one transistor, that is, the above-mentioned reset transistor T2, and the N-type region of the photodiode PD is directly connected to the floating diffusion region. In this way, the acquisition circuit 10 and the source follower circuit 20 can constitute a 3T-APS. In this case, the second phase P2 in Fig. 4b can be omitted.
  • the present disclosure may pass the signal collected by the APS for the first time through voltage conversion. After the circuit 30 performs voltage conversion, image processing is directly performed in the image processor 01. Or the signal collected by the APS for the first time is subjected to voltage conversion by the voltage conversion circuit 30, and is used as a reference value in the image processor 01, and the signals collected thereafter are compared with the reference value one by one, and then the comparison value is performed. Image Processing.
  • the present disclosure provides a CMOS image sensor including a pixel circuit of any one of the CMOS image sensors described above. It has the same advantageous effects as the CMOS image sensor provided by the foregoing embodiment, and details are not described herein again.
  • the CMOS image sensor 02 includes an acquisition area 100 and a peripheral area 101 disposed around the collection area 100.
  • the acquisition area 100 includes a plurality of scan lines SEL and read signal lines RL that are vertically and horizontally intersected.
  • the scan line SEL and the read signal line RL cross define a plurality of pixel units Pixel.
  • An acquisition circuit 10 and a source follower circuit 20 as shown in FIG. 1 are disposed in each of the pixel units Pixel.
  • the source follower circuit 20 in the pixel unit Pixel of the same column is connected to the same read signal line RL through the acquisition signal output terminal A.
  • the voltage conversion circuit 30 is disposed in the peripheral region 101, and each of the read signal lines RL is connected to a voltage conversion circuit 30. Since the acquisition circuit 10 and the source follower circuit 20 in each pixel unit Pixel are turned on row by row, the voltage conversion circuit 30 can perform voltage conversion on the source follower circuit 20 by the acquisition voltage outputted from the read signal line RL line by line, The output voltage of the source follower circuit 20 in each row of pixel cells Pixel can be made to match the operating voltage of the image processor 01.
  • Embodiments of the present disclosure provide a method of driving a pixel circuit of any one of the CMOS image sensors as described above. As shown in FIG. 6, the method includes:
  • the acquisition circuit 10 shown in FIG. 1 converts the received optical signal into an electrical signal and outputs it to the source follower circuit 20.
  • the source follower circuit 20 amplifies and buffers the received electrical signal under the control of the scan line SEL and outputs it to the acquisition signal output terminal A.
  • the current mirror 301 of the voltage conversion circuit 30 supplies a bias current to the source follower circuit 20 and the boost sub-circuit 302 under the action of the current source CS and the first voltage terminal VSS.
  • the boosting sub-circuit 302 converts the voltage of the acquisition signal output terminal A to the output voltage Vout by the bias current provided by the current mirror 301 and the second voltage terminal VDD, and is outputted by the voltage output terminal OUTPUT.
  • the output voltage Vout is located within the operating voltage range of the image processor 01.
  • the boosting process of the boosting sub-circuit 302 is as described above, and details are not described herein again.
  • the driving method of the pixel circuit of the CMOS image sensor has the same beneficial effects as the pixel circuit of the CMOS image sensor provided in the foregoing embodiment, and details are not described herein again.

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Abstract

一种CMOS图像传感器及其像素电路、驱动方法。CMOS图像传感器的像素电路包括：采集电路，用于对入射光进行采集，并将采集到的光信号转换为电信号；源跟随电路，用于在扫描线的控制下，将接收到的电信号输出至采集信号输出端；电压转换电路，配置为通过读取信号线与所述采集信号输出端相连接，将所述采集信号输出端的电压转换至输出电压，并由电压输出端输出；其中，该输出电压位于图像处理器的工作电压范围内。

Description

CMOS图像传感器及其像素电路、驱动方法 技术领域
本公开涉及图像采集技术领域，尤其涉及一种CMOS图像传感器及其像素电路、驱动方法。
背景技术
图像传感器分为互补金属氧化物(Complementary Metal Oxide Semiconductor，CMOS)图像传感器和电荷耦合器件(Charge Coupled Device，CCD)图像传感器，通常用于将光学信号转化为相应的电信号。相比之下，CMOS图像传感器因其具有工艺简单、易与其他器件集成、体积小、重量轻、功耗小、成本低等特点，而广泛应用于数码相机、移动手机、医疗器械、汽车等场合。
上述CMOS图像传感器的像素单元(Pixel)中设置有由多个晶体管以及一个光电二极管(Photo Diode，PD)构成的像素电路。上述多个晶体管可以为CMOS晶体管或者为薄膜晶体管(Thin Film Transistor，TFT)。其中CMOS晶体管的迁移率(Mobility)较大，通常为1000cm2/VS，因此由CMOS晶体管构成的像素电路可以工作在相对低压的环境下，例如，以沟道长度L为0.35μm的晶体管为例，上述像素电路的工作电压范围可以为3.3V～0V(Ground)。对于TFT而言，当有源层(Active layer)采用低温多晶硅(Low Temperature Poly-silicon，LTPS)时，该TFT的迁移率为300～600cm2/VS；而当采用无定形硅(amorphous silicon，a-Si)时，该TFT的迁移率为0.6～0.3cm2/VS。因此，TFT的迁移率远小于CMOS晶体管。在此情况下，当上述像素电路中的晶体管采用TFT时，该像素电路的工作电压范围更大。
为了使得TFT具有良好的开态，TFT源极和漏极之间需要具有较大的压差。现有技术通常采用负压对TFT的一极进行驱动，因此上述像 素电路的输出端通常输出负压。在此情况下，由于接收该像素电路输出信号的集成电路(Integrated Circuit，IC)的工作电压为正压，因此为了使得像素电路的输出电压能够与IC相匹配，需要在IC中额外增设接口电路，这样一来将会导致IC的制作成本上升。
发明内容
本公开的实施例提供一种CMOS图像传感器及其像素电路、驱动方法，无需在IC中额外增设接口电路。
为达到上述目的，本公开的实施例采用如下技术方案：
本公开实施例的一方面，提供一种CMOS图像传感器的像素电路，用于向图像处理器输出采集信号，所述像素电路包括采集电路、源跟随电路以及电压转换电路；所述采集电路配置用于对入射光进行采集，并将采集到的光信号转换为电信号；源跟随电路，配置为从所述采集电路接收电信号，所述源跟随电路还连接采集信号输出端和扫描线，配置用于在所述扫描线的控制下，将接收到的电信号输出至所述采集信号输出端；电压转换电路，配置为通过读取信号线与所述采集信号输出端相连接，将所述采集信号输出端的电压转换至输出电压，并由电压输出端输出；其中，所述输出电压位于图像处理器的工作电压范围内。
根据本公开的实施例，所述电压转换电路包括电流镜以及与所述电流镜相连接的升压子电路；所述电流镜与电流源、第一电压端、所述读取信号线以及所述升压子电路相连接，所述电流镜用于在所述电流源和所述第一电压端的作用下，向所述升压子电路以及通过所述读取信号线向所述源跟随电路提供偏置电流；所述升压子电路还连接第二电压端、电压输出端以及所述读取信号线，所述升压子电路用于在所述电流镜提供的偏置电流以及第二电压端的作用下，通过所述读取 信号线将所述采集信号输出端的电压转换至输出电压，并由所述电压输出端输出；其中，所述输出电压位于所述图像处理器的工作电压范围内。
根据本公开的实施例所述升压子电路包括：第一升压晶体管和第二升压晶体管；第一升压晶体管和第二升压晶体管均为N型晶体管；所述第一升压晶体管的栅极连接所述采集信号输出端，漏极连接所述电压输出端，源极与所述电流镜相连接；所述第二升压晶体管的栅极和漏极连接第二电压端，源极与所述电压输出端相连接。
根据本公开的实施例所述升压子电路包括：第一升压晶体管和第二升压晶体管；第一升压晶体管和第二升压晶体管均为P型晶体管；当所述升压子电路还连接第三电压端时，所述第一升压晶体管的栅极连接所述采集信号输出端，源极连接所述电压输出端，漏极与所述电流镜相连接；所述第二升压晶体管的栅极连接所述第三电压端，源极连接所述第二电压端，漏极与所述电压输出端相连接。
根据本公开的实施例，所述电流镜包括：第一共栅晶体管、第二共栅晶体管以及第三共栅晶体管；所述第一共栅晶体管、第二共栅晶体管以及第三共栅晶体管均为N型晶体管；所述第一共栅晶体管的栅极和漏极连接所述电流源，漏极与所述第一电压端相连接；所述第二共栅晶体管的栅极连接所述电流源，漏极连接所述采集信号输出端，源极与所述第一电压端相连接；所述第三共栅晶体管的栅极连接所述电流源，漏极连接所述升压子电路，源极与所述第一电压端相连接。
根据本公开的实施例，所述图像处理器提供所述电流源。
根据本公开的实施例，所述CMOS图像传感器提供所述电流源。
根据本公开的实施例，所述电压转换电路包括升压子电路，所述升压子电路连接第二电压端、所述电压输出端以及所述读取信号线，用于将所述采集信号输出端的电压转换至输出电压。
根据本公开的实施例，所述升压子电路包括：第一升压晶体管和第二升压晶体管；所述第一升压晶体管和所述第二升压晶体管均为P型晶体管；当所述升压子电路还连接第三电压端时，所述第一升压晶体管的栅极连接所述采集信号输出端，源极连接所述电压输出端，漏极连接第一电压端；所述第二升压晶体管的栅极连接所述第三电压端，源极连接所述第二电压端，漏极与所述电压输出端相连接。
根据本公开的实施例，所述源跟随电路包括源跟随晶体管和开关晶体管；所述源跟随晶体管的栅极连接所述采集电路，第一极连接所述第二电压端，第二极与所述开关晶体管的第一极相连接；所述开关晶体管的栅极连接所述扫描线，第二极与通过所述采集信号输出端与所述读取信号线相连接。
根据本公开的实施例，所述采集电路连接重置电压端、重置控制信号端、传输控制信号端以及接地端；所述采集电路包括传输晶体管、重置晶体管、光电二极管、存储电容；所述传输晶体管的栅极连接所述传输控制信号端，第一极连接所述源跟随晶体管的栅极，第二极与所述光电二极管的N型区相连接；所述光电二极管的P型区连接所述接地端；所述重置晶体管的栅极连接所述重置控制信号端，第一极连接所述重置电压端，第二极与所述源跟随晶体管的栅极相连接；所述存储电容的第一端连接所述源跟随晶体管的栅极，第二极与所述接地端相连接。
本公开实施例的另一方面，提供一种CMOS图像传感器，包括上所述的任意一种CMOS图像传感器的像素电路。
根据本公开的实施例，所述CMOS图像传感器包括采集区域以及设置于所述采集区域周围的周边区域；所述采集区域包括横纵交叉的多条扫描线与读取信号线；所述扫描线与所述读取信号线交叉界定多个像素单元；其中，每个像素单元中设置有采集电路和源跟随电路，同 一列像素单元中的所述源跟随电路通过采集信号输出端与同一条所述读取信号线相连接；电压转换电路设置于所述周边区域，每一条所述读取信号线与一个所述电压转换电路相连接。
本公开实施例的又一方面，提供一种驱动如上所述的任意一种CMOS图像传感器的像素电路的方法，所述方法包括：采集电路将接收到的光信号转换为电信号并输出至源跟随电路；所述源跟随电路在扫描线的控制下，将接收到的电信号输出至采集信号输出端；电压转换电路的电流镜在电流源和第一电压端的作用下，向所述源跟随电路以及升压子电路提供偏置电流；所述升压子电路在所述电流镜提供的偏置电流以及第二电压端的作用下，将所述采集信号输出端的电压转换至输出电压，并由电压输出端输出；其中，所述输出电压位于图像处理器的工作电压范围内。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种CMOS图像传感器的像素电路的结构示意图；
图2为图1中源跟随电路和电压转换电路的一种具体结构示意图；
图3为图1中电压转换电路的另一种结构示意图；
图4a为图1中采集电路的结构示意图；
图4b为控制图4a所示电路结构的时序信号图；
图5为本公开实施例提供的一种CMOS图像传感器的结构示意图；
图6为本公开实施例提供的一种CMOS图像传感器的像素电路的驱 动方法流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供一种CMOS图像传感器的像素电路，用于向如图1所示的图像处理器01输出采集信号。其中，该图像处理器01用于对各个像素电路的采集信号进行整合，并输出图像数据。
基于此，该像素电路包括采集电路10、源跟随电路20以及电压转换电路30。
具体的，采集电路10与源跟随电路20相连接。该采集电路10用于对入射光进行采集，并将采集到的光信号转换为电信号输出至源跟随电路20。
源跟随电路20还连接第二电压源VDD、采集信号输出端A和扫描线SEL。该源跟随电路20用于在扫描线SEL的控制下，将接收到的电信号进行放大和缓冲并输出至采集信号输出端A。
在此基础上，电压转换电路30通过读取信号线RL与采集信号输出端A相连接。电压转换电路30将所述采集信号输出端的电压转换至输出电压，并由电压输出端输出；其中，所述输出电压位于图像处理器的工作电压范围内。
根据一个实施例，如图1所示，该电压转换电路30包括电流镜301以及与电流镜301相连接的升压子电路302。
具体的，电流镜301与电流源CS、第一电压端VSS、读取信号线RL以及升压子电路302相连接。该电流镜用于在电流源CS和第一电压端VSS的作用下，向升压子电路302以及通过读取信号线RL向源跟随电路20提供偏置电流。
此外，升压子电路302还连接第二电压端VDD、电压输出端OUTPUT以及读取信号线RL。该升压子电路302用于在电流镜CS提供的偏置电流以及第二电压端VDD的作用下，通过读取信号线RL将采集信号输出端A的电压转换至输出电压Vout，并由电压输出端OUTPUT输出。其中，该输出电压Vout位于图像处理器01的工作电压范围内。
例如，当该图像处理器01的工作电压范围为0～3V时，0V＜Vout＜3V。此时，输出电压Vout与图像处理器01的工作电压相匹配。
需要说明的是，本公开实施例中是以上述第一电压端VSS输出低电平，第二电压端VDD输出高电平为例进行的说明。此外，上述第一电压端VSS输出电压的大小，例如-5V，小于图像处理器01工作电压的最小值，例如0V。第二电压端VDD输出电压的大小，例如5V，大于图像处理器01工作电压的最大值，例如3V。
综上所述，一方面，由于该电流镜301在电流源CS和第一电压端VSS的作用下可以向源跟随电路20提供偏置电流，使得读取信号线RL上有电流流过，因此能够使得读取信号线RL连接一负压接口，即上述第一电压端VSS。这样一来，通过采集信号输出端A与读取信号线RL相连接的像素电路中的晶体管可以受到上述第一电压端VSS输出的负压的驱动，使得该晶体管的源极和漏极之间具有较大的压差，以具有良好的开态。
另一方面，由于电流镜301还可以向升压子电路302提供偏置电流，因此该升压子电路302可以在偏置电流的作用下处于工作状态。在此基础上，由于电压输出端OUTPUT输出的输出电压Vout位于与该像素电路相连接的图像处理器01的工作电压范围内，因此通过电压转换电路30可以使得源跟随电路20的输出电压与图像处理器01的工作电压相匹配。这样一来，在上述升压过程中，本申请无需对图像处理器01的内部结构进行改动，从而可以避免在图像处理器01中增设接口电路导致成本上升的问题。基于此，对于迁移率较低且阈值电压Vth较高的晶体管，例如采用a-Si工艺制成的TFT，上述电压转换电路30 更加适用。
以下，对如图1所示的各个电路的具体结构进行详细的说明。
具体的，如图2所示，上述升压子电路302包括：第一升压晶体管MS1和第二升压晶体管MS2。第一升压晶体管MS1和第二升压晶体管MS2均为N型晶体管。
在此情况下，第一升压晶体管MS1的栅极连接采集信号输出端A，漏极连接电压输出端OUTPUT，源极与电流镜301相连接。
第二升压晶体管MS2的栅极和漏极连接第二电压端VDD，源极与电压输出端OUTPUT相连接。
或者，在上述升压子电路302包括第一升压晶体管MS1和第二升压晶体管MS2，且第一升压晶体管MS1和第二升压晶体管MS2均为P型晶体管的情况下，当上述升压子电路302还连接如图3所示的第三电压端Vbias时，上述第一升压晶体管MS1和第二升压晶体管MS2的连接方式为：
第一升压晶体管MS1的栅极连接采集信号输出端A，源极连接电压输出端OUTPUT，漏极与电流镜301相连接。
此外，第二升压晶体管MS2的栅极连接第三电压端Vbias，源极连接第二电压端VDD，漏极与电压输出端OUTPUT相连接。
基于此，上述电流镜301如图2所示包括：第一共栅晶体管MM1、第二共栅晶体管MM2以及第三共栅晶体管MM3。其中，第一共栅晶体管MM1、第二共栅晶体管MM2以及第三共栅晶体管MM3均为N型晶体管。
具体的，上述第一共栅晶体管MM1的栅极和漏极连接电流源CS，漏极与第一电压端VSS相连接。
第二共栅晶体管MM2的栅极连接电流源CS，漏极连接采集信号输出端A，源极与第一电压端VSS相连接。
第三共栅晶体管MM3的栅极连接电流源CS，漏极连接升压子电路302，源极与第一电压端VSS相连接。
在此情况下，流过第二共栅晶体管MM2的电流I01以及流过第三共栅晶体管MM3的电流I02可以镜像流过第一共栅晶体管MM1的电流Ir。
其中，上述电流满足以下公式：
I01/Ir＝(W/L)2/(W/L)1；  (1)
I02/Ir＝(W/L)3/(W/L)1；  (2)
(W/L)1为第一共栅晶体管MM1的宽长比；(W/L)2为第二共栅晶体管MM2的宽长比；(W/L)3为第三共栅晶体管MM3的宽长比。通过调节第二共栅晶体管MM2和第三共栅晶体管MM3的宽长比，可以调节镜像电流的大小。
此外，除了调节宽长比以外，还可以通过增设部分晶体管达到调节镜像电流的目的。例如，如图3所示该电流镜301还可以包括一个与第一共栅晶体管MM1串联的晶体管MM1’；此外，还可以包括一个与第二共栅晶体管MM2串联的晶体管MM2’。其中，晶体管MM1’与晶体管MM2’的栅极相连接。
在此基础上，当上述升压子电路302的结构如图2所示时，该第三共栅晶体管MM3的漏极连接第一升压晶体管MS1的源极。在此情况下，为了使得电压输出端OUTPUT输出的输出电压Vout位于图像处理器01的工作电压范围内，第二电压端VDD的电压，以及流过第三共栅晶体管MM3的电流I02可以满足以下公式：
Vmin＜VDD-I02×RS2＜Vmax；  (3)
其中，RS2为第二升压晶体管MS2的等效电容。Vmin为图像处理器01工作电压的最小值，例如0V，Vmax为图像处理器01工作电压的最大值，例如3V。
此外，如图2所示，第二升压体管MS2处于二极管连接(Diode-connected)形式。此时该第二升压晶体管MS2的栅极和漏极的电压相同，从而可以减小由于升压子电路302中晶体管的特性不均而产生的额外增益，使得采集信号输出端A的电压变化值与电压输出端OUTPUT输出的输出电压Vout的变化值能够尽可能同步，从而可以减小上述增益对CMOS图像传感器采集信号的精度造成的影响。
根据一个实施例，当上述升压子电路302的结构如图3所示时， 第一升压晶体管MS1的源极连接电压输出端OUTPUT，漏极连接第三升压晶体管MM3的漏极。第一升压晶体管MS1为跟随器，该第一升压晶体管MS1的源极电压Vs为栅极电压Vg与该第一升压晶体管MS1的阈值电压Vth之和，即Vg+Vth＝Vs。在此情况下，为了使得电压输出端OUTPUT输出的输出电压Vout位于图像处理器01的工作电压范围内，可以满足以下公式：
Vmin＜Vg+Vth＜Vmax  (4)。
由上述可知，由于图3中第一升压晶体管MS1为跟随器，因此该第一升压晶体管MS1的栅极电压Vg，即上述采集信号输出端A的电压变化值与电压输出端OUTPUT输出的输出电压Vout的变化值同步，从而可以避免由于升压子电路302中晶体管的特性不均而产生的额外增益对CMOS图像传感器采集信号的精度造成的影响。相对于图2所示的结构而言，图3所示的升压子电路302的电压转换精度更高。
在图3所示的实施例中，作为示例，可以省略电流镜301。此时，升压子电路302连接第二电压端、所述电压输出端以及所述读取信号线，用于将所述采集信号输出端的电压转换至输出电压。如上面公式(4)所示。
在该示例中，上述第一升压晶体管MS1和第二升压晶体管MS2的连接方式为：
第一升压晶体管MS1的栅极连接采集信号输出端A，源极连接电压输出端OUTPUT，漏极与第一电压端VSS相连接。
此外，第二升压晶体管MS2的栅极连接第三电压端Vbias，源极连接第二电压端VDD，漏极与电压输出端OUTPUT相连接。
作为另一示例，可以如图3所示，连接电流镜301。在该示例中，流过第三共栅晶体管MM3的电流I02可以对电压输出端OUTPUT输出的输出电压Vout进行微调，以使得电压输出端OUTPUT输出的输出电压Vout更好地位于图像处理器01的工作电压范围内。
综上所述，通过上述升压子电路302可以将电压输出端OUTPUT输 出的输出电压Vout转换至图像处理器01的工作电压范围内，因此解决了读取信号线RL连接负压接口，导致源跟随电路20的输出电压与图像处理器01的工作电压不匹配的问题。
在此基础上，上述电流源CS可以由外部电路单独提供，或者还可以由该CMOS图像传感器的内部电路提供；又或者，为了进一步提高源跟随电路20的输出电压与图像处理器01的工作电压的匹配程度，优选的电流源CS由该图像处理器01提供。
接下来，对源跟随电路20以及采集电路10的具体结构进行详细的说明。
具体的，如图2或图4a所示，源跟随电路20包括源跟随晶体管MSF和开关晶体管MSEL。
其中，源跟随晶体管MSF的栅极连接采集电路10，第一极连接第二电压端VDD，第二极与开关晶体管MSFL的第一极相连接。
开关晶体管MSFL的栅极连接扫描线SEL，第二极通过采集信号输出端A与读取信号线RL相连接。
在此基础上，当采集电路10连接重置电压端Vrst、重置控制信号端Reset、传输控制信号端TX以及接地端时。采集电路10如图4a所示包括传输晶体管T1、重置晶体管T2、光电二极管PD以及存储电容Cst。
其中，传输晶体管T1的栅极连接传输控制信号端TX，第一极连接源跟随晶体管MSF的栅极，第二极与光电二极管PD的N型区相连接。光电二极管PD的P型区连接接地端。
重置晶体管T2的栅极连接重置控制信号端Reset，第一极连接重置电压端Vrst，第二极与源跟随晶体管MSF的栅极相连接。
存储电容Cst的第一端连接所述源跟随晶体管MSF的栅极，第二极与接地端相连接。
基于此，上述采集电路10和源跟随电路20的驱动过程具体为：
如图4b所示，在第一阶段P1，重置控制信号端Reset输出高电平， 控制重置晶体管T2导通，以将重置电压端Vvst的电压输出至源跟随晶体管MSF的栅极，从而对该源跟随晶体管MSF的栅极电压进行重置，并将存储于存储电容Cst中的电荷进行释放。避免上一图像帧残留于源跟随晶体管MSF的栅极和存储电容Cst中的电荷对本图像帧的采集电压造成影响。
接下来，在第二阶段P2，传输控制信号端TX输出高电平，以在传输控制信号端TX的控制下，将传输晶体管T1导通，从而使得光电二极管PD接受入射光，并在光线照射下进行光电转化产生光生载流子。该光生载流子自光电二极管PD转移至浮置扩散区(Floating Diffusion，FD)。
接下来，在第三阶段P3，源跟随晶体管MSF在浮置扩散区的作用下导通。此外，扫描线SEL输出高电平，从而在扫描线SEL控制下，开关晶体管MSEL也导通，使得上述光生载流子依次从浮置扩散区经过具有放大缓冲作用的源跟随晶体管MSF、开关晶体管MSEL输出至采集信号输出端A，以及与该采集信号输出端A相连接的读取信号线RL上，从而完成了一次光信号的采集与输出。
在此基础上，电流源CS启动，以开启上述电压转换电路30。由上述可知，通过上述电压转换电路30接收上述读取信号线RL输出的电压，将该电压转换至图像处理器01的工作电压范围内，达到了读取信号线RL输出的电压与图像处理器01的工作电压相匹配的目的。
需要说明的是，上述采集电路10包括传输晶体管T1、重置晶体管T2，源跟随电路20包括源跟随晶体管MSF和开关晶体管MSEL。因此采集电路10与源跟随电路20一共包括4个晶体管，从而构成了4T-APS(Active Pixel Sensor，有源像素传感器)。或者，上述采集电路10还可以只包括一个晶体管，即上述重置晶体管T2，光电二极管PD的N型区直接与浮置扩散区相连接。这样一来，采集电路10与源跟随电路20可以构成3T-APS。在此情况下，图4b中的第二阶段P2可以省略。
此外，本公开可以将上述APS第一次采集的信号，经过电压转换 电路30进行电压转换后，在图像处理器01中直接进行图像处理。或者将APS第一次采集的信号，经过电压转换电路30进行电压转换后，在图像处理器01中作为参考值，并将之后采集的信号逐一与该参考值作比较，然后再将比较值进行图像处理。
本公开实施提供一种CMOS图像传感器，包括如上所述的任意一种CMOS图像传感器的像素电路。具有与前述实施例提供的CMOS图像传感器相同的有益效果，此处不再赘述。
此外，如图5所示，该CMOS图像传感器02包括采集区域100以及设置于采集区域100周围的周边区域101。
其中，采集区域100包括横纵交叉的多条扫描线SEL与读取信号线RL。该扫描线SEL与读取信号线RL交叉界定多个像素单元Pixel。其中每个像素单元Pixel中设置有如图1所示的采集电路10和源跟随电路20。且同一列像素单元Pixel中的源跟随电路20通过采集信号输出端A与同一条读取信号线RL相连接。
在此基础上，当该CMOS图像传感器的采集精度提高时，分辨率也随之提高，从而使得像素单元Pixel的布线面积逐渐减小。为了适应高分辨率的需求，优选的，电压转换电路30设置于周边区域101，且每一条读取信号线RL与一个电压转换电路30相连接。由于每个像素单元Pixel中的采集电路10和源跟随电路20逐行开启，因此上述电压转换电路30可以对该源跟随电路20通过读取信号线RL输出的采集电压逐行进行电压转化，以使得每一行像素单元Pixel中的源跟随电路20的输出电压均能够与图像处理器01的工作电压相匹配。
本公开实施例提供一种驱动如上所述的任意一种CMOS图像传感器的像素电路的方法，如图6所示，该方法包括：
S101、如图1所示的采集电路10将接收到的光信号转换为电信号并输出至源跟随电路20。
S102、源跟随电路20在扫描线SEL的控制下，将接收到的电信号进行放大和缓冲并输出至采集信号输出端A。
其中，当上述采集电路10和源跟随电路20的结构如图4a所示时，该采集电路10和源跟随电路20的驱动过程同上所述，此处不再赘述。
S103、电压转换电路30的电流镜301在电流源CS和第一电压端VSS的作用下，向源跟随电路20以及升压子电路302提供偏置电流。
其中，当电流镜301的结构如图2、3或4所示时，该电流镜CS提供偏置电流的过程如上所述，此处不再赘述。
S104、升压子电路302在电流镜301提供的偏置电流以及第二电压端VDD的作用下，将采集信号输出端A的电压转换至输出电压Vout，并由电压输出端OUTPUT输出。
其中，该输出电压Vout位于图像处理器01的工作电压范围内。
具体的，当升压子电路302的结构如图2或图3所示时，升压子电路302的升压过程如上所述，此处不再赘述。
上述CMOS图像传感器的像素电路的驱动方法与前述实施例提供的CMOS图像传感器的像素电路具有相同的有益效果，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种CMOS图像传感器的像素电路，用于向图像处理器输出采集信号，所述像素电路包括：
    采集电路，配置为对入射光进行采集，并将采集到的光信号转换为电信号；
    源跟随电路，配置为从所述采集电路接收电信号，所述源跟随电路还连接采集信号输出端和扫描线，配置为在所述扫描线的控制下，将接收到的电信号输出至所述采集信号输出端；以及
    电压转换电路，配置为通过读取信号线与所述采集信号输出端相连接，将所述采集信号输出端的电压转换至输出电压，并由电压输出端输出；其中，所述输出电压位于图像处理器的工作电压范围内。
  2. 根据权利要求1所述的像素电路，其中，所述电压转换电路包括电流镜以及与所述电流镜相连接的升压子电路；
    所述电流镜与电流源、第一电压端、所述读取信号线以及所述升压子电路相连接，所述电流镜用于在所述电流源和所述第一电压端的作用下，向所述升压子电路以及通过所述读取信号线向所述源跟随电路提供偏置电流；
    所述升压子电路还连接第二电压端、电压输出端以及所述读取信号线，所述升压子电路用于在所述电流镜提供的偏置电流以及第二电压端的作用下，通过所述读取信号线将所述采集信号输出端的电压转换至输出电压，并由所述电压输出端输出；其中，所述输出电压位于所述图像处理器的工作电压范围内。
  3. 根据权利要求2所述的像素电路，其中，所述升压子电路包括：第一升压晶体管和第二升压晶体管；所述第一升压晶体管和所述第二升压晶体管均为N型晶体管；
    所述第一升压晶体管的栅极连接所述采集信号输出端，漏极连接所述电压输出端，源极与所述电流镜相连接；
    所述第二升压晶体管的栅极和漏极连接第二电压端，源极与所述电压输出端相连接。
  4. 根据权利要求2所述的像素电路，其中，所述升压子电路包括：第一升压晶体管和第二升压晶体管；所述第一升压晶体管和所述第二升压晶体管均为P型晶体管；
    当所述升压子电路还连接第三电压端时，所述第一升压晶体管的栅极连接所述采集信号输出端，源极连接所述电压输出端，漏极与所述电流镜相连接；
    所述第二升压晶体管的栅极连接所述第三电压端，源极连接所述第二电压端，漏极与所述电压输出端相连接。
  5. 根据权利要求2-4中任一项所述的像素电路，其中，所述电流镜包括：第一共栅晶体管、第二共栅晶体管以及第三共栅晶体管；所述第一共栅晶体管、第二共栅晶体管以及所述第三共栅晶体管均为N型晶体管；
    所述第一共栅晶体管的栅极和漏极连接所述电流源，漏极与所述第一电压端相连接；
    所述第二共栅晶体管的栅极连接所述电流源，漏极连接所述采集信号输出端，源极与所述第一电压端相连接；
    所述第三共栅晶体管的栅极连接所述电流源，漏极连接所述升压子电路，源极与所述第一电压端相连接。
  6. 根据权利要求2-4中任一项所述的像素电路，其中，所述图像处理器提供所述电流源。
  7. 根据权利要求2-4中任一项所述的像素电路，其中，所述CMOS图像传感器提供所述电流源。
  8. 根据权利要求1所述的像素电路，其中，所述电压转换电路包括升压子电路，所述升压子电路连接第二电压端、所述电压输出端以及所述读取信号线，用于将所述采集信号输出端的电压转换至输出电压。
  9. 根据权利要求8所述的像素电路，其中所述升压子电路包括：第一升压晶体管和第二升压晶体管；所述第一升压晶体管和所述第二升压晶体管均为P型晶体管；
    当所述升压子电路还连接第三电压端时，所述第一升压晶体管的栅极连接所述采集信号输出端，源极连接所述电压输出端，漏极连接第一电压端；
    所述第二升压晶体管的栅极连接所述第三电压端，源极连接所述第二电压端，漏极与所述电压输出端相连接。
  10. 根据权利要求1-9中任一项所述的像素电路，其中，所述源跟随电路包括源跟随晶体管和开关晶体管；
    所述源跟随晶体管的栅极连接所述采集电路，第一极连接所述第二电压端，第二极与所述开关晶体管的第一极相连接；
    所述开关晶体管的栅极连接所述扫描线，第二极与通过所述采集信号输出端与所述读取信号线相连接，其中第一极是源极和漏极之一，第二极是源极和漏极中的另一极。
  11. 根据权利要求10所述的像素电路，其中，所述采集电路连接重置电压端、重置控制信号端、传输控制信号端以及接地端；所述采集电路包括传输晶体管、重置晶体管、光电二极管、存储电容；
    所述传输晶体管的栅极连接所述传输控制信号端，第一极连接所 述源跟随晶体管的栅极，第二极与所述光电二极管的N型区相连接；所述光电二极管的P型区连接所述接地端；
    所述重置晶体管的栅极连接所述重置控制信号端，第一极连接所述重置电压端，第二极与所述源跟随晶体管的栅极相连接；
    所述存储电容的第一端连接所述源跟随晶体管的栅极，第二极与所述接地端相连接。
  12. 一种CMOS图像传感器，其中，包括如权利要求1-11中任一项所述的CMOS图像传感器的像素电路。
  13. 根据权利要求12所述的CMOS图像传感器，其中，所述CMOS图像传感器包括采集区域以及设置于所述采集区域周围的周边区域；
    所述采集区域包括横纵交叉的多条扫描线与读取信号线；所述扫描线与所述读取信号线交叉界定多个像素单元；
    其中，每个像素单元中设置有采集电路和源跟随电路，同一列像素单元中的所述源跟随电路通过采集信号输出端与同一条所述读取信号线相连接；
    电压转换电路设置于所述周边区域，每一条所述读取信号线与一个所述电压转换电路相连接。
  14. 一种驱动如权利要求1-7中任一项所述的CMOS图像传感器的像素电路的方法，其中，所述方法包括：
    采集电路将接收到的光信号转换为电信号并输出至源跟随电路；
    所述源跟随电路在扫描线的控制下，将接收到的电信号输出至采集信号输出端；
    电压转换电路的电流镜在电流源和第一电压端的作用下，向所述源跟随电路以及升压子电路提供偏置电流；
    所述升压子电路在所述电流镜提供的偏置电流以及第二电压端的作用下，将所述采集信号输出端的电压转换至输出电压，并由电压输出端输出；其中，所述输出电压位于图像处理器的工作电压范围内。
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