WO2018192379A1 - Mems芯片及其电封装方法 - Google Patents

Mems芯片及其电封装方法 Download PDF

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Publication number
WO2018192379A1
WO2018192379A1 PCT/CN2018/082295 CN2018082295W WO2018192379A1 WO 2018192379 A1 WO2018192379 A1 WO 2018192379A1 CN 2018082295 W CN2018082295 W CN 2018082295W WO 2018192379 A1 WO2018192379 A1 WO 2018192379A1
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conductive
region
electrodes
layer
mems
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PCT/CN2018/082295
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English (en)
French (fr)
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魏玉明
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华为技术有限公司
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Priority to EP18787562.0A priority Critical patent/EP3597591B1/en
Publication of WO2018192379A1 publication Critical patent/WO2018192379A1/zh
Priority to US16/657,432 priority patent/US11242243B2/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0064—Packages or encapsulation for protecting against electromagnetic or electrostatic interferences
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/04—Networks or arrays of similar microstructural devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00095—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/04—Optical MEMS
    • B81B2201/042—Micromirrors, not used as optical switches
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/04—Optical MEMS
    • B81B2201/045—Optical switches
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/05—Arrays
    • B81B2207/053—Arrays of movable structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/07—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/092—Buried interconnects in the substrate or in the lid
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094—Feed-through, via
    • B81B2207/096—Feed-through, via through the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/097—Interconnects arranged on the substrate or the lid, and covered by the package seal
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0109—Bonding an individual cap on the substrate

Definitions

  • the present application relates to the field of semiconductor component packaging technologies, and in particular, to a Micro-Electro-Mechanical System (MEMS) chip and an electrical packaging method thereof.
  • MEMS Micro-Electro-Mechanical System
  • the chip is a general term for semiconductor component products.
  • the chip needs to be electrically packaged before it can be used.
  • the electrical package refers to connecting the electrodes in the chip to the PCB.
  • the electrical connection between the chip and the driver circuit enables external control of the chip.
  • the MEMS chip is characterized by a movable structure on the surface of the chip, so that the surface of the chip cannot be covered with other materials to avoid damaging the movable structure.
  • MEMS chips include micromirror MEMS chips and MEMS-SOI (Silicon On Insulator (SOI)) chips.
  • SOI Silicon On Insulator
  • the micro-mirror MEMS chip is electrically packaged by adding a dust cover to the micro-mirror MEMS chip, and then connecting the driving of each micro-mirror unit to a specific driving electrode through an electric trace on the surface of the micro-mirror MEMS chip. Then connect the corresponding driving electrode to the PCB board, and then evacuate the dust cover to avoid damage to the movable structure caused by particles generated during the electrical packaging process.
  • each cell constituting the MEMS-SOI chip is very small in size (on the order of one hundred micrometers). Due to the limitation of the manufacturing process of the MEMS-SOI chip, electric traces cannot be performed on the surface of the MEMS-SOI chip, and the driving electrodes of each unit are Just next to each unit, the drive electrodes are distributed between the movable structures, and the conventional electrical packaging method for the micromirror MEMS chips is completely unusable. Therefore, how to realize the electrical packaging of the MEMS-SOI chip is an urgent problem to be solved.
  • the present application provides a MEMS chip and an electrical packaging method thereof to solve the problem of how to implement electrical packaging of a MEMS-SOI chip.
  • a first aspect of the present application provides a MEMS chip including a MEMS device layer, a first isolation layer, and a first conductive layer, the MEMS device layer including a first region and at least one second region, the first region including the MEMS movable structure And a conductive structure, the conductive structure is distributed between the MEMS movable structures, the second area is an electrode arrangement area, and the conductive structure and the electrodes in the second area are electrically insulated on the upper surface of the MEMS chip, and the first isolation layer is located at the MEMS device layer Below, the first isolation layer has a corresponding number of first conductive vias corresponding to the position of the conductive structure in the first region and the electrode position in the second region, and the first conductive layer is located below the first isolation layer, and the first conductive layer exists M electrodes independent of each other, M electrodes are respectively connected with M first conductive vias, M is a positive integer, M is set according to the number of conductive structures and the number of electrodes in the second region; the first conductive layer correspond
  • the first isolation layer has a corresponding number of first conductive vias corresponding to the position of the conductive structure in the first region and the position of the electrode in the second region.
  • the first conductive layer has M electrodes which are independent of each other and connected to the first conductive via, and electrically connect the conductive structure in the first region and the second region in a one-to-one correspondence with the electrodes in the first region.
  • the conductive structure in the first region of the MEMS device layer is "one-to-one correspondence" into the second region, and the electrical packaging of the MEMS-SOI chip is realized, and the first region is separated from the electrode arrangement region to be packaged.
  • the MEMS movable structure in the first region can be protected by adding an isolation device, and the electrical package of the MEMS-SOI chip can be compatible with the standard electrical packaging process, thereby contributing to cost reduction.
  • the method further includes: an Nth isolation layer under the first conductive layer and an Nth conductive layer under the Nth isolation layer, N being a positive integer greater than or equal to 2; the first conductive layer The second conductive via is connected to the first conductive via in a region other than the M electrodes, and M is smaller than the sum of the number of conductive structures and the number of electrodes in the second region; the Nth isolation layer corresponds to the first
  • the 2N-2 conductive vias have second N-1 conductive vias connected in one-to-one correspondence with the second N-2 conductive vias; and the N conductive layers have mutually independent Qs connected to the second N-1 conductive vias.
  • the electrodes are smaller than or equal to the number of the second N-1 conductive vias; the electrodes on the Nth conductive layer corresponding to the positions of the conductive structures in the first region and the electrodes corresponding to the positions of the electrodes in the second region are electrically connected one-to-one.
  • the first conductive layer is composed of metal, polysilicon or doped silicon
  • the Nth conductive layer is composed of metal, polysilicon or doped silicon
  • the MEMS device layer further includes an optical input/output region on which a material having a high reflectivity exists at a position corresponding to the optical input/output region.
  • the electrode spacing in the second region is less than the first threshold, and the conductive pillars and the electrodes in the second region have copper pillar bumps.
  • the first threshold is 100 microns.
  • an electrical switch chip is soldered to the second region. Therefore, the problem that it is difficult to package when the number of conductive structures that need to be routed out in the first region on the MEMS chip is difficult to solve, the number of electrodes that need to be soldered from the MEMS chip to the PCB board can be reduced, and the damaged electrical switch chip can be easily replaced, and the electrical switch The reliability of the electrical connection between the chip and the MEMS chip is higher.
  • a second aspect of the present application provides a MEMS chip electrical packaging method, the MEMS chip comprising a MEMS device layer, a first isolation layer and a first conductive layer, the MEMS device layer comprising a first region and at least one second region, the first region comprising a MEMS a movable structure and a conductive structure, the conductive structure is distributed between the MEMS movable structures, the second area is an electrode arrangement area, and the conductive structure and the electrodes in the second area are electrically insulated on the upper surface of the MEMS chip, the method comprising:
  • the first isolation layer is disposed corresponding to the position of the conductive structure in the first region and the electrode position in the second region by a corresponding number of first conductive paths a hole; there are M electrodes independent of each other on the first conductive layer, M electrodes are respectively connected with M first conductive vias, M is a positive integer, and M is set according to the number of conductive structures and the number of electrodes in the second region;
  • the electrodes disposed corresponding to the positions of the conductive structures in the first region and the electrodes disposed corresponding to the positions of the electrodes in the second region are electrically connected in one-to-one correspondence on the first conductive layer.
  • the first isolation layer has a corresponding number of first conductive vias corresponding to the position of the conductive structure in the first region and the position of the electrode in the second region.
  • the first conductive layer is provided with M electrodes which are independent of each other and connected to the first conductive via, and electrically connect the conductive structure in the first region and the second region in a one-to-one correspondence with the electrodes in the first region.
  • the conductive structure in the first region of the MEMS device layer is "one-to-one correspondence" into the second region, and the electrical packaging of the MEMS-SOI chip is realized, and the first region is separated from the electrode arrangement region to be packaged.
  • the MEMS movable structure in the first region can be protected by adding an isolation device, and the electrical package of the MEMS-SOI chip can be compatible with the standard electrical packaging process, thereby contributing to cost reduction.
  • M is smaller than the sum of the number of conductive structures and the number of electrodes in the second region
  • the method further includes: sequentially disposing the Nth isolation layer and the Nth conductive layer under the first conductive layer, where N is a positive integer greater than or equal to 2; a second conductive via connected in a one-to-one correspondence with the first conductive via in a region other than the M electrodes on the first conductive layer; the Nth isolation layer corresponds to the 2N-2 conductive
  • the second hole is disposed at a position corresponding to the second N-1 conductive through hole connected to the second N-2 conductive through hole; the N conductive layer is provided with Q electrodes independently connected to the second N-1 conductive through hole, Q
  • the number of the second N-1 conductive vias is less than or equal to; the electrodes disposed corresponding to the positions of the conductive structures in the first region and the electrodes disposed corresponding to the positions of the electrodes in the second region are electrically connected in one-to-one correspondence on the Nth conductive layer
  • the first conductive layer is composed of metal, polysilicon or doped silicon
  • the Nth conductive layer is composed of metal, polysilicon or doped silicon
  • the MEMS device layer further includes an optical input/output region
  • the method further includes: setting a material having a high reflectivity at a position corresponding to the optical input/output region on the first conductive layer.
  • Figure 1 is a schematic diagram of the OXC routing function
  • FIG. 2 is a schematic structural diagram of an optical switch matrix
  • 3 is a schematic view showing the state of the optical switch unit
  • FIG. 4 is a schematic structural diagram of an embodiment of a MEMS chip provided by the present application.
  • FIG. 5 is a schematic structural view of a MEMS device layer
  • FIG. 6 is a schematic view of a conductive via
  • FIG. 7 is a schematic structural diagram of another embodiment of a MEMS chip provided by the present application.
  • FIG. 8 is a cross-sectional structural diagram of an embodiment of a MEMS chip provided by the present application.
  • FIG. 9 is a schematic structural view of a first conductive layer
  • FIG. 10 is a schematic structural diagram of another embodiment of a MEMS device layer of a MEMS chip provided by the present application.
  • FIG. 11 is a flowchart of a method for electrically packaging a MEMS chip according to the present application.
  • MEMS-SOI chip-based optical switch matrix has very low loss, so MEMS-SOI chip has great advantages in the application of optical switching system.
  • MEMS-SOI chip consists of optical switch matrix and optical input (I) / output (O) Regional composition.
  • the application scenario of the optical switch matrix is briefly introduced below.
  • FIG 1 is a schematic diagram of the OXC routing function. As shown in Figure 1, the signal of user 1 is input from port 1, and needs to be output from port 14. Destination; User 2's signal is input from port 7 and needs to be output from port 11 to the destination.
  • the unit that implements this routing function is called an optical cross connect (OXC), and the core device of the OXC is an optical switch matrix.
  • OXC optical cross connect
  • FIG. 2 is a schematic structural diagram of an optical switch matrix.
  • the architecture is called a cross-bar architecture.
  • the optical switch matrix includes a plurality of cross-over intersections, each of which is an optical switch unit.
  • 3 is a schematic diagram of the state of the optical switch unit. As shown in FIG. 2 and FIG. 3, at each intersection, there are two states: a through state (bar state) and a cross state (cross state), and the through state state continues along a straight line. Forward; cross-state time shifts to 90° output, it can be seen that by controlling the state of each intersection, any route to any output port can be realized.
  • the optical switch unit comprises two upper and lower optical waveguides: the lower optical waveguide forms a vertical and horizontal cross, called a bus waveguide, which is a transverse or longitudinal transmission line in the cross-bar architecture; the upper optical waveguide forms a 90° steering, called a transition waveguide.
  • the working principle of the optical switch unit is: when the optical switch unit is not powered, the upper transfer waveguide does not have any influence on the lower bus waveguide, the optical signal is bound in the bus waveguide for transmission, and the switch unit is in a "straight-through state"; When power is applied, the potential between the upper and lower optical waveguide structures is different. Due to the "electrostatic attraction", the two arms of the upper transmissive waveguide are pulled down.
  • the optical switch unit is in a "cross state", and since the arms of the optical waveguide are movable, the arms of the optical waveguide are a "MEMS movable structure".
  • the Cross-bar architecture has a huge advantage over other architectures in that it has very low losses. At present, loss performance has become a bottleneck restricting the development of optical switch matrix. Therefore, the advantages of cross-bar architecture are particularly eye-catching, but it can be seen that the cross-bar architecture also has a disadvantage that the number of switches will be many.
  • N x N port scale optical switch matrix there are N*N, which means that the number of drive electrodes of the optical switch matrix will be very large, which means that the number of drive electrodes of the MEMS-SOI chip will be very large.
  • the MEMS-SOI chip the traditional electrical packaging method for the micromirror MEMS chip is completely unusable. How to realize the electrical packaging of the MEMS-SOI chip is a problem to be solved by the present application. The technical solution for the application.
  • FIG. 4 is a schematic structural diagram of a MEMS chip embodiment provided by the present application
  • FIG. 5 is a schematic structural diagram of a MEMS device layer.
  • the MEMS chip includes a MEMS device layer 100, a first isolation layer 200, and The first conductive layer 300
  • the MEMS device layer 100 includes a first region including a MEMS movable structure and a conductive structure
  • the conductive structure is also referred to as a driving electrode
  • the conductive structure may be an electrode, a polysilicon, and a doped
  • the material is composed of silicon or the like
  • the conductive structure is distributed between adjacent MEMS movable structures
  • the second region is an electrode arrangement region
  • the conductive structure and the electrode in the second region are electrically insulated on the upper surface of the MEMS chip.
  • the first isolation layer 200 is located under the MEMS device layer 100.
  • the first isolation layer 200 is disposed corresponding to the position of the conductive structure in the first region and the position of the electrode in the second region, and a corresponding number of first conductive vias, the first conductive via There is no electrical connection.
  • the first conductive via can be a metal via, which can make a cylindrical metal via.
  • Figure 6 is a schematic diagram of a conductive via, as shown in Figure 6, the upper surface of the conductive via and the MEMS.
  • the electrodes or conductive structures on the device layer 100 are connected, and the lower surface is connected to the electrodes of the first conductive layer 300.
  • the region of the first isolation layer 200 except the first conductive via is made of an electrically insulating material, and the electrical insulating material is transparent to an optical signal of a communication wavelength band of 1550 nm wavelength and 1310 nm wavelength, for example, silicon dioxide, silicon nitride, or the like.
  • the thickness of the first isolation layer 200 is such that the electrodes or conductive structures in the MEMS device layer 100 are connected to the electrodes in the first conductive layer 300 to achieve complete electrical isolation in regions other than the electrodes.
  • the first conductive layer 300 is located under the first isolation layer 200.
  • the first conductive layer 300 has mutually independent M electrodes, and the M electrodes are respectively connected with the M first conductive vias, M is a positive integer, and M is according to the conductive structure.
  • a conductive layer may be disposed, where M is equal to the sum of the number of conductive structures and the number of electrodes in the second region.
  • M is equal to the sum of the number of conductive structures and the number of electrodes in the second region.
  • the electrodes on the first conductive layer 300 corresponding to the positions of the conductive structures in the first region and the electrodes corresponding to the positions of the electrodes in the second region are electrically connected one by one, and the one-to-one electrical connection refers to the electrodes corresponding to the first region and the corresponding first
  • the electrodes of the two regions are electrically connected one-to-one on the first conductive layer 300, and the electrical connection can be realized by means of electric traces.
  • the regions on the first conductive layer 300 except the electrodes are filled with an electrical insulating material.
  • the first conductive layer 300 may be composed of metal, polysilicon, or doped silicon.
  • the first isolation layer 200 realizes the electrical connection of the electrodes and the conductive structures in the MEMS device layer to the electrodes in the first conductive layer 300, and the electricity in the first conductive layer 300.
  • the trace connects the conductive structure in the first region and the second region in a one-to-one correspondence with the electrodes in the first region, thus finally introducing the one-to-one correspondence of the conductive structures in the first region of the MEMS device layer.
  • the first area is separated from the electrode arrangement area (second area) to be packaged, and an isolation device (such as a dust cover) may be disposed above the first area to protect the MEMS movable structure from the electrical packaging process.
  • the electrode arrangement area that needs to be packaged is separated from the MEMS movable structure, and can be compatible with the standard electric packaging process, thereby reducing the product cost, and the process of fabricating the metal and the electric trace under the MEMS movable structure can adopt CMOS. Standard process.
  • FIG. 7 is a schematic structural diagram of another embodiment of a MEMS chip provided by the present application.
  • an upper surface of the MEMS chip further has an optical input/output (I/O) region, first.
  • a material having a high reflectance exists at a position corresponding to the light input/output area on the conductive layer, and a material having a high reflectance is, for example, a metal.
  • the first isolation layer and the first conductive layer are sequentially arranged under the MEMS device layer, and the first isolation layer corresponds to the position of the conductive structure in the first region and the position of the electrode in the second region.
  • a plurality of first conductive vias wherein the first conductive layer is provided with M electrodes independent of each other and connected to the first conductive via, and the conductive structure in the first region and the second region are in "one-to-one correspondence" with the electrodes in the first region Electrical connection.
  • the conductive structure in the first region of the MEMS device layer is "one-to-one correspondence" into the second region, and the electrical packaging of the MEMS-SOI chip is realized, and the first region is separated from the electrode arrangement region to be packaged.
  • the MEMS movable structure in the first region can be protected by adding an isolation device, and the electrical package of the MEMS-SOI chip can be compatible with the standard electrical packaging process, thereby contributing to cost reduction.
  • a conductive layer may not be able to lead out all the conductive structures of the first region, and it is necessary to provide a second isolation layer, a second conductive layer, ..., The N isolation layer and the Nth conductive layer, by combining the isolation layers and the metal layers, finally connect all of the conductive structures in the first region to the electrodes of the second region.
  • the MEMS chip may further include: an Nth isolation layer and an Nth conductive layer arranged in sequence under the first conductive layer, wherein N is a positive integer greater than or equal to 2.
  • FIG. 8 is a schematic cross-sectional view of a MEMS chip according to an embodiment of the present invention. As shown in FIG. 8 , the MEMS chip of the embodiment includes a MEMS device layer, a first insulating layer, a first conductive layer, and a first a second insulating layer, a second conductive layer, ..., an Nth spacer layer and an Nth conductive layer, and a substrate, wherein FIG.
  • the second conductive via 32 is connected to the first conductive via in a one-to-one correspondence, and M is smaller than the sum of the number of conductive structures and the number of electrodes in the second region, and the corresponding light input/output on the first conductive layer 300 There is a material with high reflectivity at the location of the area.
  • the second conductive via 32 has a third conductive via connected to the second conductive via 32 at a position corresponding to the second conductive via 32.
  • the second conductive layer is independent of each other and connected to the third conductive via.
  • the Nth isolation layer corresponds to the second N-1 conductive vias and has a second N-1 conductive connection connected to the second N-2 conductive vias in one-to-one correspondence a hole
  • the Nth conductive layer has Q electrodes which are independent of each other and connected to the 2N-1 conductive via, and Q is less than or equal to the number of 2N-1 conductive vias, wherein if N is equal to 2, the embodiment
  • the K in the same is the same as Q.
  • the electrodes on the Nth conductive layer corresponding to the positions of the conductive structures in the first region and the electrodes corresponding to the positions of the electrodes in the second region are electrically connected one-to-one.
  • a material having a high reflectance is not disposed on the Nth conductive layer corresponding to the position of the light input/output region.
  • the Nth conductive layer is composed of metal, polysilicon or doped silicon.
  • the sum of the number of electrodes in the first conductive layer to the Nth conductive layer corresponding to the position of the conductive structure in the first region is greater than or equal to the number of the conductive structures in the first region on the MEMS chip, and the first conductive layer to the Nth conductive layer
  • the sum of the number of electrodes in the layer corresponding to the position of the electrodes in the second region is greater than or equal to the number of electrodes in the second region on the MEMS chip, that is to say, a free electrode is allowed.
  • all of the conductive structures in the first region are connected to the electrodes of the second region by providing a plurality of isolation layers and conductive layers.
  • the MEMS device layer 100 includes a first region and a plurality of second regions, and the second region is an electrode.
  • the electrode arrangement area may be divided into a plurality of blocks and located at different positions of the MEMS chip to facilitate the electrode to electrically route the wires in various directions.
  • the structures of the isolation layer and the conductive layer are the same as those in the above embodiment, and are not described herein again.
  • the number of conductive structures that need to be routed out in the first region on the MEMS chip is very large (for example, 10,000 or more), even if the wiring is routed to the electrode arrangement region, it is more difficult to package.
  • As an implementable manner on the basis of the foregoing embodiment, there is an isolation device above the first region, and the electrode spacing in the second region is less than the first threshold.
  • the first threshold is, for example, 100 microns, and the copper pillar bumps are disposed on the electrodes in the conductive structure and the second region.
  • an electrical switch chip is soldered on the second region, for example, a 1 ⁇ 16 electrical switch chip is soldered, and a 1 ⁇ 16 electrical switch chip is soldered on the second region.
  • the traditional electrical packaging technology introduces a 1x16 electrical switch chip onto the PCB. This embodiment reduces the number of electrodes that need to be soldered from the MEMS chip to the PCB because only the control signal electrode of the 1x16 electrical switch chip that is soldered up is needed. It can be connected to the PCB, and it is easy to replace the damaged 1x16 electrical switch chip. The electrical connection between the 1x16 electrical switch chip and the MEMS chip is more reliable.
  • the MEMS chip includes a MEMS device layer, a first isolation layer and a first conductive layer, and the MEMS device layer includes a first region and at least a second region.
  • a region includes a MEMS movable structure and a conductive structure, the conductive structure is distributed between the MEMS movable structures, the second region is an electrode arrangement region, and the conductive structure is electrically insulated from the electrode in the second region on the upper surface of the MEMS chip, such as As shown in FIG. 11, the method in this embodiment may include:
  • the first isolation layer and the first conductive layer are sequentially arranged under the MEMS device layer.
  • the first isolation layer corresponds to the position of the conductive structure in the first region and the position of the electrode in the second region, and a corresponding number of first conductive vias are disposed, and the region of the first isolation layer except the first conductive via is electrically insulated Made of materials.
  • M electrodes independent of each other on the first conductive layer, and M electrodes are respectively connected with M first conductive vias, M is a positive integer, and M is set according to the number of conductive structures and the number of electrodes in the second region.
  • the first conductive layer is composed of metal, polysilicon or doped silicon.
  • the electrodes disposed corresponding to the positions of the conductive structures in the first region and the electrodes disposed corresponding to the positions of the electrodes in the second region are electrically connected in one-to-one correspondence on the first conductive layer.
  • the region on the first conductive layer other than the electrode is filled with an electrical insulating material.
  • the method further includes:
  • N is a positive integer greater than or equal to 2.
  • the second conductive via is connected to the first conductive via in a region other than the M electrodes on the first conductive layer; the N-th isolation layer corresponds to the position of the second N-2 conductive via.
  • the second NN conductive vias are connected to the second N-1 conductive vias one by one; the N conductive layers are provided with Q electrodes independent of each other and connected to the second N-1 conductive vias, and Q is less than or equal to the 2N- 1 The number of conductive vias.
  • the electrodes disposed corresponding to the positions of the conductive structures in the first region and the electrodes disposed corresponding to the positions of the electrodes in the second region are electrically connected in one-to-one correspondence on the Nth conductive layer.
  • the first conductive layer is made of metal, polysilicon or doped silicon
  • the Nth conductive layer is made of metal, polysilicon or doped silicon.
  • the MEMS device layer further includes an optical input/output region
  • the method of the embodiment further includes: setting a high reflectivity material on the first conductive layer corresponding to the position of the light input/output region.
  • the first isolation layer and the first conductive layer are sequentially arranged under the MEMS device layer, and the first isolation layer corresponds to the position of the conductive structure in the first region and the electrode in the second region.
  • a corresponding number of first conductive vias are disposed, and the first conductive layer is provided with M electrodes independent of each other and connected to the first conductive via, and the conductive structure in the first region and the second region and the middle electrode are “one” A corresponding "electrical connection.
  • the conductive structure in the first region of the MEMS device layer is "one-to-one correspondence" into the second region, and the electrical packaging of the MEMS-SOI chip is realized, and the first region is separated from the electrode arrangement region to be packaged.
  • the MEMS movable structure in the first region can be protected by adding an isolation device, and the electrical package of the MEMS-SOI chip can be compatible with the standard electrical packaging process, thereby contributing to cost reduction.
  • the aforementioned program can be stored in a computer readable storage medium.
  • the program when executed, performs the steps including the foregoing method embodiments; and the foregoing storage medium includes various media that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

一种MEMS芯片，包括上方的MEMS器件层（100）、中间的第一隔离层（200）和下方的第一导电层（300），MEMS器件层（100）包括第一区域和至少一个第二区域，第一隔离层（200）对应第一区域中的导电结构位置和第二区域中的电极位置有相应数目的第一导电通孔，第一导电层（300）上存在相互独立的M个电极，M个电极分别与M个第一导电通孔连接，M根据导电结构数目和第二区域中的电极数目设置，第一导电层上对应第一区域中导电结构位置的电极和对应第二区域中电极位置的电极一一对应电连接。MEMS芯片中第一区域与第二区域分隔开，有利于使用标准封装工艺，降低成本。还公开了一种MEMS芯片电封装方法。

Description

MEMS芯片及其电封装方法
本申请要求于2017年04月21日提交国家知识产权局、申请号为201710267612.0、申请名称为“MEMS芯片及其电封装方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体元件封装技术领域，尤其涉及一种微机电系统(Micro-Electro-Mechanical System，MEMS)芯片及其电封装方法。
背景技术
在我们的生活中存在有很多具备各种功能的芯片，芯片是半导体元件产品的统称，芯片需要进行电封装之后才能够被使用，电封装是指将芯片中的电极连接到PCB板上，实现芯片和驱动电路的电学连接，从而能够从外部对芯片进行控制。
MEMS芯片的特点是在芯片的表面具有可动结构，因此不能在芯片的表面覆盖其它材料以免损坏可动结构。MEMS芯片包括微镜MEMS芯片和MEMS-SOI(绝缘体上的硅(Silicon on Insulator，SOI))芯片。构成微镜MEMS芯片的每个微镜单元的尺寸都比较大(毫米量级)，微镜单元的数目一般较少(百量级)。微镜MEMS芯片的电封装方法是在微镜MEMS芯片上加上一个防尘罩，然后在微镜MEMS芯片的表面通过电走线将每个微镜单元的驱动连接到特定的驱动电极上，接着将对应的驱动电极连接到PCB板上，再撤离防尘罩，避免电封装过程中产生的颗粒物对可动结构的损坏。
然而，构成MEMS-SOI芯片的每个单元尺寸非常小(百微米量级)，由于MEMS-SOI芯片制造工艺的限制，在MEMS-SOI芯片的表面无法进行电走线，每个单元的驱动电极就在每一单元的旁边，驱动电极分布在可动结构之间，传统的上述对微镜MEMS芯片的电封装方法是完全无法使用的。因此，如何实现MEMS-SOI芯片的电封装，是一个亟需解决的问题。
发明内容
本申请提供一种MEMS芯片及其电封装方法，以解决如何实现MEMS-SOI芯片的电封装的问题。
本申请第一方面提供一种MEMS芯片，MEMS芯片包括MEMS器件层、第一隔离层和第一导电层，MEMS器件层包括第一区域和至少一个第二区域，第一区域包括MEMS可动结构和导电结构，导电结构分布在MEMS可动结构之间，第二区域为电极排布区域，导电结构与第二区域中的电极在MEMS芯片的上表面电学绝缘，第一隔离层位于MEMS 器件层下方，第一隔离层对应第一区域中的导电结构位置和第二区域中的电极位置有相应数目的第一导电通孔，第一导电层位于第一隔离层下方，第一导电层上存在相互独立的M个电极，M个电极分别与M个第一导电通孔连接，M为正整数，M根据导电结构数目和第二区域中的电极数目设置；第一导电层上对应第一区域中导电结构位置的电极和对应第二区域中电极位置的电极一一对应电连接。
通过在MEMS器件层下方依次排布第一隔离层和第一导电层，第一隔离层对应第一区域中的导电结构位置和第二区域中的电极位置有相应数目的第一导电通孔，第一导电层上有相互独立且与第一导电通孔连接的M个电极，将第一区域中的导电结构和第二区域与中的电极“一一对应”的电连接。从而将MEMS器件层中第一区域中的导电结构“一一对应”的引到了第二区域中，实现了MEMS-SOI芯片的电封装，且第一区域与需要封装的电极排布区域分隔开了，第一区域中的MEMS可动结构能够通过添加隔离装置来进行保护，MEMS-SOI芯片的电封装可以与标准电封装工艺兼容，从而有利于降低成本。
在一种可能的设计中，还包括：位于第一导电层的下方的第N隔离层和位于第N隔离层下方的第N导电层，N为大于或等于2的正整数；第一导电层上除M个电极之外的区域中有与第一导电通孔一一对应连接的第二导电通孔，M小于导电结构数目和第二区域中的电极数目之和；第N隔离层对应第2N-2导电通孔的位置有与第2N-2导电通孔一一对应连接的第2N-1导电通孔；第N导电层上有相互独立且与第2N-1导电通孔连接的Q个电极，Q小于或等于第2N-1导电通孔的数目；第N导电层上对应第一区域中导电结构位置的电极和对应第二区域中电极位置的电极一一对应电连接。
通过设置多个隔离层和导电层，实现将第一区域中的所有导电结构连接到第二区域的电极上去。
在一种可能的设计中，第一导电层由金属、多晶硅或掺杂硅构成，第N导电层由金属、多晶硅或掺杂硅构成。
在一种可能的设计中，MEMS器件层还包括光输入/输出区域，第一导电层上对应光输入/输出区域的位置存在高反射率的材料。通过设置高反射率的材料，可降低光输入/输出区域的耦合损耗。
在一种可能的设计中，第一区域上方有隔离装置，第二区域中的电极间距小于第一阈值，导电结构和第二区域中的电极上有铜柱凸点。从而解决了当MEMS芯片上的第一区域中需要走线出来的导电结构数量非常多时难以封装的问题。
在一种可能的设计中，第一阈值为100微米。
在一种可能的设计中，第二区域上焊接有电学开关芯片。从而解决了当MEMS芯片上的第一区域中需要走线出来的导电结构数量非常多时难以封装的问题，可减少MEMS芯片到PCB板需要焊接的电极数量，易于更换损坏的电学开关芯片，电学开关芯片和MEMS芯片之间电连接的可靠性更高。
本申请第二方面提供一种MEMS芯片电封装方法，MEMS芯片包括MEMS器件层、第一隔离层和第一导电层，MEMS器件层包括第一区域和至少一个第二区域，第一区域包括MEMS可动结构和导电结构，导电结构分布在MEMS可动结构之间，第二区域为电极排布区域，导电结构与第二区域中的电极在MEMS芯片的上表面电学绝缘，该方法包括：
在MEMS器件层的下方依次排布第一隔离层和第一导电层，其中，第一隔离层对应第 一区域中的导电结构位置和第二区域中的电极位置设置相应数目的第一导电通孔；第一导电层上存在相互独立的M个电极，M个电极分别与M个第一导电通孔连接，M为正整数，M根据导电结构数目和第二区域中的电极数目设置；
在第一导电层上将对应第一区域中导电结构位置设置的电极和对应第二区域中电极位置设置的电极一一对应电连接。
通过在MEMS器件层下方依次排布第一隔离层和第一导电层，第一隔离层对应第一区域中的导电结构位置和第二区域中的电极位置有相应数目的第一导电通孔，第一导电层上设置相互独立且与第一导电通孔连接的M个电极，将第一区域中的导电结构和第二区域与中的电极“一一对应”的电连接。从而将MEMS器件层中第一区域中的导电结构“一一对应”的引到了第二区域中，实现了MEMS-SOI芯片的电封装，且第一区域与需要封装的电极排布区域分隔开了，第一区域中的MEMS可动结构能够通过添加隔离装置来进行保护，MEMS-SOI芯片的电封装可以与标准电封装工艺兼容，从而有利于降低成本。
在一种可能的设计中，M小于导电结构数目和第二区域中的电极数目之和，方法还包括：在第一导电层的下方依次排布第N隔离层和第N导电层，N为大于或等于2的正整数；第一导电层上除M个电极之外的区域中设置与第一导电通孔一一对应连接的第二导电通孔；第N隔离层对应第2N-2导电通孔的位置设置与第2N-2导电通孔一一对应连接的第2N-1导电通孔；第N导电层上设置相互独立且与第2N-1导电通孔连接的Q个电极，Q小于或等于第2N-1导电通孔的数目；在第N导电层上将对应第一区域中导电结构位置设置的电极和对应第二区域中电极位置设置的电极一一对应电连接。
通过设置多个隔离层和导电层，实现将第一区域中的所有导电结构连接到第二区域的电极上去。
在一种可能的设计中，第一导电层由金属、多晶硅或掺杂硅构成，第N导电层由金属、多晶硅或掺杂硅构成。
在一种可能的设计中，MEMS器件层还包括光输入/输出区域，方法还包括：在第一导电层上对应光输入/输出区域的位置设置高反射率的材料。通过设置高反射率的材料，可降低光输入/输出区域的耦合损耗。
附图说明
图1为OXC路由功能示意图；
图2为光开关矩阵的一种架构示意图；
图3为光开关单元状态示意图；
图4为本申请提供的一种MEMS芯片实施例的结构示意图；
图5为MEMS器件层的结构示意图；
图6为一种导电通孔的示意图；
图7为本申请提供的另一种MEMS芯片实施例的结构示意图；
图8为本申请提供的一种MEMS芯片实施例的剖面结构示意图；
图9为第一导电层的结构示意图；
图10为本申请提供的又一种MEMS芯片的MEMS器件层实施例的结构示意图；
图11为本申请提供的一种MEMS芯片电封装方法的流程图。
具体实施方式
基于MEMS-SOI芯片的光开关矩阵具有极低损耗，因此MEMS-SOI芯片在光交换系统的应用中具有很大的优势，MEMS-SOI芯片由光开关矩阵和光输入(I)/输出(O)区域构成。下面对光开关矩阵的应用场景进行简单介绍。
通信网络的基本功能之一是将不同来源的信号发送到指定的目的地去，图1为OXC路由功能示意图，如图1所示，用户1的信号从端口1输入，需要从端口14输出去向目的地；用户2的信号从端口7输入，需要从端口11输出去向目的地。实现该路由功能的单元称为光交叉连接(Optical cross connect，OXC)，OXC的核心器件是光开关矩阵。
图2为光开关矩阵的一种架构示意图，该架构被称为cross-bar架构，如图2所示，光开关矩阵包括多个纵横交叉的交叉点，每一个交叉点为一个光开关单元，图3为光开关单元状态示意图，如图2和图3所示，在每一个交叉点上，存在两种状态：直通态(bar状态)和交叉态(cross状态)，直通态时光沿直线继续往前传；交叉态时光转向90°输出，可以看出，通过控制每一个交叉点的状态，能够实现任意输入到任意输出端口的路由。
光开关单元包含上下两层光波导：下层光波导形成纵横交叉，称为总线波导(bus waveguide)，为cross-bar架构中横向或者纵向的传输线；上层光波导形成90°的转向，称为转轨波导。光开关单元的工作原理是：在光开关单元不加电的时候，上层转轨波导对下层总线波导不形成任何影响，光信号被束缚在总线波导中进行传输，开关单元处于“直通态”；在加电的时候，上下层光波导结构间电势不同，由于“静电吸引力”的作用，上层转轨波导的两臂被拉下来，此时，下层光波导中的光信号就会耦合到转轨波导中，这样光开关单元就处于“交叉态”，由于光波导的两臂是可以移动的，因此该光波导的两臂是一种“MEMS可动结构”。
Cross-bar架构相比于其它架构有一个巨大的优势，就是损耗极低。目前，损耗性能已经成为制约光开关矩阵发展的瓶颈，因此cross-bar架构的优势格外引人注目，但是可以看出cross-bar架构也同样存在一个缺点，即开关数目会很多。对N x N端口规模的光开关矩阵，共有N*N个，这也意味着光开关矩阵的驱动电极数量会非常多，也就是说MEMS-SOI芯片的驱动电极数量会非常多。对于MEMS-SOI芯片而言，传统的对微镜MEMS芯片的电封装方法是完全无法使用的，如何实现MEMS-SOI芯片的电封装，是本申请要解决的问题，下面结合附图详细说明本申请的技术方案。
图4为本申请提供的一种MEMS芯片实施例的结构示意图，图5为MEMS器件层的结构示意图，如图4和图5所示，MEMS芯片包括MEMS器件层100、第一隔离层200和第一导电层300，MEMS器件层100包括第一区域和至少一个第二区域，第一区域包括MEMS可动结构和导电结构，导电结构也称为驱动电极，导电结构可以为电极、多晶硅和掺杂硅等材料构成，导电结构分布在相邻的MEMS可动结构之间，第二区域为电极排布区域，导电结构与第二区域中的电极在MEMS芯片的上表面是电学绝缘的。第一隔离层200位于MEMS器件层100下方，第一隔离层200对应第一区域中的导电结构位置和第二区域中的电极位置设置相应数目的第一导电通孔，第一导电 通孔之间无电学连接，第一导电通孔可以为金属通孔，可以使圆柱形的金属通孔，图6为一种导电通孔的示意图，如图6所示，导电通孔的上表面与MEMS器件层100上的电极或导电结构相连，下表面与第一导电层300的电极相连。第一隔离层200除第一导电通孔之外的区域由电学绝缘材料制成，电学绝缘材料对1550nm波长及1310nm波长的通信波段的光信号透明，例如为二氧化硅、氮化硅等，厚度为微米量级，第一隔离层200的作用是实现MEMS器件层100中的电极或导电结构与第一导电层300中的电极的连接，在电极以外的区域实现完全的电学隔离。第一导电层300位于第一隔离层200下方，第一导电层300上存在相互独立的M个电极，M个电极分别与M个第一导电通孔连接，M为正整数，M根据导电结构数目和第二区域中的电极数目设置，导电结构数目和第二区域中的电极数目较少时，设置一个导电层即可，此时M等于导电结构数目和第二区域中的电极数目之和，导电结构数目和第二区域中的电极数目较多时，需要设置多个导电层，则M小于导电结构数目和第二区域中的电极数目之和。
其中，第一导电层300上对应第一区域中导电结构位置的电极和对应第二区域中电极位置的电极一一对应电连接，一一对应电连接是指对应第一区域的电极与对应第二区域的电极在第一导电层300上一对一地电连接，可通过电走线的方式实现电连接，第一导电层300上除电极之外的区域均填充电学绝缘材料。第一导电层300可以由金属、多晶硅或掺杂硅构成。
本实施例中，通过第一隔离层200实现了MEMS器件层中的电极、导电结构与第一导电层300中的电极“一一对应”的电连接，同时在第一导电层300中的电走线将第一区域中的导电结构和第二区域与中的电极“一一对应”的连接了起来，这样最终将MEMS器件层中第一区域中的导电结构“一一对应”的引到了第二区域中。第一区域与需要封装的电极排布区域(第二区域)分隔开了，可以在第一区域上方设置隔离装置(如防尘罩)来保护MEMS可动结构不受电封装工艺过程的破坏，需要进行封装的电极排布区域与MEMS可动结构隔开，就可以与标准电封装工艺兼容，从而有利于降低产品成本，制作MEMS可动结构下的金属和电走线的过程可以采用CMOS标准工艺。
图7为为本申请提供的另一种MEMS芯片实施例的结构示意图，在上述实施例的基础上，进一步地，MEMS芯片的上表面还具有光输入/输出(I/O)区域，第一导电层上对应光输入/输出区域的位置存在高反射率的材料，具有高反射率的材料例如为金属。通过设置高反射率的材料，可降低光输入/输出区域的耦合损耗。
本实施例提供的MEMS芯片，通过在MEMS器件层下方依次排布第一隔离层和第一导电层，第一隔离层对应第一区域中的导电结构位置和第二区域中的电极位置有相应数目的第一导电通孔，第一导电层上设置相互独立且与第一导电通孔连接的M个电极，将第一区域中的导电结构和第二区域与中的电极“一一对应”的电连接。从而将MEMS器件层中第一区域中的导电结构“一一对应”的引到了第二区域中，实现了MEMS-SOI芯片的电封装，且第一区域与需要封装的电极排布区域分隔开了，第一区域中的MEMS可动结构能够通过添加隔离装置来进行保护，MEMS-SOI芯片的电封装可以与标准电封装工艺兼容，从而有利于降低成本。
在上述实施例的基础上，当第一区域的导电结构非常多时，一层导电层可能无法将第一区域的所有导电结构引出，需要设置第二隔离层、第二导电层、……、第N隔 离层和第N导电层，通过这些隔离层与金属层的组合，最终将第一区域中的所有导电结构连接到第二区域的电极上去。
在上述实施例的基础上，进一步地，MEMS芯片还可以包括：依次排布在第一导电层的下方的第N隔离层和第N导电层，N为大于或等于2的正整数。图8为本申请提供的一种MEMS芯片实施例的剖面结构示意图，如图8所示，本实施例的MEMS芯片包括依次排布的MEMS器件层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、……、第N隔离层和第N导电层以及衬底，其中，图9为第一导电层的结构示意图，第一导电层300上除M个电极31之外的区域中设置与第一导电通孔一一对应连接的第二导电通孔32，M小于导电结构数目和第二区域中的电极数目之和，第一导电层300上对应光输入/输出区域的位置存在高反射率的材料。第二隔离层上对应第二导电通孔32的位置有与第二导电通孔32一一对应连接的第三导电通孔，第二导电层上有相互独立且与第三导电通孔连接的K个电极，K小于或等于第三导电通孔的数目；第N隔离层对应第2N-2导电通孔的位置有与第2N-2导电通孔一一对应连接的第2N-1导电通孔，第N导电层上有相互独立且与第2N-1导电通孔连接的Q个电极，Q小于或等于第2N-1导电通孔的数目，其中，如果N等于2，则本实施例中的K与Q相同。第N导电层上对应第一区域中导电结构位置的电极和对应第二区域中电极位置的电极一一对应电连接。第N导电层上对应光输入/输出区域的位置不设置高反射率的材料。第N导电层由金属、多晶硅或掺杂硅构成。
可选的，第一导电层至第N导电层中对应第一区域中导电结构位置的电极数量的总和大于或等于MEMS芯片上第一区域的导电结构的数量，第一导电层至第N导电层中对应第二区域中电极位置的电极数量的总和大于或等于MEMS芯片上第二区域的电极的数量，也就是说允许有空余电极。
本实施中，通过设置多个隔离层和导电层，实现将第一区域中的所有导电结构连接到第二区域的电极上去。
图10为本申请提供的又一种MEMS芯片的MEMS器件层实施例的结构示意图，在上述实施例的基础上，MEMS器件层100包括第一区域和多个第二区域，第二区域为电极排布区域，如图10所示，电极排布区域可以是分成多块，位于MEMS芯片的不同位置，便于电极向各个方向电走线。隔离层和导电层的结构与上述实施例中相同，此处不再赘述。
进一步地，当MEMS芯片上的第一区域中需要走线出来的导电结构数量非常多时(例如一万以上)，这时即使走线到了电极排布区域，也会比较难以封装。为解决这一问题，有两种可实施的方式，作为一种可实施的方式，在上述实施例的基础上，第一区域上方有隔离装置，第二区域中的电极间距小于第一阈值，第一阈值例如为100微米，导电结构和第二区域中的电极上设置铜柱凸点。
作为另一种可实施的方式，在上述实施例的基础上，在第二区域上焊接有电学开关芯片，例如焊接上1x16的电学开关芯片，1x16的电学开关芯片焊接在第二区域上，通过传统的电学封装技术将1x16的电学开关芯片引到PCB板上，该实施方式下可减少MEMS芯片到PCB板需要焊接的电极数量，因为只需要将焊接上去的1x16的电学开关芯片的控制信号电极连接到PCB板上即可，易于更换损坏的1x16的电学开关芯 片，1x16的电学开关芯片和MEMS芯片之间电连接的可靠性更高。
图11为本申请提供的一种MEMS芯片电封装方法的流程图，MEMS芯片包括MEMS器件层、第一隔离层和第一导电层，MEMS器件层包括第一区域和至少一个第二区域，第一区域包括MEMS可动结构和导电结构，导电结构分布在MEMS可动结构之间，第二区域为电极排布区域，导电结构与第二区域中的电极在MEMS芯片的上表面电学绝缘，如图11所示，本实施例的方法可以包括：
S101、在MEMS器件层的下方依次排布第一隔离层和第一导电层。
其中，第一隔离层对应第一区域中的导电结构位置和第二区域中的电极位置设置相应数目的第一导电通孔，第一隔离层除第一导电通孔之外的区域由电学绝缘材料制成。第一导电层上存在相互独立的M个电极，M个电极分别与M个第一导电通孔连接，M为正整数，M根据导电结构数目和第二区域中的电极数目设置。可选的，第一导电层由金属、多晶硅或掺杂硅构成。
S102、在第一导电层上将对应第一区域中导电结构位置设置的电极和对应第二区域中电极位置设置的电极一一对应电连接。
其中，第一导电层上除电极之外的区域均填充电学绝缘材料。
进一步地，M小于导电结构数目和第二区域中的电极数目之和时，方法还包括：
S103、在第一导电层的下方依次排布第N隔离层和第N导电层，N为大于或等于2的正整数。
其中，第一导电层上除M个电极之外的区域中设置与第一导电通孔一一对应连接的第二导电通孔；第N隔离层对应第2N-2导电通孔的位置设置与第2N-2导电通孔一一对应连接的第2N-1导电通孔；第N导电层上设置相互独立且与第2N-1导电通孔连接的Q个电极，Q小于或等于第2N-1导电通孔的数目。
S104、在第N导电层上将对应第一区域中导电结构位置设置的电极和对应第二区域中电极位置设置的电极一一对应电连接。
可选的，第一导电层由金属、多晶硅或掺杂硅构成，第N导电层由金属、多晶硅或掺杂硅构成。
进一步地，MEMS器件层还包括光输入/输出区域，本实施例的方法还包括：在第一导电层上对应光输入/输出区域的位置设置高反射率的材料。通过设置高反射率的材料，可降低光输入/输出区域的耦合损耗。
本实施例的方法与前述装置实施例的技术方案的实现原理类似，此处不再赘述。
本实施例提供的MEMS芯片电封装方法，通过在MEMS器件层下方依次排布第一隔离层和第一导电层，第一隔离层对应第一区域中的导电结构位置和第二区域中的电极位置有相应数目的第一导电通孔，第一导电层上设置相互独立且与第一导电通孔连接的M个电极，将第一区域中的导电结构和第二区域与中的电极“一一对应”的电连接。从而将MEMS器件层中第一区域中的导电结构“一一对应”的引到了第二区域中，实现了MEMS-SOI芯片的电封装，且第一区域与需要封装的电极排布区域分隔开了，第一区域中的MEMS可动结构能够通过添加隔离装置来进行保护，MEMS-SOI芯片的电封装可以与标准电封装工艺兼容，从而有利于降低成本。
本领域普通技术人员可以理解：实现上述各方法实施例的全部或部分步骤可以通 过程序指令相关的硬件来完成。前述的程序可以存储于一计算机可读取存储介质中。该程序在执行时，执行包括上述各方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (11)

  1. 一种MEMS芯片，其特征在于，所述MEMS芯片包括MEMS器件层、第一隔离层和第一导电层，
    所述MEMS器件层包括第一区域和至少一个第二区域，所述第一区域包括MEMS可动结构和导电结构，所述导电结构分布在所述MEMS可动结构之间，所述第二区域为电极排布区域，所述导电结构与所述第二区域中的电极在所述MEMS芯片的上表面电学绝缘；
    所述第一隔离层位于所述MEMS器件层下方，所述第一隔离层对应所述第一区域中的导电结构位置和所述第二区域中的电极位置有相应数目的第一导电通孔；
    所述第一导电层位于所述第一隔离层下方，所述第一导电层上存在相互独立的M个电极，所述M个电极分别与M个所述第一导电通孔连接，其中，M为正整数，M根据所述导电结构数目和所述第二区域中的电极数目设置；
    所述第一导电层上对应所述第一区域中导电结构位置的电极和对应所述第二区域中电极位置的电极一一对应电连接。
  2. 根据权利要求1所述的MEMS芯片，其特征在于，还包括：
    位于所述第一导电层的下方的第N隔离层和位于所述第N隔离层下方的第N导电层，N为大于或等于2的正整数；
    所述第一导电层上除所述M个电极之外的区域中有与所述第一导电通孔一一对应连接的第二导电通孔，M小于所述导电结构数目和所述第二区域中的电极数目之和；
    所述第N隔离层对应第2N-2导电通孔的位置有与所述第2N-2导电通孔一一对应连接的第2N-1导电通孔；
    所述第N导电层上有相互独立且与第2N-1导电通孔连接的Q个电极，Q小于或等于第2N-1导电通孔的数目；
    所述第N导电层上对应所述第一区域中导电结构位置的电极和对应所述第二区域中电极位置的电极一一对应电连接。
  3. 根据权利要求2所述的MEMS芯片，其特征在于，所述第一导电层由金属、多晶硅或掺杂硅构成，所述第N导电层的材料为金属、多晶硅或掺杂硅中的一种。
  4. 根据权利要求1～3任一项所述的MEMS芯片，其特征在于，所述MEMS器件层还包括光输入/输出区域，所述第一导电层上对应所述光输入/输出区域的位置存在高反射率的材料。
  5. 根据权利要求4所述的MEMS芯片，其特征在于，所述第一区域上方有隔离装置，所述第二区域中的电极间距小于第一阈值，所述导电结构和所述第二区域中的电极上有铜柱凸点。
  6. 根据权利要求5所述的MEMS芯片，其特征在于，所述第一阈值为100微米。
  7. 根据权利要求4所述的MEMS芯片，其特征在于，所述第二区域上焊接有电学开关芯片。
  8. 一种MEMS芯片电封装方法，其特征在于，MEMS芯片包括MEMS器件层、第一隔离层和第一导电层，所述MEMS器件层包括第一区域和至少一个第二区域，所 述第一区域包括MEMS可动结构和导电结构，所述导电结构分布在所述MEMS可动结构之间，所述第二区域为电极排布区域，所述导电结构与所述第二区域中的电极在所述MEMS芯片的上表面电学绝缘，所述方法包括：
    在所述MEMS器件层的下方依次排布第一隔离层和第一导电层；
    其中，所述第一隔离层对应所述第一区域中的导电结构位置和所述第二区域中的电极位置设置相应数目的第一导电通孔；
    所述第一导电层上存在相互独立的M个电极，所述M个电极分别与M个所述第一导电通孔连接，其中，M为正整数，M根据所述导电结构数目和所述第二区域中的电极数目设置；
    在所述第一导电层上将对应所述第一区域中导电结构位置设置的电极和对应所述第二区域中电极位置设置的电极一一对应电连接。
  9. 根据权利要求8所述的方法，其特征在于，M小于所述导电结构数目和所述第二区域中的电极数目之和，所述方法还包括：
    在所述第一导电层的下方依次排布第N隔离层和第N导电层，N为大于或等于2的正整数；
    所述第一导电层上除所述M个电极之外的区域中设置与所述第一导电通孔一一对应连接的第二导电通孔；
    所述第N隔离层对应第2N-2导电通孔的位置设置与所述第2N-2导电通孔一一对应连接的第2N-1导电通孔；
    所述第N导电层上设置相互独立且与第2N-1导电通孔连接的Q个电极，Q小于或等于第2N-1导电通孔的数目；
    在所述第N导电层上将对应所述第一区域中导电结构位置设置的电极和对应所述第二区域中电极位置设置的电极一一对应电连接。
  10. 根据权利要求9所述的方法，其特征在于，所述第一导电层的材料为金属、多晶硅或掺杂硅中的一种，所述第N导电层的材料为金属、多晶硅或掺杂硅中的一种。
  11. 根据权利要求8～10任一项所述的方法，其特征在于，所述MEMS器件层还包括光输入/输出区域，所述方法还包括：
    在所述第一导电层上对应所述光输入/输出区域的位置设置高反射率的材料。
PCT/CN2018/082295 2017-04-21 2018-04-09 Mems芯片及其电封装方法 WO2018192379A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6396976B1 (en) * 1999-04-15 2002-05-28 Solus Micro Technologies, Inc. 2D optical switch
US6445846B2 (en) * 1997-09-09 2002-09-03 At&T Corp. Fiber-optic free-space micromachined matrix switches
CN1555339A (zh) * 2001-09-17 2004-12-15 株式会社尼康 微致动器、微致动器装置、光学开关以及光学开关阵列
CN1847916A (zh) * 2005-04-15 2006-10-18 富士通株式会社 微移动元件及光开关器件
WO2016038984A1 (ja) * 2014-09-09 2016-03-17 日立オートモティブシステムズ株式会社 物理量センサ

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030122206A1 (en) * 2001-11-09 2003-07-03 Amal Bhattarai Multi-chip module integrating MEMS mirror array with electronics
KR20050073147A (ko) 2004-01-09 2005-07-13 삼성전기주식회사 광 스위치 및 그 제조방법
US7659617B2 (en) * 2006-11-30 2010-02-09 Tessera, Inc. Substrate for a flexible microelectronic assembly and a method of fabricating thereof
JP5391599B2 (ja) * 2008-07-14 2014-01-15 オムロン株式会社 基板接合方法及び電子部品
WO2012115333A1 (ko) * 2011-02-24 2012-08-30 단국대학교 산학협력단 기판 관통 구조물 및 이의 제조방법, 기판 관통 구조물을 포함하는 소자의 패키지 및 이의 제조 방법
US8497148B2 (en) * 2011-07-22 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS devices and methods of forming same
US20130100145A1 (en) 2011-10-21 2013-04-25 Qualcomm Mems Technologies, Inc. Electromechanical systems device
US9868631B2 (en) * 2013-09-16 2018-01-16 Ciena Corporation Systems and methods for MEMS-based cross-point electrical switching

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6445846B2 (en) * 1997-09-09 2002-09-03 At&T Corp. Fiber-optic free-space micromachined matrix switches
US6396976B1 (en) * 1999-04-15 2002-05-28 Solus Micro Technologies, Inc. 2D optical switch
CN1555339A (zh) * 2001-09-17 2004-12-15 株式会社尼康 微致动器、微致动器装置、光学开关以及光学开关阵列
CN1847916A (zh) * 2005-04-15 2006-10-18 富士通株式会社 微移动元件及光开关器件
WO2016038984A1 (ja) * 2014-09-09 2016-03-17 日立オートモティブシステムズ株式会社 物理量センサ

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3597591A4

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