WO2018179352A1 - 半導体装置の製造方法および記録媒体 - Google Patents
半導体装置の製造方法および記録媒体 Download PDFInfo
- Publication number
- WO2018179352A1 WO2018179352A1 PCT/JP2017/013632 JP2017013632W WO2018179352A1 WO 2018179352 A1 WO2018179352 A1 WO 2018179352A1 JP 2017013632 W JP2017013632 W JP 2017013632W WO 2018179352 A1 WO2018179352 A1 WO 2018179352A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- silicon film
- plasma generation
- substrate processing
- plasma
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
- H01J37/3211—Antennas, e.g. particular shapes of coils
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32174—Circuits specially adapted for controlling the RF discharge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
- H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32105—Oxidation of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32138—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
- H05H1/00—Generating plasma; Handling plasma
- H05H1/24—Generating plasma
- H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
Definitions
- the present invention relates to a semiconductor device manufacturing method and a recording medium.
- a process of etching the concave structure such as a trench structure formed on the substrate surface and processing the concave structure is performed. May be.
- the surface layer damaged by the etching process may be oxidized to form a sacrificial oxide film, and the step of removing the damaged layer may be further performed by removing the sacrificial oxide film.
- a damage layer is formed on the inner surface of the concave structure.
- the surface layer on the inner surface of the concave structure is oxidized to form a sacrificial oxide film.
- the thickness of the sacrificial oxide film is concave due to the microloading effect and the substrate dependency such as the surface orientation dependency. In some cases, desired in-plane film thickness uniformity (step coverage) within the structure cannot be obtained.
- the present invention provides a technique for forming a sacrificial oxide film with good in-plane film thickness uniformity on the inner surface of a concave structure on a substrate surface in a semiconductor device manufacturing process.
- a substrate processing chamber having a plasma generation space in which a supplied oxygen-containing gas is plasma-excited and a substrate processing space that communicates with the plasma generation space and in which a substrate is disposed during substrate processing.
- a coil that is provided on the outer periphery of the plasma generation space and has an electrical length that is an integral multiple of the wavelength of the applied high-frequency power, and a substrate that is arranged at a position below the lower end of the coil.
- a step of providing a substrate processing apparatus comprising a mounting table, and a substrate having a concave structure formed of a silicon film, wherein an inner surface of the concave structure is subjected to an etching process with respect to the inside of the concave structure.
- the processing apparatus 100 includes a processing furnace 202 that performs plasma processing on the wafer 200.
- the processing furnace 202 includes a processing container 203 that constitutes a processing chamber 201.
- the processing container 203 includes a dome-shaped upper container 210 that is a first container and a bowl-shaped lower container 211 that is a second container.
- the processing chamber 201 is formed by covering the upper container 210 on the lower container 211.
- a gate valve 244 is provided on the lower side wall of the lower container 211.
- the gate valve 244 When the gate valve 244 is open, the wafer 200 can be loaded into the processing chamber 201 via the loading / unloading port 245. Alternatively, the wafer 200 can be carried out of the processing chamber 201 via the loading / unloading port 245.
- the gate valve 244 When the gate valve 244 is closed, the gate valve 244 serves as a gate valve that maintains airtightness in the processing chamber 201.
- the processing chamber 201 has a plasma generation space 201a around which a coil 212 is provided as will be described later, and a substrate processing space 201b that communicates with the plasma generation space 201a and in which the wafer 200 is processed.
- the plasma generation space 201a is a space where plasma is generated, and refers to a space above the lower end of the coil 212 (one-dot chain line in FIG. 1) in the processing chamber, for example.
- the substrate processing space 201b is a space where the substrate is processed with plasma, and is a space below the lower end of the coil 212.
- a susceptor 217 In the center of the bottom side of the processing chamber 201, a susceptor 217 is disposed as a substrate placement portion on which the wafer 200 is placed.
- a heater 217b as a heating mechanism is integrally embedded in the susceptor 217.
- the heater 217 b is configured to be able to heat the surface of the wafer 200 from, for example, room temperature to about 700 ° C. when electric power is supplied via the heater power adjustment mechanism 276.
- the susceptor 217 is electrically insulated from the lower container 211.
- An impedance adjustment electrode 217c is provided inside the susceptor 217.
- the impedance adjustment electrode 217c is grounded via an impedance variable mechanism 275 as an impedance adjustment unit.
- the variable impedance mechanism 275 includes a coil and a variable capacitor. By controlling the inductance and resistance of the coil and the capacitance value of the variable capacitor, the impedance is changed within a range from about 0 ⁇ to the parasitic impedance value of the processing chamber 201. It is configured to be able to. Accordingly, the potential (bias voltage) of the wafer 200 can be controlled via the impedance adjustment electrode 217c and the susceptor 217.
- the substrate mounting portion according to this embodiment is mainly configured by the susceptor 217, the heater 217b, and the electrode 217c.
- the susceptor 217 is provided with a susceptor elevating mechanism 268 that elevates and lowers the susceptor 217 within the substrate processing space 201b.
- the susceptor 217 is provided with through holes 217 a, while the bottom surface of the lower container 211 is provided with at least three wafer push-up pins 266 at positions facing the through holes 217 a. When the susceptor 217 is lowered, the wafer push-up pins 266 penetrate the through holes 217a.
- the susceptor 217, the heater 217b, and the impedance adjustment electrode 217c constitute the substrate mounting portion according to the present embodiment.
- a gas supply head 236 is provided above the processing chamber 201, that is, above the upper container 210.
- the gas supply head 236 includes a cap-shaped lid 233, a gas introduction port 234, a buffer chamber 237, an opening 238, a shielding plate 240, and a gas outlet 239, and the reaction gas is introduced into the processing chamber 201. It is configured so that it can be supplied.
- the buffer chamber 237 has a function as a dispersion space for dispersing the reaction gas introduced from the gas introduction port 234.
- the gas inlet 234 has a downstream end of a gas supply pipe 232a that supplies oxygen (O 2 ) gas as an oxygen-containing gas and a downstream of a gas supply pipe 232b that supplies hydrogen (H 2 ) gas as a hydrogen-containing gas.
- the end and a gas supply pipe 232c that supplies argon (Ar) gas as an inert gas are connected so as to merge.
- the gas supply pipe 232a is provided with an O 2 gas supply source 250a, a mass flow controller (MFC) 252a as a flow rate control device, and a valve 253a as an on-off valve in order from the upstream side.
- MFC mass flow controller
- the gas supply pipe 232b is provided with an H 2 gas supply source 250b, an MFC 252b as a flow rate control device, and a valve 253b as an on-off valve in order from the upstream side.
- the gas supply pipe 232c is provided with an Ar gas supply source 250c, an MFC 252c as a flow rate control device, and a valve 253c as an on-off valve in order from the upstream side.
- a valve 243a is provided on the downstream side where the gas supply pipe 232a, the gas supply pipe 232b, and the supply pipe 232c merge, and is connected to the upstream end of the gas inlet 234.
- the gas flow rate is adjusted by the MFCs 252a, 252b, and 252c, and the oxygen-containing gas and the hydrogen gas-containing gas are passed through the gas supply pipes 232a, 232b, and 232c.
- a reactive gas such as an inert gas can be supplied into the processing chamber 201.
- the gas supply head 236 (the lid 233, the gas inlet 234, the buffer chamber 237, the opening 238, the shielding plate 240, the gas outlet 239), the gas supply pipe 232a, the MFC 252a, and the valves 253a and 243a are used to provide oxygen according to the present embodiment.
- a contained gas supply system is configured.
- the hydrogen supply system according to the present embodiment is configured by the gas supply head 236, the gas supply pipe 232b, the MFC 252b, and the valves 253b and 243a.
- the inert gas supply system is configured by the gas supply head 236, the gas supply pipe 232c, the MFC 252c, and the valves 253c and 243a.
- a gas supply unit is configured by a hydrogen-containing gas supply system, an oxygen-containing gas supply system, and an inert gas supply system.
- each of the gas supply system and the gas supply unit described above can be regarded as including a gas supply source of the gas to be supplied.
- a gas exhaust port 235 for exhausting the reaction gas from the processing chamber 201 is provided on the side wall of the lower container 211.
- the upstream end of the gas exhaust pipe 231 is connected to the gas exhaust port 235.
- the gas exhaust pipe 231 is provided with an APC (Auto Pressure Controller) valve 242 as a pressure regulator, a valve 243b as an on-off valve, and a vacuum pump 246 as a vacuum exhaust device in order from the upstream side.
- APC Auto Pressure Controller
- the gas exhaust port 235, the gas exhaust pipe 231, the APC valve 242, and the valve 243b constitute the exhaust unit according to the present embodiment.
- a spiral resonance coil 212 is provided on the outer periphery of the processing chamber 201, that is, outside the side wall of the upper container 210 so as to surround the processing chamber 201.
- An RF sensor 272, a high frequency power supply 273 and a frequency matching unit 274 are connected to the resonance coil 212.
- the high frequency power supply 273 supplies high frequency power to the resonance coil 212.
- the RF sensor 272 is provided on the output side of the high frequency power supply 273.
- the RF sensor 272 monitors information on high-frequency traveling waves and reflected waves that are supplied.
- the frequency matching unit (frequency control unit) 274 controls the high frequency power supply 273 so as to minimize the reflected wave based on the information of the reflected wave monitored by the RF sensor 272, and performs frequency matching.
- Both ends of the resonance coil 212 are electrically grounded, but at least one end of the resonance coil 212 finely adjusts the electrical length of the resonance coil during initial installation of the apparatus or when processing conditions are changed, In order to make the resonance characteristic substantially equal to that of the high-frequency power source 273, it is grounded via the movable tap 213.
- Reference numeral 214 in FIG. 1 indicates the other fixed ground.
- a power feeding unit is configured by a movable tap 215 between the grounded ends of the resonance coil 212. ing.
- the shielding plate 223 shields the leakage of electromagnetic waves to the outside of the resonance coil 212 and forms a capacitance component necessary for constituting a resonance circuit between the resonance coil 212 and the resonance coil 212.
- the shielding plate 223 is arranged at a distance of, for example, about 5 to 150 mm from the outer periphery of the resonance coil 212.
- the resonance coil 212, the RF sensor 272, and the frequency matching unit 274 constitute the plasma generation unit according to the present embodiment.
- the resonance coil 212 forms a standing wave of a predetermined wavelength, the winding diameter, the winding pitch, and the number of turns are set so as to resonate in all wavelength modes. That is, the electrical length of the resonance coil 212 is set to an integral multiple of one wavelength at a predetermined frequency of the power supplied from the high frequency power supply 273.
- the resonance coil 212 has a frequency of 800 kHz to 50 MHz, a power of 0.5 to 5 kW, and more preferably 1.
- the plasma generating space has an effective sectional area of 50 to 300 mm 2 and a coil diameter of 200 to 500 mm so that a magnetic field of about 0.01 to 10 gauss can be generated by a high frequency power of 5 to 3.5 kW. It is wound about 2 to 60 times on the outer peripheral side of the room forming 201a.
- the high frequency power supply 273 includes a power supply control means including a high frequency oscillation circuit and a preamplifier for defining an oscillation frequency and an output, and an amplifier for amplifying to a predetermined output.
- the power control means controls the amplifier based on output conditions relating to the frequency and power set in advance through the operation panel, and the amplifier supplies constant high frequency power to the resonance coil 212 via the transmission line.
- the frequency matching unit 274 detects the reflected wave power from the resonance coil 212 when plasma is generated, and the preset frequency is set so that the reflected wave power is minimized. Increase or decrease the oscillation frequency.
- the frequency matching unit 274 includes a frequency control circuit that corrects a preset oscillation frequency, and detects the reflected wave power in the transmission line on the output side of the amplifier of the high frequency power supply 273, An RF sensor 272 that feeds back a voltage signal to the frequency control circuit is interposed.
- the frequency control circuit oscillates at the no-load resonance frequency of the resonance coil 212 before plasma lighting, and oscillates at a frequency obtained by increasing or decreasing the preset frequency so that the reflected power is minimized after plasma lighting. As a result, a frequency signal is given to the high frequency power supply 273 so that the reflected wave in the transmission line becomes zero.
- the resonance coil 212 is more accurate.
- the controller 221 as a control unit is configured as a computer including a CPU 221a, a RAM 221b, a storage device 221c, and an I / O port 221d.
- the RAM 221b, the storage device 221c, and the I / O port 221d are configured to exchange data with the CPU 221a via the internal bus 221e.
- An input / output device 225 may be connected to the controller 221. Further, for example, a display or the like may be connected to the controller 221 as a display unit.
- the storage device 221c includes, for example, a flash memory, an HDD, a CD-ROM, and the like.
- a control program that controls the operation of the substrate processing apparatus 100, a process recipe that describes the procedure and conditions of the substrate processing, and the like are stored in a readable manner.
- the process recipe is a combination of functions so that a predetermined result can be obtained by causing the controller 221 to execute each procedure in a substrate processing step to be described later, and functions as a program.
- the process recipe, the control program, and the like are collectively referred to as simply a program.
- the RAM 221b is configured as a memory area in which a program, data, and the like read by the CPU 221a are temporarily stored.
- the I / O port 221d includes MFCs 252a to 252c, valves 253a to 253c, 243a and 243b, gate valve 244, APC valve 242, vacuum pump 246, heater 217b, RF sensor 272, high frequency power supply 273, frequency matching unit 274, and susceptor lifting / lowering. It is connected to the mechanism 268, the impedance variable mechanism 275, and the like.
- the CPU 221a is configured to read and execute a control program from the storage device 221c, and to read a process recipe from the storage device 221c in response to an operation command input from the input / output device 225 or the like. As shown in FIG. 1, the CPU 221a adjusts the opening degree of the APC valve 242, the opening / closing operation of the valve 243b, the start / stop of the vacuum pump 246, and the susceptor lifting / lowering mechanism in accordance with the contents of the read process recipe.
- the controller 221 is not limited to being configured as a dedicated computer, and may be configured as a general-purpose computer.
- an external storage device for example, magnetic tape, magnetic disk, optical disk, magneto-optical disk, semiconductor memory
- the controller 221 according to the present embodiment can be configured.
- the storage device 221c and the external storage device 226 are configured as computer-readable recording media. Hereinafter, these are collectively referred to simply as a recording medium.
- recording medium may include only the storage device 221c, only the external storage device 226, or both.
- the substrate processing steps (S10 to S30) according to the present embodiment shown in FIG. 4 are performed as one step of a manufacturing process of a semiconductor device such as a flash memory, for example. Further, in the oxidation treatment step S20 according to the present embodiment, the trench 301 as the concave structure shown in FIG. 6B is subjected to an oxidation treatment to form a sacrificial oxide film 305.
- (A) Etching process S10 prior to the execution of the oxidation treatment step S20 according to the present embodiment, a step of performing an etching treatment on the inside of the trench 301 shown in FIG.
- the trench 301 is formed by forming an amorphous silicon film (a-Si) film 303 as a silicon film in a trench formed in a silicon nitride film (SiN film) 302 as a base film. That is, the trench 301 is formed by the a-Si film 303.
- anisotropic dry etching or plasma etching for forming a hole or a groove penetrating the bottom of the trench 301 is performed.
- a penetrating hole or groove is formed at the bottom of the trench 301 as shown in FIG.
- the surface (exposed surface) of the a-Si film 303 and the surface of the SiN film 302 exposed by the etching process are damaged and the surface shape becomes rough.
- ions of the etching gas collide with the surface of the a-Si film 303 to generate crystal defects, or elements contained in the etching gas are used as impurities as the a-Si film 303 or the SiN film.
- the surface layer (exposed layer) of the a-Si film 303 and the SiN film 302 is altered by being added to the film from the surface of 302.
- a damage layer 304 which is an altered layer having a rough surface shape, is formed on the surface layer of the a-Si film 303 and the surface layer of the SiN film 302.
- a gas used for dry etching for example, a chlorine-based gas (Cl 2 , BCl 3, etc.) or a fluorine-based gas (F 2 , CF 4 , SF 6, etc.) is used. Added as an impurity.
- reaction products desorbed from the a-Si film 303 and the SiN film 302 by the etching treatment may adhere to the damaged layer 304. Such a deposit can be considered to be included in the damage layer 304.
- the damaged layer with a rough surface formed on the surface layer of the a-Si film 303 is removed because it deteriorates the electrical characteristics (for example, electron mobility) of the a-Si film 303 constituting the semiconductor device. Is desirable. Therefore, in the oxidation process according to the present embodiment, the sacrificial oxide film 305 is formed by performing an oxidation process on the trench 301 in which the damage layer 304 is formed, and then removed (etched back) to thereby remove the damage layer. 304 is removed. Thus, the a-Si film 303 and the SiN film 302 having a flat surface from which the damaged layer 304 has been removed can be obtained.
- the oxidation treatment step S20 is performed by the processing apparatus 100 described above. In the following description, the operation of each part constituting the processing apparatus 100 is controlled by the controller 221.
- the trench 301 formed on the surface of the wafer 200 processed in the oxidation processing step S20 according to the present embodiment has a shape with a high aspect ratio.
- high aspect ratio means a shape that satisfies D / H ⁇ 20, for example, where the depth of the trench is D, the width is H, and the aspect ratio is D / H.
- the crystal orientation may differ depending on the position.
- the crystal orientations may be different from each other.
- the inner surface of the trench 301 (including the exposed surface of the SiN film 302 exposed by the etching process) is oxidized at least by the thickness of the damaged layer 304. That is, the thickness of the sacrificial oxide film 305 is formed to be at least larger than the thickness of the damaged layer 304.
- high in-plane film thickness uniformity (step coverage) in the trench may be required. For example, when the a-Si film 303 is used as a channel layer of a transistor, it is desirable that the film thickness is thin and uniform.
- the processing temperature for forming the sacrificial oxide film 305 is 600. It is calculated
- wet etching rate (wet etching rate: WER) increases as the oxide film is formed under a low temperature condition. Therefore, in consideration of removing the sacrificial oxide film 305 by a technique such as wet etching after this step, it is more preferable that the processing temperature for forming the sacrificial oxide film 305 is as low as possible.
- a method for forming the sacrificial oxide film for example, there is a thermal oxidation method (thermal radical oxidation method) in which the wafer is heated to 700 to 1100 ° C. and the wafer is oxidized using oxygen gas or water vapor gas.
- thermal oxidation method thermal radical oxidation method
- the thermal oxidation method is applied to the trench 301 having a high aspect ratio shape as in the present embodiment, the microloading effect in the depth direction of the trench and the surface are related to the thickness of the sacrificial oxide film. It is difficult to obtain a desired in-plane film thickness uniformity (step coverage) in the trench due to the influence of the substrate dependency such as the orientation dependency.
- the sacrificial oxide film 305 is formed so as to satisfy the above-described requirements by performing the following steps (S110 to S160).
- the wafer 200 is loaded into the processing chamber 201. Specifically, the susceptor elevating mechanism 268 lowers the susceptor 217 to the transfer position of the wafer 200 so that the wafer push-up pins 266 protrude from the susceptor 217 surface. Subsequently, the gate valve 244 is opened, and the wafer 200 is placed on the wafer push-up pins 266 using a transfer mechanism not shown in the drawing. Then, the susceptor elevating mechanism 268 raises the susceptor 217 so as to be at a predetermined position between the lower end 203a of the resonance coil 212 and the upper end 245a of the loading / unloading port 245. As a result, the wafer 200 is supported on the upper surface of the susceptor 217.
- the wafer 200 is heated.
- the heater 217b is preheated, and the loaded wafer 200 is held on the susceptor 217 in which the heater 217b is embedded, so that, for example, room temperature to 600 ° C., preferably 100 to 600 ° C., more preferably 200 to 550
- the wafer 200 is heated to a predetermined value within a range of ° C.
- the temperature is preferably 550 ° C. or lower in order to suppress the crystallinity change of the a-Si film 303.
- the lower the processing temperature in the oxidation treatment the lower the quality of the oxide film formed.
- the oxide film formed in this oxidation treatment step is formed for the purpose of use as a sacrificial oxide film, the film quality of the oxide film is not required as compared with other uses. Therefore, in the oxidation process in this embodiment, the process under a low temperature condition is allowed.
- the inside of the processing chamber 201 is evacuated by the vacuum pump 246 through the gas exhaust pipe 231 to set the pressure in the processing chamber 201 to a predetermined value.
- the vacuum pump 246 is operated until at least a substrate unloading step S160 described later is completed.
- processing gas supply step S130 supply of a mixed gas of an O 2 gas that is an oxygen-containing gas and an H 2 gas that is a hydrogen-containing gas is started as a processing gas (reaction gas). Specifically, the supply of O 2 gas into the processing chamber 201 via the buffer chamber 237 is started while the valves 243a and 253a are opened and the flow rate is controlled by the MFC 252a. At the same time, the supply of H 2 gas into the processing chamber 201 via the buffer chamber 237 is started while the valve 253b is opened and the flow rate is controlled by the MFC 252b.
- Ar gas as an additive gas may be supplied from the Ar gas supply source 250c to the buffer chamber 237 via the MFC 252c, the valve 253c, and the gas supply pipe 232c.
- the total flow rate of the mixed gas of O 2 gas and H 2 gas is, for example, 100 to 3000 sccm, and the supply flow rate ratio of O 2 gas and H 2 gas is in the range of 5:95 to 99: 1.
- the oxidation rate can be maximized by setting the supply flow rate ratio to around 95: 5.
- the supply flow rate ratio in the range of 5:95 to 50:50, even when a metal film or the like is formed on the wafer 200, the oxidation of the metal film is suppressed and it is an object to be oxidized.
- the inner surface of the trench 301 can be selectively oxidized.
- the total flow rate is 1000 sccm
- the supply flow rate ratio is 95: 5.
- a mixed gas of an oxygen-containing gas and a hydrogen-containing gas is used as the processing gas.
- an oxygen-containing gas for example, O 2 gas
- the opening degree of the APC valve 242 is adjusted so that the pressure in the processing chamber 201 becomes a predetermined pressure of, for example, 10 Pa to 250 Pa, more preferably 100 Pa to 250 Pa (150 Pa in the present embodiment). Then, the processing chamber 201 is exhausted. In this manner, the supply of the mixed gas is continued until the plasma processing step S140 described later is completed while the processing chamber 201 is appropriately evacuated. Note that before supplying the mixed gas, H 2 gas may be introduced into the processing chamber 201 so that the inside of the processing chamber 201 has a predetermined pressure. By doing so, it is possible to suppress the occurrence of rapid oxidation at the start of the mixed gas supply.
- Pulsma treatment step S140 After the introduction of the mixed gas has started and a predetermined time has elapsed (for example, after several seconds have elapsed), when the pressure in the processing chamber 201 has stabilized, application of high frequency power to the resonance coil 212 from the high frequency power supply 273 via the RF sensor 272 To start.
- the frequency and power of the high-frequency power in this embodiment are 27.12 MHz and 2.5 kW.
- the power supply control means attached to the high-frequency power supply 273 compensates for the shift of the resonance point in the resonance coil 212 due to fluctuations in the capacitive coupling and inductive coupling of the plasma and maintains the resonance state, and forms a standing wave more accurately. To do.
- the capacitive coupling with the processing chamber wall and the substrate mounting table is caused by the induction electromagnetic field formed in the plasma generation space 201a at a height position corresponding to the electrical midpoint of the resonance coil 212 of the plasma generation space 201a.
- a donut-shaped induction plasma with very little electrical potential is excited.
- O 2 gas and H 2 gas are activated and dissociated by the excited plasma, and oxygen active species (radical) including oxygen (O) and hydrogen (H), oxygen ions, hydroxyl active species (radical), hydrogen activity Generates reactive species such as seeds (radicals) and hydrogen ions.
- oxygen active species including oxygen (O) and hydrogen (H)
- oxygen ions oxygen ions
- hydroxyl active species (radical) oxygen activity
- hydrogen activity Generates reactive species such as seeds (radicals) and hydrogen ions.
- a rare gas Ar gas
- the rare gas contributes to stabilization of the plasma discharge.
- the reactive species containing oxygen is supplied to the exposed surface in the trench 301, and the
- the present embodiment since plasma having an extremely low electric potential is generated, generation of a sheath on the wall of the plasma generation space 201a and the substrate mounting table can be prevented. Accordingly, ions in the plasma are not accelerated, and active species in the mixed gas and ions in an unaccelerated state are uniformly supplied into the trench 301 (particularly in the depth direction), so that the depth in the trench 301 is increased. An oxide film (sacrificial oxide film 305) with extremely good in-plane film thickness uniformity in the direction can be formed.
- the oxidation treatment of the surface layer in the trench 301 is performed using the reactive species generated by the plasma generation unit according to the present embodiment
- the magnitude of the activation energy related to the oxidation reaction is different from other plasma excitation methods (for example, It is lower than the activation energy in the case of performing oxidation treatment using a reactive species generated by microwave excitation or the like) or thermal excitation.
- this embodiment is particularly suitable when oxidizing the inside of the trench 301 with good in-plane film thickness uniformity.
- the output of the power from the high frequency power supply 273 is stopped and the plasma discharge in the processing chamber 201 is stopped. Further, the valves 253a and 253b are closed, and the supply of the mixed gas into the processing chamber 201 is stopped. Thus, the plasma processing step S140 is completed.
- the oxidation treatment in this step is preferably continued until at least the thickness of the sacrificial oxide film 305 becomes equal to or greater than the thickness of the damaged layer 304 and the damaged layer 304 is completely altered (modified) into the sacrificial oxide film 305.
- the sacrificial oxide film 305 is removed (etch back) by mainly performing wet etching.
- wet etching for example, an aqueous solution of HF (hydrofluoric acid), NH4F (ammonium fluoride), or the like is used as a chemical solution, and the wafer 200 is immersed in this chemical solution.
- the sacrificial oxide film 305 which is a silicon oxide film, is selectively removed by etching using these chemicals, and as shown in FIG. 5D, the a-Si film 303 and the SiN film from which the damage layer 304 has been removed.
- a trench 301 constituted by 302 is formed.
- the sacrificial oxide film 305 is formed with good film thickness uniformity on the inner surface of the trench 301, the thickness of the a-Si film 303 varies even after the etching process S 10 and the etch back process 30. It is possible to obtain desired electrical characteristics without the occurrence of.
- the present invention is not limited to the a-Si film, but a polysilicon (Poly-Si) film, a crystalline silicon (c-Si) film, or the like. Even when another silicon film is formed in the trench, the oxidation treatment process according to this embodiment can be applied.
- the trench structure is shown as the concave structure formed on the wafer 200.
- the substrate processing step according to the present embodiment has a concave structure such as a hole or a through hole having the same high aspect ratio. It can also be applied to.
- an etching technique other than the technique shown in the present embodiment can be applied.
- an etching technique other than the technique shown in this embodiment can be applied.
- a technique for forming a sacrificial oxide film with good in-plane film thickness uniformity on the inner surface of the concave structure on the substrate surface in a semiconductor device manufacturing process is provided.
Abstract
Description
(1)基板処理装置の構成
本発明の実施形態に係る基板処理装置について、図1から図3を用いて以下に説明する。
処理装置100は、ウエハ200をプラズマ処理する処理炉202を備えている。処理炉202は、処理室201を構成する処理容器203を備えている。処理容器203は、第1の容器であるドーム型の上側容器210と、第2の容器である碗型の下側容器211とを備えている。上側容器210が下側容器211の上に被さることにより、処理室201が形成される。
処理室201の底側中央には、ウエハ200を載置する基板載置部としてのサセプタ217が配置されている。サセプタ217の内部には、加熱機構としてのヒータ217bが一体的に埋め込まれている。ヒータ217bは、ヒータ電力調整機構276を介して電力が供給されると、ウエハ200表面を例えば室温から700℃程度まで加熱することができるように構成されている。
処理室201の上方、つまり上側容器210の上部には、ガス供給ヘッド236が設けられている。ガス供給ヘッド236は、キャップ状の蓋体233と、ガス導入口234と、バッファ室237と、開口238と、遮蔽プレート240と、ガス吹出口239とを備え、反応ガスを処理室201内へ供給できるように構成されている。バッファ室237は、ガス導入口234より導入される反応ガスを分散する分散空間としての機能を持つ。
下側容器211の側壁には、処理室201内から反応ガスを排気するガス排気口235が設けられている。ガス排気口235には、ガス排気管231の上流端が接続されている。ガス排気管231には、上流側から順に圧力調整器としてのAPC(Auto Pressure Controller)バルブ242、開閉弁としてのバルブ243b、真空排気装置としての真空ポンプ246が設けられている。
処理室201の外周部、すなわち上側容器210の側壁の外側には、処理室201を囲うように螺旋状の共振コイル212が設けられている。共振コイル212には、RFセンサ272、高周波電源273と周波数整合器274が接続される。
図3に示すように、制御部としてのコントローラ221は、CPU221a、RAM221b、記憶装置221c、I/Oポート221dを備えたコンピュータとして構成されている。RAM221b、記憶装置221c、I/Oポート221dは、内部バス221eを介して、CPU221aとデータ交換可能なように構成されている。コントローラ221には、入出力装置225が接続されていてもよい。また、コントローラ221には、表示部として、例えばディスプレイ等が接続されていてもよい。
次に、本実施形態に係る基板処理工程について図4~6を用いて説明する。図4に示す本実施形態に係る基板処理工程(S10~S30)は、例えばフラッシュメモリ等の半導体デバイスの製造工程の一工程として実施される。また、本実施形態に係る酸化処理工程S20では、図6(b)に示す凹状構造としてのトレンチ301に対して酸化処理を施し、犠牲酸化膜305を形成する。
ここで、本実施形態に係る酸化処理工程S20の実施に先立ち、図6(a)に示すトレンチ301の内側に対してエッチング処理を行う工程が実施される。トレンチ301は、下地膜であるシリコン窒化膜(SiN膜)302に形成されたトレンチ内に、シリコン膜としてのアモルファスシリコン膜(a-Si)膜303が形成されることにより形成されている。すなわち、a-Si膜303によりトレンチ301が形成されている。上述のエッチング処理では、トレンチ301の底部を貫通するホール又は溝を形成するための異方性のドライエッチング(又はプラズマエッチング)が実施される。
これにより、a-Si膜303の表層やSiN膜302の表層には、表面形状が荒れた変質層であるダメージ層304が形成される。
本実施形態に係る酸化処理工程S20は、上述の処理装置100により実施される。なお以下の説明において、処理装置100を構成する各部の動作は、コントローラ221により制御される。本実施形態に係る酸化処理工程S20で処理されるウエハ200の表面に形成されたトレンチ301は、アスペクト比が高い形状を有している。ここで、アスペクト比の高いとは、トレンチの深さをD、幅をH、アスペクト比をD/Hとした場合、例えば、D/H≧20となるような形状を言う。また、形成されたトレンチ301内面に露出したダメージ層305の表面内では、その位置によって結晶方位が異なることがある。例えば、図6(b)に示す深さ方向(垂直方向)に広がる面と、トレンチ301の底部(ここではエッチング処理前の底部の位置)でトレンチ301の幅方向(水平方向)に広がる面では、互いに結晶方位が異なることがある。
まずは、上記のウエハ200を処理室201内に搬入する。具体的には、サセプタ昇降機構268がウエハ200の搬送位置までサセプタ217を下降させて、ウエハ突き上げピン266がサセプタ217表面よりも突出した状態とする。続いて、ゲートバルブ244を開き、図中省略の搬送機構を用いてウエハ突上げピン266上にウエハ200を載置する。そして、サセプタ昇降機構268が、共振コイル212の下端203aと搬入出口245の上端245aの間の所定の位置となるよう、サセプタ217を上昇させる。その結果、ウエハ200はサセプタ217の上面に支持される。
続いて、ウエハ200の昇温を行う。ヒータ217bは予め加熱されており、ヒータ217bが埋め込まれたサセプタ217上に、搬入されたウエハ200を保持することで、例えば常温~600℃、好ましくは100~600℃、より好ましくは200~550℃の範囲内の所定値にウエハ200を加熱する。特に、a-Si膜303の結晶性変化を抑制するため、550℃以下であることが好ましい。
また、一般的に、酸化処理における処理温度は低くなるほど、形成される酸化膜の膜質が低下する傾向にある。一方、本酸化処理工程で形成される酸化膜は犠牲酸化膜としての用途を目的として形成されるため、他の用途に比べて酸化膜の膜質を要求されない。従って、本実施形態における酸化処理工程では、低温条件での処理が許容される。
次に、処理ガス(反応ガス)として、酸素含有ガスであるO2ガスと水素含有ガスであるH2ガスとの混合ガスの供給を開始する。具体的には、バルブ243a,253aを開け、MFC252aにて流量制御しながら、バッファ室237を介して処理室201内へのO2ガスの供給を開始する。同時に、バルブ253bを開け、MFC252bにて流量制御しながら、バッファ室237を介して処理室201内へのH2ガスの供給を開始する。また、必要に応じて、Arガス供給源250cからMFC252c、バルブ253c、ガス供給管232cを介してバッファ室237へ添加ガスとしてのArガスを供給してもよい。
また、本酸化処理工程では、処理後に膜中に不純物を残さないことが望ましいため、酸素及び水素のみを含むO2ガスとH2ガスの混合ガスを用いることが好適である。
混合ガスの導入を開始して所定時間経過後(例えば数秒経過後)、処理室201内の圧力が安定したら、共振コイル212に対して高周波電源273からRFセンサ272を介して、高周波電力の印加を開始する。本実施形態における高周波電力の周波数及び電力は、27.12MHz、2.5kWとする。
所定の処理時間が経過して混合ガスの供給を停止したら、ガス排気管231を用いて処理室201内を真空排気する。これにより、処理室201内の混合ガスや、混合ガスが反応した排ガス等を処理室201外へと排気する。その後、APCバルブ242の開度を調整し、処理室201内の圧力を処理室201に隣接する真空搬送室(ウエハ200の搬出先。図示せず)と同じ圧力に調整する。
処理室201内が所定の圧力となったら、サセプタ217をウエハ200の搬送位置まで下降させ、ウエハ突上げピン266上にウエハ200を支持させる。そして、ゲートバルブ244を開き、図中省略の搬送機構を用いてウエハ200を処理室201外へ搬出する。以上により、本実施形態に係る基板処理工程を終了する。
続いて本実施形態に係るエッチバック処理工程S30では、主にウエットエッチングを実施することにより、犠牲酸化膜305の除去(エッチバック)を行う。ウエットエッチングでは、例えば、HF(フッ酸)、NH4F(フッ化アンモニウム)、等の水溶液を薬液として用い、ウエハ200をこの薬液に浸漬する。これらの薬液を用いたエッチングにより、シリコン酸化膜である犠牲酸化膜305を選択的に除去し、図5(d)に示すように、ダメージ層304が除去されたa-Si膜303とSiN膜302により構成されたトレンチ301が形成される。
Claims (10)
- 供給された酸素含有ガスがプラズマ励起されるプラズマ生成空間と、前記プラズマ生成空間に連通し基板処理時に基板が配置される基板処理空間と、を有する基板処理室と、前記プラズマ生成空間の外周に設けられ、印加される高周波電力の波長の整数倍の電気長を有するコイルと、前記基板を前記コイルの下端より下の位置に配置するように構成された基板載置台と、を備えた基板処理装置を提供する工程と、
シリコン膜により形成された凹状構造を有する基板であって、前記凹状構造の内面には、前記凹状構造内に対するエッチング処理によりシリコン膜の表層が変質して生じた変質層が形成されている基板を前記基板載置台に載置する工程と、
前記基板処理室内に前記酸素含有ガスを供給する工程と、
前記コイルに高周波電力を印加して、前記プラズマ生成空間において前記酸素含有ガスのプラズマ生成を開始する工程と、
前記プラズマにより、前記基板の凹状構造内において露出している前記変性層が形成された前記シリコン膜の表面を酸化する工程と、を有する半導体装置の製造方法。 - 前記シリコン膜の表面を酸化する工程において前記シリコン膜の表層が酸化されて形成されたシリコン酸化膜を除去する工程を更に有する、
請求項1記載の半導体装置の製造方法。 - 前記シリコン膜の表面を酸化する工程では、全ての前記変性層が酸化されてシリコン酸化膜が形成される、請求項1記載の半導体装置の製造方法。
- 前記シリコン膜の表面を酸化する工程では、前記シリコン膜の表層が改質されて形成されるシリコン酸化膜の厚さが前記凹状構造内において均一になるように、前記シリコン膜の表面を酸化する、請求項3記載の半導体装置の製造方法。
- 前記シリコン膜はアモルファスシリコン膜である、請求項1記載の半導体装置の製造方法。
- 前記シリコン膜の表面を酸化する工程において、前記基板の温度は550℃以下である、請求項5記載の半導体装置の製造方法。
- 前記凹状構造は、アスペクト比が20以上の構造である、請求項1記載の半導体装置の製造方法。
- 前記変性層は、互いに異なる結晶方位を有する複数の露出面を含んでいる、請求項1記載の半導体装置の製造方法。
- 基板上においてシリコン膜により形成された凹状構造の内面に対して、エッチング処理を施す工程と、
供給された酸素含有ガスがプラズマ励起されるプラズマ生成空間と、前記プラズマ生成空間に連通し基板処理時に基板が配置される基板処理空間と、を有する基板処理室と、前記プラズマ生成空間の外周に設けられ、印加される高周波電力の波長の整数倍の電気長を有するコイルと、前記基板を前記コイルの下端より下の位置に配置するように構成された基板載置台と、を備えた基板処理装置を提供する工程と、
前記エッチング処理が施された前記基板であって、前記エッチング処理の際に、前記凹状構造の内面に前記シリコン膜の表層が変質して生じた変質層が形成されている前記基板を、前記基板載置台に載置する工程と、
前記基板処理室内に前記酸素含有ガスを供給する工程と、
前記コイルに高周波電力を印加して、前記プラズマ生成空間において前記酸素含有ガスのプラズマ生成を開始する工程と、
前記プラズマにより、前記基板の凹状構造内において露出している前記変性層が形成された前記シリコン膜の表面を酸化する工程と、
前記シリコン膜の表面を酸化する工程において前記シリコン膜の表層が酸化されて形成されたシリコン酸化膜を除去する工程と、を有する半導体装置の製造方法。 - 供給された酸素含有ガスがプラズマ励起されるプラズマ生成空間と、前記プラズマ生成空間に連通し基板処理時に基板が配置される基板処理空間と、を有する基板処理室と、前記プラズマ生成空間の外周に設けられ、印加される高周波電力の波長の整数倍の電気長を有するコイルと、前記基板を前記コイルの下端より下の位置に配置するように構成された基板載置台と、を備えた基板処理装置において、
シリコン膜により形成された凹状構造を有する基板であって、前記凹状構造の内面には、前記凹状構造内に対するエッチング処理によりシリコン膜の表層が変質して生じた変質層が形成されている基板を前記基板載置台に載置する手順と、
前記基板処理室内に前記酸素含有ガスを供給する手順と、
前記コイルに高周波電力を印加して、前記プラズマ生成空間において前記酸素含有ガスのプラズマ生成を開始する手順と、
前記プラズマにより、前記基板の凹状構造内において露出している前記変性層が形成された前記シリコン膜の表面を酸化する手順と、
をコンピュータにより前記基板処理装置に実行させるプログラムを記録したコンピュータが読み取り可能な記録媒体。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019508121A JP6752357B2 (ja) | 2017-03-31 | 2017-03-31 | 半導体装置の製造方法、基板処理装置およびプログラム |
KR1020197021740A KR102325148B1 (ko) | 2017-03-31 | 2017-03-31 | 반도체 장치의 제조 방법, 기판 처리 장치 및 컴퓨터 프로그램 |
PCT/JP2017/013632 WO2018179352A1 (ja) | 2017-03-31 | 2017-03-31 | 半導体装置の製造方法および記録媒体 |
US16/522,295 US11189483B2 (en) | 2017-03-31 | 2019-07-25 | Method of manufacturing semiconductor device and non-transitory computer-readable recording medium |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2017/013632 WO2018179352A1 (ja) | 2017-03-31 | 2017-03-31 | 半導体装置の製造方法および記録媒体 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/522,295 Continuation US11189483B2 (en) | 2017-03-31 | 2019-07-25 | Method of manufacturing semiconductor device and non-transitory computer-readable recording medium |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2018179352A1 true WO2018179352A1 (ja) | 2018-10-04 |
Family
ID=63674510
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2017/013632 WO2018179352A1 (ja) | 2017-03-31 | 2017-03-31 | 半導体装置の製造方法および記録媒体 |
Country Status (4)
Country | Link |
---|---|
US (1) | US11189483B2 (ja) |
JP (1) | JP6752357B2 (ja) |
KR (1) | KR102325148B1 (ja) |
WO (1) | WO2018179352A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2022047904A (ja) * | 2020-09-14 | 2022-03-25 | 株式会社Kokusai Electric | 半導体装置の製造方法、基板処理装置、およびプログラム |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11587789B2 (en) * | 2020-03-06 | 2023-02-21 | Applied Materials, Inc. | System and method for radical and thermal processing of substrates |
JP7222946B2 (ja) * | 2020-03-24 | 2023-02-15 | 株式会社Kokusai Electric | 半導体装置の製造方法、基板処理装置、およびプログラム |
US11569245B2 (en) * | 2020-10-22 | 2023-01-31 | Applied Materials, Inc. | Growth of thin oxide layer with amorphous silicon and oxidation |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005217202A (ja) * | 2004-01-29 | 2005-08-11 | Fuji Electric Holdings Co Ltd | トレンチ横型半導体装置およびその製造方法 |
JP2007317874A (ja) * | 2006-05-25 | 2007-12-06 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2008182194A (ja) * | 2006-12-27 | 2008-08-07 | Hitachi Kokusai Electric Inc | 半導体装置の製造方法 |
JP2014075579A (ja) * | 2012-09-12 | 2014-04-24 | Hitachi Kokusai Electric Inc | 基板処理装置及び半導体装置の製造方法 |
JP2016105457A (ja) * | 2014-11-19 | 2016-06-09 | 株式会社日立国際電気 | 三次元フラッシュメモリ、ダイナミックランダムアクセスメモリ、半導体装置、半導体装置の製造方法、基板処理装置、ガス供給システムおよびプログラム |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3716007B2 (ja) * | 1995-03-14 | 2005-11-16 | 聯華電子股▲ふん▼有限公司 | 半導体装置の製造方法 |
JP3362588B2 (ja) | 1995-12-18 | 2003-01-07 | 株式会社豊田中央研究所 | 半導体装置の製造方法 |
JP2001351895A (ja) | 2000-06-09 | 2001-12-21 | Denso Corp | 半導体装置の製造方法 |
JP2002343798A (ja) * | 2001-05-18 | 2002-11-29 | Mitsubishi Electric Corp | 配線層のドライエッチング方法、半導体装置の製造方法および該方法によって得られた半導体装置 |
JP5544893B2 (ja) * | 2010-01-20 | 2014-07-09 | 東京エレクトロン株式会社 | 基板処理方法及び記憶媒体 |
CN103730316B (zh) | 2012-10-16 | 2016-04-06 | 中微半导体设备(上海)有限公司 | 一种等离子处理方法及等离子处理装置 |
US9378971B1 (en) * | 2014-12-04 | 2016-06-28 | Lam Research Corporation | Technique to deposit sidewall passivation for high aspect ratio cylinder etch |
-
2017
- 2017-03-31 KR KR1020197021740A patent/KR102325148B1/ko active IP Right Grant
- 2017-03-31 JP JP2019508121A patent/JP6752357B2/ja active Active
- 2017-03-31 WO PCT/JP2017/013632 patent/WO2018179352A1/ja active Application Filing
-
2019
- 2019-07-25 US US16/522,295 patent/US11189483B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005217202A (ja) * | 2004-01-29 | 2005-08-11 | Fuji Electric Holdings Co Ltd | トレンチ横型半導体装置およびその製造方法 |
JP2007317874A (ja) * | 2006-05-25 | 2007-12-06 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2008182194A (ja) * | 2006-12-27 | 2008-08-07 | Hitachi Kokusai Electric Inc | 半導体装置の製造方法 |
JP2014075579A (ja) * | 2012-09-12 | 2014-04-24 | Hitachi Kokusai Electric Inc | 基板処理装置及び半導体装置の製造方法 |
JP2016105457A (ja) * | 2014-11-19 | 2016-06-09 | 株式会社日立国際電気 | 三次元フラッシュメモリ、ダイナミックランダムアクセスメモリ、半導体装置、半導体装置の製造方法、基板処理装置、ガス供給システムおよびプログラム |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2022047904A (ja) * | 2020-09-14 | 2022-03-25 | 株式会社Kokusai Electric | 半導体装置の製造方法、基板処理装置、およびプログラム |
JP7117354B2 (ja) | 2020-09-14 | 2022-08-12 | 株式会社Kokusai Electric | 半導体装置の製造方法、基板処理装置、およびプログラム |
Also Published As
Publication number | Publication date |
---|---|
US20190348282A1 (en) | 2019-11-14 |
JPWO2018179352A1 (ja) | 2019-11-07 |
US11189483B2 (en) | 2021-11-30 |
JP6752357B2 (ja) | 2020-09-09 |
KR102325148B1 (ko) | 2021-11-10 |
KR20190100313A (ko) | 2019-08-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6257071B2 (ja) | 基板処理装置及び半導体装置の製造方法 | |
CN109075071B (zh) | 衬底处理装置、半导体器件的制造方法及记录介质 | |
US11189483B2 (en) | Method of manufacturing semiconductor device and non-transitory computer-readable recording medium | |
JP6285052B2 (ja) | 半導体装置の製造方法、プログラム及び基板処理装置 | |
CN111096082B (zh) | 基板处理装置、半导体装置的制造方法和记录介质 | |
CN110431653B (zh) | 半导体装置的制造方法、记录介质以及基板处理装置 | |
JP6484388B2 (ja) | 半導体装置の製造方法、プログラム及び基板処理装置 | |
JP7165743B2 (ja) | 半導体装置の製造方法、基板処理装置、及びプログラム | |
US10453676B2 (en) | Semiconductor device manufacturing method and recording medium | |
KR102465993B1 (ko) | 기판 처리 장치, 반도체 장치의 제조 방법 및 기록 매체 | |
JP6976279B2 (ja) | 基板処理装置、半導体装置の製造方法及びプログラム | |
KR102452913B1 (ko) | 반도체 장치의 제조 방법, 기판 처리 장치 및 기록 매체 | |
JP7117354B2 (ja) | 半導体装置の製造方法、基板処理装置、およびプログラム | |
JP7203869B2 (ja) | 基板処理装置、半導体装置の製造方法、およびプログラム | |
CN115116826A (zh) | 半导体器件的制造方法、衬底处理方法、记录介质及衬底处理装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 17904147 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2019508121 Country of ref document: JP Kind code of ref document: A |
|
ENP | Entry into the national phase |
Ref document number: 20197021740 Country of ref document: KR Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 17904147 Country of ref document: EP Kind code of ref document: A1 |