WO2018176810A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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WO2018176810A1
WO2018176810A1 PCT/CN2017/106995 CN2017106995W WO2018176810A1 WO 2018176810 A1 WO2018176810 A1 WO 2018176810A1 CN 2017106995 W CN2017106995 W CN 2017106995W WO 2018176810 A1 WO2018176810 A1 WO 2018176810A1
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Prior art keywords
electrode
pixel
forming
source
connection electrode
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PCT/CN2017/106995
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English (en)
French (fr)
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姜涛
万云海
操彬彬
任襄华
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/776,193 priority Critical patent/US11307469B2/en
Publication of WO2018176810A1 publication Critical patent/WO2018176810A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133302—Rigid substrates, e.g. inorganic substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/13625—Patterning using multi-mask exposure
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present disclosure relates to an array substrate, a method of fabricating the same, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the TFT-LCD is the mainstream display method in the current flat panel display market due to its small size, light weight, low power consumption, suitable for preparing large-sized panels and no radiation.
  • the TFT-LCD is mainly composed of a TFT substrate (array substrate) and a CF substrate (color film substrate), wherein the TFT substrate is composed of a certain number of pixel arrays, and each pixel is controlled by one TFT (Thin Film Transistor) to display an image.
  • the pixel array can be completed by repeated film deposition, mask exposure, etching, and the like.
  • the signal line of the TFT is usually made of a metal or an alloy such as Al, Mo, Ni, or Cu.
  • the resistance of Cu metal is 80% of Al.
  • the use of Cu instead of Al metal as the signal line can greatly reduce the RC Delay.
  • the Cu resistance is small, a thin metal wiring can be used, and the film thickness can be compared. Thin, therefore, the Cu process can increase the LCD aperture ratio and significantly reduce the cost.
  • Cu metal has many advantages, the metal activity of Cu is relatively high, it is easy to absorb particles, water vapor and the like cause oxidation, and the process control is relatively difficult. In dry etching, if the process is improperly controlled, it will easily lead to corrosion or oxidation of the Cu surface, resulting in poor contact between Cu and other metals, affecting the LCD display.
  • an array substrate includes: a pixel array, each pixel in the pixel array having a pixel electrode; a transistor array, each transistor in the transistor array having a source; and a connection electrode for The pixel electrode is electrically connected to a corresponding source.
  • each pixel in the pixel array further includes: a common electrode, and the pixel array
  • the common electrodes of the other pixels in the column are electrically connected, wherein the connection electrodes are arranged in the same layer as the common electrode.
  • the source does not overlap the pixel electrode in a direction perpendicular to the substrate.
  • the transistor in the transistor array further has a drain, and a material forming the drain and the source includes copper.
  • a material forming the connection electrode includes indium tin oxide.
  • a display device in another aspect of the present disclosure, includes the array substrate according to the present disclosure as described above. Those skilled in the art can understand that the display device has all the features and advantages of the array substrate described above, and will not be further described herein.
  • the present disclosure provides a method of preparing an array substrate.
  • the method includes: forming a common electrode, a connection electrode, and a gate on a substrate; forming a gate insulating layer; forming an active layer; forming a drain and a source, the source being connected to the connection
  • the electrodes are electrically connected; a pixel electrode is formed, the pixel electrode is electrically connected to the connection electrode, and is electrically connected to the source through the connection electrode.
  • the common electrode and the connection electrode are formed by one patterning process.
  • the method of fabricating an array substrate further includes the step of forming a common electrode line on a side of the common electrode away from the substrate, and the gate and the common electrode line pass a patterning process form.
  • the forming of the active layer includes: forming a semiconductor layer on the gate insulating layer; forming a first via hole such that the connection electrode is exposed at a bottom of the first via hole, and The semiconductor layer is patterned to obtain an active layer, wherein the source is electrically connected to the connection electrode through the first via.
  • the forming the first via hole such that the connection electrode is exposed at the bottom of the first via hole and patterning the semiconductor layer includes: providing a semi-transparent layer on the semiconductor layer a film mask, wherein, in a direction perpendicular to the substrate, a position of the semi-transmissive film mask corresponding to the gate is an opaque region, and a region corresponding to the connecting electrode is a fully transparent region, The remaining area is a semi-transmissive region; the all-transmissive region is etched to form the first via; the semi-transmissive region is removed; and the semiconductor not covered by the opaque region is removed by etching a layer, and then removing the opaque region to form the active layer.
  • the forming the drain and the source before forming the pixel electrode, further comprising: forming a protective layer covering the drain, the active layer, the source, the connection electrode, and the gate insulating layer Providing a mask on the protective layer; etching the protective layer to form a second via, a third via, and a passivation layer; wherein the pixel electrode passes through the second via
  • the connection electrode is electrically connected and electrically connected to the common electrode line through the third via.
  • the second via does not overlap the source in a direction perpendicular to the substrate.
  • FIG. 1 shows a schematic structural view of a conventional array substrate.
  • Figure 2 shows the surface morphology of the Cu metal after etching in the prior art.
  • FIG. 3 shows a schematic structural view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 shows a schematic structural view of an array substrate according to another embodiment of the present disclosure.
  • 5 and 6A to 6H are schematic flow charts showing a method of preparing an array substrate according to an embodiment of the present disclosure.
  • FIG. 7 and 8A to 8K are schematic flow charts showing a method of preparing an array substrate according to another embodiment of the present disclosure.
  • Substrate 101 Common electrode 102: Connection electrode 201: Gate 202: Common electrode line 3: Gate insulating layer 4: Active layer 42: Semiconductor layer 5, 8: Semi-permeable film mask 601: Drain 602: Source 7: Passivation layer 72: Protective layer 9: Pixel electrode 10: Common connection electrode
  • Embodiments of the present disclosure are described in detail below.
  • the embodiments described below are illustrative only and are not to be construed as limiting the disclosure. Where specific techniques or conditions are not indicated in the examples, they are carried out according to the techniques or conditions described in the literature in the art or in accordance with the product specifications. The reagents or instruments used are not indicated by the manufacturer, and are conventional products that can be obtained commercially.
  • the pixel electrode 9 is connected to the source electrode 602 through the a hole
  • the common electrode 101 is connected to the common electrode 101 on the adjacent side through the common electrode line 202 and the common connection electrode 10 in the b hole.
  • the a hole and the b hole are formed by dry etching once, the a hole only needs to be etched through the passivation layer 7, and the b hole is required to simultaneously etch through the passivation layer 7 and the gate insulating layer 3.
  • the via etching usually has an over-etching amount of about 30% to 40%, and the etching time of the b-hole is Benchmark.
  • the over-cut amount of the a-hole will reach 400%-500%. Therefore, after the passivation layer 7 of the a hole is etched, the surface of the metal of the a hole source 602 is etched most of the time, resulting in a relatively large amount of metal surface of the source 602. During dry etching, the longer the surface of the Cu metal is bombarded by the plasma, the greater the damage to the surface of the Cu, for a long time. After the engraving, the Cu surface will oxidize and form a small pit caused by many ion bombardment (the surface morphology of the etched Cu metal is shown in Fig. 2).
  • connection electrode is provided at the same time as the formation of the common electrode, and the pixel electrode is connected to the source through the connection electrode during the via etching, thereby avoiding the source caused by the via etching.
  • the problem of high contact resistance due to the large amount of over-etching at the top of the pole can effectively reduce the contact resistance of the Cu product, prevent flicker due to high contact resistance, poor pixel, etc., and improve yield.
  • an object of the present disclosure to provide an array substrate capable of effectively reducing contact resistance, preventing flicker, reducing pixel defects, or improving production yield.
  • the present disclosure provides an array substrate that can be used in a display device such as a liquid crystal display device or the like.
  • the array substrate includes: a substrate 100, a gate 201, a common electrode 101, a connection electrode 102, a gate insulating layer 3, an active layer 4, a drain 601, a source 602, and The pixel electrode 9, wherein the source electrode 602 and the pixel electrode 9 are electrically connected by the connection electrode 102.
  • a pixel array and a transistor array for controlling the pixel array are formed on the array substrate. Each transistor in the array of transistors can control a corresponding pixel in the array of pixels.
  • substrates that can be employed according to the embodiments of the present disclosure are not particularly limited, and those skilled in the art can flexibly select as needed.
  • substrates that may be employed include, but are not limited to, glass substrates, ceramic substrates, metal substrates or polymer substrates, and the like. As a result, the source is wide, the cost is low, and the use performance is good.
  • the specific material for forming the gate electrode is also not particularly limited, and may be any material for preparing a gate electrode in the art.
  • a conductive material having good conductivity can be selected.
  • Gates are formed, including, for example, but not limited to, metals, doped polysilicon, and the like.
  • connection electrode is disposed in the same layer as the common electrode. Therefore, it can be formed by one-step patterning process, the operation steps are simple, and the development trend of thinning and thinning is facilitated.
  • connection electrode and the common electrode can be performed by forming an electrode layer on one side of the substrate, coating a photoresist on the electrode layer, and exposing the photoresist The light and development processes are then etched by the exposed electrode layer to remove the photoresist to obtain a patterned connecting electrode and a common electrode.
  • the specific material for forming the connection electrode is also not particularly limited as long as it can be prevented from being damaged during the etching step, and has a good conduction effect.
  • the material forming the connection electrode includes indium tin oxide. Thereby, the source and the pixel electrode can be effectively connected without being damaged in the dry etching.
  • the material forming the common electrode is not limited, and those skilled in the art may flexibly select according to needs, such as, but not limited to, indium tin oxide or the like.
  • the common electrode may be disposed in the same layer as the connection electrode, that is, may be formed by one patterning process, and thus, the common electrode and the connection electrode may be formed of the same material.
  • the source does not overlap the pixel electrode in a direction perpendicular to the plane of the substrate.
  • the source is generally connected to the connection electrode through the via hole, and then the pixel electrode is connected to the connection electrode through another via hole, and is disposed perpendicular to the connection electrode.
  • the source and the pixel electrode do not overlap, and when the pixel electrode is connected to the connection electrode, the via etching process does not affect the source, thereby reducing the contact resistance and improving the use of the array substrate. performance.
  • the material forming the drain and the source is also not particularly limited, and those skilled in the art can flexibly select according to actual needs.
  • the material forming the drain and the source may be Includes copper. Therefore, the resistance is small, the RC Delay of the signal line can be greatly reduced, and the thin metal wiring can be used, and the film thickness can be made thinner, thereby increasing the LCD aperture ratio and greatly reducing the cost.
  • the array substrate may further include a common electrode line 202 and a passivation layer 7, wherein the common electrode line 202 is disposed on a side of the common electrode 101 away from the substrate 100, and is connected to the gate 201 is disposed in the same layer; the passivation layer 7 is disposed on the side of the drain 601, the active layer 4, the source 602, the connection electrode 102, and the gate insulating layer 3 away from the substrate 100.
  • the passivation layer can well protect other film layer structures on the array substrate.
  • the array substrate includes a substrate 100, the common electrode 101 and the connection electrode 102 are disposed on one side of the substrate 100, and the common electrode line 202 is disposed at the common electrode 101 away from the substrate
  • One side of the substrate 100 is disposed in the same layer as the gate 201;
  • the gate insulating layer 3 is disposed away from the substrate 100, the gate 201, the connection electrode 102, the common electrode 101, and the common electrode line 202
  • the active layer 4 is disposed on the gate insulation
  • the layer 3 is away from a side of the substrate 100 and overlaps the gate 201 in a direction perpendicular to the plane of the substrate;
  • the drain 601 is disposed on the gate insulating layer 3 and the active a layer 4 is away from a side of the substrate 100;
  • the source 602 is disposed on a side of the gate insulating layer 3, the active layer 4, and the connection electrode 102 away
  • FIG. 1 shows a schematic structural diagram of a pixel unit on an array substrate.
  • One array substrate includes a plurality of pixel units arranged in an array, and the common electrode 101 is connected to a common electrode on an adjacent side. It is meant that the common electrodes in adjacent pixel units are electrically connected to each other through a common connection electrode.
  • the material forming the active layer is not particularly limited, and those skilled in the art can flexibly select as needed.
  • the active layer may be a-Si or indium gallium zinc oxide or the like.
  • a specific material forming the passivation layer is not particularly limited, and may be any material known in the art for preparing a passivation layer.
  • Materials that may be employed in some embodiments of the present disclosure include, but are not limited to, silicon oxide, silicon nitride, and the like. Therefore, the material has a wide range of sources, is easy to process into a film, and can effectively protect other film layers on the array substrate, thereby improving the performance of the array substrate.
  • the material forming the common electrode line is also not particularly limited as long as the conductive requirements are satisfied, and those skilled in the art can flexibly select as needed.
  • the common electrode line may be formed with the gate by one patterning process, and thus, the material forming the common electrode line may be identical to the material forming the gate, and will not be described in detail herein.
  • the present disclosure provides a display device.
  • the display device includes the array substrate described above. Those skilled in the art can understand that the display device has all the features and advantages of the array substrate described above, and will not be further described herein.
  • the specific kind of the display device is not particularly limited and may be any known in the art.
  • the device, the device, and the like having a display function include, but are not limited to, a display panel, a mobile phone, a tablet computer, a computer display, a television, a game machine, a wearable device, and various household, living appliances, and the like having a display function.
  • the display device of the present disclosure further includes the necessary structures and components provided by the conventional display device, and may further include, for example, a housing, a necessary circuit structure, and the like. Too much more details.
  • the present disclosure provides a method of preparing an array substrate. According to an embodiment of the present disclosure, referring to FIG. 5 and FIG. 6A to FIG. 6D, the method includes the following steps:
  • S100 The common electrode 101, the connection electrode 102, and the gate electrode 201 are sequentially formed on one side of the substrate 100, and a schematic structural view is shown in FIG. 6A.
  • a specific method of forming the common electrode, the connection electrode, and the gate is not particularly limited, and those skilled in the art can flexibly select as needed.
  • the common electrode, the connection electrode and the gate electrode may be sequentially formed by a coating, exposure, and etching process in this step, thereby being simple, convenient, and easy to control, and having no special equipment and technicians. Requirements, easy to achieve large-scale production.
  • the connection electrode and the common electrode are disposed in the same layer, and may be formed by one patterning process, that is, an electrode layer may be formed on one side of the substrate, and then light is coated on the side of the electrode layer away from the substrate.
  • connection electrode and a common electrode are the same as those described in the array substrate described above, and will not be further described herein.
  • S200 forming a gate insulating layer 3, and a schematic structural view is shown in FIG. 6B.
  • a specific method of forming the gate insulating layer is not particularly limited, and a person skilled in the art can flexibly select according to actual conditions.
  • the method of forming the gate insulating layer includes, but is not limited to, a deposition method, a plating method, etc., specifically, but not limited to, chemical vapor deposition, physical vapor deposition, magnetron sputtering, vacuum evaporation, and the like. .
  • the process is mature, easy to operate, and low in cost.
  • the material forming the gate insulating layer is not particularly limited as long as it satisfies the requirements of the insulating property, and may be any material that can be used as a gate insulating layer in the art.
  • materials that may be employed to form the gate insulating layer include, but are not limited to, silicon oxide, silicon nitride, polymers, and the like. Thus, it has good insulation properties, and has a wide range of materials and low cost.
  • S300 The active layer 4 is formed, and a schematic structural view is shown in FIG. 6G.
  • the active layer 4 may be formed by the following steps:
  • a semiconductor layer 42 is formed on a side of the gate insulating layer 3 away from the substrate 100.
  • Figure 6C the specific manner of forming the semiconductor layer 42 is not particularly limited, and for example, chemical vapor deposition, physical vapor deposition, or the like can be employed.
  • methods that may be employed include, but are not limited to, magnetron sputtering, vacuum evaporation, and the like. Thus, the process is mature, the operation is simple, and the cost is low.
  • a first via hole a1 is formed on a side of the connection electrode 102 away from the substrate 100 by a mask, and a third via hole a3 is formed on a side of the common electrode away from the substrate, and The semiconductor layer 42 is patterned to obtain the active layer 4.
  • the source 602 will be electrically connected to the connection electrode 102 through the first via a1.
  • a first via hole a1 is formed on a side of the connection electrode 102 away from the substrate 100 by a mask, and a side is formed on a side of the common electrode away from the substrate
  • the three vias a3 and patterning the semiconductor layer 42 can be performed by the following steps:
  • a semi-permeable membrane mask 5 is disposed on a side of the semiconductor layer 42 away from the substrate 100, wherein the semi-permeable membrane mask 5 corresponds to the gate in a direction perpendicular to the plane of the substrate
  • the position of 201 is the opaque area C
  • the area corresponding to the connection electrode 102 and the common electrode 101 is the total transparent area A
  • the remaining area is the semi-transmissive area B. See FIG. 6D for a schematic structural view.
  • the all-transmission region A is etched to form the first via hole a1 and the third via hole a3, and a schematic structural view is shown in FIG. 6E.
  • the etching method employed in this step is not particularly limited as long as the via holes can be effectively formed without adversely affecting other structures, and those skilled in the art can flexibly select as needed.
  • dry etching may be employed, whereby operation is convenient, fast, and does not affect the performance of the array substrate.
  • the semi-transmissive region B is removed, and the structure is shown in FIG. 6F.
  • the manner of removing the semi-transmissive region B in this step is not particularly limited, and those skilled in the art can flexibly select according to needs.
  • the semi-transmissive region B may be removed by an ashing method. Thus, the operation is simple, convenient, and low in cost.
  • the semiconductor layer 42 not covered by the opaque region C is etched, and the opaque region C is removed to form the active layer 4. See FIG. 6G for a schematic structural view.
  • the active layer 4, the first via hole a1, and the third via hole a3 can be formed by one mask, and the steps are simple and the cost is low.
  • the source 602 and the connection electrode 102 can be electrically connected in a subsequent step by providing the first via a1, and the third via a3 can be electrically connected in the subsequent step.
  • the specific manner of etching the semiconductor layer in this step is also not particularly limited as long as the active layer 4 can be effectively formed without affecting other structures.
  • S400 Forming a drain 601 and a source 602, the source 602 is electrically connected to the connection electrode 102, and a schematic structural view is shown in FIG. 6H.
  • the source and drain electrodes are plated, exposed, and etched on the side of the gate insulating layer away from the substrate to form a source and a drain, wherein the source overlaps the connecting electrode portion. . Therefore, the operation is simple, convenient, and easy to control, and has no special requirements for equipment and technicians, and is easy to realize large-scale production.
  • the drain and source involved in this step are the same as those described in the previous array substrate, and are not described herein again.
  • the pixel electrode and the common connection electrode described in this step may be formed by one patterning process, and specifically, may be formed by coating, exposure, and etching. Therefore, by providing the connection electrode to electrically connect the source and the pixel electrode, the source and the pixel electrode can be directly connected in the prior art, which may cause damage to the source during the etching process, resulting in an increase in contact resistance.
  • the problem of flicker or poor pixel is that the obtained array substrate has a high yield and a good use performance. Moreover, this method does not increase the number of masks and the cost is low.
  • the inventors have found that the array substrate described above can be efficiently and quickly prepared by the method, and the steps are simple, the production yield and production efficiency are greatly improved, and mass production is easy.
  • the method can avoid the problem that the source has a high contact resistance due to a large amount of over-etching caused by the etching without increasing the number of masks, thereby reducing problems such as flicker and pixel defects.
  • the method may further include the step of forming a common electrode line and a passivation layer.
  • a method of preparing an array substrate will be described in detail below with reference to FIGS. 7 and 8A to 8K. Specifically, the method for preparing an array substrate may include the following steps:
  • S10 The common electrode 101, the common electrode line 202, the connection electrode 102, and the gate electrode 201 are sequentially formed on one side of the substrate 100, and a schematic structural view is shown in FIG. 8A.
  • the common electrode 101 and the connection electrode 102 may be formed in the same steps as in the step S100, and then the gate electrode 201 and the common electrode line 202 are formed by one patterning process, wherein the common electrode line 202 is formed at the common electrode
  • the 101 is away from the side of the substrate 100 and is electrically connected to the common electrode 101.
  • this step is consistent with the description in step S200, and will not be further described herein.
  • the active layer 4 may be formed by the following steps:
  • a semiconductor layer 42 is formed on a side of the gate insulating layer 3 away from the substrate 100. See FIG. 8C for a schematic structural view.
  • the specific manner of forming the semiconductor layer 42 is not particularly limited, and for example, chemical vapor deposition, Methods such as physical vapor deposition.
  • methods that may be employed include, but are not limited to, magnetron sputtering, vacuum evaporation, and the like. Thus, the process is mature, the operation is simple, and the cost is low.
  • a first via hole a1 is formed on a side of the connection electrode 102 away from the substrate 100 by a mask, and the semiconductor layer 42 is patterned to obtain the active layer 4, wherein The source electrode 602 is electrically connected to the connection electrode 102 through the first via hole a1.
  • the first via hole a1 is formed on a side of the connection electrode 102 away from the substrate 100 by one mask, and patterning the semiconductor layer 42 may be performed by the following steps :
  • a semi-permeable membrane mask 5 is disposed on a side of the semiconductor layer 42 away from the substrate 100, wherein the semi-permeable membrane mask 5 corresponds to the gate in a direction perpendicular to the plane of the substrate
  • the position of 201 is the opaque area C
  • the area corresponding to the connection electrode 102 is the total transparent area A
  • the remaining area is the semi-transmissive area B. See FIG. 8D for a schematic structural view.
  • the all-transmission region A is etched to form the first via hole a1, and the structure is schematically shown in FIG. 8E.
  • the etching method employed in this step is not particularly limited as long as the via holes can be effectively formed without adversely affecting other structures, and those skilled in the art can flexibly select as needed.
  • dry etching may be employed, whereby operation is convenient, fast, and does not affect the performance of the array substrate.
  • the semi-transmissive region B is removed, and the structure is shown in FIG. 8F.
  • the manner of removing the semi-transmissive region B in this step is not particularly limited, and those skilled in the art can flexibly select according to needs.
  • the semi-transmissive region B may be removed by an ashing method. Thus, the operation is simple, convenient, and low in cost.
  • the semiconductor layer 42 not covered by the opaque region C is etched, and the opaque region C is removed to form the active layer 4. See FIG. 8G for a schematic structural view.
  • the active layer 4 and the first via hole a1 can be formed by one side mask, which is simple in steps and low in cost.
  • the specific manner of etching the semiconductor layer in this step is also not particularly limited as long as the active layer 4 can be effectively formed without affecting other structures.
  • S40 forming a drain 601 and a source 602, and the source 602 is electrically connected to the connection electrode 102. See FIG. 8H for a schematic diagram of the structure.
  • the source 602 and the drain 601 are formed by coating, exposing, and etching the source and drain metal on the side of the gate insulating layer 3 away from the substrate 100, wherein the source 602 passes through
  • the first via hole a1 is partially overlapped with the connection electrode 102. Therefore, the operation is simple, convenient, and easy to control, and has no special requirements for equipment and technicians, and is easy to realize large-scale production.
  • the passivation layer 7 may be formed by the following steps:
  • the drain 601, the active layer 4, the source 602, the connection electrode 102, and the gate insulating layer 3 are away from the substrate 100.
  • One side forms a protective layer 72, and the structure is shown in FIG. 8I.
  • a specific method of forming the protective layer 72 is not particularly limited, and for example, a method such as chemical vapor deposition, physical vapor deposition, or the like may be employed.
  • methods that may be employed include, but are not limited to, magnetron sputtering, vacuum evaporation, and the like. Thus, the process is mature, the operation is simple, and the cost is low.
  • a mask 8 is disposed on the protective layer 72. See FIG. 8J for a schematic structural view.
  • the mask 8 used in this step may be a semi-permeable membrane mask having full transmissive regions D and E, and in the direction perpendicular to the plane of the substrate, the full transmissive region D and the source 602 are not overlapping. Therefore, in the subsequent etching step, etching damage is not caused to the source, the contact resistance can be effectively reduced, problems such as flicker and pixel defects are avoided, the production yield of the array substrate is improved, and the use performance is improved.
  • the protective layer 72 is etched to form a second via a2, a third via a3 and the passivation layer 7, and the second via a2 is formed at the connection electrode 102 away from the substrate
  • the third via hole a3 is formed on a side of the common electrode line 202 away from the substrate 100, and a schematic structural view is shown in FIG. 8K.
  • dry etching can be performed in this step, thereby effectively etching the passivation layer without adversely affecting other structures, and the process is mature and convenient to operate.
  • FIG. 4 is a schematic structural view.
  • the pixel electrode 9 and the common connection electrode 10 described in this step may be formed by one patterning process, and specifically, may be formed by plating, exposure, and etching.
  • the pixel electrode 9 is electrically connected to the connection electrode 102 through the second via hole a2, and is electrically connected to the common electrode line 202 through the third via hole a3, and the common connection electrode 10 is used for
  • the common electrodes of adjacent pixel units are electrically connected.
  • the pixel electrode 9 and the source electrode 602 can be electrically connected through the connection electrode 102, thereby avoiding damage to the source electrode 602 during the etching process, resulting in high contact resistance, thereby reducing problems such as flicker and pixel defects.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • the meaning of “plurality” is two or two Above, unless specifically stated otherwise.
  • the terms “installation”, “connected”, “connected”, “fixed”, and the like, are to be understood broadly, and may be either a fixed connection or a detachable connection, unless explicitly stated or defined otherwise. , or integrated; can be mechanical connection, or can be electrical connection; can be directly connected, or can be indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction of two elements.
  • the specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.
  • the first feature "on” or “under” the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.
  • the first feature "above”, “above” and “above” the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature may be that the first feature is directly below or obliquely below the second feature, or merely that the first feature level is less than the second feature.

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Abstract

一种阵列基板及其制备方法、显示装置。该阵列基板包括：像素阵列，像素阵列中的每个像素具有像素电极(9)；晶体管阵列，晶体管阵列中的每个晶体管具有源极(602)；以及连接电极(102)，用于将像素电极与对应的源极电连接。

Description

阵列基板及其制备方法、显示装置
相关申请的交叉引用
本公开要求于2017年3月29日提交到中国专利局的中国发明专利申请No.201710198640.1的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及阵列基板及其制备方法、显示装置。
背景技术
TFT-LCD(薄膜晶体管液晶显示器)由于其体积小、重量轻、功耗低、适合制备大尺寸面板以及无辐射等优点，是目前的平板显示市场中的主流显示方式。TFT-LCD主要由TFT基板(阵列基板)和CF基板(彩膜基板)组成，其中TFT基板由一定数量的像素阵列构成，每个像素由一个TFT(薄膜晶体管)进行控制以显示图像。像素阵列可通过反复的薄膜沉积，掩膜曝光，刻蚀等工程完成。其中TFT的信号线通常由Al，Mo，Ni，Cu等金属或合金制成。随着面板尺寸的大型化，信号线的电路延时(RC Delay)效应也越大，对LCD面板的影响也越大，因此，如何降低信号线的RC Delay，对提高LCD的品质，有重要意义。Cu金属的电阻是Al的80％，使用Cu代替Al金属作为信号线，可以大幅降低RC Delay，除此之外，由于Cu电阻小，可以采用较细的金属布线，膜厚也可以做的比较薄，因此，Cu工艺可以提高LCD开口率，大幅降低成本。Cu金属虽然有很多优点，但是，由于Cu的金属活性比较高，容易吸收颗粒，水汽等导致氧化，工艺控制难度比较大。在干法刻蚀中，工艺控制不当，就会容易导致Cu表面腐蚀或氧化，导致Cu与其他金属的接触不良，影响LCD显示。
因而，目前的阵列基板仍有待改进。
发明内容
在本公开的一个方面，提供了一种阵列基板。根据本公开的实施例，该阵列基板包括：像素阵列，所述像素阵列中的每个像素具有像素电极；晶体管阵列，所述晶体管阵列中的每个晶体管具有源极；以及连接电极，用于将所述像素电极与对应的源极电连接。
根据本公开的实施例，所述像素阵列中的每个像素还包括：公共电极，与所述像素阵 列中其它像素的公共电极电连接，其中所述连接电极与所述公共电极布置在同一层中。
根据本公开的实施例，在垂直于所述衬底的方向上，所述源极与所述像素电极不重叠。
根据本公开的实施例，所述晶体管阵列中的晶体管还具有漏极，形成所述漏极和所述源极的材料包括铜。
根据本公开的实施例，形成所述连接电极的材料包括氧化铟锡。
在本公开的另一个方面，提供了一种显示装置。根据本公开的实施例，该显示装置包括前面所述的根据本公开的阵列基板。本领域技术人员可以理解，该显示装置具有前面所述的阵列基板的所有特征和优点，在此不再一一赘述。
在本公开的又一个方面，本公开提供了一种制备阵列基板的方法。根据本公开的实施例，该方法包括：在衬底上形成公共电极、连接电极和栅极；形成栅绝缘层；形成有源层；形成漏极和源极，所述源极与所述连接电极电连接；形成像素电极，所述像素电极与所述连接电极电连接，且通过所述连接电极与所述源极电连接。
根据本公开的实施例，所述公共电极和所述连接电极通过一次构图工艺形成。
根据本公开的实施例，该制备阵列基板的方法进一步包括在所述公共电极远离所述衬底的一侧形成公共电极线的步骤，且所述栅极和所述公共电极线通过一次构图工艺形成。
根据本公开的实施例，形成有源层的步骤包括：在所述栅绝缘层上形成半导体层；形成第一过孔，使得所述连接电极暴露在所述第一过孔底部，并对所述半导体层进行图案化，得到有源层，其中，所述源极通过所述第一过孔与所述连接电极电连接。
根据本公开的实施例，形成第一过孔，使得所述连接电极暴露在所述第一过孔底部，并对所述半导体层进行图案化的步骤包括：在所述半导体层上设置半透膜掩膜，其中，在垂直于所述衬底的方向上，所述半透膜掩膜对应所述栅极的位置为不透光区，对应所述连接电极的区域为全透光区，其余区域为半透光区；对所述全透光区进行刻蚀，形成所述第一过孔；去除所述半透光区；通过刻蚀去除未被所述不透光区覆盖的半导体层，然后去除所述不透光区，以形成所述有源层。
根据本公开的实施例，形成所述漏极和源极之后，形成所述像素电极之前，还包括：形成保护层，覆盖所述漏极、有源层、源极、连接电极和栅绝缘层；在所述保护层上设置掩膜；对所述保护层进行刻蚀，以形成第二过孔、第三过孔和钝化层；其中，所述像素电极通过所述第二过孔与所述连接电极电连接，并通过所述第三过孔与所述公共电极线电连接。
根据本公开的实施例，在垂直于所述衬底的方向上，所述第二过孔与所述源极不重叠。
附图说明
图1显示了现有阵列基板的结构示意图。
图2显示现有技术中刻蚀后的Cu金属表面形貌。
图3显示了根据本公开一个实施例的阵列基板的结构示意图。
图4显示了根据本公开另一个实施例的阵列基板的结构示意图。
图5和图6A至图6H显示了根据本公开一个实施例的制备阵列基板的方法的流程示意图。
图7和图8A至图8K显示了根据本公开另一个实施例的制备阵列基板的方法的流程示意图。
附图标记：
100：衬底 101：公共电极 102：连接电极 201：栅极 202：公共电极线 3：栅绝缘层 4：有源层 42：半导体层 5、8：半透膜掩膜 601：漏极 602：源极 7：钝化层 72：保护层 9：像素电极 10：公共连接电极
具体实施方式
下面详细描述本公开的实施例。下面描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。实施例中未注明具体技术或条件的，按照本领域内的文献所描述的技术或条件或者按照产品说明书进行。所用试剂或仪器未注明生产厂商者，均为可以通过市购获得的常规产品。
本公开是基于发明人的以下发现而完成的：
目前常见的阵列基板中，参照图1，像素电极9通过a孔与源极602相连，公共电极101通过b孔内的公共电极线202和公共连接电极10与相邻侧的公共电极101相连。a孔和b孔为干法刻蚀一次形成，a孔只需刻穿钝化层7，而b孔则需要同时刻穿钝化层7和栅绝缘层3。为了保持玻璃基板100的刻蚀均一性，防止过孔没有刻穿的情况，过孔刻蚀通常会有30％-40％左右的过刻量，而过刻量以b孔的刻穿时间为基准。通常情况下，在b孔只有30％过刻量时，a孔的过刻量会达到400％-500％左右。因此a孔的钝化层7被刻穿后，大部分时间在刻蚀a孔源极602金属的表面，导致源极602金属表面的过刻量比较大。干法刻蚀时，Cu金属表面受到等离子体的轰击时间越长，Cu表面受到的损害越大，在长时间 的过刻后，Cu表面会氧化，并形成许多离子轰击导致的小坑(刻蚀后的Cu金属表面形貌如图2所示)。这些小坑的存在会导致像素电极9与Cu表面进行搭接时，接触电阻增加，从而导致像素充电不足，造成闪烁等不良。要降低a孔的过刻量，可以通过a孔和b孔分别通过两道掩膜和刻蚀进行避免，但是这样会导致掩膜数量增加，大幅增加成本。为此，发明人进行了深入研究，研究发现在形成公共电极的同时，设置连接电极，过孔刻蚀时通过连接电极让像素电极与源极相连，避免了在过孔刻蚀时导致的源极上方由于过刻量较大导致的接触电阻较高的问题，可以有效降低Cu产品的接触电阻，防止由于接触电阻较高导致的闪烁，像素不良等，提高良率。
为此，本公开的一个目的在于提出一种能够有效降低接触电阻、防止闪烁、减少像素不良或提高生产良率的阵列基板。
在本公开的一个方面，本公开提供了一种阵列基板，该阵列基板可以用于显示装置，例如液晶显示装置等。根据本公开的实施例，参照图3，该阵列基板包括：衬底100、栅极201、公共电极101、连接电极102、栅绝缘层3、有源层4、漏极601、源极602和像素电极9，其中，所述源极602和所述像素电极9通过所述连接电极102电连接。通常，阵列基板上形成有像素阵列和用于控制像素阵列的晶体管阵列。晶体管阵列中的每个晶体管可以控制像素阵列中的一个对应像素。在本公开的各个附图中，为了简明起见，仅示意性的示出了一个晶体管和对应的像素。发明人意外的发现，通过连接电极将像素电极与源极相连，可以在不增加掩膜次数的同时避免由于过刻量较大导致的接触电阻较高的问题，可以有效减小接触电阻，防止由于接触电阻较高导致的闪烁，像素不良等问题，提高良率。
根据本公开的实施例，可以采用的衬底的具体种类不受特别限制，本领域技术人员可以根据需要灵活选择。在本公开的一些实施例中，可以采用的衬底包括但不限于玻璃衬底、陶瓷衬底、金属衬底或聚合物衬底等。由此，来源广泛，成本较低，且使用性能良好。
根据本公开的实施例，形成栅极的具体材料也没有特别限制，可以为本领域任何已知的用于制备栅极的材料，为了提高阵列基板的使用性能，可以选择导电性能良好的导体材料形成栅极，例如包括但不限于金属、掺杂的多晶硅等。
根据本公开的实施例，所述连接电极与所述公共电极同层设置。由此，可以通过一步构图工艺形成，操作步骤简单，且利于轻薄化发展趋势。
需要说明的是，本文中所使用的描述方式“一次构图工艺”包括形成膜层结构、涂覆光刻胶、曝光、显影、刻蚀和去除光刻胶的步骤。例如，形成连接电极和公共电极可以通过以下步骤进行：在衬底的一侧形成电极层，在电极层上涂覆光刻胶，并对光刻胶进行曝 光和显影处理，然后暴露的电极层进行刻蚀，去除光刻胶，得到图案化的连接电极和公共电极。
根据本公开的实施例，形成连接电极的具体材料也没有特别限制，只要能够在刻蚀步骤中不受损伤，具有良好的导通效果即可。在本公开的一些实施例中，形成所述连接电极的材料包括氧化铟锡。由此，可以在干法刻蚀中不受损伤，有效连接源极和像素电极。
根据本公开的实施例，形成所述公共电极的材料不受限制，本领域技术人员可以根据需要灵活选择，例如包括但不限于氧化铟锡等。在本公开的实施例中，公共电极可以与连接电极同层设置，即可通过一次构图工艺形成，因此，公共电极与连接电极可以采用同样的材料形成。
根据本公开的实施例，在垂直于所述衬底平面的方向上，所述源极与所述像素电极不重叠。由此，可以避免刻蚀过程中对源极造成的损伤，进而减小接触电阻。具体的，在本公开的实施例中，根据制备步骤的需要，一般先将源极通过过孔与连接电极相连，然后再通过另一过孔将像素电极与连接电极相连，通过设置在垂直于衬底平面的方向上，源极与像素电极不重叠，可以在将像素电极与连接电极相连时，过孔刻蚀过程不会对源极产生影响，进而减小接触电阻，提高阵列基板的使用性能。
根据本公开的实施例，形成所述漏极和所述源极的材料也没有特别限制，本领域技术人员可以根据实际需要灵活选择。在本公开的一些实施例中，为了进一步减小信号线的RC Delay和电阻，减小布线宽度，降低膜层厚度，进而提高显示器的品质，形成所述漏极和所述源极的材料可以包括铜。由此，电阻小，可以大幅度降低信号线的RC Delay，同时可以采用较细的金属布线，膜厚也可以做的比较薄，进而，提高LCD开口率，大幅降低成本。
根据本公开的实施例，参照图4，该阵列基板还可以包括公共电极线202和钝化层7，其中，公共电极线202设置在公共电极101远离衬底100的一侧，且与栅极201同层设置；钝化层7设置于漏极601、有源层4、源极602、连接电极102和栅绝缘层3远离衬底100的一侧。由此，可以进一步提高阵列基板的使用性能，且钝化层可以对阵列基板上的其它膜层结构起到良好的保护作用。
根据本公开的实施例，参照图4，详细描述本公开的阵列基板的结构。具体的，该阵列基板包括衬底100，所述栅极201，公共电极101和连接电极102设置于所述衬底100的一侧；所述公共电极线202设置在所述公共电极101远离所述衬底100的一侧，且与所述栅极201同层设置；所述栅绝缘层3设置在所述衬底100、栅极201、连接电极102、公共电极101和公共电极线202远离所述衬底100的一侧；所述有源层4设置于所述栅绝缘 层3远离所述衬底100的一侧，且在垂直于所述衬底平面的方向上与所述栅极201重叠；所述漏极601设置在所述栅绝缘层3和所述有源层4远离所述衬底100的一侧；所述源极602设置在所述栅绝缘层3、所述有源层4和所述连接电极102远离所述衬底100的一侧；所述钝化层7设置于所述漏极601、有源层4、源极602、连接电极102和栅绝缘层3远离所述衬底100的一侧；所述像素电极9设置在所述连接电极102、栅绝缘层3和钝化层7远离所述衬底100的一侧；公共连接电极10设置在钝化层7和公共电极线202远离衬底的一侧；第一过孔a1贯穿所述栅绝缘层3，所述源极602通过所述第一过孔a1与所述连接电极102电连接；第二过孔a2贯穿所述钝化层7和所述栅绝缘层3，所述像素电极9通过所述第二过孔a2与所述连接电极102电连接；第三过孔a3贯穿所述钝化层7和所述栅绝缘层3，公共连接电极10通过所述第三过孔a3与所述公共电极线202电连接，进而使得公共电极101与相邻侧的公共电极相连。由此，可以在不增加掩膜次数的同时避免刻蚀时导致的源极由于过刻量较大引起的接触电阻较高的问题，进而减少闪烁、像素不良等问题。
需要说明的是，本公开的附图示出的为阵列基板上一个像素单元的结构示意图，一个阵列基板上包括阵列设置的多个像素单元，上述的公共电极101与相邻侧的公共电极相连是指相邻像素单元中的公共电极通过公共连接电极彼此导通。
根据本公开的实施例，形成所述有源层的材料并没有特别限制，本领域技术人员可以根据需要灵活选择。在本公开的一些实施例中，有源层可以为a-Si或铟镓锌氧化物等。由此，可以有效形成导电通道，且导通效果理想，有利于提高阵列基板的使用性能。
根据本公开的实施例，形成钝化层的具体材料没有特别限制，可以为本领域任何已知的用于制备钝化层的材料。在本公开的一些实施例中，可以采用的材料包括但不限于氧化硅、氮化硅等。由此，材料来源广泛，易于加工成膜，且能够有效对阵列基板上的其它膜层结构起到保护作用，利于提高阵列基板的使用性能。
根据本公开的实施例，形成公共电极线的材料也没有特别限制，只要满足导电要求，本领域技术人员可以根据需要灵活选择。在本公开的一些实施例中，公共电极线可以与栅极通过一次构图工艺形成，因此，形成公共电极线的材料可以与形成栅极的材料一致，在此不再过多赘述。
在本公开的另一个方面，本公开提供了一种显示装置。根据本公开的实施例，该显示装置包括前面所述的阵列基板。本领域技术人员可以理解，该显示装置具有前面所述的阵列基板的所有特征和优点，在此不再一一赘述。
根据本公开的实施例，该显示装置的具体种类没有特别限制，可以为本领域任何已知 的具有显示功能的装置、设备等，例如包括但不限于显示面板、手机、平板电脑、计算机显示器、电视机、游戏机、可穿戴设备、及各种具有显示功能的家用、生活电器等。
根据本公开的实施例，除了前面所述的阵列基板，本公开的显示装置还包括常规显示装置所具备的必要的结构和部件，例如还可以包括外壳、必要的电路结构等等，在此不再过多赘述。
在本公开的又一个方面，本公开提供了一种制备阵列基板的方法。根据本公开的实施例，参照图5和图6A至图6D，该方法包括以下步骤：
S100：在衬底100的一侧依次形成公共电极101、连接电极102和栅极201，结构示意图参见图6A。
根据本公开的实施例，形成公共电极、连接电极和栅极的具体方法没有特别限制，本领域技术人员可以根据需要灵活选择。在本公开的一些实施例中，该步骤中可通过镀膜，曝光，刻蚀工艺依次形成公共电极、连接电极和栅极，由此，操作简单、方便，易于控制，对设备和技术人员没有特殊要求，易于实现规模化生产。具体的，在一些实施例中，连接电极和公共电极同层设置，可以通过一次构图工艺形成，即可在衬底的一侧形成电极层，然后在电极层远离衬底的一侧涂覆光刻胶，并对光刻胶进行曝光、显影处理，接着对电极层进行刻蚀，然后去除光刻胶，形成连接电极和公共电极。根据本公开的实施例，该方法中涉及的衬底、栅极、公共电极、连接电极与前面所述的阵列基板中的描述一致，在此不再过多赘述。
S200：形成栅绝缘层3，结构示意图参见图6B。
根据本公开的实施例，形成栅绝缘层的具体方法没有特别限制，本领域技术人员可以根据实际条件灵活选择。在本公开的一些实施例中，形成栅绝缘层的方法包括但不限于沉积法、镀膜法等，具体的，包括但不限于化学气相沉积、物理气相沉积、磁控溅射、真空蒸镀等。由此，工艺成熟，易于操作，且成本较低。
根据本公开的实施例，形成栅绝缘层的材料没有特别限制，只要满足绝缘性能的要求，可以为本领域任何可以作为栅绝缘层的材料。在本公开的一些实施例中，可以采用的用于形成栅绝缘层的材料包括但不限于氧化硅、氮化硅、聚合物等。由此，具有良好的绝缘性能，且材料来源广泛，成本较低。
S300：形成有源层4，结构示意图见图6G。
根据本公开的实施例，该步骤中，有源层4可以通过以下步骤形成：
首先，在所述栅绝缘层3远离所述衬底100的一侧形成半导体层42，结构示意图参见 图6C。具体的，形成半导体层42的具体方式没有特别限制，例如可以采用化学气相沉积、物理气相沉积等方法。在本公开的一些具体示例中，可以采用的方法包括但不限于磁控溅射、真空蒸镀等。由此，工艺成熟，操作简单，成本较低。
接着，通过一次掩膜，在所述连接电极102远离所述衬底100的一侧形成第一过孔a1，在所述公共电极远离所述衬底的一侧形成第三过孔a3，并对所述半导体层42进行图案化，得到所述有源层4。在后面的步骤中，所述源极602将通过所述第一过孔a1与所述连接电极102电连接。
根据本公开的一些实施例，通过一次掩膜，在所述连接电极102远离所述衬底100的一侧形成第一过孔a1，在所述公共电极远离所述衬底的一侧形成第三过孔a3，并对所述半导体层42进行图案化可以通过以下步骤进行：
在所述半导体层42远离所述衬底100的一侧设置半透膜掩膜5，其中，在垂直于所述衬底平面的方向上，所述半透膜掩膜5对应所述栅极201的位置为不透光区C，对应所述连接电极102和所述公共电极101的区域为全透光区A，其余区域为半透光区B，结构示意图参见图6D。
对所述全透光区A进行刻蚀，形成所述第一过孔a1和第三过孔a3，结构示意图见图6E。根据本公开的实施例，该步骤中采用的刻蚀方法没有特别限制，只要能够有效形成过孔，且不会对其它结构产生负面影响，本领域技术人员可以根据需要灵活选择。在本公开的一些具体示例中，可以采用干法刻蚀，由此，操作方便、快速，且不会影响阵列基板的性能。
去除所述半透光区B，结构示意图参见图6F。根据本公开的实施例，该步骤中去除半透光区B的方式没有特别限制，本领域技术人员可以根据需要灵活选择。在本公开的一些实施例中，可以通过灰化方法将半透光区B去除。由此，操作简单，方便，成本较低。
对未被所述不透光区C覆盖的半导体层42进行刻蚀，并去除所述不透光区C，以形成所述有源层4，结构示意图参见图6G。由此，可以通过一次掩膜形成有源层4、第一过孔a1和第三过孔a3，步骤简单，成本较低。通过设置第一过孔a1可以在后续步骤中使得源极602与连接电极102电连接，设置第三过孔a3可以在后续步骤中使得相邻像素单元中的公共电极101电连接。根据本公开的实施例，该步骤中对半导体层进行刻蚀的具体方式也没有特别限制，只要能够有效形成有源层4，且不会影响其它结构即可。
S400：形成漏极601和源极602，所述源极602与所述连接电极102电连接，结构示意图见图6H。
根据本公开的实施例，该步骤中通过在栅绝缘层远离衬底的一侧进行源漏极金属的镀膜，曝光，刻蚀形成源极和漏极，其中，源极与连接电极部分搭接。由此，操作简单、方便，易于控制，对设备和技术人员没有特殊要求，易于实现规模化生产。
根据本公开的实施例，该步骤涉及的漏极和源极与前面阵列基板中描述的一致，在此不再赘述。
S500：形成像素电极9和公共连接电极10，其中，所述像素电极9与所述连接电极102电连接，且通过所述连接电极102与所述源极602电连接，结构示意图参见图3。根据本公开的实施例，该步骤中所述的像素电极和公共连接电极可以通过一次构图工艺形成，具体的，可以通过镀膜，曝光，刻蚀形成。由此，通过设置连接电极使得源极与像素电极电连接，可以避免现有技术中将源极与像素电极直接连接，导致刻蚀过程中会对源极造成损伤，导致接触电阻增大，像素闪烁或像素不良的问题，获得的阵列基板良率较高，使用性能较佳。而且，该方法并不会增加掩膜数量，成本较低。
发明人发现，通过该方法可以有效、快速的制备前面所述的阵列基板，步骤简单，大大提升了生产良率和生产效率，易于大规模生产。另外，该方法可以在不增加掩膜次数的同时避免刻蚀时导致的源极由于过刻量较大引起的接触电阻较高的问题，进而减少闪烁、像素不良等问题。
根据本公开的实施例，针对具有不同结构的阵列基板，该方法还可以包括形成公共电极线和钝化层的步骤。下面参照图7和图8A至图8K，详细描述制备阵列基板的方法。具体的，该制备阵列基板的方法可以包括以下步骤：
S10：在衬底100的一侧依次形成公共电极101、公共电极线202、连接电极102和栅极201，结构示意图参见图8A。
具体的，在步骤中，可以按照与步骤S100中相同的步骤形成公共电极101和连接电极102，然后通过一次构图工艺形成栅极201和公共电极线202，其中，公共电极线202形成在公共电极101远离衬底100的一侧，且与公共电极101电连接。
S20：形成栅绝缘层3，结构示意图参见图8B。
根据本公开的实施例，该步骤中与步骤S200中的描述一致，在此不再一一赘述。
S30：形成有源层4，结构示意图参见图8G。
根据本公开的实施例，该步骤中，有源层4可以通过以下步骤形成：
首先，在所述栅绝缘层3远离所述衬底100的一侧形成半导体层42，结构示意图参见图8C。具体的，形成半导体层42的具体方式没有特别限制，例如可以采用化学气相沉积、 物理气相沉积等方法。在本公开的一些具体示例中，可以采用的方法包括但不限于磁控溅射、真空蒸镀等。由此，工艺成熟，操作简单，成本较低。
接着，通过一次掩膜，在所述连接电极102远离所述衬底100的一侧形成第一过孔a1，并对所述半导体层42进行图案化，得到所述有源层4，其中，所述源极602通过所述第一过孔a1与所述连接电极102电连接。
根据本公开的一些实施例，通过一次掩膜，在所述连接电极102远离所述衬底100的一侧形成第一过孔a1，并对所述半导体层42进行图案化可以通过以下步骤进行：
在所述半导体层42远离所述衬底100的一侧设置半透膜掩膜5，其中，在垂直于所述衬底平面的方向上，所述半透膜掩膜5对应所述栅极201的位置为不透光区C，对应所述连接电极102的区域为全透光区A，其余区域为半透光区B，结构示意图参见图8D。
对所述全透光区A进行刻蚀，形成所述第一过孔a1，结构示意图见图8E。根据本公开的实施例，该步骤中采用的刻蚀方法没有特别限制，只要能够有效形成过孔，且不会对其它结构产生负面影响，本领域技术人员可以根据需要灵活选择。在本公开的一些具体示例中，可以采用干法刻蚀，由此，操作方便、快速，且不会影响阵列基板的性能。
去除所述半透光区B，结构示意图参见图8F。根据本公开的实施例，该步骤中去除半透光区B的方式没有特别限制，本领域技术人员可以根据需要灵活选择。在本公开的一些实施例中，可以通过灰化方法将半透光区B去除。由此，操作简单，方便，成本较低。
对未被所述不透光区C覆盖的半导体层42进行刻蚀，并去除所述不透光区C，以形成所述有源层4，结构示意图参见图8G。由此，可以通过一侧掩膜形成有源层4和第一过孔a1，步骤简单，成本较低。根据本公开的实施例，该步骤中对半导体层进行刻蚀的具体方式也没有特别限制，只要能够有效形成有源层4，且不会影响其它结构即可。
S40：形成漏极601和源极602，源极602与连接电极102电连接，结构示意图参见图8H。
根据本公开的实施例，该步骤中通过在栅绝缘层3远离衬底100的一侧进行源漏极金属的镀膜，曝光，刻蚀形成源极602和漏极601，其中，源极602通过第一过孔a1与连接电极102部分搭接。由此，操作简单、方便，易于控制，对设备和技术人员没有特殊要求，易于实现规模化生产。
S50：形成钝化层7，结构示意图参见图8K。
根据本公开的实施例，钝化层7可以通过以下步骤形成：
在所述漏极601、有源层4、源极602、连接电极102和栅绝缘层3远离所述衬底100 的一侧形成保护层72，结构示意图参见图8I。根据本公开的实施例，形成保护层72的具体方法没有特别限制，例如可以采用化学气相沉积、物理气相沉积等方法。在本公开的一些具体示例中，可以采用的方法包括但不限于磁控溅射、真空蒸镀等。由此，工艺成熟，操作简单，成本较低。
在所述保护层72上设置掩膜8，结构示意图参见图8J。根据本公开的实施例，该步骤采用的掩膜8可以为半透膜掩膜，具有全透区D和E，且在垂直于衬底平面的方向上，全透区D与源极602不重叠。由此，在后续刻蚀步骤中，不会对源极造成刻蚀损伤，能够有效减小接触电阻，避免闪烁、像素不良等问题，提高阵列基板的生产良率，提高使用性能。
对所述保护层72进行刻蚀，以形成第二过孔a2、第三过孔a3和所述钝化层7，所述第二过孔a2形成在所述连接电极102远离所述衬底100的一侧，所述第三过孔a3形成在所述公共电极线202远离所述衬底100的一侧，结构示意图参见图8K。根据本公开的实施例，该步骤中可以采用干法刻蚀进行，由此可以有效对钝化层进行刻蚀，且不会对其他结构产生负面影响，且工艺成熟、操作方便。
S60：形成像素电极9和公共连接电极10，结构示意图参见图4。
根据本公开的实施例，该步骤中所述的像素电极9和公共连接电极10可以通过一次构图工艺形成，具体的，可以通过镀膜，曝光，刻蚀形成。其中，所述像素电极9通过所述第二过孔a2与所述连接电极102电连接，并通过所述第三过孔a3与所述公共电极线202电连接，公共连接电极10用于将相邻像素单元的公共电极电连接。由此，可以使得像素电极9与源极602通过连接电极102导通，避免刻蚀过程中对源极602造成损伤，引起接触电阻较高，进而减少闪烁、像素不良等问题。
在本公开的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，“多个”的含义是两个或两个 以上，除非另有明确具体的限定。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (13)

  1. 一种阵列基板，其特征在于，包括：
    像素阵列，所述像素阵列中的每个像素具有像素电极；
    晶体管阵列，所述晶体管阵列中的每个晶体管具有源极；以及
    连接电极，用于将所述像素电极与对应的源极电连接。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述像素阵列中的每个像素还包括：
    公共电极，与所述像素阵列中其它像素的公共电极电连接，其中所述连接电极与所述公共电极布置在同一层中。
  3. 根据权利要求1所述的阵列基板，其特征在于，在垂直于所述衬底的方向上，所述源极与所述像素电极不重叠。
  4. 根据权利要求1所述的阵列基板，其特征在于，所述晶体管阵列中的晶体管还具有漏极，形成所述漏极和所述源极的材料包括铜。
  5. 根据权利要求1所述的阵列基板，其特征在于，形成所述连接电极的材料包括氧化铟锡。
  6. 一种显示装置，其特征在于，包括权利要求1-5中任一项所述的阵列基板。
  7. 一种制备阵列基板的方法，其特征在于，包括：
    在衬底上形成公共电极、连接电极和栅极；
    形成栅绝缘层；
    形成有源层；
    形成漏极和源极，所述源极与所述连接电极电连接；
    形成像素电极，所述像素电极与所述连接电极电连接，且通过所述连接电极与所述源极电连接。
  8. 根据权利要求7所述的方法，其特征在于，所述公共电极和所述连接电极通过一次构图工艺形成。
  9. 根据权利要求7所述的方法，其特征在于，进一步包括在所述公共电极远离所述衬底的一侧形成公共电极线的步骤，且所述栅极和所述公共电极线通过一次构图工艺形成。
  10. 根据权利要求7所述的方法，其特征在于，形成有源层的步骤包括：
    在所述栅绝缘层上形成半导体层；
    形成第一过孔，使得所述连接电极暴露在所述第一过孔底部，并对所述半导体层进行 图案化，得到所述有源层，
    其中，所述源极通过所述第一过孔与所述连接电极电连接。
  11. 根据权利要求10所述的方法，其特征在于，形成第一过孔，使得所述连接电极暴露在所述第一过孔底部，并对所述半导体层进行图案化的步骤包括：
    在所述半导体层上设置半透膜掩膜，其中，在垂直于所述衬底的方向上，所述半透膜掩膜对应所述栅极的位置为不透光区，对应所述连接电极的区域为全透光区，其余区域为半透光区；
    对所述全透光区进行刻蚀，形成所述第一过孔；
    去除所述半透光区；
    通过刻蚀去除未被所述不透光区覆盖的半导体层，然后去除所述不透光区，以形成所述有源层。
  12. 根据权利要求11所述的方法，其特征在于，形成所述漏极和源极之后，形成所述像素电极之前，还包括：
    形成保护层，覆盖所述漏极、有源层、源极、连接电极和栅绝缘层；
    在所述保护层上设置掩膜；
    对所述保护层进行刻蚀，以形成第二过孔、第三过孔和钝化层；
    其中，所述像素电极通过所述第二过孔与所述连接电极电连接，并通过所述第三过孔与所述公共电极线电连接。
  13. 根据权利要求12所述的方法，其特征在于，在垂直于所述衬底的方向上，所述第二过孔与所述源极不重叠。
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