WO2018176538A1 - 一种差异化控制蚀刻深度的方法 - Google Patents

一种差异化控制蚀刻深度的方法 Download PDF

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WO2018176538A1
WO2018176538A1 PCT/CN2017/081775 CN2017081775W WO2018176538A1 WO 2018176538 A1 WO2018176538 A1 WO 2018176538A1 CN 2017081775 W CN2017081775 W CN 2017081775W WO 2018176538 A1 WO2018176538 A1 WO 2018176538A1
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pattern layer
etching
layer
etch
etchant
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French (fr)
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王威
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H10P50/644—Anisotropic liquid etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts

Definitions

  • the present invention relates to the field of display technology, and in particular to a method for differentially controlling the etching depth.
  • etching is a process that is often used. Generally, in order to achieve electrical contact, panel bending, etc., dry etching or wet etching is required to etch vias of different depths.
  • the present invention mainly provides a method for differentially controlling the etching depth, and aims to solve the problem that the process of using a plurality of masks for different depths of the via holes makes the process time-consuming.
  • one technical solution adopted by the present invention is to provide a method for differentially controlling the etching depth, wherein the method includes: setting a first etching stopper pattern on at least one layer of the stacked structure panel; a layer, at least one of the layers of the stacked structure is provided with a second etch stop pattern layer, wherein the layer of the second etch stop pattern layer is located at a layer where the first etch stop pattern layer is located
  • the first etching is performed on the panel by using a first etchant, so that the panel forms a first etching depth at a position where the first etch barrier pattern layer is disposed, and the first etching is not disposed
  • another technical solution adopted by the present invention is to provide a method for differentially controlling the etching depth, wherein the method includes: setting a first etching stopper in at least one layer of the panel of the laminated structure a patterning layer; performing a first etching on the panel by using a first etchant, such that the panel forms a first etching depth at a position where the first etching stopper pattern layer is disposed, and the first etching is not provided
  • the position of the etch stop pattern layer forms a second etch depth, the second etch depth is deeper than the bottom surface of the first etch stop pattern layer by controlling the etch time; the second etchant is used to perform the second etchant Sub-etching etches away the first etch stop pattern layer.
  • the present invention provides a first etch stop pattern layer in at least one layer of the stacked structure panel; the first etchant is used to etch the panel for the first time, Forming a first etching depth at a position where the first etching stopper pattern layer is disposed, forming a second etching depth at a position where the first etching stopper pattern layer is not disposed, and controlling the etching time to make the second etching depth deeper than a bottom surface of the first etch stop pattern layer; a second etching using the second etchant to etch the first etch stop pattern layer layer, such that the first etch stop pattern layer layer is not provided
  • the position of the first etch stop pattern layer is formed to be different in depth, so that different depths can be etched only by converting the etchant in the same mask process, which reduces the process time and reduces the production cost.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for differentially controlling etch depth provided by the present invention
  • Figure 2 is a schematic view showing the state of the laminated structure of Figure 1 in step S12;
  • Figure 3 is a schematic view showing the state of the laminated structure of Figure 1 in step S13;
  • FIG. 4 is a schematic flow chart of a second embodiment of a method for differentially controlling etch depth provided by the present invention.
  • Figure 5 is a schematic view showing the state of the laminated structure of Figure 4 in step S22;
  • Figure 6 is a schematic view showing the state of the laminated structure of Figure 4 in step S23;
  • Figure 7 is a schematic view showing the state of the laminated structure of Figure 4 in step S24;
  • Figure 8 is a schematic view showing the state of the laminated structure of Figure 4 in step S25.
  • a first embodiment of a method for differentially controlling etch depth provided by the present invention includes:
  • the laminated structure is exemplified by a laminated structure in a flexible display panel, that is, the stacked structure includes a substrate 101, a barrier layer 102, a buffer layer 103, an active layer 104, and an active layer covering from bottom to top.
  • holes to be etched at different depths such as the hole A1 to be etched and the hole B1 to be etched as shown in FIG. 1, and the hole A1 to be etched is used to realize the data line and the active
  • the layer 104 is in contact with each other and needs to be etched to the upper surface of the active layer 104.
  • the hole B1 to be etched is used to reduce the stress when the panel is bent, and needs to be etched to the upper surface of the buffer layer 103. Therefore, in the embodiment, the hole A1 to be etched is required.
  • the depth to be etched is smaller than the depth to be etched of the hole B1 to be etched.
  • a first etch barrier pattern layer 110 is disposed at a position where the hole A1 is to be etched.
  • a first etch barrier pattern layer 110 disposed in the same layer as the capacitor electrode pattern layer 108 is formed on the upper surface of the capacitor dielectric layer 107 at a position of the hole A1 to be etched, and a capacitor electrode may be formed in order to simplify the process.
  • the first etch barrier pattern layer 110 is formed by the same photolithography process while the pattern layer 108 is being used.
  • the material of the laminated structure is an inorganic material such as SiN x or SiO 2
  • the material of the first etch barrier pattern layer 108 is a metal material such as Mo, Ti, Al or TiAl alloy metal.
  • the first etching is performed on the panel by using the first etchant, and the hole A1 to be etched and the hole B1 to be etched are simultaneously etched, as shown by the arrow in FIG. 2, and etched at the position of the hole A1 to be etched.
  • the first etching is performed on the upper surface of the barrier pattern layer 110, the etching is stopped because the etchant cannot etch the first etch barrier pattern layer 110, and the first to be etched depth is formed, and the hole B1 to be etched is not provided with the first etch. Etching the pattern layer 110 and continuing the etching.
  • the position of the hole B1 to be etched is etched to a position beyond the bottom surface of the first etch barrier pattern layer 110 to form a second etch depth, and in this embodiment.
  • the depth of the bottom surface of the first etch barrier pattern layer 110 may be made equal to the thickness of the active layer 104 by controlling the etching time.
  • the first etchant when dry etching is used, may be a mixed gas including but not limited to CF 4 and O 2 or a mixed gas of C 2 FH 5 , A1r and H 2 ; when wet etching is used, first The etchant can be a liquid including, but not limited to, HF or B1OE.
  • the second etching is performed on the panel by using the second etchant.
  • the first etch barrier pattern layer 110 of the metal material can be used. Etching is performed such that etching is not performed at the position of the hole B1 to be etched, and the position of the hole A1 to be etched is continuously etched until the first etch barrier pattern layer is etched away, since the second etch depth is deeper than the first in step S12.
  • the bottom surface of the barrier pattern layer 110 is etched such that the etching depth of the hole B1 to be etched is greater than the etching depth of the hole A1 to be etched.
  • the second etchant when dry etching is used, may be a mixed gas including, but not limited to, SF 6 and O 2 , a mixed gas of Cl 2 and O 2 or a mixed gas of Cl 2 and B 1 F 3 ;
  • the second etchant when etching, may be a liquid including, but not limited to, H 3 PO 4 , HNO 3 or HCOOH.
  • the hole B1 to be etched is in contact with the buffer layer 103, and the first etchant may be repeatedly used to etch the panel until the hole A1 to be etched is etched.
  • the hole B1 to be etched is etched into contact with the buffer layer 103, and since the etching time is controlled in step S12, the depth of the bottom surface of the first etch barrier pattern layer 110 is equal to the thickness of the active layer 104, so that When the etching is continued, the hole A1 to be etched and the hole B1 to be etched can be simultaneously contacted with the active layer 104 and the buffer layer 103, respectively, and the etching of the hole A1 to be etched and the hole B1 to be etched can be completed.
  • a second embodiment of the method for differentially controlling the etch depth provided by the present invention includes:
  • At least one of the stacked layers of the panel is provided with a first etch stop pattern layer 210 and a second etch stop pattern layer 211;
  • the layer where the second etch barrier pattern layer 211 is located is located below the layer where the first etch barrier pattern layer 210 is located, and the number of patterns of the second etch barrier pattern layer 211 is less than the first etch barrier pattern.
  • the number of patterns of the layer 210 is less than the first etch barrier pattern.
  • the hole to be etched in the laminated structure of the flexible display panel is exemplified by the hole to be etched A2, the hole to be etched B2, and the hole to be etched C. Similar to the hole A1 to be etched and the hole B1 to be etched in the first embodiment described above, the hole C to be etched is used to realize the bending of a larger radius of curvature, and etching to the substrate 201 is required.
  • a first etch barrier pattern layer 210 and a second etch barrier pattern layer 211 are disposed at positions of the holes A2 to be etched, a first etch barrier pattern layer 210 is disposed at a position where the holes B2 are to be etched, and a first etch barrier pattern layer is disposed.
  • the method of 210 is the same as that of the first embodiment described above.
  • a second etch barrier pattern layer 211 disposed in the same layer as the gate pattern layer 206 may be formed on the surface of the gate insulating layer 205, and In order to simplify the process, the second etch barrier pattern layer 211 may be formed by the same photolithography process while the gate pattern layer 206 is formed.
  • the first etching is performed on the panel by using the first etchant. As shown by the arrow in FIG. 5, the etching is stopped at the position of the hole A2 to be etched and the hole B2 to be etched due to the presence of the first etch barrier pattern layer 210.
  • the hole C to be etched may be etched and etched to a position beyond the bottom surface of the first etch barrier pattern layer 210.
  • the specific principle is the same as that of the step S12 in the first embodiment, and is not described herein again.
  • the position of the hole C to be etched in this step exceeds the depth of the bottom surface of the first etch barrier pattern layer 210 by the sum of the thicknesses of the barrier layer 202 and the buffer layer 203.
  • the second etching is performed on the panel by using the second etchant.
  • the first etch barrier pattern layer 210 is etched away at the position of the hole A2 to be etched and the hole B2 to be etched, and is to be etched.
  • the position of the hole C is not etched, and the principle is the same as the above step S13, and details are not described herein again.
  • the etchant is switched, The etchant is further etched using the first etchant.
  • the hole to be etched A2, the hole to be etched B2, and the hole to be etched C are etched simultaneously, as shown by the arrow in FIG. 7, when the hole to be etched is etched to the second etch.
  • the position of the hole A2 to be etched is stopped, and the hole B2 to be etched and the hole C to be etched are continuously etched.
  • the etching depth of the position of the hole B2 to be etched exceeds the bottom surface of the second etch stop pattern layer 211.
  • the position of the hole B2 to be etched exceeds the bottom surface of the second etch barrier pattern layer 211 by a depth equal to the thickness of the active layer 204.
  • the etchant is continuously converted, and the second etch barrier layer 211 is etched away by using the same second etchant as in step S23.
  • the hole B2 to be etched and the hole C to be etched are not etched, and at this time.
  • the remaining depth to be etched is the same.
  • the etchant is continuously converted, and the etched hole A2, the hole to be etched B2, and the hole to be etched C are etched by using the first etchant. Since the remaining etched depth of the three holes to be etched is the same, the hole A2 and the active layer to be etched are 204 contact, the hole B2 to be etched is in contact with the buffer layer 203, and the hole C to be etched is in contact with the substrate 201 to be simultaneously etched, thereby forming three etch holes of different depths.
  • the present invention provides a first etch stop pattern layer in at least one layer of the stacked structure panel; the first etchant is used to etch the panel for the first time, so that the panel is provided with the first
  • the position of the etch stop pattern layer forms a first etch depth, and the second etch depth is formed at a position where the first etch stop pattern layer is not disposed, and the second etch depth is deeper than the first etch stop pattern layer by controlling the etching time a bottom surface; a second etching using a second etchant to etch the first etch stop pattern layer such that the first etch stop pattern layer is not provided and the first etch stop is provided
  • the position of the pattern layer is formed to be different in depth, so that different depths can be etched only by converting the etchant in the same mask process, which reduces the process time and reduces the production cost.

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Abstract

一种差异化控制蚀刻深度的方法，包括在层叠结构至少一层设置第一蚀刻阻挡图案层（S11）；采用第一蚀刻剂进行蚀刻，在设置有第一蚀刻阻挡图案层的位置形成第一蚀刻深度，未设置有第一蚀刻阻挡图案层的位置形成第二蚀刻深度，第二蚀刻深度深于第一蚀刻阻挡图案层底面（S12）；采用第二蚀刻剂将第一蚀刻阻挡图案层蚀刻掉（S13）。通过上述方法，使得在同一道光罩工艺中通过转换蚀刻剂即可蚀刻出不同深度，减少工艺耗时，降低生产成本。

Description

一种差异化控制蚀刻深度的方法 【技术领域】
本发明涉及显示技术领域，特别是涉及一种差异化控制蚀刻深度的方法。
【背景技术】
在面板制作中，蚀刻是需要经常用到的工艺，通常，为了达到电学接触、面板弯曲等目的，需要采用干法蚀刻或湿法蚀刻，蚀刻出不同深度的过孔。
现有技术中，对于不同深度的过孔，一般需要采用几道光罩才能实现，这样会使得工艺耗时较长，增加了生产成本。
【发明内容】
本发明主要提供一种差异化控制蚀刻深度的方法，旨在解决不同深度的过孔采用多道光罩而使得工艺耗时较长的问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种差异化控制蚀刻深度的方法，其中，所述方法包括：在层叠结构的面板中的至少一层设置第一蚀刻阻档图案层，在所述层叠结构的面板中的至少一层设置第二蚀刻阻档图案层，其中所述第二蚀刻阻档图案层所在的层位于所述第一蚀刻阻档图案层所在的层的下方；采用第一蚀刻剂对所述面板进行第一次蚀刻，使得所述面板在设置有所述第一蚀刻阻档图案层的位置形成第一蚀刻深度，在未设置有所述第一蚀刻阻档图案层的位置形成第二蚀刻深度，通过控制蚀刻时间使得所述第二蚀刻深度深于所述第一蚀刻阻档图案层的底面；采用第二蚀刻剂对所述面板进行第二次蚀刻，将所述第一蚀刻阻档图案层蚀刻掉；采用所述第一蚀刻剂对所述面板进行第三次蚀刻，使得所述面板在设置有所述第二蚀刻阻档图案层的位置和在未设置有所述第二蚀刻阻档图案层的位置同步蚀刻直至蚀刻到未设置有所述第二蚀刻阻档图案层的位置的蚀刻深度深于所述第二蚀刻阻档图案层的底面；采用所述第二蚀刻剂对所述面板进行第四次蚀刻，将所述第二蚀刻阻档图案层蚀刻掉；采用所述第一蚀刻剂对所述面板进行第五次蚀刻；其中，所述层叠结构包括由下至上的基板、阻隔层、缓冲层、主动层、覆盖所述主动层的栅极绝缘层、栅极图案层、覆盖所述栅极图案层的电容介电层、电容电极图案层及覆盖所述电容电极图案层的绝缘层，所述第一蚀刻阻档图案层与所述电 容电极图案层同层设置于所述电容介电层的表面；所述第一蚀刻阻挡图案层与所述电容电极图案层采用同一光刻工艺同时图案化形成；所述第二蚀刻阻挡图案层与所述栅极图案层同层设置于所述栅极绝缘层的表面，且与所述栅极图案层采用同一光刻工艺同时图案化形成。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种差异化控制蚀刻深度的方法，其中，所述方法包括：在层叠结构的面板中的至少一层设置第一蚀刻阻档图案层；采用第一蚀刻剂对所述面板进行第一次蚀刻，使得所述面板在设置有所述第一蚀刻阻档图案层的位置形成第一蚀刻深度，在未设置有所述第一蚀刻阻档图案层的位置形成第二蚀刻深度，通过控制蚀刻时间使得所述第二蚀刻深度深于所述第一蚀刻阻档图案层的底面；采用第二蚀刻剂对所述面板进行第二次蚀刻，将所述第一蚀刻阻档图案层蚀刻掉。
本发明的有益效果是：区别于现有技术的情况，本发明通过在层叠结构的面板中的至少一层设置第一蚀刻阻档图案层；采用第一蚀刻剂对面板进行第一次蚀刻，使得面板在设置有第一蚀刻阻档图案层的位置形成第一蚀刻深度，在未设置有第一蚀刻阻档图案层的位置形成第二蚀刻深度，通过控制蚀刻时间使得第二蚀刻深度深于第一蚀刻阻档图案层的底面；采用第二蚀刻剂对面板进行第二次蚀刻，将第一蚀刻阻档图案层蚀刻掉的方法，使得未设有第一蚀刻阻档图案层的位置与设有第一蚀刻阻档图案层的位置形成深度差异化，进而使得在同一道光罩工艺中仅通过转换蚀刻剂即可蚀刻出不同的深度，减少了工艺耗时，降低了生产成本。
【附图说明】
图1是本发明提供的差异化控制蚀刻深度的方法第一实施例的流程示意图；
图2是图1中层叠结构在步骤S12中的状态示意图；
图3是图1中层叠结构在步骤S13中的状态示意图；
图4是本发明提供的差异化控制蚀刻深度的方法第二实施例的流程示意图；
图5是图4中层叠结构在步骤S22中的状态示意图；
图6是图4中层叠结构在步骤S23中的状态示意图；
图7是图4中层叠结构在步骤S24中的状态示意图；
图8是图4中层叠结构在步骤S25中的状态示意图。
【具体实施方式】
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的一种差异化控制蚀刻深度的方法做进一步详细描述。
参阅图1和图2，本发明提供的差异化控制蚀刻深度的方法的第一实施例包括：
S11：在层叠结构的面板中的至少一层设置第一蚀刻阻档图案层110；
为了便于说明，在本实施例中，层叠结构以柔性显示面板中的层叠结构为例，即该层叠结构包括由下至上的基板101、阻隔层102、缓冲层103、主动层104、覆盖主动层104的栅极绝缘层105、栅极图案层106、覆盖栅极图案层106的电容介电层107、电容电极图案层108及覆盖电容电极图案层108的绝缘层109。
一般的，在柔性显示面板的层叠结构中，需要蚀刻出不同深度的待蚀刻孔，比如图1中所示的待蚀刻孔A1及待蚀刻孔B1，待蚀刻孔A1用于实现数据线与主动层104接触，因而需要蚀刻至主动层104的上表面，待蚀刻孔B1用于减轻面板弯曲时的应力，需要蚀刻至缓冲层103的上表面，因此，在本实施例中，待蚀刻孔A1的待蚀刻深度小于待蚀刻孔B1的待蚀刻深度。
进一步地，在待蚀刻孔A1的位置设置第一蚀刻阻挡图案层110。
可选的，在待蚀刻孔A1的位置，在电容介电层107的上表面形成与电容电极图案层108同层设置的第一蚀刻阻挡图案层110，且为了简化工艺，可在形成电容电极图案层108的同时采用同一道光刻工艺形成第一蚀刻阻挡图案层110。
其中，层叠结构的材料为无机材料，比如SiNx或SiO2，第一蚀刻阻挡图案层108的材料为金属材料，比如Mo、Ti、A1l或TiA1l合金金属。
S12：采用第一蚀刻剂对面板进行第一次蚀刻，使得面板在设置有第一蚀刻阻档图案层110的位置形成第一蚀刻深度，在未设置有第一蚀刻阻档图案层110的位置形成第二蚀刻深度，通过控制蚀刻时间使得第二蚀刻深度深于第一蚀刻阻档图案层110的底面；
具体地，采用第一蚀刻剂对面板进行第一次蚀刻，在待蚀刻孔A1及待蚀刻孔B1的位置会同时被蚀刻，如图2中箭头所示，当待蚀刻孔A1的位置处蚀刻到第一蚀刻阻挡图案层110的上表面时，由于蚀刻剂不能蚀刻第一蚀刻阻挡图案层110而停止蚀刻，形成第一待蚀刻深度，而待蚀刻孔B1由于未设置第一蚀 刻阻挡图案层110而会继续蚀刻，此时，通过控制蚀刻时间，使得待蚀刻孔B1的位置蚀刻到超过第一蚀刻阻挡图案层110底面的位置，形成第二蚀刻深度，且在本实施例中，可通过控制蚀刻时间使超过第一蚀刻阻挡图案层110底面的深度等于主动层104的厚度。
其中，当采用干法蚀刻时，第一蚀刻剂可以是包括但不限于CF4与O2的混合气体或C2FH5、A1r与H2的混合气体；当采用湿法蚀刻时，第一蚀刻剂可以是包括但不限于HF或B1OE的液体。
S13：采用第二蚀刻剂对面板进行第二次蚀刻，将第一蚀刻阻档图案层110蚀刻掉。
具体地，采用第二蚀刻剂对面板进行第二次蚀刻，如图3中箭头所示，由于第二蚀刻剂不能蚀刻无机材料的层叠结构，只能对金属材料的第一蚀刻阻挡图案层110进行蚀刻，而使得在待蚀刻孔B1的位置不进行蚀刻，待蚀刻孔A1的位置继续蚀刻，直至将第一蚀刻阻挡图案层蚀刻掉，由于在步骤S12中，第二蚀刻深度深于第一蚀刻阻档图案层110的底面，而使得待蚀刻孔B1的蚀刻深度要大于待蚀刻孔A1的蚀刻深度。
其中，当采用干法蚀刻时，第二蚀刻剂可以是包括但不限于SF6与O2的混合气体、Cl2与O2的混合气体或Cl2与B1F3的混合气体；当采用湿法蚀刻时，第二蚀刻剂可以是包括但不限于H3PO4、HNO3或HCOOH的液体。
进一步地，在本实施例中，为了使得待蚀刻孔A1与主动层104接触，待蚀刻孔B1与缓冲层103接触，可重复使用第一蚀刻剂对面板进行蚀刻，直至待蚀刻孔A1蚀刻到与主动层104接触、待蚀刻孔B1蚀刻到与缓冲层103接触，且由于步骤S12中，可通过控制蚀刻时间使超过第一蚀刻阻挡图案层110底面的深度等于主动层104的厚度，使得在继续蚀刻时，待蚀刻孔A1与待蚀刻孔B1可同时分别与主动层104及缓冲层103接触，此时即可完成待蚀刻孔A1与待蚀刻孔B1的蚀刻。
参阅图4及图5，本发明提供的差异化控制蚀刻深度的方法的第二实施例包括：
S21：在层叠结构的面板中的至少一层设置第一蚀刻阻挡图案层210及第二蚀刻阻档图案层211；
其中，第二蚀刻阻挡图案层211所在的层位于第一蚀刻阻挡图案层210所在的层的下方，且第二蚀刻阻挡图案层211的图案的数量少于第一蚀刻阻挡图 案层210的图案的数量。
如图5所示，本实施例中，柔性显示面板的层叠结构中的待蚀刻孔以待蚀刻孔A2、待蚀刻孔B2及待蚀刻孔C为例，其中，待蚀刻A2、待蚀刻孔B2与上述第一实施例中的待蚀刻孔A1、待蚀刻孔B1相同，待蚀刻孔C用于实现更大曲率半径的弯折，需要蚀刻至基板201。
具体地，在待蚀刻孔A2的位置设置第一蚀刻阻挡图案层210及第二蚀刻阻挡图案层211，在待蚀刻孔B2的位置设置第一蚀刻阻挡图案层210，设置第一蚀刻阻挡图案层210的方法与上述第一实施例相同，设置第二蚀刻阻挡图案层211时，可在栅极绝缘层205的表面形成与栅极图案层206同层设置的第二蚀刻阻挡图案层211，且为了简化工艺，可在形成栅极图案层206的同时采用同一道光刻工艺形成第二蚀刻阻挡图案层211。
S22：采用第一蚀刻剂对面板进行第一次蚀刻，使得面板在设置有第一蚀刻阻档图案层210的位置形成第一蚀刻深度，在未设置有第一蚀刻阻档图案层210的位置形成第二蚀刻深度，通过控制蚀刻时间使得第二蚀刻深度深于第一蚀刻阻档图案层210的底面；
具体地，采用第一蚀刻剂对面板进行第一次蚀刻，如图5中箭头所示，在待蚀刻孔A2及待蚀刻孔B2的位置由于第一蚀刻阻挡图案层210的存在而停止蚀刻，待蚀刻孔C可继续蚀刻，并蚀刻至超过第一蚀刻阻挡图案层210的底面的位置，具体原理与上述第一实施例中的步骤S12相同，在此不再赘述，在本实施例中，待蚀刻孔C的位置在该步骤中的超过第一蚀刻阻挡图案层210的底面的深度等于阻隔层202和缓冲层203的厚度之和。
S23：采用第二蚀刻剂对面板进行第二次蚀刻，将第一蚀刻阻档图案层210蚀刻掉；
具体地，采用第二蚀刻剂对面板进行第二次蚀刻，如图6中箭头所示，在待蚀刻孔A2及待蚀刻孔B2的位置将第一蚀刻阻挡图案层210蚀刻掉，而待蚀刻孔C位置不会进行蚀刻，原理与上述步骤S13相同，在此不再赘述。
S24：采用第一蚀刻剂对面板进行第三次蚀刻，使得面板在设置有第二蚀刻阻档图案层211的位置和在未设置有第二蚀刻阻档图案层211的位置同步蚀刻直至未设置有所述第二蚀刻阻档图案层211的位置的蚀刻深度深于第二蚀刻阻档图案层211的底面；
具体地，当步骤S23中蚀刻掉第一蚀刻阻挡图案层210之后，转换蚀刻剂， 继续使用第一蚀刻剂对面板进行蚀刻，此时，待蚀刻孔A2、待蚀刻孔B2及待蚀刻孔C同步蚀刻，如图7中箭头所示，当待蚀刻孔A2位置蚀刻到第二蚀刻阻挡图案层的表面时待蚀刻孔A2的位置停止蚀刻，待蚀刻孔B2与待蚀刻孔C继续蚀刻，通过控制蚀刻时间使得待蚀刻孔B2位置的蚀刻深度超过第二蚀刻阻挡图案层211的底面，且在本实施例中，待蚀刻孔B2位置超过第二蚀刻阻挡图案层211的底面的深度等于主动层204的厚度。
S25：采用第二蚀刻剂对面板进行第四次蚀刻，将第二蚀刻阻档图案层211蚀刻掉。
参阅图8，继续转换蚀刻剂，采用与步骤S23中相同的第二蚀刻剂将第二蚀刻阻挡层211蚀刻掉，此时，待蚀刻孔B2与待蚀刻孔C不会被蚀刻，且此时，在三个待蚀刻孔的位置，剩余的待蚀刻深度是相同的。
S26：采用第一蚀刻剂对面板进行第五次蚀刻。
继续转换蚀刻剂，采用第一蚀刻剂继续对待蚀刻孔A2、待蚀刻孔B2及待蚀刻孔C进行蚀刻，由于三个待蚀刻孔剩余的待蚀刻深度相同，因此，待蚀刻孔A2与主动层204接触、待蚀刻孔B2与缓冲层203接触、待蚀刻孔C与基板201接触可同时蚀刻完成，进而形成三个不同深度的蚀刻孔。
区别于现有技术的情况，本发明通过在层叠结构的面板中的至少一层设置第一蚀刻阻档图案层；采用第一蚀刻剂对面板进行第一次蚀刻，使得面板在设置有第一蚀刻阻档图案层的位置形成第一蚀刻深度，在未设置有第一蚀刻阻档图案层的位置形成第二蚀刻深度，通过控制蚀刻时间使得第二蚀刻深度深于第一蚀刻阻档图案层的底面；采用第二蚀刻剂对面板进行第二次蚀刻，将第一蚀刻阻档图案层蚀刻掉的方法，使得未设有第一蚀刻阻档图案层的位置与设有第一蚀刻阻档图案层的位置形成深度差异化，进而使得在同一道光罩工艺中仅通过转换蚀刻剂即可蚀刻出不同的深度，减少了工艺耗时，降低了生产成本。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种差异化控制蚀刻深度的方法，其中，所述方法包括：
    在层叠结构的面板中的至少一层设置第一蚀刻阻档图案层，在所述层叠结构的面板中的至少一层设置第二蚀刻阻档图案层，其中所述第二蚀刻阻档图案层所在的层位于所述第一蚀刻阻档图案层所在的层的下方；
    采用第一蚀刻剂对所述面板进行第一次蚀刻，使得所述面板在设置有所述第一蚀刻阻档图案层的位置形成第一蚀刻深度，在未设置有所述第一蚀刻阻档图案层的位置形成第二蚀刻深度，通过控制蚀刻时间使得所述第二蚀刻深度深于所述第一蚀刻阻档图案层的底面；
    采用第二蚀刻剂对所述面板进行第二次蚀刻，将所述第一蚀刻阻档图案层蚀刻掉；
    采用所述第一蚀刻剂对所述面板进行第三次蚀刻，使得所述面板在设置有所述第二蚀刻阻档图案层的位置和在未设置有所述第二蚀刻阻档图案层的位置同步蚀刻直至蚀刻到未设置有所述第二蚀刻阻档图案层的位置的蚀刻深度深于所述第二蚀刻阻档图案层的底面；
    采用所述第二蚀刻剂对所述面板进行第四次蚀刻，将所述第二蚀刻阻档图案层蚀刻掉；
    采用所述第一蚀刻剂对所述面板进行第五次蚀刻；
    其中，所述层叠结构包括由下至上的基板、阻隔层、缓冲层、主动层、覆盖所述主动层的栅极绝缘层、栅极图案层、覆盖所述栅极图案层的电容介电层、电容电极图案层及覆盖所述电容电极图案层的绝缘层，所述第一蚀刻阻档图案层与所述电容电极图案层同层设置于所述电容介电层的表面；
    所述第一蚀刻阻挡图案层与所述电容电极图案层采用同一光刻工艺同时图案化形成；
    所述第二蚀刻阻挡图案层与所述栅极图案层同层设置于所述栅极绝缘层的表面，且与所述栅极图案层采用同一光刻工艺同时图案化形成。
  2. 根据权利要求1所述的方法，其中，所述第二蚀刻阻挡图案层的图案的数量少于所述第一蚀刻阻挡图案层的图案的数量。
  3. 根据权利要求2所述的方法，其中，所述采用所述第一蚀刻剂对所述面 板进行第五次蚀刻包括：
    采用所述第一蚀刻剂对所述面板进行第五次蚀刻，使得所述面板在设有所述第一蚀刻阻档图案层及所述第二蚀刻阻档图案层的位置蚀刻至所述主动层、所述面板设有所述第一蚀刻阻挡图案层且未设有所述第二蚀刻阻档图案层的位置蚀刻至所述缓冲层。
  4. 根据权利要求1所述的方法，其中，所述蚀刻为干法蚀刻，所述第一蚀刻剂为CF4与O2的混合气体或C2FH5、Alr与H2的混合气体，所述第二蚀刻剂为SF6与O2的混合气体、Cl2与O2的混合气体或Cl2与BlF3的混合气体。
  5. 根据权利要求1所述的方法，其中，所述蚀刻为湿法蚀刻，所述第一蚀刻剂为HF或BlOE，所述第二蚀刻剂为H3PO4、HNO3或HCOOH。
  6. 一种差异化控制蚀刻深度的方法，其中，所述方法包括：
    在层叠结构的面板中的至少一层设置第一蚀刻阻档图案层；
    采用第一蚀刻剂对所述面板进行第一次蚀刻，使得所述面板在设置有所述第一蚀刻阻档图案层的位置形成第一蚀刻深度，在未设置有所述第一蚀刻阻档图案层的位置形成第二蚀刻深度，通过控制蚀刻时间使得所述第二蚀刻深度深于所述第一蚀刻阻档图案层的底面；
    采用第二蚀刻剂对所述面板进行第二次蚀刻，将所述第一蚀刻阻档图案层蚀刻掉。
  7. 根据权利要求6所述的方法，其中，所述在层叠结构的面板中的至少一层设置第一蚀刻阻档图案层还包括：
    在所述层叠结构的面板中的至少一层设置第二蚀刻阻档图案层，其中所述第二蚀刻阻档图案层所在的层位于所述第一蚀刻阻档图案层所在的层的下方；
    所述采用第二蚀刻剂对所述面板进行第二次蚀刻，将所述第一蚀刻阻档图案层蚀刻掉之后进一步包括：
    采用所述第一蚀刻剂对所述面板进行第三次蚀刻，使得所述面板在设置有所述第二蚀刻阻档图案层的位置和在未设置有所述第二蚀刻阻档图案层的位置同步蚀刻直至蚀刻到未设置有所述第二蚀刻阻档图案层的位置的蚀刻深度深于所述第二蚀刻阻档图案层的底面；
    采用所述第二蚀刻剂对所述面板进行第四次蚀刻，将所述第二蚀刻阻档图案层蚀刻掉。
  8. 根据权利要求7所述的方法，其中，所述采用所述第二蚀刻剂对所述面 板进行第四次蚀刻，将所述第二蚀刻阻档图案层蚀刻掉之后进一步包括：
    采用所述第一蚀刻剂对所述面板进行第五次蚀刻。
  9. 根据权利要求8所述的方法，其中，所述层叠结构包括由下至上的基板、阻隔层、缓冲层、主动层、覆盖所述主动层的栅极绝缘层、栅极图案层、覆盖所述栅极图案层的电容介电层、电容电极图案层及覆盖所述电容电极图案层的绝缘层，所述第一蚀刻阻档图案层与所述电容电极图案层同层设置于所述电容介电层的表面。
  10. 根据权利要求9所述的方法，其中，所述第一蚀刻阻挡图案层与所述电容电极图案层采用同一光刻工艺同时图案化形成。
  11. 根据权利要求9所述的方法，其中，所述第二蚀刻阻挡图案层与所述栅极图案层同层设置于所述栅极绝缘层的表面，且与所述栅极图案层采用同一光刻工艺同时图案化形成。
  12. 根据权利要求11所述的方法，其中，所述第二蚀刻阻挡图案层的图案的数量少于所述第一蚀刻阻挡图案层的图案的数量。
  13. 根据权利要求12所述的方法，其中，所述采用所述第一蚀刻剂对所述面板进行第五次蚀刻包括：
    采用所述第一蚀刻剂对所述面板进行第五次蚀刻，使得所述面板在设有所述第一蚀刻阻档图案层及所述第二蚀刻阻档图案层的位置蚀刻至所述主动层、所述面板设有所述第一蚀刻阻挡图案层且未设有所述第二蚀刻阻档图案层的位置蚀刻至所述缓冲层。
  14. 根据权利要求6所述的方法，其中，所述蚀刻为干法蚀刻，所述第一蚀刻剂为CF4与O2的混合气体或C2FH5、Alr与H2的混合气体，所述第二蚀刻剂为SF6与O2的混合气体、Cl2与O2的混合气体或Cl2与BlF3的混合气体。
  15. 根据权利要求6所述的方法，其中，所述蚀刻为湿法蚀刻，所述第一蚀刻剂为HF或BlOE，所述第二蚀刻剂为H3PO4、HNO3或HCOOH。
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