WO2018171187A1 - 面板测试装置 - Google Patents

面板测试装置 Download PDF

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Publication number
WO2018171187A1
WO2018171187A1 PCT/CN2017/107435 CN2017107435W WO2018171187A1 WO 2018171187 A1 WO2018171187 A1 WO 2018171187A1 CN 2017107435 W CN2017107435 W CN 2017107435W WO 2018171187 A1 WO2018171187 A1 WO 2018171187A1
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WO
WIPO (PCT)
Prior art keywords
test
pin
testing device
panel
signal
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PCT/CN2017/107435
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English (en)
French (fr)
Inventor
艾雨
谢学武
刘博文
孙诗
刘浩
韩坤
张阿猛
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/758,869 priority Critical patent/US10559239B2/en
Publication of WO2018171187A1 publication Critical patent/WO2018171187A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0425—Test clips, e.g. for IC's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
    • G01R1/06716—Elastic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3172—Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/191—Deposition of organic active material characterised by provisions for the orientation or alignment of the layer to be deposited
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0693—Calibration of display systems
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • Embodiments of the present disclosure relate to a panel testing device.
  • test pin corresponds to the signal pin in the panel pad (Pad); due to the higher resolution of the current panel, in actual production, the alignment deviation (test pin) It is difficult to avoid the misalignment of the signal pin, which affects the accuracy of the detection process for the signal pin.
  • the panel testing device provided by the embodiment of the present disclosure can better align the signal pin and the test pin, avoid misalignment of the signal pin and the test pin, and improve the detection accuracy.
  • Embodiments of the present disclosure provide a panel testing device including: a support member; and a plurality of test pins disposed on the support member, wherein the plurality of test pins and the plurality of signal pins on the panel to be tested are one by one Correspondingly, any of the test pins satisfies: d ⁇ D ⁇ d + L; wherein D is the width of the test pin; d is the width of the signal pin corresponding to the test; L is the signal pin and its adjacent The minimum distance between the signal pins.
  • Figure 1 is a plan view of the test block
  • FIG. 2 is a top view of a panel to be tested
  • 3 is a top view of the panel to be tested and the test block in alignment
  • FIG. 5 is a top plan view of a panel testing device according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic view of the panel testing device of the embodiment of the present disclosure as viewed from the back;
  • Figure 7 is a cross-sectional view of a conductive member of an embodiment of the present disclosure.
  • Figure 8 is a cross-sectional view of a conductive member according to another embodiment of the present disclosure.
  • FIG. 9 is a top view of the panel testing device of the embodiment of the present disclosure in alignment with the panel to be tested;
  • FIG. 10 is a top view of the panel testing device and the panel to be tested in a dislocated position according to an embodiment of the present disclosure
  • Figure 11 is a front elevational view of the panel testing device of the embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a conductive member according to still another embodiment of the present disclosure.
  • Figure 1 is a schematic diagram of a test pin on a test block
  • Figure 2 is a schematic view of a signal pin on a panel pad.
  • the resolution is 3840*2160. Since four sub-pixels of RGBW are used to form one pixel, the data signal input side (ie, the source side) has 15360 (3840*4) metal lines.
  • the width of the signal pin on the panel is narrow and the pitch is small, so that it is difficult to ensure that the test pin on the test block has a one-to-one correspondence with the position of the signal pin Pin in the panel pad, which may cause a misalignment.
  • Figure 3 is a schematic diagram of the alignment of the test pin on the test block and the position of the signal pin in the panel pad.
  • Figure 4 shows the misalignment of the test pin on the test block and the position of the signal pin in the panel pad. schematic diagram. In actual production, the situation in Figure 4 often occurs. The test pin on the test block and the signal pin in the panel pad are misaligned (the position of the signal pin is misjudged), which affects the accuracy of the judgment.
  • the panel testing device provided by the embodiment of the present disclosure, as shown in FIG. 5, FIG. 9 and FIG. 10, includes: a support member 1; and a plurality of test pins 2 disposed on the support member 1, a plurality of the test pins The position of 2 corresponds one-to-one with the position of the signal pin 4 on the panel 3 to be tested, and any of the test pins 2 satisfies: d ⁇ D ⁇ d + L.
  • the panel testing device provided by the present disclosure increases the width of the test pin 2, so that when the panel testing device is aligned with the panel 3 to be tested, the signal pin 4 and the test pin 2 can be better aligned to avoid signal pin 4
  • the condition of the misalignment of the test pin 2 is such that the state of each of the signal pins 4 is accurately detected, which effectively improves the detection accuracy of the signal pin 4.
  • each test pin 2 has the same width D.
  • each signal pin 4 has the same width d.
  • the width between each two adjacent signal pins is equal and equal to the minimum pitch described above. The above configuration enables the alignment operation between the signal pin and the test pin to be performed more quickly and efficiently.
  • the width of the test pin 2 is larger than the width of the signal pin 4, so that the projection of the test pin 2 in the direction perpendicular to the plane of the panel 3 to be tested (y direction) during the alignment operation is
  • the projections of the signal pins 4 in the y direction are completely overlapped, making it easier to achieve accurate alignment.
  • test pin 2 is projected in the direction (y direction) perpendicular to the plane of the panel 3 to be tested and the test pin 2
  • two adjacent test pins 2 are on different levels (which may include two layers, three layers, four layers, etc., all of which can achieve the purpose of the present application), ensuring adjacent test pins 2 They are independent of each other, preventing the adjacent test pins 2 from being short-circuited and affecting the detection accuracy of the signal pins 4.
  • a plurality of test pins 2a, 2b are arranged in two rows, the test pin 2a is located on the upper layer, and the test pin 2b is located on the lower layer, thereby avoiding shorting between adjacent test pins 2a, 2b.
  • the support member 1 is provided with grooves of different depths, the depths of the adjacent grooves are different, and the test pin 2 is installed in the groove, so that the adjacent test pins 2 are realized on different levels.
  • the support member 1 is provided with a plurality of grooves 8a, 8b having a depth smaller than the depth of the groove 8b.
  • the test pin 2a mounted in the recess 8a is located on the upper layer
  • the test pin 2b mounted in the recess 8b is located on the lower layer.
  • This structure may be that the connection between the test pin and the support 1 is more stable. It can be understood that the test pin can also be fixed to the support by other means, such as by riveting, welding or the like.
  • the plurality of test pins 2 are parallel to each other, which further ensures the accuracy of the alignment.
  • the arrangement of the test pin 2 is consistent with the arrangement of the signal pin 4. By optimizing the layout of the test pin 2, it is more advantageous to detect the signal pin 4 and also reduce the difficulty in manufacturing the panel test device.
  • the panel testing device further includes: a conductive member 50 for resisting the signal pin 4, disposed on the test pin 2, and connected (electrically connected) to the test pin 2, tested
  • the needle 2 is electrically connected to the corresponding signal pin 4 through the conductive member 50 disposed thereon, and the conductive member 50 is better in contact with the test pin 2.
  • a plurality of conductive members 50 are covered on the test pin 2 (ie, the test pins 2 are evenly distributed by the plurality of conductive members 50) such that the conductive members 50 on the test pins 2 are aligned with the corresponding signal pins 4. At least a portion of the conductive member 50 is in contact with the signal pin 4.
  • multiple guides on each signal pin 4 The electrical components 50 are arranged in a matrix, and in the lateral and longitudinal directions, the plurality of conductive members 50 are arranged in an equally spaced manner.
  • the conductive member 50 is disposed on the side of the test pin 2 near the panel 3 to be tested (i.e., the back side of the test pin 2).
  • the signal pin 4 is placed under the test pin 2 to be in contact with the conductive member 50 on the back side.
  • Figure 12 illustrates a top view of the test pin 2 with the conductive member 50 disposed on the side of the test pin 2 remote from the panel 3 to be tested, i.e., the front side of the test pin 2.
  • the signal pin 4 is placed above the test pin 2 to make it contact with the conductive member 50 on the front side.
  • the conductive member 50 includes: a conductive portion 5; and an insulating portion 6 disposed at least on a pair of opposite sides of the conductive portion 5, the pair The opposite sides are, for example, two sides in the lateral direction (longitudinal direction) of the support member 1 to prevent the conductive members 50 on the adjacent test pins 2 from being short-circuited by the oblique contact (the conductive members 50 on the adjacent test pins 2)
  • the insulating portion 6 on the side faces are in contact with each other, so that the communication is not short-circuited, and the accuracy of the detection is ensured.
  • the conductive portion 5 is made of a conductive material such as a metal or an alloy or the like.
  • the insulating portion 6 is made of an insulating material such as silicon dioxide, nitrogen oxide or the like.
  • the projection of the test pin 2 in the y direction and the projection of the signal pin 4 corresponding to the test pin 2 in the y direction overlap each other, as shown in FIG. 9, the y direction is perpendicular to the panel 3 to be tested. flat.
  • the test pin 2 and the signal pin 4 are electrically connected to each other by at least one conductive member 50 in the overlapping region.
  • the insulating portion 6 is disposed on a pair of opposite sides of the conductive portion 5 in the x direction such that the test pin 2 is electrically connected in the y direction with the signal pin 4 corresponding to the test pin 2, the y direction Vertical to the x direction.
  • the conductive member 50 further includes an elastic portion 7 on which the conductive portion 5 is wrapped.
  • the conductive portion covers the entire surface of the elastic portion 7 so that the surface thereof has almost no exposed portion.
  • the elastic portion 7 can make the conductive member 50 elastically deform, and better ensure that the conductive member 50 is in compact contact with the corresponding signal pin 4, thereby avoiding the situation of contact failure.
  • the elastic portion 7 is made of an elastic material.
  • the conductive members 50 are evenly arranged on the test pin 2, and each of the conductive members 50 on the same test pin 2 is in communication with the test pin 2. As long as there is a conductive member 50 and a corresponding signal pin 4 on the test pin 2 Contact is the purpose of communication, and the test accuracy is better and the utility is better.
  • the conductive member 50 is in the shape of a ball (as shown in Figures 7 and 12) or Column shape (as shown in Figure 8).
  • the conductive member 50 can also be other shapes, such as an elliptical shape, a rectangular shape, etc., which can achieve the object of the present disclosure and fall within the protection scope of the present disclosure.
  • the support member 1 is elongated and transverse, the plurality of test pins 2 are located on one side of the support member 1, and the plurality of tests One end of the needle 2 adjacent to the support member 1 is fixed on the support member 1, which is more convenient for taking and storing the panel test device, and is also convenient for the panel test device to be aligned with the panel 3.
  • the width d of the plurality of signal pins 4 are equal, and the spacing L between the adjacent two signal pins is also equal.
  • the width D of the plurality of test pins 2 is also They are all equal, and the spacing L0 between two adjacent test pins 2 is designed to be equal. In this case, the pitch L0 is smaller than the pitch L.
  • the panel testing device provided by the embodiment of the present disclosure increases the width of the test pin, so that when the panel testing device and the detecting panel are aligned, the signal pin and the test pin can be better aligned to avoid occurrence.
  • the condition of the signal pin and the test pin being misaligned is such that the state of each signal pin is accurately detected, which effectively improves the detection accuracy of the signal pin.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Measuring Leads Or Probes (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

一种面板测试装置，包括：支撑件(1)和设置在支撑件(1)上的多个测试针(2)，其中多个测试针(2)与待测面板(3)上的多个信号针(4)一一对应，任一测试针(2)满足：d≤D≤d+L；其中，D为该测试针(2)的宽度；d为与该测试针(2)对应的信号针(4)的宽度；L为信号针(4)和其相邻信号针(4)之间的最小距离。本面板测试装置能够更好地实现信号针与测试针之间的对位，避免出现错位的状况，有效提升了信号针的检测精准性。

Description

面板测试装置
相关申请的交叉引用
本申请基于并且要求于2017年3月22日递交的中国专利申请第201710174015.3号的优先权，在此全文引用上述中国专利申请公开的内容。
技术领域
本公开实施例涉及一种面板测试装置。
背景技术
在LCD及OLED的生产过程中，经过切割后的面板需要进行测试Test，为了达到对不良的准确检出，需要用到全触点检测(Full Contact)，全触点检测是将测试块(Block)中的每个测试针(Pin)与面板(Panel)焊盘(Pad)中的信号针一一对应；由于目前面板的分辨率越来越高，在实际生产中，对位偏差(测试针和信号针错位)很难避免，影响了检测工序对信号针不良检出的准确性。
发明内容
本公开实施例提供的面板测试装置，可以更好地对位信号针与测试针，避免信号针与测试针错位，提升检测精准性。
本公开实施例提供了一种面板测试装置，包括：支撑件；和设置在所述支撑件上的多个测试针，其中多个所述测试针与待测面板上的多个信号针一一对应，任一所述测试针满足：d≤D≤d+L；其中，D为该测试针的宽度；d为与该测试针对应的信号针的宽度；L为该信号针和其相邻的信号针之间的最小距离。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例， 而非对本公开的限制。
图1为测试块的俯视图；
图2为待测面板的俯视图；
图3为待测面板和测试块对位情况下的俯视图；
图4为待测面板和测试块错位情况下的俯视图；
图5为本公开实施例的面板测试装置的俯视图；
图6为本公开实施例的面板测试装置的从背面观察的示意图；
图7为本公开实施例的导电件的剖视图；
图8为本公开另一实施例的导电件的剖视图；
图9为本公开实施例的面板测试装置与待测面板对位情况下的俯视图；
图10为本公开实施例的面板测试装置与待测面板错位情况下的俯视图；
图11为本公开实施例的面板测试装置的主视图；
图12为本公开再一实施例的导电件的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对 象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为测试块上的测试针的示意图，图2为面板焊盘上信号针示意图。以目前的55”OLED为例，分辨率为3840*2160，由于采用RGBW四个亚像素组成一个像素，因此数据信号输入侧(即，source侧)有15360(3840*4)根金属线，这造成面板上的信号针的宽度很窄、间距(pitch)很小，使得要保证测试块上的测试针与面板焊盘中的信号针Pin位置一一对应很困难，会造成对位偏差。
图3为测试块上的测试针与面板焊盘中的信号针位置一致时的对位情况示意图，图4为测试块上的测试针与面板焊盘中的信号针位置不一致时的针错位情况示意图。实际生产中，图4的情况经常发生，测试块上的测试针与面板焊盘中的信号针错位的地方会检测出不良(对信号针的位置误判)，影响判断的准确性。
本公开实施例提供的面板测试装置，如图5、图9和图10所示，包括：支撑件1；和设置在所述支撑件1上的多个测试针2，多个所述测试针2的位置与待测面板3上的信号针4的位置一一对应，任一所述测试针2满足：d≤D≤d+L。
其中，D为测试针2的宽度；d为与该测试针对应的待测面板上的信号针4的宽度；L为相邻两个信号针4之间的最小间距。
本公开提供的面板测试装置，增大了测试针2的宽度，使得面板测试装置与待测面板3进行对位时，信号针4与测试针2能够更好地进行对位，避免出现信号针4与测试针2错位的状况，以使得各个信号针4的状态被准确地检测出，有效提升了信号针4的检测精准性。
在一个示例中，每个测试针2具有相同的宽度D。在另一个示例中，每个信号针4具有相同的宽度d。在再一个示例中，每两个相邻的信号针之间的宽度相等，且等于上述最小间距。以上构造能更快速高效地实现信号针与测试针之间的对位操作。
如图9所示，测试针2的宽度大于信号针4的宽度，这样，在对位操作时，测试针2在垂直于所述待测面板3的平面的方向(y方向)上的投影与信号针4在y方向上的投影完全重叠，从而更容易实现准确的对位。
在面板测试装置与待测面板3对位时，由于测试针2的宽度增大，这就 保证了测试针2上至少部分区域与相应地信号针4能够接触而连通，从而有效增加测试针2和信号针4的对位准确性，使得各个信号针4的状态被准确的检测出，确保信号针4的检测质量。
如图10所示，在对位操作时，即使存在一定的对位偏差，但由于测试针2在垂直于所述待测面板3的平面的方向(y方向)上的投影与该测试针2对应的信号针4在y方向上的投影部分重叠，这样，仍能保持测试针2与信号针4之间的电连通。
至少一些实施例中，相邻两个所述测试针2处于不同的层面(可以包括两层、三层、四层等，均可实现本申请的目的)上，确保相邻的测试针2之间相互独立，防止相邻的测试针2短接而影响信号针4的检测准确性。例如，如图11所示，多个测试针2a、2b排列成上下两行，测试针2a位于上层，测试针2b位于下层，由此避免相邻测试针2a、2b之间的短接。
至少一些实施例中，支撑件1上设置有不同深度的凹槽，相邻凹槽的深度不同，测试针2安装在凹槽内，这样相邻的测试针2就实现了处于不同的层面上。如图11所示，支撑件1上设置有多个凹槽8a、8b，凹槽8a的深度比凹槽8b的深度小。这样，安装在凹槽8a中的测试针2a位于上层，安装在凹槽8b中的测试针2b位于下层。该结构可以是测试针与支撑件1之间的连接更稳固。可以理解，还可以采用其他方式将测试针固定于支撑件上，例如通过铆接、焊接等方式。
至少一些实施例中，所述多个测试针2相互平行，这样进一步确保对位的准确性。测试针2的布置方式与信号针4的布置方式相一致，通过优化测试针2的布局，更有利于检测信号针4，同时也降低了面板测试装置的制作难度。
至少一些实施例中，如图6所示，所述面板测试装置还包括：用于抵触信号针4的导电件50，设置在测试针2上、并与测试针2连通(电连接)，测试针2通过其上设置的导电件50与对应的信号针4导通，导电件50可更好地与测试针2接触。
例如，多个导电件50布满在测试针2上(即：测试针2上由多个导电件50均匀分布)，这样测试针2上的导电件50在与对应的信号针4对位时，至少部分导电件50会与信号针4接触连通。例如，每个信号针4上的多个导 电件50以矩阵方式排布，并且在横向和纵向上，多个导电件50以等间距方式排列。
如图6所示，导电件50设置在测试针2靠近待测面板3的一侧(即测试针2的背面)。在对位操作时，信号针4放置于测试针2下方，使其与背面的导电件50接触。图12示意了测试针2的俯视图，其中导电件50设置在测试针2远离待测面板3的一侧，即测试针2的正面。在对位操作时，信号针4放置于测试针2的上方，使其与正面的导电件50接触。
至少一些实施例中，如图7和图8所示，所述导电件50包括：导电部5；和绝缘部6，至少设置在所述导电部5的一对相对的侧面上，该一对相对的侧面例如为处于支撑件1的横向(长度方向)上的两个侧面，防止相邻测试针2上的导电件50因倾斜相碰而短接(相邻测试针2上的导电件50在倾斜抵触时，是通过侧面上的绝缘部6抵触在一起的，因此不会短接连通)，确保检测的准确性。导电部5由导电材料制成，例如金属或合金等。绝缘部6由绝缘材料制成，例如二氧化硅、氧化氮等。
至少一些实施例中，测试针2在y方向上的投影和对应于该测试针2的信号针4在y方向上的投影彼此重叠，如图9所示，y方向垂直于待测面板3的平面。当测试针2上设置有导电件50时，在重叠区域中，测试针2与信号针4通过至少一个导电件50彼此电连接。例如，如图7所示，绝缘部6设置在导电部5沿x方向的一对相对侧面上，使得测试针2与对应于该测试针2的信号针4在y方向上电连接，y方向与x方向垂直。这样，可以防止相邻测试针2上的导电件50因倾斜相碰而短接。
至少一些实施例中，如图7和图8所示，所述导电件50还包括：弹性部7，所述导电部5包裹在所述弹性部7上。导电部覆盖在弹性部7的整个表面，使其表面几乎没有暴露区域。弹性部7可使得导电件50能够发生弹性变形，更好地确保导电件50与相应的信号针4压实接触，避免出现接触不实的情况。弹性部7由弹性材料制成。
上述实施例中，导电件50均匀布置在测试针2上，同一测试针2上的各个导电件50均与该测试针2连通，测试针2上只要有一个导电件50与对应的信号针4接触即实现了连通的目的，其测试准确性更好、实用性更好。
至少一些实施例中，所述导电件50呈球形状(如图7和图12所示)或 柱形状(如图8所示)。
可以理解，导电件50也可以是其它形状，如椭圆形状，矩形状等，均可实现本公开的目的，并且属于本公开的保护范围内。
至少一些实施例中，如图5所示，所述支撑件1呈长条形板状且横置，所述多个测试针2位于所述支撑件1的一侧，且所述多个测试针2的临近所述支撑件1的一端固定在所述支撑件1上，更利于拿取和存放面板测试装置，同时也方便于面板测试装置与面板3对位检测。
至少一些实施例中，如图9、10所示，多个信号针4的宽度d均相等，相邻两信号针之间的间距L也均相等，同样，多个测试针2的宽度D也均相等，相邻两测试针2之间的间距L0设计为也相等。在此情况下，间距L0小于间距L。
综上所述，本公开实施例提供的面板测试装置，增大了测试针的宽度，使得面板测试装置与检测面板进行对位时，信号针与测试针能够更好地进行对位，避免出现信号针与测试针错位的状况，以使得各个信号针的状态被准确地检测出，有效提升了信号针的检测精准性。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。另外，有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。

Claims (14)

  1. 一种面板测试装置，包括：
    支撑件；和
    设置在所述支撑件上的多个测试针，其中多个所述测试针与待测面板上的多个信号针一一对应，任一所述测试针满足：d≤D≤d+L；
    其中，D为该测试针的宽度；d为与该测试针对应的信号针的宽度；L为该信号针和其相邻信号针之间的最小间距。
  2. 根据权利要求1所述的面板测试装置，其中相邻两个测试针处于不同的层面上。
  3. 根据权利要求1或2所述的面板测试装置，其中所述支撑件包括凹槽，至少一个测试针设置在所述凹槽内。
  4. 根据权利要求1至3中任一项所述的面板测试装置，其中多个所述测试针相互平行。
  5. 根据权利要求1至4中任一项所述的面板测试装置，还包括：
    用于抵触信号针的导电件，其中所述导电件设置在至少一个测试针上、并与至少一个测试针电连接，该至少一个测试针通过该导电件与该测试针对应的信号针电连接。
  6. 根据权利要求5所述的面板测试装置，其中所述导电件包括：
    导电部；和
    绝缘部，至少设置在所述导电部沿第一方向的一对相对的侧面上，以使所述第一方向上的相邻两个导电件之间彼此绝缘。
  7. 根据权利要求6所述的面板测试装置，其中所述导电件还包括：
    弹性部，所述导电部包裹所述弹性部。
  8. 根据权利要求5所述的面板测试装置，其中所述导电件包括多个导电件，所述多个导电件均匀布置在所述至少一个测试针上，至少部分导电件与该测试针电连接。
  9. 根据权利要求5所述的面板测试装置，其中所述导电件呈球形状或柱形状。
  10. 根据权利要求1至9中任一项所述的面板测试装置，其中所述多个 测试针位于所述支撑件的同一侧，所述多个测试针的临近所述支撑件的一端固定在所述支撑件上。
  11. 根据权利要求1至10中任一项所述的面板测试装置，其中所述支撑件为条形板。
  12. 根据权利要求1至11中任一项所述的面板测试装置，其中所述至少一个测试针第二方向上的投影与对应于该测试针的信号针在所述第二方向上的投影重叠，所述第二方向垂直于所述待测面板的平面。
  13. 根据权利要求12所述的面板测试装置，其中在重叠区域中，所述至少一个测试针与对应于该测试针的信号针通过导电件彼此电连接。
  14. 根据权利要求1至13中任一项所述的面板测试装置，其中所述多个信号针以第一间距等间距排列，所述多个测试针以第二间距等间距排列，所述第一间距大于所述第二间距。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106959381A (zh) 2017-03-22 2017-07-18 京东方科技集团股份有限公司 一种面板测试装置
CN108401360B (zh) * 2018-05-03 2019-07-05 京东方科技集团股份有限公司 柔性电路板、检测装置及显示面板的检测方法
CN109523943B (zh) * 2018-12-28 2023-06-20 厦门天马微电子有限公司 显示面板和显示装置
JP2020119809A (ja) * 2019-01-25 2020-08-06 株式会社ジャパンディスプレイ 表示装置及びその製造方法並びに多面取り表示パネル
CN110426536A (zh) * 2019-07-29 2019-11-08 重庆伟鼎电子科技有限公司 Pcb导电布测试线路板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1721861A (zh) * 1999-11-16 2006-01-18 东丽工程株式会社 探测装置及其制造方法与使用它的基板检测方法
CN201138366Y (zh) * 2008-01-10 2008-10-22 环国科技股份有限公司 面板测试结构
JP2010164452A (ja) * 2009-01-16 2010-07-29 Micronics Japan Co Ltd プローブ及びプローブカード
CN102136234A (zh) * 2010-01-25 2011-07-27 寇地斯股份有限公司 用于测试微间距阵列的探针单元
CN205333695U (zh) * 2016-01-27 2016-06-22 合肥京东方光电科技有限公司 一种电检装置
CN106959381A (zh) * 2017-03-22 2017-07-18 京东方科技集团股份有限公司 一种面板测试装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107806A (en) * 1997-07-30 2000-08-22 Candescent Technologies Corporation Device for magnetically sensing current in plate structure
US6281701B1 (en) * 1999-06-04 2001-08-28 Chi Mei Optoelectronics Corporation Apparatus for testing flat panel display
US6675469B1 (en) * 1999-08-11 2004-01-13 Tessera, Inc. Vapor phase connection techniques
JP2004333332A (ja) * 2003-05-08 2004-11-25 Yamaha Corp プローブユニット及びその製造方法
JP4882529B2 (ja) * 2005-08-26 2012-02-22 セイコーエプソン株式会社 欠陥検出方法および欠陥検出装置
US8400177B2 (en) * 2008-09-01 2013-03-19 Chimei Innolux Corporation Device and method for testing display panel
KR101094289B1 (ko) * 2009-10-14 2011-12-19 삼성모바일디스플레이주식회사 원장 검사 장치 및 그 검사 방법
KR101152182B1 (ko) * 2010-05-04 2012-06-15 주식회사디아이 프로브 블록용 프로브 필름 및 이의 제조 방법
JP6273131B2 (ja) * 2013-11-27 2018-01-31 株式会社日本マイクロニクス 検査装置、及び検査方法
US20160091116A1 (en) * 2014-09-26 2016-03-31 Michael Shoecraft Cable management
TWI562108B (en) * 2016-03-02 2016-12-11 Au Optronics Corp Display panel and method for verifying driving lines thereon

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1721861A (zh) * 1999-11-16 2006-01-18 东丽工程株式会社 探测装置及其制造方法与使用它的基板检测方法
CN201138366Y (zh) * 2008-01-10 2008-10-22 环国科技股份有限公司 面板测试结构
JP2010164452A (ja) * 2009-01-16 2010-07-29 Micronics Japan Co Ltd プローブ及びプローブカード
CN102136234A (zh) * 2010-01-25 2011-07-27 寇地斯股份有限公司 用于测试微间距阵列的探针单元
CN205333695U (zh) * 2016-01-27 2016-06-22 合肥京东方光电科技有限公司 一种电检装置
CN106959381A (zh) * 2017-03-22 2017-07-18 京东方科技集团股份有限公司 一种面板测试装置

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