WO2018170973A1 - 用于4m制程制备tft的光罩及4m制程tft阵列制备方法 - Google Patents

用于4m制程制备tft的光罩及4m制程tft阵列制备方法 Download PDF

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WO2018170973A1
WO2018170973A1 PCT/CN2017/080510 CN2017080510W WO2018170973A1 WO 2018170973 A1 WO2018170973 A1 WO 2018170973A1 CN 2017080510 W CN2017080510 W CN 2017080510W WO 2018170973 A1 WO2018170973 A1 WO 2018170973A1
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layer
source
tft array
fabricating
drain
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刘晓娣
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0241—Manufacture or treatment of multiple TFTs using liquid deposition, e.g. printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks

Definitions

  • the present invention relates to the field of liquid crystal displays, and more particularly to a photomask for preparing a TFT for a 4M process and a method for preparing a 4M process TFT array.
  • LCDs liquid crystal displays
  • LCDs liquid crystal displays
  • FIG. 1 it is a schematic diagram of a TFT layout structure of a second mask process in the prior 4M process.
  • the TFT pattern 1 in the layout corresponds to the source and drain regions on the panel, and is exposed and developed on the photoresist layer in the second mask process.
  • FIG. 2 it is a schematic diagram of a conventional 4M process, showing a second mask process in the existing 4M process.
  • Existing 4M processes generally include:
  • the gate layer 12 is formed on the glass substrate 11, and the gate layer 12 is patterned; then the gate insulating layer 13, the active layer, the source and drain layers 16, and the photoresist layer are prepared. 17, the active layer may include a channel layer 14, a contact layer 15;
  • the second mask in this example is a gray scale mask, and the photoresist layer 17 is exposed and developed; the first wet etching, patterning the source and drain layers 16 to form a source and drain region And the metal wire structure of the active region; the first dry etching forms an active layer island structure, that is, the patterned channel layer 14, the contact layer 15; oxygen ashing, reducing the thickness of the photoresist layer 17 to expose the trench The source and drain layers 16 of the track region; the second wet etching, patterning the source and drain; the second etching, etching the active layer, that is, etching the channel layer 14 and the contact layer 15 to form a thin film transistor structure;
  • a transparent electrode layer is prepared and the transparent electrode layer is patterned.
  • Another object of the present invention is to provide a method for fabricating a 4M process TFT array that reduces or eliminates the problem of amorphous silicon and heavily doped silicon residues on the second metal edge.
  • the present invention provides a photomask for preparing a TFT in a 4M process.
  • a line pattern disposed along an outer edge of the TFT pattern is provided on an outer edge of the adjacent TFT pattern.
  • the line pattern does not intersect with the TFT pattern, or the line pattern meets the TFT pattern.
  • the invention also provides a method for preparing a 4M process TFT array, which uses the above-mentioned photomask as a photomask for the second mask process.
  • the 4M process TFT array preparation method comprises:
  • Step 10 in the first mask process, preparing a gate layer on the glass substrate, and patterning the gate layer; then preparing a gate insulating layer, an active layer, a source drain layer, and a photoresist layer;
  • Step 20 in the second mask process, the photoresist layer is exposed and developed; the first wet etching, patterning the source and drain layers, forming the source and drain regions and the active region of the metal wire structure; Dry etching, forming an active layer island structure; oxygen ashing, reducing the thickness of the photoresist layer to expose the source and drain layers of the channel region; second wet etching, patterning the source and drain; second dry etching, Etching the active layer to form a thin film transistor structure;
  • Step 30 in the third mask process, preparing a passivation layer, and patterning the passivation layer;
  • Step 40 In the fourth mask process, a transparent electrode layer is prepared, and the transparent electrode layer is patterned.
  • the step 20 further includes two times of oxygen ashing, specifically: exposing and developing the photoresist layer in the second mask process; first etching, patterning the source and drain layers to form source and drain The metal wire structure of the polar region and the active region; the first oxygen ashing reduces the size of the active layer tailing of the source and drain metal layers; the first dry etching forms an active layer island structure; the second oxygen Ashing, reducing the thickness of the photoresist layer to expose the source and drain layers of the channel region; second wet etching, patterning the source and drain; third oxygen ashing, reducing contact layer tailing; second dry etching The active layer is etched to form a thin film transistor structure.
  • the TFT array is a TFT array of a display area or a GOA circuit area.
  • the second mask is a gray scale mask or a halftone mask.
  • the gate layer is prepared by sputtering, sol-gel, atomic layer deposition, evaporation, or printing.
  • the material of the gate layer is Cu, Cu/Mo, Mo/Cu/Mo, MoNb/Cu/MoNb, Ti/Cu/Ti, Al, Al/Mo, or Mo/Al/Mo.
  • the gate insulating layer is prepared by plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, or sputtering.
  • the material of the gate insulating layer is silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or tantalum oxide.
  • the active layer includes a channel layer and a contact layer.
  • the channel layer and the contact layer are formed by depositing a silicon substrate, sputtering a metal oxide semiconductor layer, or atomically depositing a metal oxide semiconductor layer.
  • the metal oxide is IGZO, IZO, or ITZO.
  • the invention also provides a method for preparing a 4M process TFT array, which uses the above-mentioned photomask as a photomask for the second mask process;
  • Step 10 in the first mask process, preparing a gate layer on the glass substrate, and patterning the gate layer; then preparing a gate insulating layer, an active layer, a source drain layer, and a photoresist layer;
  • Step 20 in the second mask process, the photoresist layer is exposed and developed; the first wet etching, patterning the source and drain layers, forming the source and drain regions and the active region of the metal wire structure; Dry etching, forming an active layer island structure; oxygen ashing, reducing the thickness of the photoresist layer to expose the source and drain layers of the channel region; second wet etching, patterning the source and drain; second dry etching, Etching the active layer to form a thin film transistor structure;
  • Step 30 in the third mask process, preparing a passivation layer, and patterning the passivation layer;
  • Step 40 in the fourth mask process, preparing a transparent electrode layer, and patterning the transparent electrode layer;
  • the step 20 further includes two times of oxygen ashing, specifically: exposing and developing the photoresist layer in the second mask process; first etching, patterning the source and drain layers to form source and drain The metal wire structure of the polar region and the active region; the first oxygen ashing reduces the size of the active layer tailing of the source and drain metal layers; the first dry etching forms an active layer island structure; the second oxygen Ashing, reducing the thickness of the photoresist layer to expose the source and drain layers of the channel region; second wet etching, patterning the source and drain; third oxygen ashing, reducing contact layer tailing; second dry etching Etching the active layer to form a thin film transistor structure;
  • the TFT array is a TFT array of a display area or a GOA circuit area
  • the second mask is a gray scale mask or a halftone mask
  • the gate layer is prepared by sputtering, sol-gel, atomic layer deposition, evaporation, or printing;
  • the material of the gate layer is Cu, Cu/Mo, Mo/Cu/Mo, MoNb/Cu/MoNb, Ti/Cu/Ti, Al, Al/Mo, or Mo/Al/Mo.
  • the reticle for fabricating a TFT for a 4M process achieves a thin edge structure by changing the edge exposure of the reticle, thereby making the structure easier to plasma etch, thereby reducing amorphous silicon on the second metal edge. And heavily doped silicon residual problem; the 4M process TFT array manufacturing method of the present invention combines the photomask of the present invention with a matched 4M process to reduce the problem of amorphous silicon and heavily doped silicon residual on the second metal edge.
  • 1 is a schematic view showing the structure of a TFT layout of a second mask process in the prior 4M process
  • FIG. 2 is a schematic view of a conventional 4M process
  • FIG. 3 is a schematic view showing a process of a preferred embodiment of a method for fabricating a 4M process TFT array according to the present invention
  • 4 is a schematic view of a 4M process using an existing photomask
  • FIG. 5 is a schematic view showing a 4M process of using a photomask for preparing a TFT in a 4M process of the present invention
  • FIG. 6 and FIG. 7 are schematic diagrams showing the structure of a TFT of a first preferred embodiment and a second preferred embodiment of a photomask for preparing a TFT in a 4M process according to the present invention
  • Figure 8 is a photograph of a TFT structure prepared using a conventional photomask
  • Figure 9 is a photograph showing the structure of a TFT of a photomask for preparing a TFT using the 4M process of the present invention.
  • FIG. 6 is a schematic structural diagram of a TFT of a first preferred embodiment and a second preferred embodiment of a photomask for preparing a TFT in a 4M process.
  • the reticle for preparing a TFT for a 4M process according to the present invention in the TFT layout structure of the reticle, the outer edge of the adjacent TFT pattern 61 is provided with a line pattern 62 disposed along the outer edge of the TFT pattern 61, and the adjacent TFT pattern 71 The outer edge is provided with a line pattern 72 disposed along the outer edge of the TFT pattern 71.
  • the line pattern 62 does not intersect with the TFT pattern 61.
  • the line pattern 72 and the TFT pattern 71 intersect.
  • Figure 6 and Figure 7 correspond to two different complementary value design methods to achieve a more uniform device structure design.
  • FIG. 4 is a schematic view of a 4M process using a conventional photomask
  • FIG. 5 is a schematic view of a 4M process for fabricating a TFT for a 4M process using the present invention, comparing the photoresist layer 47 and the photoresist.
  • Layer 57 shows the function of the reticle of the present invention.
  • the invention improves the edge exposure of the reticle
  • the structure with a thin edge at the edge makes the structure easier to plasma etch, thereby reducing the problem of amorphous silicon and heavily doped silicon residue on the second metal edge.
  • the specific design involves changing the peripheral metal line width and metal line distance of the thin film transistor (TFT) and the second layer of metal on the mask to achieve the best problem of eliminating amorphous silicon and heavily doped silicon residual.
  • TFT thin film transistor
  • Figure 8 is a photograph of a TFT structure prepared using a conventional photomask
  • Figure 9 is a photograph of a TFT structure for fabricating a photomask for preparing a TFT using the present invention.
  • the photomask of the present invention can improve the optical stability and electrical performance of the TFT, the aperture ratio, the reliability, and the power consumption reduction, and improve the overall performance of the array substrate, and can successfully succeed in the ditch on the basis of the original process.
  • the channel area reduces the heavy doping residual, which is reduced by about 0.5 um. If combined with the matching process, the effect will be more obvious.
  • the reticle for preparing TFT in 4M process can reduce or eliminate the problem of amorphous silicon and heavily doped silicon residual on the second metal edge, and the reticle can be applied to the existing 4M process to obtain the corresponding 4M process TFT array.
  • the preparation method can successfully eliminate the heavy doping residue on the outer side of the second layer metal on the basis of the original 4M process without changing the process, and if the new process is matched, the effect will be more significant.
  • FIG. 3 it is a schematic diagram of a process for fabricating a 4M process TFT array according to a preferred embodiment of the present invention.
  • the photomask is used in conjunction with a new process to display a second mask process, that is, an optimized portion of the existing process.
  • the preparation method of the 4M process TFT array of the preferred embodiment mainly includes:
  • Step 10 in the first mask process, preparing a gate layer on the glass substrate, and patterning the gate layer; then preparing a gate insulating layer, an active layer, a source drain layer, and a photoresist layer;
  • the gate layer 22 is formed on the glass substrate 21, and the gate layer 22 is patterned; then the gate insulating layer 23, the active layer, the source and drain electrodes are prepared.
  • the layer 26, the photoresist layer 27, and the active layer may include a channel layer 24 and a contact layer 25.
  • Step 20 in the second reticle process of applying the gray scale reticle:
  • the first oxygen ashing reduces the size of the active layer tailing on the side of the source and drain metal layer 26; increasing the main role of the oxygen ashing is to reduce the amorphous silicon residue;
  • the first dry etching forming an active layer island structure, that is, the patterned channel layer 24, the contact layer 25;
  • the third oxygen ashing reduces the tailing of the contact layer; increasing the oxygen ashing is mainly to reduce the heavy doped silicon residue;
  • the second dry etching etches the active layer, that is, etches the channel layer 24 and the contact layer 25 to form a thin film transistor structure.
  • Step 30 In the third mask process, preparing a passivation layer and patterning the passivation layer.
  • Step 40 In the fourth mask process, a transparent electrode layer is prepared, and the transparent electrode layer is patterned.
  • the method for fabricating a 4M process TFT array of the present invention specifically relates to an optimized 4M process backplane development, which can be used for development and display of TFT arrays including display regions and GOA circuit regions, and circuit performance optimization.
  • the invention comprises the preparation of a gate electrode, which can prepare Cu, Cu/Mo, Mo/Cu/Mo, MoNb/Cu/MoNb, Ti/Cu/Ti by sputtering, sol-gel, atomic layer deposition, evaporation, printing, etc. Electrode materials such as Al, Al/Mo, Mo/Al/Mo, and patterned.
  • the invention includes the preparation of a gate insulating layer, and specifically comprises a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide or cerium oxide prepared by plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, sputtering or the like.
  • the present invention includes depositing a silicon-based, sputtering, and atomic layer-deposited metal oxide semiconductor layer such as IGZO, IZO, ITZO, etc. as a channel layer and a contact layer.
  • the second mask can be a gray scale mask or a halftone mask.
  • the passivation layer deposition, the contact hole etching, and the transparent electrode such as ITO extraction in steps 30 and 40 can be used in the prior art, and will not be described herein.
  • the reticle for fabricating a TFT for a 4M process achieves a thin edge structure by changing the edge exposure of the reticle, thereby making the structure easier to plasma etch, thereby reducing amorphous silicon on the second metal edge.
  • the problem of heavily doped silicon residue improve the overall performance of the array substrate, can be based on the original 4M process, without changing the process, successfully eliminate the heavy doping residue on the outside of the second layer of metal, if combined with the new process, the effect will be even more Significantly;
  • the 4M process TFT array preparation method of the present invention combines the photomask of the present invention with a matched 4M process to reduce the problem of amorphous silicon and heavily doped silicon residual on the second metal edge.

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Abstract

一种用于4M制程制备TFT的光罩及4M制程TFT阵列制备方法，该光罩的TFT版图结构中，邻近TFT图案外缘设有沿TFT图案外缘走向设置的线条图案。该光罩通过改变光罩的边缘曝光实现边缘偏薄的结构，使得易于等离子体刻蚀，从而减少第二层金属边缘有不定形硅和重掺杂硅残留问题。

Description

用于4M制程制备TFT的光罩及4M制程TFT阵列制备方法 技术领域
本发明涉及液晶显示器领域，尤其涉及一种用于4M制程制备TFT的光罩及4M制程TFT阵列制备方法。
背景技术
液晶显示器(LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
为了降低成本、提高良率，各家显示阵列基板制备和研究厂商和机构不断开发新的制程工艺和技术，其中，4M(四道光罩)代替5M(五道光罩)为业内研发和制程趋势。在4M制程中存在第二层金属边缘有不定形硅和重掺杂硅残留问题，第二层金属即源漏极层金属。该问题影响TFT(薄膜晶体管)光学稳定性和电学性能，开口率，功耗和可靠性，这是由于其采用HTM(半色调光罩)或GTM(灰阶光罩)曝光图形化过程引起。
参见图1，其为现有4M制程中第二道光罩制程的TFT版图结构示意图。版图中的TFT图案1对应于面板上的源漏极区域，在第二道光罩制程中在光刻胶层上曝光显影。
参见图2，其为现有4M制程示意图，显示了现有4M制程中的第二道光罩制程。现有4M制程一般包括：
在第一道光罩制程中，在玻璃基板11上制备栅极层12，并图形化栅极层12；然后制备栅极绝缘层13、有源层、源漏极层16、光刻胶层17，有源层可以包括沟道层14、接触层15；
在第二道光罩制程中，此示例中第二道光罩为灰阶光罩，对光刻胶层17进行曝光显影；第一次湿刻，图形化源漏极层16，形成源漏极区域和有源区域的金属导线结构；第一次干刻，形成有源层岛状结构，也就是图形化沟道层14、接触层15；氧气灰化，降低光刻胶层17厚度以露出沟道区域的源漏极层16；第二次湿刻，图形化源漏极；第二次干刻，刻蚀有源层，也就是刻蚀开沟道层14、接触层15，形成薄膜晶体管结构；
在第三道光罩制程中，制备钝化层，并图案化钝化层；
在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
发明内容
本发明的目的在于提供一种用于4M制程制备TFT的光罩，减少或消除第二层金属边缘有不定形硅和重掺杂硅残留的问题。
本发明的另一目的在于提供一种4M制程TFT阵列制备方法，减少或消除第二层金属边缘有不定形硅和重掺杂硅残留的问题。
为实现上述目的，本发明提供一种用于4M制程制备TFT的光罩，在该光罩的TFT版图结构中，邻近TFT图案外缘设有沿TFT图案外缘走向设置的线条图案。
其中，所述线条图案与TFT图案不交汇，或者所述线条图案与TFT图案交汇。
本发明还提供了一种4M制程TFT阵列制备方法，使用上述的光罩作为第二道光罩制程的光罩。
该4M制程TFT阵列制备方法包括：
步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次干刻，形成有源层岛状结构；氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层；
步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
其中，所述步骤20还包括两次氧气灰化，具体为：在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层，形成薄膜晶体管结构。
其中，所述TFT阵列为显示区或GOA电路区的TFT阵列。
其中，该第二道光罩为灰阶光罩或半色调光罩。
其中，通过溅射，溶胶凝胶，原子层沉积，蒸发，或者打印方式制备所述栅极层。
其中，所述栅极层的材料为Cu，Cu/Mo，Mo/Cu/Mo，MoNb/Cu/MoNb，Ti/Cu/Ti，Al，Al/Mo，或者Mo/Al/Mo。
其中，通过等离子体化学气相沉积，常压化学气相沉积，或者溅射制备所述栅绝缘层。
其中，所述栅绝缘层的材料为氮化硅，氧化硅，氮氧化硅，氧化铝，或者氧化铪。
其中，所述有源层包括沟道层和接触层。
其中，所述沟道层和接触层通过沉积硅基，溅射金属氧化物半导体层，或者原子层沉积金属氧化物半导体层形成。
其中，所述金属氧化物为IGZO，IZO，或者ITZO。
本发明还提供一种4M制程TFT阵列制备方法，使用上述的光罩作为第二道光罩制程的光罩；
包括：
步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次干刻，形成有源层岛状结构；氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层；
步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层；
其中，所述步骤20还包括两次氧气灰化，具体为：在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
其中，所述TFT阵列为显示区或GOA电路区的TFT阵列；
其中，该第二道光罩为灰阶光罩或半色调光罩；
其中，通过溅射，溶胶凝胶，原子层沉积，蒸发，或者打印方式制备所述栅极层；
其中，所述栅极层的材料为Cu，Cu/Mo，Mo/Cu/Mo，MoNb/Cu/MoNb，Ti/Cu/Ti，Al，Al/Mo，或者Mo/Al/Mo。
综上，本发明用于4M制程制备TFT的光罩通过改变光罩的边缘曝光实现边缘偏薄的结构，进而使得该结构比较易于等离子体刻蚀，从而减少第二层金属边缘有不定形硅和重掺杂硅残留问题；本发明的4M制程TFT阵列制备方法，将本发明的光罩结合匹配的4M制程，减少第二层金属边缘有不定形硅和重掺杂硅残留问题。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有4M制程中第二道光罩制程的TFT版图结构示意图；
图2为现有4M制程示意图；
图3为本发明4M制程TFT阵列制备方法一较佳实施例的制程示意图；
图4为使用现有光罩的4M制程示意图；
图5为使用本发明用于4M制程制备TFT的光罩的4M制程示意图；
图6和图7，其为本发明用于4M制程制备TFT的光罩第一较佳实施例和第二较佳实施例的TFT版图结构示意图；
图8为使用现有光罩制备的TFT结构照片；
图9为使用本发明用于4M制程制备TFT的光罩的制备的TFT结构照片。
具体实施方式
参见图6和图7，其为本发明用于4M制程制备TFT的光罩第一较佳实施例和第二较佳实施例的TFT版图结构示意图。本发明所提供的用于4M制程制备TFT的光罩，在该光罩的TFT版图结构中，邻近TFT图案61外缘设有沿TFT图案61外缘走向设置的线条图案62，邻近TFT图案71外缘设有沿TFT图案71外缘走向设置的线条图案72。图6中，线条图案62与TFT图案61不交汇，图7中，线条图案72与TFT图案71交汇。在图6和图7对应为两种不同的补值设计方法，以达到更均匀的器件结构设计。
参见图4和图5，图4为使用现有光罩的4M制程示意图，图5为使用本发明用于4M制程制备TFT的光罩的4M制程示意图，比较光刻胶层47和光刻胶层57可知本发明光罩的作用。本发明通过改变光罩的边缘曝光实 现边缘偏薄的结构，进而使得该结构比较易于等离子体刻蚀，从而达到减少第二层金属边缘有不定形硅和重掺杂硅残留问题。具体设计涉及改变光罩(Mask)上，薄膜晶体管(TFT)和第二层金属的外围金属线宽和金属线距离来到达最佳的消除不定型硅和重掺杂硅残留问题。
参见图8和图9，图8为使用现有光罩制备的TFT结构照片，图9为使用本发明用于4M制程制备TFT的光罩的制备的TFT结构照片。比较图8和图9可知，本发明的光罩可达到提高TFT光学稳定性和电学性能，开口率，可靠性以及减低功耗目的，提高阵列基板的整体性能，可以在原制程基础上成功在沟道区减少重掺杂残留，减少约0.5um，如果结合匹配制程，效果将更加明显。
本发明用于4M制程制备TFT的光罩可以减少或消除第二层金属边缘有不定形硅和重掺杂硅残留问题，将该光罩应用于现有4M制程可以得到相应的4M制程TFT阵列制备方法，可以在原4M制程基础上，不改变制程前提下，成功在第二层金属外侧消除重掺杂残留，而且如果配合新的制程，效果将更加显著。
参见图3，其为本发明4M制程TFT阵列制备方法一较佳实施例的制程示意图，将光罩配合新的制程使用，显示了第二道光罩制程，也就是对现有制程优化的部分。
该较佳实施例的4M制程TFT阵列制备方法主要包括：
步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
在第二道光罩制程前的第一道光罩制程中，在玻璃基板21上制备栅极层22，并图形化栅极层22；然后制备栅极绝缘层23、有源层、源漏极层26、光刻胶层27，有源层可以包括沟道层24、接触层25。
步骤20、然后，在应用灰阶光罩的第二道光罩制程中：
应用灰阶光罩，对光刻胶层27进行曝光显影；
第一次湿刻，图形化源漏极层26，形成源漏极区域和有源区域的金属导线结构；
第一次氧气灰化，减少源漏金属层26边的有源层拖尾大小；增加此次氧气灰化主要作用是减少不定形硅残留；
第一次干刻，形成有源层岛状结构，也就是图形化沟道层24、接触层25；
第二次氧气灰化，降低光刻胶层27厚度以露出沟道区域的源漏极层16；
第二次湿刻，图形化源漏极；
第三次氧气灰化，减少接触层拖尾；增加此次氧气灰化主要作用为减少重掺杂硅残留；
第二次干刻，刻蚀有源层，也就是刻蚀开沟道层24、接触层25，形成薄膜晶体管结构。
步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层。
步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
本发明的4M制程TFT阵列制备方法具体涉及一种优化的4M制程工艺背板开发，可用于包括显示区和GOA电路区TFT阵列开发和显示以及电路性能优化。本发明包括栅电极制备，可通过溅射，溶胶凝胶，原子层沉积，蒸发，打印等方式制备Cu，Cu/Mo，Mo/Cu/Mo，MoNb/Cu/MoNb，Ti/Cu/Ti，Al，Al/Mo，Mo/Al/Mo等电极材料，并图形化。本发明包括栅绝缘层制备，具体包括等离子体化学气相沉积，常压化学气相沉积，溅射等制备的氮化硅，氧化硅，氮氧化硅，氧化铝，氧化铪等介质材料。本发明包括沉积硅基，溅射和原子层沉积金属氧化物半导体层，如IGZO，IZO，ITZO等做为沟道层和接触层。第二道光罩可采用灰阶光罩或半色调光罩。步骤30及40中钝化层沉积，接触孔刻蚀，和透明电极如ITO引出等，可采用现有技术，在此不再赘述。
综上，本发明用于4M制程制备TFT的光罩通过改变光罩的边缘曝光实现边缘偏薄的结构，进而使得该结构比较易于等离子体刻蚀，从而减少第二层金属边缘有不定形硅和重掺杂硅残留问题，提高阵列基板的整体性能，可以在原4M制程基础上，不改变制程前提下，成功在第二层金属外侧消除重掺杂残留，如果配合新的工艺，效果将更加显著；本发明的4M制程TFT阵列制备方法，将本发明的光罩结合匹配的4M制程，减少第二层金属边缘有不定形硅和重掺杂硅残留问题。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (20)

  1. 一种用于4M制程制备TFT的光罩，在该光罩的TFT版图结构中，邻近TFT图案外缘设有沿TFT图案外缘走向设置的线条图案。
  2. 如权利要求1所述的用于4M制程制备TFT的光罩，其中，所述线条图案与TFT图案不交汇，或者所述线条图案与TFT图案交汇。
  3. 一种4M制程TFT阵列制备方法，使用如权利要求1所述的光罩作为第二道光罩制程的光罩。
  4. 如权利要求3所述的4M制程TFT阵列制备方法，包括：
    步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
    步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次干刻，形成有源层岛状结构；氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
    步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层；
    步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
  5. 如权利要求4所述的4M制程TFT阵列制备方法，其中，所述步骤20还包括两次氧气灰化，具体为：在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层，形成薄膜晶体管结构。
  6. 如权利要求3所述的4M制程TFT阵列制备方法，其中，所述TFT阵列为显示区或GOA电路区的TFT阵列。
  7. 如权利要求3所述的4M制程TFT阵列制备方法，其中，该第二道光罩为灰阶光罩或半色调光罩。
  8. 如权利要求4所述的4M制程TFT阵列制备方法，其中，通过溅射，溶胶凝胶，原子层沉积，蒸发，或者打印方式制备所述栅极层。
  9. 如权利要求8所述的4M制程TFT阵列制备方法，其中，所述栅极 层的材料为Cu，Cu/Mo，Mo/Cu/Mo，MoNb/Cu/MoNb，Ti/Cu/Ti，Al，Al/Mo，或者Mo/Al/Mo。
  10. 如权利要求4所述的4M制程TFT阵列制备方法，其中，通过等离子体化学气相沉积，常压化学气相沉积，或者溅射制备所述栅绝缘层。
  11. 如权利要求10所述的4M制程TFT阵列制备方法，其中，所述栅绝缘层的材料为氮化硅，氧化硅，氮氧化硅，氧化铝，或者氧化铪。
  12. 如权利要求4所述的4M制程TFT阵列制备方法，其中，所述有源层包括沟道层和接触层。
  13. 如权利要求12所述的4M制程TFT阵列制备方法，其中，所述沟道层和接触层通过沉积硅基，溅射金属氧化物半导体层，或者原子层沉积金属氧化物半导体层形成。
  14. 如权利要求13所述的4M制程TFT阵列制备方法，其中，所述金属氧化物为IGZO，IZO，或者ITZO。
  15. 一种4M制程TFT阵列制备方法，使用如权利要求1所述的光罩作为第二道光罩制程的光罩；
    包括：
    步骤10、在第一道光罩制程中，在玻璃基板上制备栅极层，并图形化栅极层；然后制备栅极绝缘层、有源层、源漏极层、光刻胶层；
    步骤20、在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次干刻，形成有源层岛状结构；氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
    步骤30、在第三道光罩制程中，制备钝化层，并图案化钝化层；
    步骤40、在第四道光罩制程中，制备透明电极层，并图案化透明电极层；
    其中，所述步骤20还包括两次氧气灰化，具体为：在第二道光罩制程中，对光刻胶层进行曝光显影；第一次湿刻，图形化源漏极层，形成源漏极区域和有源区域的金属导线结构；第一次氧气灰化，减少源漏金属层边的有源层拖尾大小；第一次干刻，形成有源层岛状结构；第二次氧气灰化，降低光刻胶层厚度以露出沟道区域的源漏极层；第二次湿刻，图形化源漏极；第三次氧气灰化，减少接触层拖尾；第二次干刻，刻蚀有源层，形成薄膜晶体管结构；
    其中，所述TFT阵列为显示区或GOA电路区的TFT阵列；
    其中，该第二道光罩为灰阶光罩或半色调光罩；
    其中，通过溅射，溶胶凝胶，原子层沉积，蒸发，或者打印方式制备所述栅极层；
    其中，所述栅极层的材料为Cu，Cu/Mo，Mo/Cu/Mo，MoNb/Cu/MoNb，Ti/Cu/Ti，Al，Al/Mo，或者Mo/Al/Mo。
  16. 如权利要求15所述的4M制程TFT阵列制备方法，其中，通过等离子体化学气相沉积，常压化学气相沉积，或者溅射制备所述栅绝缘层。
  17. 如权利要求16所述的4M制程TFT阵列制备方法，其中，所述栅绝缘层的材料为氮化硅，氧化硅，氮氧化硅，氧化铝，或者氧化铪。
  18. 如权利要求15所述的4M制程TFT阵列制备方法，其中，所述有源层包括沟道层和接触层。
  19. 如权利要求18所述的4M制程TFT阵列制备方法，其中，所述沟道层和接触层通过沉积硅基，溅射金属氧化物半导体层，或者原子层沉积金属氧化物半导体层形成。
  20. 如权利要求19所述的4M制程TFT阵列制备方法，其中，所述金属氧化物为IGZO，IZO，或者ITZO。
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