WO2018163679A1 - アナログ-デジタル変換器、固体撮像素子、及び、電子機器 - Google Patents
アナログ-デジタル変換器、固体撮像素子、及び、電子機器 Download PDFInfo
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Definitions
- the present disclosure relates to an analog-digital converter, a solid-state imaging device, and an electronic device.
- a ⁇ analog-digital converter is known as one of analog-digital converters (AD converters) (see, for example, Patent Document 1).
- AD converters analog-digital converters
- DA converters digital-to-analog converters
- the stability of the feedback loop can be achieved.
- the power consumption in the digital-analog conversion units in the feedback loop increases.
- an object of the present disclosure is to provide an analog-digital converter capable of reducing power consumption, a solid-state imaging device using the analog-digital converter, and an electronic apparatus having the solid-state imaging device. To do.
- an analog-to-digital converter of the present disclosure includes: A loop filter having at least two integrators connected in cascade; A quantization circuit unit for converting the output of the loop filter into a digital value; and A current steering type digital-analog conversion unit provided in a feedback loop for feeding back the output of the quantization circuit unit to a loop filter is provided.
- a first input signal current path for passing the first input signal current to the input terminal of the first-stage integrator of the loop filter;
- a first feedback current path for connecting one feedback output terminal of the current steering type digital-analog converter to an input terminal of the first-stage integrator of the loop filter; and
- a second feedback current path is included that connects the other feedback output terminal of the current steering type digital-analog converter to the input terminal of the second-stage integrator of the loop filter.
- a solid-state imaging device of the present disclosure is provided.
- a pixel array unit in which unit pixels including a photoelectric conversion unit are arranged in a matrix, and
- a loop filter having at least two integrators connected in cascade; A quantization circuit unit for converting the output of the loop filter into a digital value; and A current steering type digital-analog conversion section provided in a feedback loop for feeding back the output of the quantization circuit section to a loop filter; A first input signal current path for passing the first input signal current to the input terminal of the first-stage integrator of the loop filter; A second input signal current path for passing a second input signal current having a sign opposite to that of the first input signal current to the input terminal of the second-stage integrator of the loop filter; A first feedback current path for connecting one feedback output terminal of the current steering type digital-analog converter to an input terminal of the first-stage integrator of the loop filter; and A second feedback current path is included that connects the other feedback output terminal of the current steering type digital-analog converter to the input terminal of the second-stage integrator of the loop filter.
- an electronic apparatus for achieving the above object includes the solid-state imaging
- the second input signal current path and the second feedback current path are both connected to the input terminal of the second-stage integrator.
- the output current on one side of the current steering type digital-analog converter and the second input signal current cancel each other.
- the power consumption can be reduced and the dependency of the current consumption on the input level can be reduced.
- the effects described here are not necessarily limited, and any of the effects described in the present specification may be used. Moreover, the effect described in this specification is an illustration to the last, Comprising: It is not limited to this, There may be an additional effect.
- FIG. 1 is a circuit diagram showing a circuit configuration of a continuous-time ⁇ analog-digital converter according to Conventional Example 1.
- FIG. 2 is a circuit diagram showing a circuit configuration of a continuous-time ⁇ analog-digital converter according to Conventional Example 2.
- FIG. 3 is a circuit diagram illustrating a circuit configuration of the continuous-time ⁇ analog-digital converter according to the first embodiment.
- FIG. 4 is a circuit diagram illustrating a circuit configuration of a continuous-time ⁇ analog-digital converter according to the second embodiment.
- FIG. 5 is a circuit diagram illustrating a circuit configuration of a continuous-time ⁇ analog-digital converter according to the third embodiment.
- FIG. 1 is a circuit diagram showing a circuit configuration of a continuous-time ⁇ analog-digital converter according to Conventional Example 1.
- FIG. 2 is a circuit diagram showing a circuit configuration of a continuous-time ⁇ analog-digital converter according to Conventional Example 2.
- FIG. 3 is a circuit diagram illustrating a circuit configuration
- FIG. 6 is a circuit diagram illustrating a circuit configuration of a continuous-time ⁇ analog-digital converter according to the fourth embodiment.
- FIG. 7 is a circuit diagram illustrating a circuit configuration of a continuous-time ⁇ analog-digital converter according to the fifth embodiment.
- FIG. 8 is a schematic configuration diagram illustrating a basic system configuration of the solid-state imaging device of the present disclosure.
- FIG. 9 is an exploded perspective view showing an outline of the configuration of a stacked CMOS image sensor.
- FIG. 10 is a block diagram illustrating a configuration of an imaging apparatus that is an example of the electronic apparatus of the present disclosure.
- Example 2 (example when there is one digital-analog converter in the feedback loop) 2-3.
- Example 1 (basic form of ⁇ analog-to-digital converter according to this embodiment: example of second-order ⁇ analog-to-digital converter) 2-4.
- Example 2 (Modification of Example 1: Example of having a voltage-current conversion circuit section in the input stage) 2-5.
- Example 3 (Modification of Example 2: Example of using differential transconductance amplifier as voltage-current conversion circuit section) 2-6.
- Example 4 (Modification of Example 1: Example in which loop filter is configured using active RC integrator) 2-7.
- Example 5 (Example of third-order ⁇ analog-digital converter) 2-8.
- Solid-state imaging device of the present disclosure (example of CMOS image sensor) 3-1.
- Electronic device of the present disclosure (example of imaging device) 5). Configurations that can be taken by the present disclosure
- the second-stage integrator can be inverted in the loop filter.
- the voltage for supplying the first input signal current and the second input signal current to the input stage ⁇ It can be set as the structure which has a current conversion circuit part.
- the voltage-current conversion circuit unit is composed of a current source for supplying a bias current and a circuit unit for distributing the bias current to the first input signal current and the second input signal current, or differentially. It can be configured by a transconductance amplifier.
- the loop filter can be configured using an active RC integrator.
- the voltage-current conversion circuit unit can be configured to take a difference between the reset level and the signal level.
- the analog-to-digital converter (AD converter) of the present disclosure uses a ⁇ modulator that uses a ⁇ modulator that converts a DC signal or a low-frequency input signal into a digital signal with a low resolution (1 bit to several bits) and a high sampling rate. It is a digital converter.
- the analog-digital converter according to the embodiment of the present disclosure is a continuous-time ⁇ analog-digital converter having a current steering type digital-analog conversion unit (DA conversion unit) in a feedback loop. By providing the digital-analog converter in the feedback loop, the stability of the feedback loop can be achieved.
- DA conversion unit current steering type digital-analog conversion unit
- the continuous-time ⁇ analog-to-digital converter uses a first input signal and a second input signal having an opposite sign (reverse polarity) to the first input signal as a current input. For example, when the first input signal is input as the current I sig , the second input signal is input as a current of I bias ⁇ I sig with respect to the predetermined bias current I bias .
- Conventional example 1 is an example in which there are two digital-analog converters in the feedback loop.
- FIG. 1 shows a circuit configuration of a continuous-time ⁇ analog-digital converter according to Conventional Example 1.
- the continuous-time ⁇ analog-digital converter 1 includes a loop filter 10, a quantization circuit unit 20, a decimation filter 30 as an example of a digital filter, a first digital-analog conversion unit 40, and a second digital-analog conversion.
- the configuration includes a unit 50 and a control circuit unit 60.
- the loop filter 10, the quantization circuit unit 20, the first digital-analog conversion unit 40, the second digital-analog conversion unit 50, and the control circuit unit 60 constitute a ⁇ modulator.
- the loop filter 10 is a single-ended loop filter.
- the loop filter 10 includes, for example, two integrators connected in cascade, that is, an integration circuit unit including a first-stage integrator 11 and a second-stage integrator 12, and is a first analog input signal. The difference between the input signal current I sig and the feedback value is integrated.
- the first-stage integrator 11 is configured by a capacitive element C 1 connected between the current input terminal N 1 of the integrator 11 and a reference potential point (for example, GND).
- the second-stage integrator 12 includes a g m amplifier 121 that converts a voltage into a current.
- the resistor element R 2 and the capacitor element C 2 are connected in series.
- the quantization circuit unit 20 is composed of, for example, a comparator 21 and quantizes the output of the loop filter 10 by comparing the output of the loop filter 10 with the reference voltage V ref in synchronization with the clock signal CLK. Output as a 1-bit digital signal. This digital signal is supplied to the decimation filter 30 and the control circuit unit 60.
- the decimation filter 30 includes a quantum filter generated by a ⁇ modulator including the loop filter 10, the quantization circuit unit 20, the first digital-analog conversion unit 40, the second digital-analog conversion unit 50, and the control circuit unit 60.
- the sampling frequency is reduced by decimation and output as a digital signal OUT.
- the first digital-analog converter 40 and the second digital-analog converter 50 are current steering type digital-analog converters and are provided in the feedback loop of the ⁇ analog-digital converter 1.
- the first digital-analog converter 40 is configured by a differential switch circuit including a current source 41 and two switch elements 42 and 43. One end of each of the switch elements 42 and 43 is commonly connected to the other end of the current source 41 whose one end is grounded. The other end of the switch element 42 is electrically connected to the current input terminal N 1 of the first-stage integrator 11. The other end of the switch element 43 is connected to the node of the power supply voltage Vdd via the transistor 44.
- the transistor 44 functions as a load element when a predetermined bias voltage is applied to the gate electrode.
- the second digital-analog conversion unit 50 includes a differential switch circuit including a current source 51 and two switch elements 52 and 53. One end of each of the switch elements 52 and 53 is commonly connected to the other end of the current source 51 whose one end is grounded. The other end of the switch element 52 is electrically connected to the current input terminal N 2 of the second-stage integrator 12. The other end of the switch element 53 is connected to the node of the power supply voltage Vdd via the transistor 54.
- the transistor 54 functions as a load element when a predetermined bias voltage is applied to the gate electrode.
- the first digital-analog conversion unit 40 configured as described above generates a feedback value according to the output of the quantization circuit unit 20 under the control of the control unit 60, and supplies the feedback value to the first-stage integrator 11.
- the second digital-analog conversion unit 50 configured as described above generates a feedback value according to the output of the quantization circuit unit 20 under the control of the control unit 60 and supplies the feedback value to the second-stage integrator 12. Supply.
- the control unit 60 includes, for example, a D-FF (flip-flop) 61 that uses the output of the quantization circuit unit 20 as a D input.
- the D-FF 61 performs on / off control of the switch element 42 of the first digital-analog converter 40 and the switch element 52 of the second digital-analog converter 50 according to the Q output. Further, the D-FF 61 performs on / off control of the switch element 43 of the first digital-analog converter 40 and the switch element 53 of the second digital-analog converter 50 by the inverted output of the Q output.
- the ⁇ analog-digital converter 1 includes a current generation unit 70.
- the current generator 70 includes a current source 71 and two P-channel MOS transistors 72 and 73.
- the current source 71 is connected between the drain electrode of the MOS transistor 72 and a reference potential point (for example, GND).
- MOS transistors 72 and 73 have a current mirror circuit in which each source electrode is connected to a node of power supply voltage V dd , each gate electrode is connected in common, and the common connection node is connected to the drain electrode of MOS transistor 72. It has become.
- the drain electrode of the MOS transistor 73 is electrically connected to the current input terminal N 2 of the second-stage integrator 12.
- the continuous-time ⁇ analog-digital converter 1 includes a plurality of digital-analog conversion units, for example, two digital-analog conversion units 40 and 50 in the feedback loop.
- the feedback loop is stabilized.
- the ⁇ analog-to-digital converter 1 according to the conventional example 1 employs a configuration in which the copy current I sig_copy of the first input signal current I sig is also supplied to the second-stage integrator 12.
- Conventional example 2 is an example in the case where there is one digital-analog converter in the feedback loop.
- FIG. 2 shows a circuit configuration of a continuous-time ⁇ analog-digital converter according to Conventional Example 2.
- the delta-sigma analog-digital converter 1 connects the resistance element R 1 in series with the capacitive element C 1 constituting the first-stage integrator 11, thereby enabling digital-analog in the feedback loop. Even in a configuration in which one conversion unit 40 is arranged, a design with a stable loop is possible. As a result, the current consumption corresponding to the reduced digital-analog converter 50 (see FIG. 1) can be reduced.
- the digital-to-analog conversion unit corresponding to the second-stage integrator 12 is not arranged in the feedback loop. Since no current is drawn, there is no need to supply current from the current generator 70 to the second-stage integrator 12. However, as will be described later, for example, when used as an analog-to-digital converter in a column processing unit of a CMOS image sensor, if the consumption current of the analog-to-digital converter is dependent on the input level, the IR drop of the power supply wiring may Interference with other analog-to-digital converters occurs, leading to image quality deterioration called streaking.
- the current generator 70 cannot be completely eliminated, and the current generator 70 includes a current source 71, a gate electrode, and a drain electrode. And a P-channel MOS transistor 72 commonly connected to each other.
- a feedback current path that connects one feedback output terminal of the digital-analog converter 40 and the input terminal N 1 of the first-stage integrator 11.
- L feedback_1 a rectangular wave feedback current whose pulse width and density change according to the input level flows.
- the average current of the feedback current is approximately equal to the first input signal current I sig .
- the current is discarded from the other feedback output terminal of the digital-analog converter 40 to the node of the power supply voltage Vdd .
- the average current of the discarded current is approximately (I dac -I sig ) when the current of the current source 41 is I dac .
- the current consumption in the portion of the discarded current has the input level dependency of the ⁇ analog-digital converter 1, and thus the above streaking problem occurs.
- the second input signal current I bias -I sig having the opposite sign to the first input signal current I sig is turned back by the current generation unit 70 and the power supply voltage V dd is changed. It is conceivable to draw extra from the node. However, this method has a problem that extra power is consumed.
- Example 1 is a basic form of a continuous-time ⁇ analog-digital converter according to this embodiment.
- the first embodiment will be described by taking a secondary ⁇ analog-digital converter as an example.
- FIG. 3 shows a circuit configuration of the continuous-time ⁇ analog-digital converter according to the first embodiment.
- the ⁇ analog-digital converter 1 includes a loop filter 10 and a quantization circuit unit 20 that constitute a ⁇ modulator, and a decimation filter 30 that is an example of a digital filter.
- the ⁇ analog-digital converter 1 includes one digital-analog conversion unit in the feedback loop that feeds back the output of the quantization circuit unit 20 to the loop filter 10, specifically, a current steering type digital-analog.
- the conversion unit 40 is arranged.
- the loop filter 10 includes two integrators, a first-stage integrator 11 and a second-stage integrator 12.
- the g m amplifier 121 constituting the second-stage integrator 12 uses the output of the first-stage integrator 11 as an inverting ( ⁇ ) input and the reference voltage V ref as a non-inverting (+) input.
- the comparator 21 constituting the quantization circuit unit 20 uses the output of the loop filter 10 as an inverting input and the reference voltage Vref as a non-inverting input.
- the first input signal current I sig is supplied to the integrator 11 of the first stage of the loop filter 10 through the first input signal current path L input_1 . It is supplied to the input terminal N 1 .
- the second input signal current I bias -I sig which is opposite in sign to the first input signal current I sig , passes through the second input signal current path L input_2 and is the current input terminal of the second-stage integrator 12 of the loop filter 10. Supplied to N 2 .
- one feedback output terminal of the current steering type digital-analog converter 40 that is, the other end of the switch element 42 is input to the first-stage integrator 11 of the loop filter 10 through the first feedback current path L feedback_1.
- the other feedback output end of the current steering type digital-analog converter 40 that is, the other end of the switch element 43 is connected to the current input end of the second-stage integrator 12 of the loop filter 10 through the second feedback current path L feedback_2.
- N 2 Connected to N 2 .
- the second input signal current path L input — 2 through which the second input signal current flows, and one side of the digital-to-analog converter 40 (the other feedback) A configuration is employed in which the second feedback current path L feedback — 2 through which the output current on the output end side) flows is connected to the current input end N 2 of the second-stage integrator 12.
- the second-stage integrator 12 to which the second input signal current path L input_2 and the second feedback current path L feedback_2 are connected receives a signal having an opposite sign to those in the conventional examples 1 and 2. Will be. Therefore, as described above, while the output of the first stage integrator 11 and the inverting input of the g m amplifier 121, and the output of the loop filter 10 and the inverting input of comparator 21. Then, by operating only the second-stage integrator 12 with the reverse polarity, that is, the inverting operation, ⁇ loop characteristics such as stability can be maintained.
- the method of the first embodiment in which the second input signal current path L input_2 and the second feedback current path L feedback_2 are connected in common and connected to the loop filter 10 is preferable.
- the common connection point of the second input signal current path L input_2 and the second feedback current path L feedback_2 in the loop filter 10 the above-described mismatch and instantaneous current difference are caused by the action of feedback. Since it is absorbed, the voltage at the common connection point can be kept within a certain range.
- the second input signal current path L input_2 and the second feedback current path L feedback_2 are both included in the integrator 12 in the second stage. It is connected to the input terminal N 2.
- the output current on one side (the other feedback output end side) of the digital-analog converter 40 and the second input signal current cancel each other, so that power consumption can be reduced.
- the dependency of the consumption current on the input level is greatly reduced, and the current uniformity is increased.
- the second embodiment is a modification of the first embodiment, and is an example in which a voltage-current conversion circuit unit is provided in the input stage of the ⁇ analog-digital converter.
- FIG. 4 shows a circuit configuration of a continuous-time ⁇ analog-digital converter according to the second embodiment.
- the continuous-time ⁇ analog-digital converter 1 has a voltage-current conversion circuit unit 80 at its input stage.
- the voltage-current conversion circuit unit 80 includes a current source 81, two buffer amplifiers 82 and 83, two P-channel MOS transistors 84 and 85, and a resistance element 86, and has a circuit configuration in which a bias current I bias is distributed. It has become.
- one end of the current source 81 is connected to the node of the power supply voltage Vdd , and a bias current Ibias flows.
- the buffer amplifier 82 has the first input voltage V in + as an input, and its output terminal is connected to the gate electrode of the P-channel MOS transistor 84.
- the buffer amplifier 83 has the second input voltage V in ⁇ as an input, and its output terminal is connected to the gate electrode of the P-channel MOS transistor 85.
- the P-channel MOS transistor 84 has a source electrode connected to the other end of the current source 81, and supplies a second input signal current I bias ⁇ I sig to the second input signal current path L input —2 .
- the P-channel MOS transistor 85 has a source electrode connected to the other end of the current source 81 via a resistance element 86, and supplies the first input signal current I sig to the first input signal current path L input_1 .
- the configurations other than the voltage-current conversion circuit unit 80 provided in the input stage that is, the configurations of the loop filter 10, the quantization circuit unit 20, the decimation filter 30, the digital-analog conversion unit 40, and the control circuit unit 60 are as follows. This is basically the same as in the first embodiment. Therefore, also in the ⁇ analog-digital converter 1 according to the second embodiment, the power consumption can be reduced and the dependency of the current consumption on the input level can be greatly reduced as in the case of the first embodiment. Increased consistency.
- the third embodiment is a modification of the second embodiment and is an example in which a differential transconductance amplifier is used as the voltage-current conversion circuit unit.
- FIG. 5 shows a circuit configuration of a continuous-time ⁇ analog-digital converter according to the third embodiment.
- the continuous time type ⁇ analog-digital converter 1 uses a differential transconductance amplifier 87 as the voltage-current conversion circuit unit 80 instead of the voltage-current conversion circuit unit 80 of the second embodiment. It has a configuration.
- the differential transconductance amplifier 87 receives the first input voltage V in + and the second input voltage V in ⁇ as inputs, and supplies the first input signal current I sig to the first input signal current path L input_1 .
- the second input signal current I bias -I sig is supplied to the second input signal current path L input_2 .
- the configuration of the control circuit unit 60 is basically the same as that in the first embodiment. Therefore, also in the ⁇ analog-digital converter 1 according to the third embodiment, the power consumption can be reduced and the dependency of the current consumption on the input level can be greatly reduced, as in the case of the first embodiment. Increased consistency.
- the fourth embodiment is a modification of the first embodiment, and is an example in which the loop filter is configured using an active RC integrator.
- FIG. 6 shows a circuit configuration of a continuous-time ⁇ analog-digital converter according to the fourth embodiment.
- the loop filter 10 is configured using an active RC integrator.
- the first input voltage V in + is input to the loop filter 10 through the resistance element R 1p
- the second input voltage V in ⁇ is input through the resistance element R 1m .
- the first input voltage V in + is supplied to the current input terminal N 1 of the first-stage integrator 11 through the resistance element R 1p as the first input signal current I sig by the first input signal current path L input_1 . Is done.
- the second input voltage V in ⁇ is passed through the resistance element R 1m as the second input signal current I bias ⁇ I sig , and the second input signal current path L input_2 causes the current input terminal of the integrator 12 at the second stage. Supplied to N 2 .
- the integrator 11 in the first stage has a circuit configuration using the operational amplifier OP 1 .
- a first input signal current I sig is input to the inverting ( ⁇ ) input terminal of the operational amplifier OP 1 through the resistance element R 1p , and a feedback current is input through the first feedback current path L feedback — 1.
- the reference voltage V ref is input to the non-inverting (+) input terminal of the operational amplifier OP 1 .
- a capacitive element C 1 is connected between the inverting input terminal and the output terminal of the operational amplifier OP 1m .
- 2-stage integrator 12 has a circuit configuration using an operational amplifier OP 2.
- the output of the first-stage integrator 11 is input to the inverting input terminal of the operational amplifier OP 2 through the resistance element R 2, and the second input signal current I bias ⁇ I sig is input through the resistance element R 1m .
- a feedback current is input through the second input signal current path L input_2 .
- the non-inverting input of the operational amplifier OP 2 the reference voltage V ref is inputted.
- a capacitive element C 2 and a resistance element R c are connected in series between the inverting input terminal and the output terminal of the operational amplifier OP 2 .
- the configuration of the loop filter 10 other than the active RC integrator that is, the configuration of the quantization circuit unit 20, the decimation filter 30, the digital-analog conversion unit 40, and the control circuit unit 60 is the same as that of the first embodiment. Basically the same. Therefore, also in the ⁇ analog-digital converter 1 according to the fifth embodiment, the power consumption can be reduced and the dependency of the current consumption on the input level can be greatly reduced as in the case of the first embodiment. Increased consistency.
- the technique of the fourth embodiment can also be applied to the continuous-time ⁇ analog-digital converter 1 according to the first to third embodiments.
- Example 5 is an example of a third-order ⁇ analog-digital converter.
- FIG. 7 shows a circuit configuration of a continuous-time ⁇ analog-digital converter according to the fifth embodiment.
- the first-stage integrator 11 and the second-stage integrator 12 have the same circuit configuration as in the first embodiment.
- the circuit configuration is not limited to this, and for example, a circuit using the operational amplifier OP 1 and the operational amplifier OP 2 as in the fourth embodiment for the first-stage integrator 11 and the second-stage integrator 12. It may be a configuration.
- g m has an amplifier 131, the g m output end N 3 and a reference potential point of the amplifier 131 (e.g., GND) between the resistance elements R 3 and a capacitor C 3 Are connected in series.
- GND reference potential point of the amplifier 131
- the configurations other than the loop filter 10 including the three-stage integrators 11, 12, and 13, that is, the configurations of the quantization circuit unit 20, the decimation filter 30, the digital-analog conversion unit 40, and the control circuit unit 60 are implemented. This is basically the same as in Example 1. Therefore, also in the ⁇ analog-digital converter 1 according to the fifth embodiment, the power consumption can be reduced and the dependency of the current consumption on the input level can be greatly reduced as in the case of the first embodiment. Increased consistency.
- the ⁇ analog-digital converter 1 According to the ⁇ analog-digital converter 1 according to the first to fifth embodiments described above, the number of digital-analog conversion units provided in the feedback loop, an extra current source, and the like are reduced compared to the conventional example 1. Therefore, the circuit area can be reduced and the cost can be reduced. In addition, since the current flowing through the second input signal current path L input_2 and the current flowing through the second feedback current path L feedback_2 are balanced on average, the current balance in the loop filter 10 is good. Thus, an extra increase in internal amplitude can be avoided. As a result, compatibility with low power supply voltage is improved, and loss of dynamic range can be minimized. These effects can be realized without consuming extra power.
- FIG. 8 is a schematic configuration diagram illustrating a basic system configuration of the solid-state imaging device of the present disclosure.
- a CMOS image sensor which is a kind of XY address type solid-state image sensor will be described as an example of the solid-state image sensor.
- a CMOS image sensor is an image sensor created by applying or partially using a CMOS process.
- the CMOS image sensor 90 includes a pixel array unit 91 formed on a semiconductor substrate (chip) (not shown), and a peripheral circuit unit integrated on the same semiconductor substrate as the pixel array unit 91. It has become.
- the peripheral circuit unit includes, for example, a vertical drive unit 92, a column processing unit 93, a horizontal drive unit 94, and a system control unit 95.
- the CMOS image sensor 90 further includes a signal processing unit 98 and a data storage unit 99.
- the signal processing unit 98 and the data storage unit 99 may be mounted on the same substrate as the CMOS image sensor 90 or may be disposed on a different substrate from the CMOS image sensor 90.
- Each processing of the signal processing unit 98 and the data storage unit 99 may be processing by an external signal processing unit provided on a substrate different from the CMOS image sensor 90, for example, a DSP (Digital Signal Processor) circuit or software. .
- DSP Digital Signal Processor
- the pixel array unit 91 performs photoelectric conversion to generate a photoelectric charge corresponding to the received light amount, and also includes a unit pixel including a photoelectric conversion unit that accumulates (hereinafter, may be simply referred to as “pixel”). 2 is two-dimensionally arranged in the row direction and the column direction, that is, in a matrix.
- the row direction refers to the arrangement direction of pixels in a pixel row (so-called horizontal direction)
- the column direction refers to the arrangement direction of pixels in a pixel column (so-called vertical direction).
- pixel drive lines 96 (96 1 to 96 m ) are wired along the row direction for each pixel row, and vertical signal lines 97 (97 1 to 97 1 for each pixel column). 97 n ) are wired along the column direction.
- the pixel drive line 96 transmits a drive signal, which will be described later, for performing drive when reading a signal from the pixel.
- the pixel drive line 96 is shown as one wiring, but is not limited to one.
- One end of the pixel drive line 96 is connected to an output end corresponding to each row of the vertical drive unit 92.
- the vertical drive unit 92 is configured by a shift register, an address decoder, or the like, and drives each pixel 2 of the pixel array unit 91 at the same time or in units of rows. That is, the vertical drive unit 92 constitutes a drive unit that drives each pixel 2 of the pixel array unit 91 together with the system control unit 95 that controls the vertical drive unit 92.
- the vertical drive unit 92 is not shown in the figure for its specific configuration, but generally has a configuration having two scanning systems, a reading scanning system and a sweeping scanning system.
- the readout scanning system In order to read out a signal from the unit pixel 2, the readout scanning system selectively scans the unit pixels 2 of the pixel array section 91 in units of rows. A signal read from the unit pixel 2 is an analog signal.
- the sweep-out scanning system performs sweep-out scanning on the readout line on which readout scanning is performed by the readout scanning system prior to the readout scanning by the time corresponding to the shutter speed.
- a so-called electronic shutter operation is performed by sweeping (resetting) unnecessary charges by the sweep scanning system.
- the electronic shutter operation refers to an operation in which the photoelectric charge of the photoelectric conversion unit is discarded and exposure is newly started (photocharge accumulation is started).
- the signal read out by the readout operation by the readout scanning system corresponds to the amount of light received after the immediately preceding readout operation or electronic shutter operation.
- the period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the photo charge exposure period in the unit pixel 2.
- a signal output from each pixel 2 of the pixel row selectively scanned by the vertical driving unit 92 is input to the column processing unit 93 through each of the vertical signal lines 97 for each pixel column.
- the column processing unit 93 converts an analog pixel signal output from each pixel 2 of the selected row through the vertical signal line 97 into a digital signal for each pixel column of the pixel array unit 91 or in units of a plurality of pixel columns.
- An analog-digital converter (AD converter) 931 is included.
- the horizontal drive unit 94 is configured by a shift register, an address decoder, and the like, and selectively scans unit circuits corresponding to one pixel column or a plurality of pixel columns in the column processing unit 93 in order. By the selective scanning by the horizontal driving unit 94, pixel signals subjected to signal processing such as AD conversion for each unit circuit in the column processing unit 93 are sequentially output.
- the system control unit 95 includes a timing generator that generates various timing signals, and the vertical driving unit 92, the column processing unit 93, and the horizontal driving unit 94 are based on various timings generated by the timing generator. Drive control is performed.
- the signal processing unit 98 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing on the pixel signal output from the column processing unit 93.
- the data storage unit 99 temporarily stores data necessary for the signal processing in the signal processing unit 98.
- the above-described first to third embodiments are used as the analog-digital converter 931 provided in the column processing unit 93 for each pixel column of the pixel array unit 91 or in units of a plurality of pixel columns.
- the ⁇ analog-digital converter 1 according to the fifth embodiment can be used.
- the ⁇ analog-digital converter 1 according to the first to fifth embodiments it is possible to reduce power consumption. Therefore, by using the ⁇ analog-digital converter 1 according to the first to fifth embodiments as the analog-digital converter 931, the power consumption of the analog-digital converter 931, and thus the CMOS image sensor 90, is reduced. be able to.
- the ⁇ analog-digital converter 1 according to the first to fifth embodiments the dependency of the consumption current on the input level is greatly reduced, and the current uniformity is increased. Therefore, by using the ⁇ analog-to-digital converter 1 according to the first to fifth embodiments as the analog-to-digital converter 931, interference with other analog-to-digital converters via the IR drop of the power supply wiring ( Streaking) can be suppressed.
- noise removal processing by correlated double sampling (CDS) is performed in order to remove noise during the reset operation of the unit pixel 2.
- CDS correlated double sampling
- the reset level (P phase) and the signal level (D phase) are read from the unit pixel 2 in this order.
- the reset level corresponds to the potential of the charge storage unit when the charge storage unit (floating diffusion) of the unit pixel 2 is reset.
- the signal level corresponds to a potential obtained by photoelectric conversion in the photoelectric conversion element, that is, a potential of the charge accumulation unit when the charge accumulated in the photoelectric conversion element is transferred to the charge accumulation unit.
- the random noise generated at the time of resetting is held in the charge storage unit, so the signal level read by adding signal charge has the same amount of noise as the reset level. Is held. Therefore, it is possible to obtain a signal from which these noises are removed by performing a correlated double sampling operation in which the reset level is subtracted from the signal level.
- the analog-digital converter 931 uses the analog-digital converter.
- a correlated double sampling operation can be performed.
- the reset level (P phase) is input as the first input voltage V in +
- the signal level (D phase) is input as the second input voltage V in ⁇ .
- a correlated double sampling operation can be realized.
- a signal level (D phase) is input as the first input voltage V in +
- a reset level (P phase) is input as the second input voltage V in ⁇ .
- the above-described system configuration of the CMOS image sensor 90 is an example and is not limited to this.
- the data storage unit 99 is arranged at the subsequent stage of the column processing unit 93 and the pixel signal output from the column processing unit 93 is supplied to the signal processing unit 98 via the data storage unit 99. Good.
- a system configuration in which the data storage unit 99 and the signal processing unit 98 are provided in parallel to the column processing unit 93 may be employed.
- CMOS image sensor 90 In the CMOS image sensor 90 described above, a so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so-called so
- a laminated structure in which a semiconductor substrate 202 on which a peripheral circuit part such as the storage part 99 is formed is laminated can be exemplified.
- the first layer semiconductor substrate 201 needs only to have a size (area) sufficient to form the pixel array unit 91, and thus the size (area) of the first layer semiconductor substrate 201 is sufficient. ) As a result, the size of the entire chip can be reduced. Further, since a process suitable for pixel creation can be applied to the first layer semiconductor substrate 201 and a process suitable for circuit creation can be applied to the second layer semiconductor substrate 202, the CMOS image sensor 90 can be manufactured. There is also an advantage that the process can be optimized.
- the laminated structure is not limited to two layers, and may be a laminated structure of three or more layers.
- the solid-state imaging device of the present disclosure described above is an electronic device such as an imaging device such as a digital still camera or a video camera, a portable terminal device having an imaging function such as a mobile phone, or a copying machine using a solid-state imaging device for an image reading unit. In general, it can be used as the imaging unit (image capturing unit).
- the solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.
- a camera module is used as an imaging device.
- FIG. 10 is a block diagram illustrating a configuration of an imaging apparatus that is an example of the electronic apparatus of the present disclosure.
- an imaging apparatus 100 includes an imaging optical system 101 including a lens group and the like, an imaging unit 102, a DSP circuit 103, a frame memory 104, a display device 105, a recording device 106, an operation system 107, And a power supply system 108 and the like.
- the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.
- the imaging optical system 101 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging unit 102.
- the imaging unit 102 converts the amount of incident light imaged on the imaging surface by the optical system 101 into an electrical signal for each pixel and outputs the electrical signal as a pixel signal.
- the DSP circuit 103 performs general camera signal processing, such as white balance processing, demosaic processing, and gamma correction processing.
- the frame memory 104 is used for storing data as appropriate during the signal processing in the DSP circuit 103.
- the display device 105 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the imaging unit 102.
- the recording device 106 records the moving image or still image captured by the imaging unit 102 on a recording medium such as a portable semiconductor memory, an optical disk, or an HDD (Hard Disk Disk Drive).
- the operation system 107 issues operation commands for various functions of the imaging apparatus 100 under the operation of the user.
- the power supply system 108 appropriately supplies various power supplies serving as operation power for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.
- the above-described CMOS image sensor 90 according to the present disclosure can be used as the imaging unit 102.
- the CMOS image sensor 90 according to the present disclosure power consumption can be reduced in the ⁇ analog-digital converter 1. Therefore, by using the CMOS image sensor 90 according to the present disclosure as the imaging unit 102, the power consumption of the imaging device 100 can be reduced.
- the CMOS image sensor 90 according to the present disclosure can reduce the streaking because the dependency of the consumption current on the input level is greatly reduced and the current uniformity is increased. Therefore, by using the CMOS image sensor 90 according to the present disclosure as the imaging unit 102, it is possible to provide a display image without image quality deterioration called streaking.
- Analog-to-digital converter >> [A-1] a loop filter having at least two integrators connected in cascade; A quantization circuit unit for converting the output of the loop filter into a digital value; and A current steering type digital-analog conversion section provided in a feedback loop for feeding back the output of the quantization circuit section to a loop filter; A first input signal current path for passing the first input signal current to the input terminal of the first-stage integrator of the loop filter; A second input signal current path for passing a second input signal current having a sign opposite to that of the first input signal current to the input terminal of the second-stage integrator of the loop filter; A first feedback current path for connecting one feedback output terminal of the current steering type digital-analog converter to an input terminal of the first-stage integrator of the loop filter; and Including a second feedback current path connecting the other feedback output terminal of the current steering type digital-analog converter to the input terminal of the second-
- the loop filter inverts the second-stage integrator.
- the input stage has a voltage-current conversion circuit section for supplying the first input signal current and the second input signal current.
- the voltage-current conversion circuit unit includes a current source for supplying a bias current and a circuit unit for distributing the bias current to the first input signal current and the second input signal current.
- the voltage-current conversion circuit unit is composed of a differential transconductance amplifier. The analog-digital converter according to [A-3] above.
- the loop filter is configured using an active RC integrator.
- the analog-digital converter according to any one of [A-1] to [A-5] above.
- ⁇ B. Solid-state image sensor >> [B-1] A pixel array unit in which unit pixels including a photoelectric conversion unit are arranged in a matrix, and A column processing unit including an analog-digital converter that converts an analog pixel signal output from a unit pixel into a digital pixel signal; Analog-to-digital converter A loop filter having at least two integrators connected in cascade; A quantization circuit unit for converting the output of the loop filter into a digital value; and A current steering type digital-analog conversion section provided in a feedback loop for feeding back the output of the quantization circuit section to a loop filter; A first input signal current path for passing the first input signal current to the input terminal of the first-stage integrator of the loop filter; A second input signal current path for passing a second input signal current having a sign opposite to that of the first input signal current to the input terminal of the second-
- the loop filter inverts the second-stage integrator.
- the input stage includes a voltage-current conversion circuit unit that supplies the first input signal current and the second input signal current.
- the voltage-current conversion circuit unit includes a current source for supplying a bias current and a circuit unit for distributing the bias current to the first input signal current and the second input signal current.
- the voltage-current conversion circuit unit is composed of a differential transconductance amplifier.
- the unit pixel outputs, as an analog pixel signal, a reset level when the charge storage unit is reset and a signal level when photoelectric conversion is performed by the photoelectric conversion element,
- the voltage-current conversion circuit unit takes the difference between the reset level and the signal level.
- the loop filter is configured using an active RC integrator.
- a pixel array unit in which unit pixels including a photoelectric conversion unit are arranged in a matrix, and A column processing unit including an analog-digital converter that converts an analog pixel signal output from a unit pixel into a digital pixel signal;
- Analog-to-digital converter A loop filter having at least two integrators connected in cascade;
- a quantization circuit unit for converting the output of the loop filter into a digital value;
- a current steering type digital-analog conversion section provided in a feedback loop for feeding back the output of the quantization circuit section to a loop filter;
- a first input signal current path for passing the first input signal current to the input terminal of the first-stage integrator of the loop filter;
- a second input signal current path for passing a second input signal current having a sign opposite to that of the first input signal current to the input terminal of the second-stage integrator of the loop filter;
- a first feedback current path for connecting one feedback output terminal of the current steering type digital-analog converter to an input terminal of the first-stage integrator
- the loop filter inverts the second-stage integrator.
- the input stage has a voltage-current conversion circuit section for supplying the first input signal current and the second input signal current.
- the voltage-current conversion circuit unit includes a current source for supplying a bias current, and a circuit unit for distributing the bias current to the first input signal current and the second input signal current.
- [C-5] The voltage-current conversion circuit unit is composed of a differential transconductance amplifier. The electronic device according to [C-3] above.
- [C-6] The unit pixel outputs, as an analog pixel signal, a reset level when the charge storage unit is reset and a signal level when photoelectric conversion is performed by the photoelectric conversion element,
- the voltage-current conversion circuit unit takes the difference between the reset level and the signal level.
- [C-7] The loop filter is configured using an active RC integrator.
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Abstract
Description
縦続接続された少なくとも2つの積分器を有するループフィルタ、
ループフィルタの出力をデジタル値に変換する量子化回路部、及び、
量子化回路部の出力をループフィルタにフィードバックするフィードバックループ中に設けられたカレントステアリング型デジタル-アナログ変換部を備える。そして、
第1の入力信号電流をループフィルタの1段目の積分器の入力端に流す第1の入力信号電流パス、
第1の入力信号電流と逆符号の第2の入力信号電流をループフィルタの2段目の積分器の入力端に流す第2の入力信号電流パス、
カレントステアリング型デジタル-アナログ変換部の一方のフィードバック出力端を、ループフィルタの1段目の積分器の入力端に接続する第1のフィードバック電流パス、及び、
カレントステアリング型デジタル-アナログ変換部の他方のフィードバック出力端を、ループフィルタの2段目の積分器の入力端に接続する第2のフィードバック電流パスを含む。
光電変換部を含む単位画素が行列状に配置されて成る画素アレイ部、及び、
単位画素から出力されるアナログ画素信号をデジタル画素信号に変換するアナログ-デジタル変換器を含むカラム処理部を備える。そして、
アナログ-デジタル変換器は、
縦続接続された少なくとも2つの積分器を有するループフィルタ、
ループフィルタの出力をデジタル値に変換する量子化回路部、及び、
量子化回路部の出力をループフィルタにフィードバックするフィードバックループ中に設けられたカレントステアリング型デジタル-アナログ変換部を備え、
第1の入力信号電流をループフィルタの1段目の積分器の入力端に流す第1の入力信号電流パス、
第1の入力信号電流と逆符号の第2の入力信号電流をループフィルタの2段目の積分器の入力端に流す第2の入力信号電流パス、
カレントステアリング型デジタル-アナログ変換部の一方のフィードバック出力端を、ループフィルタの1段目の積分器の入力端に接続する第1のフィードバック電流パス、及び、
カレントステアリング型デジタル-アナログ変換部の他方のフィードバック出力端を、ループフィルタの2段目の積分器の入力端に接続する第2のフィードバック電流パスを含む。また、上記の目的を達成するための本開示の電子機器は、上記の構成の固体撮像素子を有する。
1.本開示のアナログ-デジタル変換器、固体撮像素子、及び、電子機器、全般に関する説明
2.本開示のアナログ-デジタル変換器
2-1.従来例1(フィードバックループ中のデジタル-アナログ変換部が2つの場合の例)
2-2.従来例2(フィードバックループ中のデジタル-アナログ変換部が1つの場合の例)
2-3.実施例1(本実施形態に係るΔΣアナログ-デジタル変換器の基本形:2次のΔΣアナログ-デジタル変換器の例)
2-4.実施例2(実施例1の変形例:入力段に電圧-電流変換回路部を有する例)
2-5.実施例3(実施例2の変形例:電圧-電流変換回路部として差動トランスコンダクタンスアンプを用いる例)
2-6.実施例4(実施例1の変形例:ループフィルタがアクティブRC型積分器を用いて構成される例)
2-7.実施例5(3次のΔΣアナログ-デジタル変換器の例)
2-8.変形例
3.本開示の固体撮像素子(CMOSイメージセンサの例)
3-1.基本的なシステム構成
3-2.積層構造
4.本開示の電子機器(撮像装置の例)
5.本開示がとることができる構成
本開示のアナログ-デジタル変換器、固体撮像素子、及び、電子機器にあっては、ループフィルタについて、2段目の積分器を反転動作させる構成とすることができる。
本開示のアナログ-デジタル変換器(AD変換器)は、直流信号や低周波の入力信号を低分解能(1bit~数bit)で高サンプリンレートのデジタル信号に変換するΔΣ変調器を用いるΔΣアナログ-デジタル変換器である。また、本開示の実施形態に係るアナログ-デジタル変換器は、フィードバックループ中にカレントステアリング型デジタル-アナログ変換部(DA変換部)を有する連続時間型のΔΣアナログ-デジタル変換器である。フィードバックループ中にデジタル-アナログ変換部を有することで、フィードバックループの安定性を図ることができる。
従来例1は、フィードバックループ中のデジタル-アナログ変換部が2つの場合の例である。従来例1に係る連続時間型のΔΣアナログ-デジタル変換器の回路構成を図1に示す。
従来例2は、フィードバックループ中のデジタル-アナログ変換部が1つの場合の例である。従来例2に係る連続時間型のΔΣアナログ-デジタル変換器の回路構成を図2に示す。
実施例1は、本実施形態に係る連続時間型のΔΣアナログ-デジタル変換器の基本形である。ここでは、実施例1について、2次のΔΣアナログ-デジタル変換器を例に挙げて説明する。実施例1に係る連続時間型のΔΣアナログ-デジタル変換器の回路構成を図3に示す。
実施例2は、実施例1の変形例であり、ΔΣアナログ-デジタル変換器の入力段に電圧-電流変換回路部を有する例である。実施例2に係る連続時間型のΔΣアナログ-デジタル変換器の回路構成を図4に示す。
実施例3は、実施例2の変形例であり、電圧-電流変換回路部として差動トランスコンダクタンスアンプを用いる例である。実施例3に係る連続時間型のΔΣアナログ-デジタル変換器の回路構成を図5に示す。
実施例4は、実施例1の変形例であり、ループフィルタがアクティブRC型積分器を用いて構成される例である。実施例4に係る連続時間型のΔΣアナログ-デジタル変換器の回路構成を図6に示す。
実施例5は、3次のΔΣアナログ-デジタル変換器の例である。実施例5に係る連続時間型のΔΣアナログ-デジタル変換器の回路構成を図7に示す。
上記の実施例1乃至実施例5では、1bitのΔΣアナログ-デジタル変換器に適用した場合について説明したが、1bitのΔΣアナログ-デジタル変換器への適用に限られるものではない。すなわち、本開示の技術は、マルチbitのΔΣアナログ-デジタル変換器に対しても同様に適用することができる。
[基本的なシステム構成]
図8は、本開示の固体撮像素子の基本的なシステム構成を示す概略構成図である。ここでは、固体撮像素子として、X-Yアドレス方式の固体撮像素子の一種であるCMOSイメージセンサを例に挙げて説明する。CMOSイメージセンサとは、CMOSプロセスを応用して、または、部分的に使用して作成されたイメージセンサである。
また、上記のCMOSイメージセンサ90では、画素アレイ部91と同じ半導体基板上に、アナログ-デジタル変換器931を含むカラム処理部93や、信号処理部98などの周辺回路部を形成した、所謂、平置構造のCMOSイメージセンサを例に挙げて説明したが、平置構造のCMOSイメージセンサへの適用に限られるものではない。すなわち、複数の半導体基板が互いに積層されて成る、所謂、積層構造のCMOSイメージセンサにも適用することができる。積層構造の一具体例としては、例えば図9に示すように、画素アレイ部91が形成された半導体基板201と、アナログ-デジタル変換器931を含むカラム処理部93や、信号処理部98、データ格納部99等の周辺回路部が形成された半導体基板202とが積層されて成る積層構造を例示することができる。
上述した本開示の固体撮像素子は、デジタルスチルカメラやビデオカメラ等の撮像装置や、携帯電話機などの撮像機能を有する携帯端末装置や、画像読取部に固体撮像素子を用いる複写機などの電子機器全般において、その撮像部(画像取込部)として用いることができる。尚、固体撮像素子はワンチップとして形成された形態であってもよいし、撮像部と、信号処理部または光学系とがまとめてパッケージングされた撮像機能を有するモジュール状の形態であってもよい。電子機器に搭載される上記モジュール状の形態、即ち、カメラモジュールを撮像装置とする場合もある。
図10は、本開示の電子機器の一例である撮像装置の構成を示すブロック図である。図10に示すように、本例に係る撮像装置100は、レンズ群等を含む撮像光学系101、撮像部102、DSP回路103、フレームメモリ104、表示装置105、記録装置106、操作系107、及び、電源系108等を有している。そして、DSP回路103、フレームメモリ104、表示装置105、記録装置106、操作系107、及び、電源系108がバスライン109を介して相互に接続された構成となっている。
尚、本開示は、以下のような構成をとることもできる。
≪A.アナログ-デジタル変換器≫
[A-1]縦続接続された少なくとも2つの積分器を有するループフィルタ、
ループフィルタの出力をデジタル値に変換する量子化回路部、及び、
量子化回路部の出力をループフィルタにフィードバックするフィードバックループ中に設けられたカレントステアリング型デジタル-アナログ変換部を備え、
第1の入力信号電流をループフィルタの1段目の積分器の入力端に流す第1の入力信号電流パス、
第1の入力信号電流と逆符号の第2の入力信号電流をループフィルタの2段目の積分器の入力端に流す第2の入力信号電流パス、
カレントステアリング型デジタル-アナログ変換部の一方のフィードバック出力端を、ループフィルタの1段目の積分器の入力端に接続する第1のフィードバック電流パス、及び、
カレントステアリング型デジタル-アナログ変換部の他方のフィードバック出力端を、ループフィルタの2段目の積分器の入力端に接続する第2のフィードバック電流パスを含む、
アナログ-デジタル変換器。
[A-2]ループフィルタは、2段目の積分器を反転動作させる、
上記[A-1]に記載のアナログ-デジタル変換器。
[A-3]入力段に、第1の入力信号電流及び第2の入力信号電流を供給する電圧-電流変換回路部を有する、
上記[A-1]又は上記[A-2]に記載のアナログ-デジタル変換器。
[A-4]電圧-電流変換回路部は、バイアス電流を流す電流源、及び、バイアス電流を第1の入力信号電流と第2の入力信号電流とに振り分ける回路部とから成る、
上記[A-3]に記載のアナログ-デジタル変換器。
[A-5]電圧-電流変換回路部は、差動トランスコンダクタンスアンプから成る、
上記[A-3]に記載のアナログ-デジタル変換器。
[A-6]ループフィルタは、アクティブRC型積分器を用いて構成される、
上記[A-1]から上記[A-5]のいずれかに記載のアナログ-デジタル変換器。
≪B.固体撮像素子≫
[B-1]光電変換部を含む単位画素が行列状に配置されて成る画素アレイ部、及び、
単位画素から出力されるアナログ画素信号をデジタル画素信号に変換するアナログ-デジタル変換器を含むカラム処理部を備え、
アナログ-デジタル変換器は、
縦続接続された少なくとも2つの積分器を有するループフィルタ、
ループフィルタの出力をデジタル値に変換する量子化回路部、及び、
量子化回路部の出力をループフィルタにフィードバックするフィードバックループ中に設けられたカレントステアリング型デジタル-アナログ変換部を備え、
第1の入力信号電流をループフィルタの1段目の積分器の入力端に流す第1の入力信号電流パス、
第1の入力信号電流と逆符号の第2の入力信号電流をループフィルタの2段目の積分器の入力端に流す第2の入力信号電流パス、
カレントステアリング型デジタル-アナログ変換部の一方のフィードバック出力端を、ループフィルタの1段目の積分器の入力端に接続する第1のフィードバック電流パス、及び、
カレントステアリング型デジタル-アナログ変換部の他方のフィードバック出力端を、ループフィルタの2段目の積分器の入力端に接続する第2のフィードバック電流パスを含む、
固体撮像素子。
[B-2]ループフィルタは、2段目の積分器を反転動作させる、
上記[B-1]に記載の固体撮像素子。
[B-3]入力段に、第1の入力信号電流及び第2の入力信号電流を供給する電圧-電流変換回路部を有する、
上記[B-1]又は上記[B-2]に記載の固体撮像素子。
[B-4]電圧-電流変換回路部は、バイアス電流を流す電流源、及び、バイアス電流を第1の入力信号電流と第2の入力信号電流とに振り分ける回路部とから成る、
上記[B-3]に記載の固体撮像素子。
[B-5]電圧-電流変換回路部は、差動トランスコンダクタンスアンプから成る、
上記[B-3]に記載の固体撮像素子。
[B-6]単位画素からはアナログ画素信号として、電荷蓄積部をリセットしたときのリセットレベル、及び、光電変換素子で光電変換したときの信号レベルが出力され、
電圧-電流変換回路部は、リセットレベルと信号レベルとの差分をとる、
上記[B-4]又は上記[B-5]に記載の固体撮像素子。
[B-7]ループフィルタは、アクティブRC型積分器を用いて構成される、
上記[B-1]から上記[B-6]のいずれかに記載の固体撮像素子。
≪C.電子機器≫
[C-1]光電変換部を含む単位画素が行列状に配置されて成る画素アレイ部、及び、
単位画素から出力されるアナログ画素信号をデジタル画素信号に変換するアナログ-デジタル変換器を含むカラム処理部を備え、
アナログ-デジタル変換器は、
縦続接続された少なくとも2つの積分器を有するループフィルタ、
ループフィルタの出力をデジタル値に変換する量子化回路部、及び、
量子化回路部の出力をループフィルタにフィードバックするフィードバックループ中に設けられたカレントステアリング型デジタル-アナログ変換部を備え、
第1の入力信号電流をループフィルタの1段目の積分器の入力端に流す第1の入力信号電流パス、
第1の入力信号電流と逆符号の第2の入力信号電流をループフィルタの2段目の積分器の入力端に流す第2の入力信号電流パス、
カレントステアリング型デジタル-アナログ変換部の一方のフィードバック出力端を、ループフィルタの1段目の積分器の入力端に接続する第1のフィードバック電流パス、及び、
カレントステアリング型デジタル-アナログ変換部の他方のフィードバック出力端を、ループフィルタの2段目の積分器の入力端に接続する第2のフィードバック電流パスを含む、
固体撮像素子を有する電子機器。
[C-2]ループフィルタは、2段目の積分器を反転動作させる、
上記[C-1]に記載の電子機器。
[C-3]入力段に、第1の入力信号電流及び第2の入力信号電流を供給する電圧-電流変換回路部を有する、
上記[C-1]又は上記[C-2]に記載の電子機器。
[C-4]電圧-電流変換回路部は、バイアス電流を流す電流源、及び、バイアス電流を第1の入力信号電流と第2の入力信号電流とに振り分ける回路部とから成る、
上記[C-3]に記載の電子機器。
[C-5]電圧-電流変換回路部は、差動トランスコンダクタンスアンプから成る、
上記[C-3]に記載の電子機器。
[C-6]単位画素からはアナログ画素信号として、電荷蓄積部をリセットしたときのリセットレベル、及び、光電変換素子で光電変換したときの信号レベルが出力され、
電圧-電流変換回路部は、リセットレベルと信号レベルとの差分をとる、
上記[C-4]又は上記[C-5]に記載の電子機器。
[C-7]ループフィルタは、アクティブRC型積分器を用いて構成される、
上記[C-1]から上記[C-6]のいずれかに記載の電子機器。
Claims (20)
- 縦続接続された少なくとも2つの積分器を有するループフィルタ、
ループフィルタの出力をデジタル値に変換する量子化回路部、及び、
量子化回路部の出力をループフィルタにフィードバックするフィードバックループ中に設けられたカレントステアリング型デジタル-アナログ変換部を備え、
第1の入力信号電流をループフィルタの1段目の積分器の入力端に流す第1の入力信号電流パス、
第1の入力信号電流と逆符号の第2の入力信号電流をループフィルタの2段目の積分器の入力端に流す第2の入力信号電流パス、
カレントステアリング型デジタル-アナログ変換部の一方のフィードバック出力端を、ループフィルタの1段目の積分器の入力端に接続する第1のフィードバック電流パス、及び、
カレントステアリング型デジタル-アナログ変換部の他方のフィードバック出力端を、ループフィルタの2段目の積分器の入力端に接続する第2のフィードバック電流パスを含む、
アナログ-デジタル変換器。 - ループフィルタは、2段目の積分器を反転動作させる、
請求項1に記載のアナログ-デジタル変換器。 - 入力段に、第1の入力信号電流及び第2の入力信号電流を供給する電圧-電流変換回路部を有する、
請求項1に記載のアナログ-デジタル変換器。 - 電圧-電流変換回路部は、バイアス電流を流す電流源、及び、バイアス電流を第1の入力信号電流と第2の入力信号電流とに振り分ける回路部とから成る、
請求項3に記載のアナログ-デジタル変換器。 - 電圧-電流変換回路部は、差動トランスコンダクタンスアンプから成る、
請求項3に記載のアナログ-デジタル変換器。 - ループフィルタは、アクティブRC型積分器を用いて構成される、
請求項1に記載のアナログ-デジタル変換器。 - 光電変換部を含む単位画素が行列状に配置されて成る画素アレイ部、及び、
単位画素から出力されるアナログ画素信号をデジタル画素信号に変換するアナログ-デジタル変換器を含むカラム処理部を備え、
アナログ-デジタル変換器は、
縦続接続された少なくとも2つの積分器を有するループフィルタ、
ループフィルタの出力をデジタル値に変換する量子化回路部、及び、
量子化回路部の出力をループフィルタにフィードバックするフィードバックループ中に設けられたカレントステアリング型デジタル-アナログ変換部を備え、
第1の入力信号電流をループフィルタの1段目の積分器の入力端に流す第1の入力信号電流パス、
第1の入力信号電流と逆符号の第2の入力信号電流をループフィルタの2段目の積分器の入力端に流す第2の入力信号電流パス、
カレントステアリング型デジタル-アナログ変換部の一方のフィードバック出力端を、ループフィルタの1段目の積分器の入力端に接続する第1のフィードバック電流パス、及び、
カレントステアリング型デジタル-アナログ変換部の他方のフィードバック出力端を、ループフィルタの2段目の積分器の入力端に接続する第2のフィードバック電流パスを含む、
固体撮像素子。 - ループフィルタは、2段目の積分器を反転動作させる、
請求項7に記載の固体撮像素子。 - 入力段に、第1の入力信号電流及び第2の入力信号電流を供給する電圧-電流変換回路部を有する、
請求項7に記載の固体撮像素子。 - 電圧-電流変換回路部は、バイアス電流を流す電流源、及び、バイアス電流を第1の入力信号電流と第2の入力信号電流とに振り分ける回路部とから成る、
請求項9に記載の固体撮像素子。 - 電圧-電流変換回路部は、差動トランスコンダクタンスアンプから成る、
請求項9に記載の固体撮像素子。 - 単位画素からはアナログ画素信号として、電荷蓄積部をリセットしたときのリセットレベル、及び、光電変換素子で光電変換したときの信号レベルが出力され、
電圧-電流変換回路部は、リセットレベルと信号レベルとの差分をとる、
請求項11に記載の固体撮像素子。 - ループフィルタは、アクティブRC型積分器を用いて構成される、
請求項7に記載の固体撮像素子。 - 光電変換部を含む単位画素が行列状に配置されて成る画素アレイ部、及び、
単位画素から出力されるアナログ画素信号をデジタル画素信号に変換するアナログ-デジタル変換器を含むカラム処理部を備え、
アナログ-デジタル変換器は、
縦続接続された少なくとも2つの積分器を有するループフィルタ、
ループフィルタの出力をデジタル値に変換する量子化回路部、及び、
量子化回路部の出力をループフィルタにフィードバックするフィードバックループ中に設けられたカレントステアリング型デジタル-アナログ変換部を備え、
第1の入力信号電流をループフィルタの1段目の積分器の入力端に流す第1の入力信号電流パス、
第1の入力信号電流と逆符号の第2の入力信号電流をループフィルタの2段目の積分器の入力端に流す第2の入力信号電流パス、
カレントステアリング型デジタル-アナログ変換部の一方のフィードバック出力端を、ループフィルタの1段目の積分器の入力端に接続する第1のフィードバック電流パス、及び、
カレントステアリング型デジタル-アナログ変換部の他方のフィードバック出力端を、ループフィルタの2段目の積分器の入力端に接続する第2のフィードバック電流パスを含む、
固体撮像素子を有する電子機器。 - ループフィルタは、2段目の積分器を反転動作させる、
請求項14に記載の電子機器。 - 入力段に、第1の入力信号電流及び第2の入力信号電流を供給する電圧-電流変換回路部を有する、
請求項14に記載の電子機器。 - 電圧-電流変換回路部は、バイアス電流を流す電流源、及び、バイアス電流を第1の入力信号電流と第2の入力信号電流とに振り分ける回路部とから成る、
請求項16に記載の電子機器。 - 電圧-電流変換回路部は、差動トランスコンダクタンスアンプから成る、
請求項16に記載の電子機器。 - 単位画素からはアナログ画素信号として、電荷蓄積部をリセットしたときのリセットレベル、及び、光電変換素子で光電変換したときの信号レベルが出力され、
電圧-電流変換回路部は、リセットレベルと信号レベルとの差分をとる、
請求項18に記載の電子機器。 - ループフィルタは、アクティブRC型積分器を用いて構成される、
請求項14に記載の電子機器。
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