WO2018151553A1 - 반도체 소자 - Google Patents

반도체 소자 Download PDF

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Publication number
WO2018151553A1
WO2018151553A1 PCT/KR2018/001978 KR2018001978W WO2018151553A1 WO 2018151553 A1 WO2018151553 A1 WO 2018151553A1 KR 2018001978 W KR2018001978 W KR 2018001978W WO 2018151553 A1 WO2018151553 A1 WO 2018151553A1
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Prior art keywords
layer
semiconductor
electrode
semiconductor device
disposed
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PCT/KR2018/001978
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English (en)
French (fr)
Korean (ko)
Inventor
이상열
김청송
문지형
박선우
조현민
Original Assignee
엘지이노텍 주식회사
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Priority claimed from KR1020170021277A external-priority patent/KR20180094751A/ko
Priority claimed from KR1020170021276A external-priority patent/KR20180094750A/ko
Priority claimed from KR1020170128157A external-priority patent/KR102528386B1/ko
Priority claimed from KR1020170136025A external-priority patent/KR102415244B1/ko
Application filed by 엘지이노텍 주식회사 filed Critical 엘지이노텍 주식회사
Publication of WO2018151553A1 publication Critical patent/WO2018151553A1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the embodiment relates to a semiconductor device.
  • a semiconductor device including a compound such as GaN, AlGaN, etc. has many advantages, such as having a wide and easy-to-adjust band gap energy, and can be used in various ways as a light emitting device, a light receiving device, and various diodes.
  • light emitting devices such as light emitting diodes and laser diodes using semiconductors of Group 3-5 or Group 2-6 compound semiconductors have been developed through the development of thin film growth technology and device materials.
  • Various colors such as blue and ultraviolet light can be realized, and efficient white light can be realized by using fluorescent materials or combining colors.Low power consumption, semi-permanent lifespan, and fast response speed compared to conventional light sources such as fluorescent and incandescent lamps can be realized. It has the advantages of safety, environmental friendliness.
  • a light-receiving device such as a photodetector or a solar cell
  • a group 3-5 or 2-6 compound semiconductor material of a semiconductor the development of device materials absorbs light in various wavelength ranges to generate a photocurrent.
  • light in various wavelengths can be used from gamma rays to radio wavelengths. It also has the advantages of fast response speed, safety, environmental friendliness and easy control of device materials, making it easy to use in power control or microwave circuits or communication modules.
  • the semiconductor device may replace a light emitting diode backlight, a fluorescent lamp, or an incandescent bulb, which replaces a cold cathode tube (CCFL) constituting a backlight module of an optical communication means, a backlight of a liquid crystal display (LCD) display device.
  • CCFL cold cathode tube
  • LCD liquid crystal display
  • micro-sized light emitting diodes are very small in size and thus have a weak problem in impact.
  • the etching surface of the light emitting diode coincides with the cleavage plane, or the mesa angle is large, there is a problem that it is easily broken even with a small impact.
  • the embodiment provides a semiconductor device having a reduced operating voltage.
  • the present invention provides a semiconductor device having improved crack generation.
  • the present invention provides a semiconductor device in which the position does not change during transfer.
  • a semiconductor device may include a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; A first electrode electrically connected to the first conductive semiconductor layer; And a second electrode electrically connected to the second conductive semiconductor layer, wherein the semiconductor structure includes: a first upper surface on which the first electrode is disposed; a second upper surface on which the second electrode is disposed; And an inclined surface disposed between the first upper surface and the second upper surface, the first minimum height from the bottom surface of the semiconductor structure to the second upper surface and the first upper surface on the bottom surface of the semiconductor structure.
  • the ratio of the second minimum height to is from 1: 0.6 to 1: 0.95, and the difference between the first minimum height and the second minimum height is smaller than 2 ⁇ m.
  • the area ratio of the upper surface and the side surface of the semiconductor structure may be 1: 0.4 to 1: 0.9.
  • the first inclination angle between the side surfaces of the semiconductor structure and the horizontal plane may be greater than the second inclination angle between the inclined plane and the horizontal plane.
  • the first inclination angle may be 70 ° to 90 °, and the second inclination angle may be 20 ° to 70 °.
  • a boundary line between the inclined surface and the first upper surface may cross a plurality of crystal directions of the semiconductor structure on a plane.
  • the boundary line between the inclined surface and the first upper surface may be disposed between the adjacent crystal directions.
  • It may include an insulating layer disposed on the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer.
  • the insulating layer may include irregularities formed at an end portion.
  • the semiconductor structure may include a plurality of uneven patterns disposed on side surfaces thereof.
  • a pixel of a display may be implemented by a semiconductor device.
  • a semiconductor device having a reduced operating voltage can be manufactured.
  • a semiconductor device having low power consumption and improved electrode area can be manufactured.
  • FIG. 1 is a cross-sectional view and a plan view of a semiconductor device according to an embodiment
  • FIG. 2 is a view showing an area ratio of an active layer and a second electrode
  • FIG. 3 is a modification of FIG.
  • FIG. 4 is a plan view of a semiconductor device according to various comparative examples
  • FIG. 5 is a graph of operating voltage and current of a semiconductor device according to an embodiment
  • 9A to 9F are views illustrating a method of manufacturing a semiconductor device according to the embodiment.
  • FIG. 10 is a photo illustrating a semiconductor device according to an embodiment
  • 11A to 11C are views for explaining the range of the second inclination angle
  • 12A to 12D illustrate a process of transferring a semiconductor device
  • FIG. 13 is a cross-sectional view of a semiconductor device according to an embodiment
  • FIG. 14 is a plan view of FIG. 13;
  • 15 and 16 are views showing a state in which a position is shifted in the process of transferring a semiconductor device
  • 17 is a cross-sectional view of a semiconductor device having reduced angles of inclined surfaces according to one embodiment of the present invention.
  • FIG. 18 is a plan view of FIG. 17;
  • 19A to 19F are views illustrating manufacturing steps of a semiconductor device according to an embodiment of the present invention.
  • 20A to 20E are flowcharts illustrating a process of transferring a semiconductor device to a display device according to an embodiment.
  • 21 is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.
  • 22A is a view showing a crystal direction of a sapphire substrate
  • 22B is a view showing a crystal direction of a semiconductor structure
  • FIG. 23 is a view showing a crystal lattice of a semiconductor structure
  • 24A illustrates a plurality of semiconductor devices in which mesa etching is performed along a crystal direction
  • 24B is an enlarged view of a portion A of FIG. 24A;
  • 24C is a side view of FIG. 24A
  • FIG. 25 is a diagram illustrating a semiconductor device manufactured by having a mesa etching direction shifted from a crystal direction;
  • FIG. 26 is a first modification of FIG. 25;
  • FIG. 27 is a second modification of FIG. 25;
  • FIG. 29 is a view illustrating a semiconductor device in which a mesa etching direction is shifted from a crystal direction of a GaAs semiconductor structure
  • FIG. 30 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.
  • 31A is a perspective view of the semiconductor structure of FIG. 1,
  • 31B is a top view of the semiconductor structure of FIG. 1,
  • 35 is a sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 36 is a top view of FIG. 35;
  • 38A to 38E are views illustrating manufacturing steps of a semiconductor device according to an embodiment of the present invention.
  • 39A to 39E are flowcharts illustrating a process of transferring a semiconductor device to a display device according to an embodiment
  • FIG. 40 is a conceptual diagram of a display device to which a semiconductor device is transferred according to an exemplary embodiment.
  • FIG. 1 is a cross-sectional view and a plan view of a semiconductor device according to an embodiment
  • FIG. 2 is a view illustrating an area ratio of an active layer and a second electrode.
  • a semiconductor device may include a substrate 110, a semiconductor structure 120, a first electrode 131, and a second electrode 132.
  • the substrate 110 may be formed of a material selected from sapphire (Al 2 O 3 ), GaAs, SiC, GaN, ZnO, Si, GaP, InP, and Ge, but is not particularly limited as long as the material transmits visible light.
  • the substrate 110 may include a metal or a semiconductor material. If necessary, the substrate 110 may be omitted.
  • the semiconductor structure 120 may be disposed on the substrate 110.
  • the semiconductor structure 120 according to the embodiment may be formed between the first conductive semiconductor layer 121, the second conductive semiconductor layer 123, the first conductive semiconductor layer 121, and the second conductive semiconductor layer 123. It may include an active layer 122 disposed in.
  • the first conductivity type semiconductor layer 121 may be disposed on the substrate 110.
  • the first conductive semiconductor layer 121 may be formed of a compound semiconductor such as a group III-V group or a group II-VI, and a first dopant may be doped into the first conductive semiconductor layer 121.
  • the first conductive semiconductor layer 121 is a semiconductor material having a composition formula of In x1 Al y1 Ga 1 -x1- y1 N (0 ⁇ x1 ⁇ 1, 0 ⁇ y1 ⁇ 1, 0 ⁇ x1 + y1 ⁇ 1), for example For example, it may be selected from GaN, AlGaN, InGaN, InAlGaN and the like.
  • the first dopant may be an n-type dopant such as Si, Ge, Sn, Se, or Te. When the first dopant is an n-type dopant, the first conductive semiconductor layer 121 doped with the first dopant may be an n-type semiconductor layer.
  • the active layer 122 may be disposed on the first conductivity type semiconductor layer 121. In addition, the active layer 122 may be disposed between the first conductive semiconductor layer 121 and the second conductive semiconductor layer 123.
  • the width L2 in the first direction (X-axis direction) of the active layer 122 may be 20 ⁇ m to 25 ⁇ m. However, the present invention is not limited to this length and may be variously changed according to the size of the semiconductor device.
  • the first direction (X-axis direction) may be defined as a direction perpendicular to the thickness direction of the semiconductor structure 120.
  • the active layer 122 is a layer where electrons (or holes) injected through the first conductivity type semiconductor layer 121 and holes (or electrons) injected through the second conductivity type semiconductor layer 123 meet each other.
  • the active layer 122 may transition to a low energy level as electrons and holes recombine, and may generate light having a corresponding wavelength.
  • the active layer 122 may have any one of a single well structure, a multi well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, or a quantum line structure.
  • the structure is not limited to this.
  • the active layer 122 may output light in one of wavelength bands of blue, green, and red. However, the present invention is not limited thereto, and the active layer 122 may generate light in the ultraviolet wavelength band or light in the infrared wavelength band.
  • the second conductivity type semiconductor layer 123 may be disposed on the active layer 122.
  • the second conductivity type semiconductor layer 123 is formed on the active layer 122, and may be implemented as a compound semiconductor such as a group III-V group or a group II-VI. Dopants may be doped.
  • the second conductivity-type semiconductor layer 123 is a semiconductor material or AlInN having a composition formula of In x5 Al y2 Ga 1 -x5- y2 N (0 ⁇ x5 ⁇ 1, 0 ⁇ y2 ⁇ 1, 0 ⁇ x5 + y2 ⁇ 1). , AlGaAs, GaP, GaAs, GaAsP, AlGaInP may be formed of a material selected from.
  • the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, or Ba
  • the second conductive semiconductor layer 123 doped with the second dopant may be a p-type semiconductor layer.
  • the first electrode 131 may be disposed on the first conductivity type semiconductor layer 121.
  • the first electrode 131 may be electrically connected to the first conductive semiconductor layer 121.
  • the second electrode 132 may be disposed on the second conductivity type semiconductor layer 123.
  • the second electrode 132 may be electrically connected to the second conductive semiconductor layer 123.
  • the first electrode 131 and the second electrode 132 are indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZO), and indium gallium zinc oxide (IGZO). ), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga) ZnO), ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, or Ni / IrOx / Au / ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, At least one of Ru, Mg, Zn, Pt, Au, and Hf may be formed, but is not limited thereto.
  • the semiconductor device may include an insulating layer 141 of FIG. 13 that exposes only a portion of the electrodes 131 and 132 and covers the semiconductor structure 120.
  • the semiconductor structure 120 may be insulated from the outside by the insulating layer.
  • the insulating layer may include at least one of SiO 2 , SixOy, Si 3 N 4 , SixNy, SiOxNy, Al 2 O 3 , TiO 2 , AlN, but is not limited thereto.
  • the first to third side surfaces P1, P2, and P3 of the side surface of the second electrode 132 may be formed by the same etching process as the semiconductor structure 120. That is, when etching the semiconductor structure 120, the first to third side surfaces P1, P2, and P3 of the second electrode 132 may also be etched together. Accordingly, side surfaces of the first, second, and third side surfaces P1, P2, and P3 may coincide with the side surfaces of the semiconductor structure 120. In detail, the first to third side surfaces P1, P2, and P3 may extend from side surfaces of the second conductive semiconductor layer 123 to form the same inclined surface as the side surfaces of the second conductive semiconductor layer 123.
  • the inclination angles of the first to third side surfaces P1, P2, and P3 may be the same as the side inclination angle of the second conductive semiconductor layer 123.
  • the widths of the first to third side surfaces P1, P2, and P3 may be the same as the widths of the side surfaces of the second conductive semiconductor layer 123. That is, the second electrode 132 may be formed on the second conductivity type semiconductor layer 123 by the first to third side surfaces P1, P2, and P3.
  • the present invention is not limited thereto, and only one or two sides of the semiconductor structure 120 and the second electrode 132 may coincide with each other.
  • only the second side surface P2 and the third side surface P3 facing each other among the side surfaces of the second electrode 132 may have the same angle as the inclination angle of the side surface of the semiconductor structure 120 in plan view.
  • the first to third side surfaces P1, P2, and P3 of the side surfaces of the second electrode 132 except for the side surface P4 facing the first electrode 131 may be formed as the second conductive semiconductor layer ( Since the surface has the same etching surface as that of the side of 123, the area of the second electrode 132 may be widened.
  • a ratio (active layer area: second electrode area) of the area F2 of the active layer 122 and the area F1 of the second electrode 132 may be 1: 0.5 to 1: 0.95.
  • an area where the active layer 122 and the second electrode 132 overlap may be the same as the area F1 of the second electrode 132.
  • the size of the second electrode 132 may be reduced, thereby increasing the operating voltage.
  • the ratio of the area F2 of the active layer 122 to the area F1 of the second electrode 132 is greater than 1: 0.95, the reduction efficiency of the operating voltage according to the increase of the area of the second electrode is not large. There may be limitations in fabrication size.
  • the semiconductor device may have an area of the second electrode 132 in a substantial ratio with respect to the area of the active layer 122. Accordingly, the density of the injected current per area of the second electrode 132 may be increased, thereby reducing the operating voltage.
  • the semiconductor device according to the embodiment may be a micro light emitting diode constituting a unit pixel of the display. Therefore, the size of the semiconductor device may be very small compared to a general light emitting diode. For example, the semiconductor device according to the embodiment may have a size of 100 ⁇ m or less. Therefore, it may be advantageous to make the second electrode 132 relatively large.
  • the width L1 of the first direction (X-axis direction) of the second electrode 132 may be 10 ⁇ m to 30 ⁇ m.
  • the ratio of the first width L1 of the second electrode 132 to the first width L2 of the active layer 122 may be 1: 1.24 to 1: 1.56. If this is satisfied, the light emitting area can be increased while lowering the driving voltage.
  • the first inclination angle ⁇ 1 which is a side inclination angle of the semiconductor structure 120 and the second electrode 132, may be 70 ° to 90 °. In this case, all sides of the semiconductor structure 120 may have a first inclination angle ⁇ 1 (see FIG. 31A). Some side surfaces of the second electrode 132 may have a first inclination angle ⁇ 1 .
  • the inclination angle ⁇ 1 is 70 ° to 90 °
  • the inclination angle is increased, so that the widths of the side surfaces of the second electrode 132 and the second conductivity-type semiconductor layer 123 may be defined by the light emitting structure ( 120) can be increased in the direction.
  • the width of the side surface of the top surface of the second conductivity-type semiconductor layer 123 may be the same as the width of the side surface of the bottom surface of the second electrode 132.
  • the fourth side surface positioned between the second electrode 132 and the first electrode 131 may have the same inclined surface as the side surface of the active layer 122.
  • the second electrode 132 and the second conductivity-type semiconductor layer 123 may have the same widths of the remaining side surfaces except for the side facing the first electrode 131 in the first direction (X direction). As a result, the second electrode 132 disposed on the semiconductor structure 120 may have a relatively large area.
  • the side inclination angles of the semiconductor structure 120 and the second electrode 132 may be 70 ° to 90 °.
  • the inclination angle can be generated or intentionally controlled by various process conditions.
  • the top side surface of the semiconductor structure 120 and the bottom side surface of the second electrode 132 may coincide on the plane. That is, the line L3 connecting the upper end of the second electrode 132 at the lower end of the semiconductor structure 120 may be substantially straight.
  • the active layer 122 may have an inclined surface C1 between the first electrode 131 and the second electrode 132.
  • the second inclination angle ⁇ 2 of the inclined surface C1 may have 20 ° to 70 ° or 20 ° to 50 °.
  • the second inclination angle ⁇ 2 When the second inclination angle ⁇ 2 is greater than 70 °, a problem may occur in which the first conductive semiconductor layer 121 partially remains between adjacent semiconductor devices in the process of manufacturing the semiconductor device. In addition, when the second inclination angle ⁇ 2 is smaller than 20 °, there is a problem in that the area of the light emitting area is reduced and the light output is reduced. Therefore, the second inclination angle ⁇ 2 may be smaller than the first inclination angle ⁇ 1 .
  • the present invention is not limited thereto, and the second inclination angle ⁇ 2 may have various angles according to the mesa etching process of the semiconductor structure 120.
  • FIG. 4 is a plan view of a semiconductor device according to various comparative examples.
  • FIG. 4 (a) is a plan view (comparative example 1) of a semiconductor device having a smaller area of the second electrode than that of FIG. 2, and FIG. 4 (b) shows an area of the second electrode shown in FIG. ) Is a plan view (comparative example 2) of a semiconductor device larger than the area of the second electrode but smaller than the area of the second electrode in FIG. 2, and FIG. 4C shows that the area of the semiconductor device 4 is a plan view of the semiconductor device (Example 2), and FIG. 4 (d) shows a plan view of the semiconductor device (Example 3) that is larger than the area of the semiconductor device in FIG. 4 (c) but smaller than the area of the semiconductor device in FIG. One drawing.
  • Table 1 below shows the results of measuring the area, the injection current, the current density, and the operating voltage of the active layer 122 of the semiconductor device of FIGS. 2 and 4 (a) to 4 (d). (The light emitting region in Table 1 refers to the upper surface of the active layer)
  • the operating voltage when a current of 4.7 uA is injected into the light emitting region and the current density is 1 A / cm 2 , the operating voltage is 2.587 V, and a current density of 47.2 uA is injected into the light emitting region and the current density is 10. In the case of A / cm 2 , the operating voltage is 2.758 V.
  • Comparative Example 1 when the area of the second electrode was 33.3% compared to the embodiment, when a current of 4.7 uA was injected into the light emitting region and the current density was 1 A / cm 2 , the operating voltage was 2.659 V. When 47.2uA of current is injected and the current density is 10 A / cm 2 , the operating voltage is 2.869V.
  • Comparative Example 2 when the area of the second electrode was 43.8% compared to the embodiment, when a current of 4.7 uA was injected into the light emitting region and the current density was 1 A / cm 2 , the operating voltage was 2.634 V. Injecting a current of 47.2uA in a current density of 10 A / cm 2 , the operating voltage is 2.825V.
  • Example 2 in the case where the light emitting area is 55% of the embodiment, the area of the second electrode is 59.1% of the embodiment, when a current of 2.6uA is injected into the light emitting area and the current density is 1 A / cm 2
  • the operating voltage is 2.568V, and when a current of 26.0uA is injected into the light emitting region and the current density is 10 A / cm 2 , the operating voltage is 2.746V.
  • Example 3 In Example 3 (in the case where the light emitting area is 62% of the embodiment and the area of the second electrode is 68.1% of the embodiment), a current of 2.9 uA is injected into the light emitting area and the current density is 1 A / cm 2 .
  • the operating voltage is 2.579V, and when a current of 29.3uA is injected into the light emitting region and the current density is 10 A / cm 2 , the operating voltage is 2.753V.
  • FIG. 5 is a graph illustrating an operating voltage and a current of a semiconductor device according to an embodiment.
  • the semiconductor device has a second etching side of the second electrode having the same etching surface as the side of the second conductivity-type semiconductor layer except for the side positioned between the second electrode and the second electrode. It may be advantageous to form a large area of the electrode.
  • FIG. 6 is a graph of operating voltage when the current density is the same as the area of the second electrode of the semiconductor device according to the embodiment.
  • FIG. 6 when the current density per area of the second electrode is the same, an operating voltage graph of the example and the comparative example is shown. As shown in FIG. 6, when the current density per area of the second electrode is the same, the operating voltage is also the same. That is, the operating voltage may be affected by the current density per area of the second electrode.
  • FIG. 7 is a graph of operating voltage when the current density is equal to the area of the active layer of the semiconductor device according to the embodiment.
  • the operating voltage of the embodiment having the large area of the second electrode exhibits the lowest characteristic.
  • the operating voltage is influenced by the area of the second electrode rather than the light emitting region (upper surface of the active layer) when comparing FIGS.
  • the semiconductor device may have a low power consumption due to a decrease in operating voltage.
  • the other side of the side of the second electrode except the side facing the second electrode has the same inclination angle as the side of the second conductivity-type semiconductor layer can increase the area of the second electrode.
  • the operating voltage can be reduced.
  • FIG. 8 is a graph showing the light output of a semiconductor device compared to the area of an active layer of the semiconductor device according to the embodiment.
  • the light output of the semiconductor device increases as the area of the light emitting area increases.
  • the area of the light emitting area of the second embodiment is 84.9% of the area of the light emitting area of the first embodiment, and The area is 87.7% of the area of the light emitting area of the first embodiment.
  • the area of the light emitting area increases, the amount of light generated by recombination of electrons and holes increases, and thus output may be improved.
  • the area of the active layer (the area of the light emitting area) may be larger than the case where the first inclination angle is large when the first inclination angle is large. That is, the area (area of the light emitting area) of the active layer may be controlled according to the first inclination angle. Accordingly, it is possible to provide a semiconductor device having an improved light output by increasing the area of the light emitting area by controlling the first inclination angle to be 70 degrees or more.
  • FIGS. 9A to 9F are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment.
  • the semiconductor structure 120 may be grown on the growth substrate 1.
  • the growth substrate 1 may be formed of a material selected from sapphire (Al 2 O 3 ), GaAs, SiC, GaN, ZnO, Si, GaP, InP, and Ge, but is not particularly limited as long as it is a material that transmits visible light.
  • the first conductive semiconductor layer 121, the active layer 122, and the second conductive semiconductor layer 123 may be disposed on the growth substrate 1.
  • the structure of each of the semiconductor layers 121, 122, and 123 may be identically applied.
  • the semiconductor structure 120 may be mesa-etched.
  • Mesa etching may be performed up to a part of the first conductivity type semiconductor layer 121.
  • the angle of mesa etching may be 20 ° to 70 °.
  • the second inclination angle of the interface between the first conductivity type semiconductor layer 121 and the active layer 122 may be formed between 20 ° and 70 °.
  • the electrode layer 130 may be entirely formed on the etched semiconductor structure 120.
  • the electrode layer 130 when the electrode layer 130 is etched by using a mask (not shown) on the electrode layer 130, the electrode layer 130 may be separated into the first electrode 131 and the second electrode 132. have.
  • the first electrode 131 may be formed on the first conductive semiconductor layer 121
  • the second electrode 132 may be formed on the second conductive semiconductor layer 123.
  • a mask layer 210 may be disposed on the semiconductor structure 120, the first electrode 131, and the second electrode 132.
  • the mask layer 210 may include an organic material.
  • Organic matter is SiO- 2 , It may include an oxide.
  • the resist layer 220 may be disposed on the mask layer 210.
  • the resist layer 220 may include a photo resist.
  • the resist layer 220 may be disposed on the mask layer 210 in the size of a semiconductor device to be manufactured. Thus, the resist layer 220 may be formed on the first electrode 131 up to the second electrode 132.
  • the mask layer 210 other than the region where the resist layer 220 is formed may be etched.
  • etching may be performed in the mask layer 210.
  • the mask layer 210 may include an organic material, and thus, an etching rate of the mask layer 210 may be slower than an etching rate of the semiconductor structure 120.
  • the etching rate for the mask layer 210 may be 10 times slower than the etching rate for the semiconductor structure 120.
  • etching may be performed to the lower portion of the semiconductor structure 120 according to the etching angle of FIG. 9E.
  • the side of the semiconductor structure 120 and the side of the second electrode 132 may have the same etching surface.
  • the first inclination angles of the semiconductor structure 120 and the second electrode 132 may be controlled to 70 ° to 90 °.
  • the area of the second electrode 132 may be reduced, and the operating voltage may increase.
  • the first tilt angle is smaller than 70 °, when the semiconductor structure 120 is separated from the growth substrate 1 by laser lift off (LLO), a crack occurs in the semiconductor structure 120. Problems may arise with the reliability of the device. For example, as the first inclination angle is smaller, the thickness of the edge of the first conductivity-type semiconductor layer 121 under the semiconductor structure 120 may be gradually thinner. As a result, as the semiconductor structure 120 is separated from the growth substrate 1, cracks may occur at the edge of the first conductivity-type semiconductor layer 121.
  • the first inclination angle may preferably be 85 ° to 90 °.
  • the thickness of the first conductivity-type semiconductor layer 121 is less likely to change to the edge side, thereby improving the problem of cracking due to the thickness as described above.
  • the semiconductor device may provide an improved light output.
  • the semiconductor structure 120, the first electrode 131, and the second electrode 132 may be simultaneously etched.
  • the other side of the side of the second electrode 132 except the side facing the first electrode 131 may have the same inclined surface as the side of the semiconductor structure 120.
  • an area of the second electrode 132 disposed on the semiconductor structure 120 may increase.
  • each of the semiconductor devices may be isolated by etching.
  • the plurality of semiconductor devices may be disposed on the growth substrate 1 to be structurally separated. That is, the separation space W may be formed between adjacent semiconductor devices.
  • the plurality of semiconductor devices formed on the growth substrate 1 may be transferred to a transfer substrate by a laser lift off (LLO) or the like, respectively.
  • LLO laser lift off
  • FIG. 10 is a photo illustrating a semiconductor device according to an embodiment.
  • a space W is formed between the plurality of semiconductor devices by etching.
  • the semiconductor device according to the embodiment may have a rectangular shape having a long axis and a short axis.
  • the side surface may be inclined in a direction away from the substrate (thickness direction).
  • 11A through 11C are views illustrating a process of forming the first conductive semiconductor layer 121 remaining in the separation space of FIG. 10.
  • the first electrode 131, the second electrode 132, The mask layer 210 and the resist layer 220 may be formed.
  • the mask layer 210 other than the region where the resist layer 220 is formed may be etched. However, when the mesa etching performed on the semiconductor structure 120 is large, some resist layers 220a may remain due to the step difference.
  • a portion of the resist layer 220 may remain due to a step formed between the first electrode 131 and the second electrode 132 between adjacent semiconductor devices.
  • the first conductive semiconductor layer 121 disposed under the remaining resist layer 220 may remain after etching.
  • the etching angle of the semiconductor structure 120 is greater than 70 °, the first conductivity-type semiconductor layer R remaining between the adjacent semiconductor devices may be formed.
  • the angle of the mesa etching of the semiconductor structure 120 is less than 70 °, some of the resist layer 220 does not remain due to the step formed between the first electrode 131 and the second electrode 132 between adjacent semiconductor devices. You may not. As a result, formation of the remaining first conductivity-type semiconductor layer R may be prevented.
  • 12A through 12E illustrate a method of transferring a semiconductor device.
  • one of the plurality of semiconductor devices 10 may be attached to the bonding layer 2a of the transfer member 2.
  • the transfer member 2 may include a translucent material.
  • the bonding layer 2a may include a material such as sapphire (Al 2 O 3 ), glass, SU-8, PDMS (polydimethylsiloxane), or the like.
  • the bonding layer 2a may be made of a UV photosensitive resin. That is, the bonding layer 2a may include a material that loses bonding strength due to a change in physical properties by UV light.
  • the semiconductor device 10 may be separated from the substrate 1 by irradiating a laser on the lower portion of the growth substrate 1.
  • a technique for separating the substrate all known LLO techniques may be applied.
  • the laser light LS1 may be irradiated only to the semiconductor element 10 bonded to the bonding layer 2a.
  • the present invention is not limited thereto and may be irradiated to the entire plurality of semiconductor devices 10.
  • the growth substrate 1 may transmit laser light, and the sacrificial layer 124 disposed under the semiconductor device 10 may absorb the laser light LS1.
  • the sacrificial layer 124 may absorb the laser light and be thermo-chemical dissolution. By this reaction, part or all of the sacrificial layer 124 may be removed and the semiconductor device 10 may be lifted off from the substrate 1.
  • the sacrificial layer 124 is not particularly limited as long as it is a material that can absorb and decompose the laser.
  • the semiconductor device 10 may be disposed on the panel substrate 3. At this time, the semiconductor device 10 may be bonded to the transfer member 2 and moved.
  • the pinned layer 3a may be disposed on the panel substrate 3.
  • the semiconductor device 10 may be fixed on the panel substrate 3 by the pinned layer 3a.
  • the pinned layer 3a may include an adhesive material.
  • the pinned layer 3a may include a material that is cured by UV light LS2.
  • the semiconductor element 10 when light is irradiated to the transfer member 2, the semiconductor element 10 may be separated from the transfer member 2 and fixed to the panel substrate 3. At this time, the light may be irradiated from the upper portion of the transfer member (2).
  • the light irradiated onto the semiconductor device 10 may be UV (ultraviolet) light.
  • UV light can be absorbed by the bonding layer 2a.
  • the bonding layer 2a may absorb light and lose the bonding force.
  • the pinned layer 3a can be cured by absorbing light. That is, as light is irradiated, the semiconductor device 10 may be separated from the bonding layer 2a. In addition, as the light is irradiated, the semiconductor device 10 may be bonded onto the panel substrate 3.
  • the RGB (Red, Green, Blue) pixels can be easily implemented by selectively transferring the semiconductor device 10 and then transferring the selected semiconductor device 10 onto the panel.
  • FIG. 13 is a cross-sectional view of a semiconductor device according to an exemplary embodiment
  • FIG. 14 is a plan view of FIG. 1.
  • the semiconductor device 10 may include a semiconductor structure 120, a first electrode 131, a second electrode 132, and an insulating layer 141.
  • the semiconductor structure 120 may include a first conductive semiconductor layer 121, an active layer 122, and a second conductive semiconductor layer 123.
  • the semiconductor structure 120 may have a structure in which the first conductive semiconductor layer 121, the active layer 122, and the second conductive semiconductor layer 123 are sequentially stacked in the thickness direction (Y-axis direction).
  • the structure described with reference to FIG. 1 may be applied to the structures of the first conductive semiconductor layer 121, the active layer 122, and the second conductive semiconductor layer 123.
  • the semiconductor structure 120 may include metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam growth (Molecular Beam). Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), Sputtering, or the like.
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • MBE Hydride Vapor Phase Epitaxy
  • Sputtering or the like.
  • the thickness of the first conductive semiconductor layer 121 may be 3.0 ⁇ m to 6.0 ⁇ m, and the thickness of the active layer 122 may be 100 nm to 180 nm.
  • the thickness of the second conductivity-type semiconductor layer 123 may be 250 nm to 350 nm.
  • the thickness of each layer may be variously modified according to the size of the semiconductor device 10.
  • the first electrode 131 may be disposed on the first conductivity type semiconductor layer 121. Here, a portion of the first conductivity type semiconductor layer 121 may be exposed by etching. In addition, the first electrode 131 may be disposed on the first conductive semiconductor layer 121 exposed by etching.
  • the first electrode 131 may be electrically connected to the first conductive semiconductor layer 121.
  • the second electrode 132 may be disposed on the second conductivity type semiconductor layer 123.
  • the second electrode 132 may be electrically connected to the second conductive semiconductor layer 123.
  • the first electrode 131 and the second electrode 132 may be indium tin oxide (ITO), but are not limited thereto.
  • the thickness of the first electrode 131 and the second electrode 132 may be 40 nm to 70 nm. However, the present invention is not limited thereto, and the thicknesses of the first electrode 131 and the second electrode 132 may be different from each other, or may have different compositions. In this case, at least one side of the first electrode 131 may have the same slope as the side surface of the semiconductor structure 120 as described with reference to FIG. 1.
  • the insulating layer 141 may be disposed on the top and side surfaces of the semiconductor structure.
  • the insulating layer 141 may include holes H1 and H2 exposing portions of the first electrode 131 and the second electrode 132.
  • the insulating layer 141 may electrically insulate the semiconductor structure 120 from the outside.
  • the insulating layer 141 may include at least one of SiO 2 , SixOy, Si 3 N 4 , SixNy, SiOxNy, Al 2 O 3 , TiO 2 , AlN, but is not limited thereto.
  • Top surfaces S11, S12, and S13 of the semiconductor structure 120 may include a first upper surface S11 on which the first electrode 131 is disposed, and a second upper surface on which the second electrode 132 is disposed ( S12) and an inclined surface S13 disposed between the first upper surface S11 and the second upper surface S12.
  • the first upper surface S11 may be defined as a surface on which the first conductive semiconductor layer 121 is exposed, and the second upper surface S12 may be defined as an upper surface of the second conductive semiconductor layer 123. have.
  • the inclined surface S13 may be defined as an inclined region disposed between the first upper surface S11 formed flat by mesa etching and the second upper surface S12 formed flat.
  • the second inclination angle ⁇ 2 that the inclined surface S13 makes with the virtual horizontal plane may be 20 ° to 70 °.
  • the area of the second upper surface S12 may be reduced to reduce the light output.
  • the second inclination angle ⁇ 2 is greater than 70 °, the inclination angle may be increased to increase the risk of damage due to external impact. This will be described later.
  • the first inclination angle ⁇ 1 formed at the side surface of the semiconductor structure 120 with the horizontal plane may be 70 ° to 90 °.
  • the area of the second upper surface S12 may be reduced, thereby lowering the light output.
  • the second upper surface S12 may be higher than the first upper surface S11 by the etched thickness. That is, as the etching deepens, the height difference d3 between the first upper surface S11 and the second upper surface S12 may increase.
  • the chip When the height difference d3 between the first upper surface S11 and the second upper surface S12 is greater than 2 ⁇ m, the chip may be horizontally displaced during the transfer process as shown in FIGS. 15 and 16. Therefore, it can be observed that the lower surface B1 of the chip is inclined.
  • the transfer process may mean an operation of transferring the chip from the growth substrate using the transfer member 2. That is, the larger the step, the more difficult the chip is to keep horizontal.
  • the ratio d1: d2 of the second minimum height d2 to the upper surface S11 may be 1: 0.6 to 1: 0.95.
  • the step height may increase, and a defect rate may be increased during the transfer process, and when the height ratio is smaller than 1: 0.95, the mesa etching depth may be lowered to partially reduce the first conductive semiconductor layer ( 121) may not be exposed.
  • the first minimum height d1 from the bottom surface of the semiconductor structure 120 to the second upper surface S12 may be 5 ⁇ m to 8 ⁇ m. That is, the first minimum height d1 may be the overall thickness of the semiconductor structure 120.
  • the second minimum height d2 from the bottom surface of the semiconductor structure 120 to the first upper surface S11 may be 3.0 ⁇ m to 7.6 ⁇ m.
  • the difference d3 between the first minimum height d1 and the second minimum height d2 may be 350 nm or more and 2.0 ⁇ m or less.
  • the height difference d3 is larger than 2.0 ⁇ m, a distortion occurs during the transfer of the semiconductor device, which makes it difficult to transfer the semiconductor device to a desired position.
  • the height difference d3 is smaller than 350 nm, the first conductive semiconductor layer 121 may not be partially exposed.
  • the upper surface of the semiconductor structure is substantially flat, which facilitates transfer and suppresses crack generation.
  • the difference d3 between the first minimum height d1 and the second minimum height d2 may be 0.6 ⁇ m ⁇ 0.2 ⁇ m, but is not limited thereto.
  • the semiconductor device according to the embodiment may have a long side surface S22 and a short side surface S23 on a plane. That is, the semiconductor device according to the embodiment may have a rectangular shape.
  • the long side surface S22 may have a length of 30 ⁇ m to 60 ⁇ m
  • the short side surface S23 may have a length of 8 ⁇ m to 35 ⁇ m.
  • the long side surface S22 may have a length of 45 ⁇ m ⁇ 5 ⁇ m
  • the short side surface S23 may have a length of 21 ⁇ m ⁇ 5 ⁇ m, but is not limited thereto.
  • FIG. 17 is a cross-sectional view of a semiconductor device having reduced angles of inclined surfaces according to an embodiment of the present invention
  • FIG. 18 is a plan view of FIG. 17.
  • the second inclination angle ⁇ 2 that the inclined surface S13 makes with the virtual horizontal plane may be 20 ° to 70 ° or 20 ° to 50 °.
  • the second inclination angle ⁇ 2 is greater than 20 °, the area of the inclined surface S13 is reduced, so that the area of the second upper surface S12 may be relatively increased.
  • the light output can be improved.
  • the second inclination angle ⁇ 2 becomes smaller than 70 °, the problem that cracks are generated on the inclined surface S13 due to external impact can be improved.
  • the probability of cracking may be high.
  • the angle of the inclined surface S13 is lowered to 70 ° or 50 ° or less as in the embodiment, the probability of cracking may be lowered.
  • 19A through 19F are flowcharts illustrating a method of manufacturing a semiconductor device, according to an embodiment.
  • the semiconductor structure 120 may be grown on the growth substrate 1.
  • the growth substrate 1 may be formed of a material selected from sapphire (Al 2 O 3 ), GaAs, SiC, GaN, ZnO, Si, GaP, InP, and Ge, but is not particularly limited as long as it is a material that transmits visible light.
  • the first conductive semiconductor layer 121, the active layer 122, and the second conductive semiconductor layer 123 may be sequentially formed on the growth substrate 1.
  • the semiconductor structure 120 may include metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam growth (Molecular Beam).
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • MBE Hydride Vapor Phase Epitaxy
  • Sputtering or the like.
  • the semiconductor structure 120 may be mesa etched.
  • Mesa etching may be performed up to a part of the first conductivity type semiconductor layer 121.
  • the angle of mesa etching may be 20 ° to 70 °.
  • the second inclination angle ⁇ 2 may be an angle formed by the mesa etching angle.
  • the second electrode 132 may be formed on the second conductive semiconductor layer 123, and the first electrode 131 may be formed on the first conductive semiconductor layer 121. have. In this case, one side of the first electrode 131 may be etched as in the isolation process of etching the side surface of the semiconductor structure 120.
  • the first electrode 131 and the second electrode 132 are indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZAO), and indium gallium zinc oxide (IGZO).
  • IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au may be formed to include at least one, but is not limited to these materials.
  • a semiconductor device may be separated into one semiconductor device on a substrate through etching. That is, each of the semiconductor devices may be isolated by etching.
  • the inclination of the outer surface of the semiconductor device may be adjusted by the etching angle.
  • the aforementioned first inclination angle ⁇ 1 may be an angle formed by an etching angle.
  • the first inclination angle ⁇ 1 may be 70 ° to 90 °.
  • the area of the second electrode 132 may be reduced, thereby increasing the operating voltage.
  • the first inclination angle ⁇ 1 is greater than 90 °, when the semiconductor structure 120 is separated from the growth substrate 1 by laser lift off (LLO), cracks may occur in the semiconductor structure 120. This may cause a problem in the reliability of the semiconductor device.
  • the first inclination angle ⁇ 1 may be greater than the second inclination angle ⁇ 2.
  • the etching may be performed to the bottom of the semiconductor structure 120.
  • the first conductive semiconductor layer 121, the active layer 122, and the second conductive semiconductor layer 123 may have the same etching surface and inclination angle by etching.
  • an insulating layer 141 may be disposed on a plurality of semiconductor devices.
  • the insulating layer 141 may be disposed on the side and top surfaces of the semiconductor structure 120, on the first electrode 131, and the second electrode 132.
  • 20A to 20E are flowcharts illustrating a process of transferring a semiconductor device to a display device according to an embodiment.
  • a semiconductor device including a plurality of semiconductor devices disposed on a growth substrate 1 is selectively irradiated with a laser to separate the semiconductor device from the substrate. And disposing the separated semiconductor device on the panel substrate 300.
  • the semiconductor device may include a first conductive semiconductor layer, an active layer disposed on the first conductive semiconductor layer, a second conductive semiconductor layer disposed on the active layer, and a first electrode disposed on the first conductive semiconductor layer. It may include a second electrode disposed on the second conductive semiconductor layer and an insulating layer covering the semiconductor structure.
  • the growth substrate may be the same as the growth substrate 1 described above with reference to FIGS. 19A to 19F.
  • a plurality of semiconductor devices may be disposed on the growth substrate.
  • the plurality of semiconductor devices may include a first semiconductor device 10-1, a second semiconductor device 10-2, a third semiconductor device 10-3, and a fourth semiconductor device 10-4. have.
  • the present invention is not limited thereto, and the semiconductor device may have various numbers.
  • the transfer member 2 may include a first bonding layer 211 and a transfer frame 212 disposed below.
  • the carrier frame 212 may have an uneven structure, and may easily bond the semiconductor element and the first bonding layer 211 to each other. However, it is not limited to this shape.
  • the first bonding layer 211 may include a material such as polydimethylsiloxane (PDMS).
  • PDMS polydimethylsiloxane
  • the first bonding layer 211 may be made of a UV photosensitive resin. That is, the first bonding layer 211 may include a material that loses bonding strength by changing physical properties by UV light.
  • the selected semiconductor device may be separated from the growth substrate 1 by irradiating a laser LS1 under the selected semiconductor device.
  • the transfer member 2 moves upward, and the semiconductor element may move along the movement of the transfer member 2.
  • the growth substrate 10 and the first semiconductor element 10- are irradiated with a laser under a region where the first semiconductor element 10-1 and the third semiconductor element 10-3 are disposed on the growth substrate 10. 1) and the third semiconductor device 10-3 may be separated.
  • the present invention is not limited thereto, and the transfer member 2 may be formed such that the bonding layer 211 is bonded to one semiconductor element so as to separate one semiconductor element at a time.
  • a laser lift-off (LLO) using a photon beam having a specific wavelength band may be applied to the method of separating the semiconductor device from the growth substrate 10.
  • a protective layer (not shown) may be disposed between the semiconductor device and the growth substrate 10 in order to prevent physical damage between the semiconductor devices due to laser lift-off (LLO).
  • LLO laser lift-off
  • the semiconductor device separated into the growth substrate 10 may have a predetermined separation interval.
  • the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated from the growth substrate, and the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated from each other.
  • the second semiconductor device 10-2 and the fourth semiconductor device 10-4 having the same separation distance from each other may be separated in the same manner. As a result, semiconductor devices having the same separation distance may be transferred to the display panel.
  • the position at the time of bonding to the bonding layer 211 may be changed. Or part of the upper surface may not be bonded to the bonding layer. Therefore, as described above, the height difference d3 between the first upper surface S11 and the second upper surface S12 may be set smaller than 2 ⁇ m.
  • the selected semiconductor device may be disposed on the panel substrate 300.
  • the first semiconductor element 10-1 and the third semiconductor element 10-3 may be disposed on the panel substrate 300.
  • the second bonding layer 310 may be disposed on the panel substrate 300, and the first semiconductor element 10-1 and the third semiconductor element 10-3 may be disposed on the second bonding layer 310. It can be placed on. Accordingly, the first semiconductor device 10-1 and the third semiconductor device 10-3 may be in contact with the second bonding layer. In this manner, semiconductor devices having spaced intervals may be disposed on the panel substrate to improve the efficiency of the transfer process.
  • Light LS2 may be irradiated to separate the first bonding layer 211 and the selected semiconductor device.
  • the first bonding layer 211 and the selected semiconductor device may be physically separated.
  • the first bonding layer 211 may include various polymer materials that lose adhesiveness when irradiated with UV light.
  • the first semiconductor element 10-1 and the third semiconductor element 10-3 may be separated from the transfer member 2. have.
  • coupling between the second bonding layer 310, the first semiconductor device 10-1, and the third semiconductor device 10-3 may be performed.
  • 21 is a cross-sectional view of a semiconductor device according to another exemplary embodiment.
  • a semiconductor device 200 may be, for example, a semiconductor device generating red light. Accordingly, the structure of each layer described below may be different from that of FIG. 1, but the X-axis direction and the Y-axis direction with respect to the thickness are equally applied.
  • the semiconductor device 200 includes a sacrificial layer 220, a coupling layer 230 disposed on the sacrificial layer 220, a first conductive semiconductor layer 241, an active layer 243, and a second conductive semiconductor layer 244. ), A first electrode 251 connected to the first conductive semiconductor layer 241, and a second electrode 252 connected to the second conductive semiconductor layer 244.
  • the sacrificial layer 220 may be disposed on a substrate (not shown).
  • the sacrificial layer 220 may be removed while transferring the semiconductor device to the display device.
  • the sacrificial layer 220 may be separated by a laser irradiated during the transfer.
  • the sacrificial layer 220 may be formed to be separated at the wavelength of the irradiated laser.
  • the wavelength of the laser can be 532 nm or 1064 nm.
  • the sacrificial layer 220 may include an oxide or nitride. However, the present invention is not limited thereto.
  • the sacrificial layer 220 may be a silicate or silicic acid type in the case of an SOG thin film.
  • the sacrificial layer 220 may include silicate, siloxane, methyl silsequioxane (MSQ), hydrogen silsequioxane (HSQ), MQS + HSQ, perhydrosilazane (TCPS), or polysilazane, ITO, or Ti in the case of a spin on dielectric (SOD) thin film. have.
  • MSQ methyl silsequioxane
  • HSQ hydrogen silsequioxane
  • MQS + HSQ perhydrosilazane
  • TCPS perhydrosilazane
  • ITO spin on dielectric
  • Ti spin on dielectric
  • the sacrificial layer 220 may be formed by an E-beam evaporator, a thermal evaporator, a metal organic chemical vapor deposition (MOCVD), a sputtering, and a pulsed laser deposition (PLD) method. It is not limited to this.
  • the bonding layer 230 may be disposed on the sacrificial layer 220. However, the present invention is not limited thereto and may be disposed under the sacrificial layer 220.
  • the bonding layer 230 may include any one of Si, C, O, N, and H.
  • the bonding layer 230 may include resin, SiO 2 .
  • the sacrificial layer 220 and the bonding layer 230 are layers for transferring and transferring a semiconductor device to a display panel by performing laser lift off (LLO) by irradiating a laser of a high wavelength. May be removed in some cases.
  • LLO laser lift off
  • the thickness of the bonding layer 230 may be 1.8 ⁇ m to 2.2 ⁇ m. However, the present invention is not limited thereto. Here, the thickness may be a length in the Y-axis direction.
  • the semiconductor structure 240 may be disposed on the bonding layer 230.
  • the semiconductor structure 240 is formed between the first conductivity type semiconductor layer 241, the second conductivity type semiconductor layer 244b, and the first conductivity type semiconductor layer 241 and the second conductivity type semiconductor layer 244b. It may include an active layer 243 disposed in.
  • the first conductivity type semiconductor layer 241 may be disposed on the coupling layer 230.
  • the first conductive semiconductor layer 241 may have a thickness of 1.8 ⁇ m to 2.2 ⁇ m.
  • the present invention is not limited thereto.
  • the above-described configuration may be applied to the first conductive semiconductor layer 241 as it is.
  • the first clad layer 242 may be disposed on the first conductivity type semiconductor layer 241.
  • the first cladding layer 242 may be disposed between the first conductivity type semiconductor layer 241 and the active layer 243.
  • the first clad layer 242 may include a plurality of layers.
  • the first cladding layer 242 may include an AlInP-based layer / AlInGaP-based layer.
  • the thickness of the first cladding layer 242 may be 0.45 ⁇ m to 0.55 ⁇ m. However, the present invention is not limited thereto.
  • the active layer 243 may be disposed on the first clad layer 242.
  • the active layer 243 may be disposed between the first conductivity type semiconductor layer 241 and the second conductivity type semiconductor layer 244b.
  • the active layer 243 may generate light having a red wavelength.
  • the thickness of the active layer 243 may be 0.54 ⁇ m to 0.66 ⁇ m. However, the present invention is not limited thereto. Electrons are cooled in the first cladding layer 242 so that the active layer 243 may generate more emission recombination.
  • the second conductivity-type semiconductor layer 244 may be disposed on the active layer 243.
  • the second conductive semiconductor layer 244 may include a 2-1 conductive semiconductor layer 244a and a 2-2 conductive semiconductor layer 244b.
  • the 2-1 conductivity type semiconductor layer 244a may be disposed on the active layer 243.
  • the 2-2 conductivity type semiconductor layer 244b may be disposed on the 2-1 conductivity type semiconductor layer 244a.
  • the 2-1 conductive semiconductor layer 244a may include TSBR and P-AllnP.
  • the thickness of the 2-1 conductive semiconductor layer 244a may be 0.57 ⁇ m to 0.70 ⁇ m. However, the present invention is not limited thereto.
  • the 2-1 conductivity type semiconductor layer 244a may be a p-type semiconductor layer when the 2-1 conductivity type semiconductor layer 244a doped with the second dopant is doped.
  • the 2-2 conductivity type semiconductor layer 244b may be disposed on the 2-1 conductivity type semiconductor layer 244a.
  • the second-2 conductive semiconductor layer 244b may include a p-type GaP-based layer.
  • the second-second conductive semiconductor layer 244b may include a superlattice structure of a GaP layer / InxGa1-xP layer (where 0 ⁇ x ⁇ 1).
  • Mg of about 10 ⁇ 10 ⁇ 18 concentration may be doped into the 2-2 conductivity type semiconductor layer 244b, but is not limited thereto.
  • the 2-2 conductivity type semiconductor layer 244b may be formed of a plurality of layers, and Mg may be doped only in some layers.
  • the thickness d12 of the second-2 conductivity type semiconductor layer 244b may be 0.9 ⁇ m to 1.1 ⁇ m. However, the present invention is not limited thereto.
  • the second electrode 252 may be disposed on the second-second conductive semiconductor layer 244b.
  • the second electrode 252 may be electrically connected to the second-second conductive semiconductor layer 244b.
  • the ratio of (d2) may be 1: 0.6 to 1: 0.95.
  • the first minimum height d1 from the bottom surface of the semiconductor structure 120 to the second upper surface S12 may be 5 ⁇ m to 8 ⁇ m. That is, the first minimum height d1 may be the overall thickness of the semiconductor structure 120.
  • the second minimum height d2 from the bottom surface of the semiconductor structure 120 to the first upper surface S11 may be 3.0 ⁇ m to 7.6 ⁇ m.
  • the difference d3 between the first minimum height d1 and the second minimum height d2 may be 2.0 ⁇ m or less.
  • the difference in height is larger than 2.0 ⁇ m, there is a problem in that transfer occurs during transfer of the semiconductor device, which makes it difficult to transfer the semiconductor device to a desired position.
  • the difference d3 between the first minimum height d1 and the second minimum height d2 is 1.0 ⁇ m or less, the upper surface of the semiconductor structure is almost flat, thereby facilitating transfer and suppressing crack generation.
  • FIG. 22A illustrates a crystal direction of a sapphire substrate
  • FIG. 22B illustrates a crystal direction of a semiconductor structure
  • FIG. 23 illustrates a crystal lattice of a semiconductor structure.
  • the growth substrate 1 may have a hexagonal crystal structure (HCP).
  • the growth substrate may be a sapphire substrate.
  • the hexagonal crystal structure may have a plurality of crystal orientations and cleaved surfaces.
  • a cleaved surface can be defined as a surface vulnerable to cracks.
  • the crystal direction may be a line connecting vertices facing each other on the C-plane of the hexagonal crystal structure.
  • the GaN thin film may be grown by rotating 30 degrees on the sapphire substrate 1. This rotation may be due to lattice mismatch. Therefore, the crystal directions D11, D12, and D13 and / or cleaved surfaces also rotate 30 degrees relative to the sapphire substrate 1. If the inclined surface of the GaN thin film is formed along the crystal directions D11, D12, and D13 and / or the cleaved surface, cracks may easily propagate.
  • the crystal structure of the GaN semiconductor structure may include a C-plane, an A-plane, and an M-plane.
  • the M-plane may be a cleaved surface.
  • the GaN semiconductor structure may have six cleaved surfaces.
  • FIG. 24A is a diagram illustrating a plurality of semiconductor devices having mesa etching along a crystal direction
  • FIG. 24B is an enlarged view of a portion A of FIG. 24A
  • FIG. 24C is a side view of FIG. 24A.
  • a plurality of semiconductor devices 10 may be manufactured by isolating the semiconductor structure 120 formed on the sapphire substrate 1.
  • a portion of the first conductive semiconductor layer may be mesa-etched.
  • a detailed method of manufacturing a semiconductor device may be the same as that of FIGS. 19A to 19F.
  • the semiconductor device 10 may include a semiconductor structure 120 including a first conductive semiconductor layer 121, a second conductive semiconductor layer 123, and an active layer 122;
  • the first electrode 131 is disposed in the exposed region of the first conductive semiconductor layer 121, and the second electrode 132 is disposed on the second conductive semiconductor layer 123.
  • the upper surface of the semiconductor structure may include a first upper surface S11 on which the first electrode 131 is disposed and a second electrode 132 on which the second electrode 132 is disposed.
  • the second upper surface S12 and the inclined surface S13 disposed between the first upper surface S11 and the second upper surface S12 may be formed.
  • the second inclination angle ⁇ 2 may be 20 degrees to 70 degrees.
  • the extension direction of the boundary line P1 where the inclined surface S13 and the first upper surface S11 meet is horizontal to the crystal directions D11, D12, D13 and / or the cleaved surface M-plane of the semiconductor structure 120.
  • cracks may occur on the inclined surface in the process of transferring the semiconductor device 10. That is, if the inclined surface (S13) has the M-plane (breaking surface) of the crystal lattice, there is a problem that the chip is easily broken after the LLO process.
  • the inclined surface S13 extends in the Z-axis direction, so that the inclined surface S13 may extend horizontally with the crystal direction D13 and / or the cleaved surface (M-plane) to easily cause cracks R1.
  • FIG. 25 is a diagram illustrating a semiconductor device in which a mesa etching direction is shifted from a crystal direction
  • FIG. 26 is a first modified example of FIG. 25
  • FIG. 27 is a second modified example of FIG. 25.
  • the extending direction of the boundary line P1 of the active layer 122 is not horizontal to the crystal directions D11, D12, and D13 and / or the cleaved surface (M-plane).
  • the extension direction (X direction) of the boundary line P1 may coincide with a normal line D2 perpendicular to the crystal directions D11, D12, and D13. That is, the extension direction of the boundary line P1 may be perpendicular to at least one of the crystal directions D11, D12, and D13.
  • the inclined surface S13 may have an A-plane of a hexagonal crystal lattice. Therefore, the occurrence of cracks can be suppressed.
  • the extension direction of the boundary line P1 may be disposed to have an inclination with both of the plurality of crystal directions D11, D12, and D13 and the cleaved surface (M-plane). . That is, the extending direction of the boundary line P1 may be disposed not to be horizontal or perpendicular to the plurality of crystal directions D11, D12, and D13 and the cleaved surface (M-plane).
  • the extension direction of the boundary line P1 may be disposed between two adjacent crystal directions D11 and D12. That is, the extending direction of the boundary line P1 is between the first crystal direction D11 and the second crystal direction D12, between the first crystal direction D11 and the third crystal direction D13, and the second crystal direction ( D12) and the third crystal direction D13.
  • the extension direction of the boundary line P1 may have a normal line D2 that bisects two adjacent crystal directions D11 and D12 and angle differences ⁇ 31 and ⁇ 32 between ⁇ 10 degrees and +10 degrees.
  • the angle differences ⁇ 31 and ⁇ 32 from the normal line D2 are smaller than -10 degrees or larger than +10 degrees, the angle formed between the crystal directions D11, D12, and D13 and the cleavage plane (M-plane) becomes horizontal. The risk of cracking can increase.
  • FIG. 28 is a view illustrating a crystal direction of a GaAs semiconductor structure
  • FIG. 29 is a view illustrating a semiconductor device in which a mesa etching direction is shifted from a crystal direction of a GaAs semiconductor structure.
  • the GaAs-based semiconductor structure 120B may be disposed to be inclined with the cleaved surfaces D14, D15, D16, and D17.
  • the cleaved surfaces D14, D15, D16, and D17 may be defined as horizontal cleaved surfaces D14 and D15 and vertical cleaved surfaces D16 and D17.
  • the extension direction of the boundary line P1 of the semiconductor structure may be disposed to be inclined with both the horizontal cleaved surfaces D14 and D15 and the vertical cleaved surfaces D16 and D17. That is, it may not be arranged perpendicularly or horizontally to any one cleaved surface. According to this configuration, cracks may not easily propagate to the semiconductor structure even when an external impact is applied.
  • the first crossing angle ⁇ 41 formed between the extending direction of the boundary line P1 of the semiconductor structure and the vertical cleaving surfaces D16 and D17 may be 30 to 60 degrees.
  • the second crossing angle ⁇ 42 formed between the extending direction of the boundary line P1 of the semiconductor structure and the horizontal cleaved surfaces D14 and D15 may be 30 to 60 degrees.
  • the sum of the first cross angle ⁇ 41 and the second cross angle ⁇ 42 may be 90 degrees.
  • FIG. 30 is a cross-sectional view of a semiconductor device according to an example embodiment.
  • FIG. 31A is a perspective view of the semiconductor structure of FIG. 1
  • FIG. 31B is a plan view of the semiconductor structure of FIG. 1
  • FIG. 32 is a semiconductor according to an embodiment.
  • SEM picture showing the side of the device
  • Figure 33 is a SEM picture showing the side of the semiconductor device without irregularities.
  • the semiconductor device 10 may include a substrate, a semiconductor structure 120, a first electrode 131, a second electrode 132, and an insulating layer 141. have.
  • the semiconductor structure 120 may include a first conductive semiconductor layer 121, an active layer 122, and a second conductive semiconductor layer 123.
  • the semiconductor structure 120 may have a structure in which the first conductive semiconductor layer 121, the active layer 122, and the second conductive semiconductor layer 123 are sequentially stacked in the thickness direction (Y-axis direction).
  • the structure of the first conductive semiconductor layer 121, the active layer 122, and the second conductive semiconductor layer 123 may be applied as it is.
  • the first electrode 131 may be disposed on the first conductivity type semiconductor layer 121. Here, a portion of the first conductivity type semiconductor layer 121 may be exposed by etching. In addition, the first electrode 131 may be disposed on the first conductive semiconductor layer 121 exposed by etching.
  • the first electrode 131 may be electrically connected to the first conductive semiconductor layer 121.
  • the second electrode 132 may be disposed on the second conductivity type semiconductor layer 123.
  • the second electrode 132 may be electrically connected to the second conductive semiconductor layer 123.
  • the first electrode 131 and the second electrode 132 are indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZO), and indium gallium zinc oxide (IGZO). ), Indium gallium tin oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZO (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga) ZnO), ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au may be formed to include at least one, but is not limited to these materials.
  • the first electrode 131 and the second electrode 132 may be indium tin oxide (ITO), but are not limited thereto.
  • the thickness of the first electrode 131 and the second electrode 132 may be 40 nm to 70 nm. However, the present invention is not limited thereto, and the thicknesses of the first electrode 131 and the second electrode 132 may be different from each other, or may have different compositions.
  • the insulating layer 141 may be disposed on the top and side surfaces of the semiconductor structure.
  • the insulating layer 141 may include a first hole H1 exposing a part of the first electrode 131 and a second hole H2 exposing a part of the second electrode 132.
  • the insulating layer 141 may electrically insulate the semiconductor structure 120.
  • the insulating layer 141 may include at least one of SiO 2 , SixOy, Si 3 N 4 , SixNy, SiOxNy, Al 2 O 3 , TiO 2 , AlN, but is not limited thereto.
  • Top surfaces S11, S12, and S13 of the semiconductor structure 120 may include a first upper surface S11 on which the first electrode 131 is disposed, and a second upper surface on which the second electrode 132 is disposed. S12 and the inclined surface S13 disposed between the first upper surface S11 and the second upper surface S12.
  • the first upper surface S11 may be defined as a surface on which the first conductive semiconductor layer 121 is exposed
  • the second upper surface S12 may be defined as an upper surface of the second conductive semiconductor layer 123.
  • the inclined surface S13 may be defined as an inclined region disposed between the first upper surface S11 and the second upper surface S12 by mesa etching. That is, the inclined surface S13 may be defined by side surfaces of the first conductive semiconductor layer 121, the active layer 122, and the second conductive semiconductor layer 123 exposed by mesa etching.
  • the second inclination angle ⁇ 2 that the inclined surface S13 makes with the virtual horizontal plane may be 20 ° to 70 ° or 20 ° to 50 °.
  • the second inclination angle ⁇ 2 is smaller than 20 °, the area of the second upper surface S12 may be reduced, thereby lowering the light output.
  • the second inclination angle ⁇ 2 is greater than 70 °, the inclination angle is increased to increase the risk of damage due to external impact.
  • the first inclination angle ⁇ 1 formed at the side surface of the semiconductor structure 120 with the horizontal plane may be 70 ° to 90 °.
  • the area of the second upper surface S12 may be reduced, which may reduce light output.
  • the second upper surface S12 may be higher than the first upper surface S11 by the etched thickness. That is, as the etching deepens, the height difference d3 between the first upper surface S11 and the second upper surface S12 may increase.
  • the chip When the height difference d3 between the first upper surface S11 and the second upper surface S12 is larger than 2 ⁇ m, the chip may be horizontally displaced during the transfer process. That is, the larger the step, the more difficult the chip is to keep horizontal.
  • the transfer process may mean an operation of transferring a chip from a growth substrate to another substrate.
  • the ratio d1: d2 of the second minimum height d2 may be 1: 0.6 to 1: 0.95.
  • the step height may increase, and a defect rate may be increased during the transfer process, and when the height ratio is smaller than 1: 0.95, the mesa etching depth may be lowered to partially reduce the first conductive semiconductor layer ( 121) may not be exposed.
  • the first minimum height d1 from the bottom surface of the semiconductor structure 120 to the second upper surface S12 may be 5 ⁇ m to 8 ⁇ m. That is, the first minimum height d1 may be the overall thickness of the semiconductor structure 120.
  • the second minimum height d2 from the bottom surface of the semiconductor structure 120 to the first upper surface S11 may be 3.0 ⁇ m to 7.6 ⁇ m.
  • the difference d3 between the first minimum height d1 and the second minimum height d2 may be 350 nm or more and 2.0 ⁇ m or less.
  • the height difference d3 is larger than 2.0 ⁇ m, a distortion occurs during the transfer of the semiconductor device, which makes it difficult to transfer the semiconductor device to a desired position.
  • the height difference d3 is smaller than 350 nm, the first conductive semiconductor layer 121 may not be partially exposed.
  • the upper surface of the semiconductor structure is substantially flat, which facilitates transfer and suppresses crack generation.
  • the difference d3 between the first minimum height d1 and the second minimum height d2 may be 0.6 ⁇ m ⁇ 0.2 ⁇ m, but is not limited thereto.
  • four side surfaces S21, S22, S23, and S24 of the semiconductor structure 120 may be inclined at the same angle. That is, the first inclination angle ⁇ 1 of the four side surfaces S21, S22, S23, and S24 of the semiconductor structure may be 70 ° to 90 °.
  • the width of the inclined surface S13 may become narrower from the first upper surface S11 to the second upper surface S12 (W4> W3). This structure can be equally applied to the semiconductor structures of FIGS. 1 and 13.
  • the first side surface S21 and the second side surface S22 are long side surfaces, and the third side surface S23 and the fourth side surface S24 have short sides. can do. That is, the semiconductor device according to the embodiment may have a rectangular shape.
  • the width W1 of the first side may have a length of 30 ⁇ m to 60 ⁇ m, and the width W2 of the third side may have a length of 8 ⁇ m to 35 ⁇ m.
  • the width W1 of the first side may have a length of 45 ⁇ m ⁇ 5 ⁇ m, and the width W2 of the third side may have a length of 21 ⁇ m ⁇ 5 ⁇ m, but is not limited thereto.
  • an area ratio between an upper surface and a side surface may be 1: 0.4 to 1: 0.9.
  • the semiconductor device according to the embodiment has a micro size having a long side surface and a short side surface of 50 ⁇ m or less, the area ratio of the side surface is relatively large. Therefore, in the light emitting device having a micro size, the light extraction efficiency at the side surface may greatly affect the overall light emission efficiency.
  • the uneven pattern Q11 may be disposed on a plurality of side surfaces S21, S22, S23, and S24.
  • the uneven pattern Q11 may extend in the upper direction (thickness direction) from the bottom of the semiconductor structure, and may be continuously disposed along the side surface of the semiconductor structure.
  • the uneven pattern Q11 may improve light extraction efficiency toward the side of the semiconductor structure. Therefore, the luminous efficiency can be improved in the semiconductor device of the same size.
  • the uneven pattern Q11 may be controlled by adjusting a mixing ratio of an etching solution used when isolating a plurality of semiconductor structures.
  • the uneven pattern Q11 of FIG. 3 may be formed using an etching solution in which BCl 3 and Cl 2 are mixed. At this time, by adjusting the BCl 3 to 10wt% or less can form a columnar irregularities.
  • etching process a mask (not shown) is covered on the upper portion of the semiconductor structure, and the etching process may be performed by spraying an etching solution on the side surface of the semiconductor structure.
  • the uneven pattern Q11 is formed on the side surfaces S21, S22, S23, and S24, so that light extraction efficiency may be improved.
  • the inclined surface S13 of the semiconductor structure and the bottom surface B1 of the semiconductor structure may be relatively flatter than the side surfaces S21, S22, S23, and S24.
  • the stepped surface S13 is too low, about 2 ⁇ m or less, unevenness may be hardly formed.
  • the bottom surface B1 since the bottom surface B1 is separated from the substrate by the LLO process, the bottom surface B1 may have a relatively flat surface. That is, the surface roughness of the inclined surface S13 and the bottom surface B1 may be smaller than the surface roughness of the side surface of the semiconductor structure.
  • FIG. 34 is a modification of FIG. 30.
  • the insulating layer 141 according to the embodiment may expose the lower side of the semiconductor structure 120.
  • the bonding force of the insulating layer 141 may be relatively low. Therefore, the insulating layer 141 may not completely cover the side surface of the semiconductor structure 120, and a portion of the semiconductor structure 120 may be exposed.
  • the end surface of the insulating layer 141 may have an irregular concave-convex pattern 141a formed while the insulating layer is broken.
  • FIG. 35 is a cross-sectional view illustrating a semiconductor device in accordance with another embodiment of the present invention
  • FIG. 36 is a plan view of FIG. 35
  • FIG. 37 is a SEM photograph showing a side surface of a semiconductor device according to another embodiment.
  • a plurality of uneven patterns Q21 and Q22 may be disposed on side surfaces of the semiconductor structure 120.
  • the uneven patterns Q21 and Q22 may include a first uneven pattern Q21 and a second uneven pattern Q22 disposed above the first uneven pattern Q21.
  • the first uneven pattern Q21 may be disposed under the side surface of the semiconductor structure 120, and the second uneven pattern Q22 may be disposed at an intermediate position of the side surface.
  • the first uneven pattern Q21 may protrude more toward the side of the semiconductor structure than the second uneven pattern Q22.
  • the uneven pattern may be controlled by adjusting the mixing ratio of the etching solution when the plurality of semiconductor structures are isolated.
  • the first uneven pattern Q21 and the second uneven pattern Q22 of FIG. 37 may be formed using an etching solution in which BCl 3 and Cl 2 are mixed.
  • the BCl 3 to 10wt% or more can form irregularities having a step.
  • the irregularities can be formed by forming the lateral inclination of the mask at 60 degrees or more as described above.
  • the uneven patterns Q21 and Q22 may be disposed in a region lower than the active layer 122.
  • the uneven patterns Q21 and Q22 cover the side surfaces of the active layer 122, light extraction efficiency may decrease.
  • the height of the uneven patterns Q21 and Q22 may be adjusted by controlling the etching time. For example, as the etching time is extended, heights of the first uneven pattern Q21 and the second uneven pattern Q22 may gradually decrease.
  • 38A to 38E are flowcharts illustrating a method of manufacturing a semiconductor device according to an embodiment.
  • the semiconductor structure 120 may be grown on the growth substrate 1.
  • the growth substrate 1 may be formed of a material selected from sapphire (Al 2 O 3 ), GaAs, SiC, GaN, ZnO, Si, GaP, InP, and Ge, but is not particularly limited as long as it is a material that transmits visible light.
  • the first conductive semiconductor layer 121, the active layer 122, and the second conductive semiconductor layer 123 may be sequentially formed on the growth substrate 1.
  • the semiconductor structure 120 may include metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam growth (Molecular Beam).
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • MBE Hydride Vapor Phase Epitaxy
  • Sputtering or the like.
  • the semiconductor structure 120 may be mesa etched.
  • Mesa etching may be performed up to a part of the first conductivity type semiconductor layer 121.
  • the angle of mesa etching may be 20 ° to 70 °.
  • the second inclination angle ⁇ 2 may be formed by mesa etching.
  • the second electrode 132 may be formed on the second conductive semiconductor layer 123, and the first electrode 131 may be formed on the first conductive semiconductor layer 121.
  • a semiconductor device may be separated into one semiconductor device on a substrate through etching. That is, each of the semiconductor devices may be isolated by etching.
  • the inclination of the side surface of the semiconductor device may be adjusted by the etching angle.
  • the aforementioned first inclination angle ⁇ 1 may be an angle formed by an etching angle.
  • the first inclination angle ⁇ 1 may be 70 ° to 90 °.
  • the thickness of the edge of the first conductivity-type semiconductor layer 121 under the semiconductor structure 120 may become thinner. As a result, there is a problem that cracks occur at the edge of the first conductivity-type semiconductor layer 121 while the semiconductor structure 120 is separated from the growth substrate 1.
  • the first inclination angle ⁇ 1 may be greater than the second inclination angle ⁇ 2.
  • the etching may be performed to the bottom of the semiconductor structure 120.
  • the first conductive semiconductor layer 121, the active layer 122, and the second conductive semiconductor layer 123 may have the same etching surface and inclination angle by the etching.
  • an uneven pattern Q11 may be formed on the side surface of the semiconductor structure.
  • an insulating layer 141 may be disposed on the plurality of semiconductor devices.
  • the insulating layer 141 may be disposed on the side and top surfaces of the semiconductor structure 120, on the first electrode 131, and the second electrode 132.
  • 39A to 39E are flowcharts illustrating a process of transferring a semiconductor device to a display device according to an embodiment.
  • a method of manufacturing a display device separates a semiconductor device from a substrate by selectively irradiating a laser to a semiconductor device including a plurality of semiconductor devices disposed on the growth substrate 1. And disposing the separated semiconductor device on the panel substrate 300.
  • the semiconductor device may include a first conductive semiconductor layer, an active layer disposed on the first conductive semiconductor layer, a second conductive semiconductor layer disposed on the active layer, and a first electrode disposed on the first conductive semiconductor layer. It may include a second electrode disposed on the second conductive semiconductor layer and an insulating layer covering the semiconductor structure.
  • the growth substrate may be the same as the growth substrate 1 described above with reference to FIGS. 38A through 38E.
  • a plurality of semiconductor devices may be disposed on the growth substrate 1.
  • the insulating layer 141 may be continuously formed along the top and side surfaces of the plurality of semiconductor devices.
  • the plurality of semiconductor devices may include a first semiconductor device 10-1, a second semiconductor device 10-2, a third semiconductor device 10-3, and a fourth semiconductor device 10-4. have.
  • the present invention is not limited thereto, and the semiconductor device may have various numbers.
  • the growth substrate is a semiconductor wafer, micro-sized semiconductor devices can be arranged in a very large number.
  • the transfer member 2 may include a first bonding layer 211 and a transfer frame 212 disposed below.
  • the carrier frame 212 may have an uneven structure, and may easily bond the semiconductor element and the first bonding layer 211 to each other. However, it is not limited to this shape.
  • the selected semiconductor device may be separated from the growth substrate 1 by irradiating a laser under the selected semiconductor device.
  • the transfer member 2 moves upward, and the semiconductor element may move along the movement of the transfer member 2.
  • the growth substrate 10 and the first semiconductor element 10- are irradiated with a laser under a region where the first semiconductor element 10-1 and the third semiconductor element 10-3 are disposed on the growth substrate 10. 1) and the third semiconductor device 10-3 may be separated.
  • the present invention is not limited thereto, and the transfer member 2 may protrude so that the bonding layer 211 is bonded to one semiconductor element so as to separate one semiconductor element at a time.
  • a laser lift-off (LLO) using a photon beam having a specific wavelength band may be applied.
  • a protective layer (not shown) may be disposed between the semiconductor device and the growth substrate 10 in order to prevent physical damage between the semiconductor devices due to laser lift-off (LLO).
  • LLO laser lift-off
  • the semiconductor device separated into the growth substrate 10 may have a predetermined separation interval.
  • the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated from the growth substrate, and the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated from each other.
  • the second semiconductor device 10-2 and the fourth semiconductor device 10-4 having the same separation distance from each other may be separated in the same manner. As a result, semiconductor devices having the same separation distance may be transferred to the display panel.
  • the insulating layer may be broken while the first semiconductor device 10-1 and the third semiconductor device 10-3 are separated from the growth substrate. Therefore, the uneven pattern 141a may be formed in the insulating layer 141 formed on the side surface of the semiconductor device.
  • the selected semiconductor device may be disposed on the panel substrate 300.
  • the first semiconductor element 10-1 and the third semiconductor element 10-3 may be disposed on the panel substrate 300.
  • the second bonding layer 310 may be disposed on the panel substrate 300, and the first semiconductor element 10-1 and the third semiconductor element 10-3 may be disposed on the second bonding layer 310. It can be placed on. Accordingly, the first semiconductor device 10-1 and the third semiconductor device 10-3 may be in contact with the second bonding layer. In this manner, semiconductor devices having spaced intervals may be disposed on the panel substrate to improve the efficiency of the transfer process.
  • a laser may be irradiated to separate the first bonding layer 211 and the selected semiconductor device.
  • the first bonding layer 211 and the selected semiconductor device may be physically separated.
  • the first bonding layer 211 may include various polymer materials that lose adhesiveness when irradiated with laser.
  • the first semiconductor element 10-1 and the third semiconductor element 10-3 may be separated from the transfer member 2. have.
  • coupling between the second bonding layer 310, the first semiconductor device 10-1, and the third semiconductor device 10-3 may be performed.
  • FIG. 40 is a conceptual diagram of a display device to which a semiconductor device is transferred according to an exemplary embodiment.
  • a display device including a semiconductor device includes a second panel substrate 410, a driving thin film transistor T2, a planarization layer 430, a common electrode CE, a pixel electrode AE, and a semiconductor. It may include a device.
  • the driving thin film transistor T2 includes a gate electrode GE, a semiconductor layer SCL, an ohmic contact layer OCL, a source electrode SE, and a drain electrode DE.
  • the driving thin film transistor is a driving device and may be electrically connected to the semiconductor device to drive the semiconductor device.
  • the gate electrode GE may be formed together with the gate line.
  • the gate electrode GE may be covered with the gate insulating layer 440.
  • the gate insulating layer 440 may be formed of a single layer or a plurality of layers made of an inorganic material, and may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like.
  • the semiconductor layer SCL may be disposed on the gate insulating layer 440 in a predetermined pattern (or island) form so as to overlap the gate electrode GE.
  • the semiconductor layer SCL may be formed of a semiconductor material including any one of amorphous silicon, polycrystalline silicon, oxide, and organic material, but is not limited thereto.
  • the ohmic contact layer OCL may be disposed on the semiconductor layer SCL in a predetermined pattern (or island) form.
  • the ohmic contact layer PCL may be for an ohmic contact between the semiconductor layer SCL and the source / drain electrodes SE and DE.
  • the source electrode SE is formed on the other side of the ohmic contact layer OCL to overlap one side of the semiconductor layer SCL.
  • the drain electrode DE may be formed on the other side of the ohmic contact layer OCL to be spaced apart from the source electrode SE while overlapping the other side of the semiconductor layer SCL.
  • the drain electrode DE may be formed together with the source electrode SE.
  • the planarization layer may be disposed on an entire surface of the second panel substrate 410.
  • the driving thin film transistor T2 may be disposed in the planarization layer.
  • the planarization layer according to an embodiment may include an organic material such as benzocyclobutene or photo acryl, but is not limited thereto.
  • the groove 450 may be a predetermined emission region, and a semiconductor device may be disposed.
  • the light emitting area may be defined as a remaining area of the display apparatus except for a circuit area.
  • the groove 450 may be concave in the planarization layer 430, but is not limited thereto.
  • the semiconductor device may be disposed in the groove 450.
  • the first and second electrodes of the semiconductor device may be connected to a circuit (not shown) of the display device.
  • the semiconductor device may be attached to the groove 450 through the adhesive layer 420.
  • the adhesive layer 420 may be the second bonding layer, but is not limited thereto.
  • the second electrode 132 of the semiconductor device may be electrically connected to the source electrode SE of the driving thin film transistor T2 through the pixel electrode AE.
  • the first electrode 131 of the semiconductor device may be connected to the common power line CL through the common electrode CE.
  • the first and second electrodes 131 and 132 may be stepped with each other, and the electrode 131 at a relatively lower position among the first and second electrodes 131 and 132 is the same as the top surface of the planarization layer 430. It can be located on a horizontal line. However, the present invention is not limited thereto.
  • the pixel electrode AE may electrically connect the source electrode SE of the driving thin film transistor T2 and the second electrode of the semiconductor device.
  • the common electrode CE may electrically connect the common power line CL and the first electrode of the semiconductor device.
  • the pixel electrode AE and the common electrode CE may each include a transparent conductive material.
  • the transparent conductive material may include a material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.
  • SD standard definition
  • FHD full HD
  • UH. UH.
  • the semiconductor device according to the embodiment may be arranged and connected in plurality in accordance with the resolution.
  • the display device may be a display panel or a TV having a diagonal size of 100 inches or more, and the pixel may be implemented as a light emitting diode (LED).
  • LED light emitting diode
  • the embodiment implements an image and an image using a semiconductor device, color purity and color reproduction are excellent.
  • the embodiment implements an image and an image by using a light emitting device package having excellent linearity, thereby enabling a clear large display device of 100 inches or more.
  • the embodiment can realize a high resolution 100 inch or larger display device at low cost.
  • the semiconductor device according to the embodiment may further include an optical member such as a light guide plate, a prism sheet, and a diffusion sheet to function as a backlight unit.
  • the semiconductor device of the embodiment may be further applied to a display device, a lighting device, and a pointing device.
  • the display device may include a bottom cover, a reflector, a light emitting module, a light guide plate, an optical sheet, a display panel, an image signal output circuit, and a color filter.
  • the bottom cover, the reflector, the light emitting module, the light guide plate, and the optical sheet may form a backlight unit.
  • the reflecting plate is disposed on the bottom cover, and the light emitting module emits light.
  • the light guide plate is disposed in front of the reflective plate to guide light emitted from the light emitting module to the front, and the optical sheet includes a prism sheet or the like and is disposed in front of the light guide plate.
  • the display panel is disposed in front of the optical sheet, the image signal output circuit supplies the image signal to the display panel, and the color filter is disposed in front of the display panel.
  • the lighting apparatus may include a light source module including a substrate and a semiconductor device of an embodiment, a heat dissipation unit for dissipating heat of the light source module, and a power supply unit for processing or converting an electrical signal provided from the outside and providing the light source module to the light source module.
  • the lighting device may include a lamp, a head lamp, a street lamp or the like.
  • the camera flash of the mobile terminal may include a light source module including the semiconductor device of the embodiment.

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113410356A (zh) * 2021-07-21 2021-09-17 山西中科潞安紫外光电科技有限公司 一种倒装结构深紫外发光二极管芯片及其制备方法
US11522112B2 (en) * 2019-02-01 2022-12-06 Lextar Electronics Corporation Light emitting diode and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070040260A (ko) * 2005-10-11 2007-04-16 삼성전기주식회사 질화물 반도체 발광소자 및 제조방법
KR20080072555A (ko) * 2007-02-01 2008-08-06 니치아 카가쿠 고교 가부시키가이샤 반도체 발광 소자
KR20130047143A (ko) * 2011-10-31 2013-05-08 엘지이노텍 주식회사 발광소자 및 발광소자 제조방법
KR20140060149A (ko) * 2012-11-09 2014-05-19 서울바이오시스 주식회사 발광 소자 및 그것을 제조하는 방법
KR20140071689A (ko) * 2012-12-04 2014-06-12 주식회사 세미콘라이트 반도체 발광소자 및 이를 제조하는 방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014088322A1 (ko) * 2012-12-04 2014-06-12 주식회사 세미콘라이트 반도체 발광소자 및 이를 제조하는 방법
KR102284597B1 (ko) * 2013-03-13 2021-08-04 루미리즈 홀딩 비.브이. 다공성 반사성 콘택트를 생성하기 위한 방법 및 장치
JP2016195176A (ja) * 2015-03-31 2016-11-17 ウシオ電機株式会社 窒化物半導体発光素子

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070040260A (ko) * 2005-10-11 2007-04-16 삼성전기주식회사 질화물 반도체 발광소자 및 제조방법
KR20080072555A (ko) * 2007-02-01 2008-08-06 니치아 카가쿠 고교 가부시키가이샤 반도체 발광 소자
KR20130047143A (ko) * 2011-10-31 2013-05-08 엘지이노텍 주식회사 발광소자 및 발광소자 제조방법
KR20140060149A (ko) * 2012-11-09 2014-05-19 서울바이오시스 주식회사 발광 소자 및 그것을 제조하는 방법
KR20140071689A (ko) * 2012-12-04 2014-06-12 주식회사 세미콘라이트 반도체 발광소자 및 이를 제조하는 방법

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11522112B2 (en) * 2019-02-01 2022-12-06 Lextar Electronics Corporation Light emitting diode and manufacturing method thereof
CN113410356A (zh) * 2021-07-21 2021-09-17 山西中科潞安紫外光电科技有限公司 一种倒装结构深紫外发光二极管芯片及其制备方法
CN113410356B (zh) * 2021-07-21 2023-11-17 山西中科潞安紫外光电科技有限公司 一种倒装结构深紫外发光二极管芯片及其制备方法

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