WO2018119652A1 - 阵列基板制作方法 - Google Patents

阵列基板制作方法 Download PDF

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WO2018119652A1
WO2018119652A1 PCT/CN2016/112346 CN2016112346W WO2018119652A1 WO 2018119652 A1 WO2018119652 A1 WO 2018119652A1 CN 2016112346 W CN2016112346 W CN 2016112346W WO 2018119652 A1 WO2018119652 A1 WO 2018119652A1
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pixel
thin film
film transistor
layer
array substrate
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French (fr)
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洪日
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to CN201680044134.0A priority patent/CN108064415A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of manufacturing liquid crystal panels, and in particular, to a method for fabricating an array substrate.
  • an oxide semiconductor TFT (Thin Film Transistor) device is fabricated by patterning PNL (planarization) after PV (passivation) is completed.
  • PNL planarization
  • PV passivation
  • PE pixel electrode
  • PDL pixel definition layer
  • the present application provides a method for fabricating an array substrate, which reduces the number of masks of the array substrate and saves production costs.
  • the method for fabricating an array substrate according to the present invention includes: forming a thin film transistor and a pixel thin film transistor on a substrate; wherein the circuit thin film transistor and the pixel thin film transistor each include a semiconductor layer, a gate electrode, a source electrode, and a drain electrode;
  • a support layer is formed on the flat layer.
  • the step of patterning the flat layer by a halftone mask with a semi-permeable film, forming a pixel defining area and a hole defining area on the flat layer including: providing a light shielding area, a full transparent area, and a half The halftone mask of the transmissive region,
  • a mask of the halftone mask defining a pattern of the pixel defining area and the hole defining area on the flat layer; wherein the corresponding position of the semi-permeable area forms the pixel definition;
  • the halftone mask is removed and the pixel definition area and the hole definition area are formed on the flat layer by development.
  • the step of etching the hole defining region to form a via that communicates with one of a source electrode and a drain electrode of the pixel thin film crystal; comprising: dry etching the insulating layer corresponding to the hole defining region to form a through-hole The via of the insulating layer.
  • the pixel electrode is electrically connected to one of a source and a drain electrode of the pixel thin film transistor by covering a pixel defining region and the via hole.
  • step of forming a support layer covering the boundary of the pixel electrode on the flat layer comprises:
  • the support layer is formed by patterning the organic insulating layer by a patterning patterning process.
  • the step of forming a pixel electrode electrically connected to one of the source electrode and the drain electrode of the pixel thin film transistor on the pixel defining region is formed in the flat layer and the pixel defining region by patterning a patterning process
  • the pixel electrode material layer is formed inside.
  • the patterned patterning process patterns the organic insulating layer to form a reticle in the supporting layer as a halftone mask reticle mode.
  • the circuit thin film transistor and the pixel thin film transistor are respectively formed corresponding to the circuit region and the pixel region; wherein a gate of the circuit thin film transistor is electrically connected to one of a source electrode and a drain electrode of the pixel thin film transistor.
  • the pixel definition area orthographic projection part covers the pixel thin film transistor.
  • the support layer covers both sides of the pixel electrode.
  • the circuit thin film transistor and the pixel thin film transistor formed on the substrate are used to control the same pixel to emit light, wherein the number of circuit thin film transistors is at least one and/or the number of pixel thin film transistors is at least one.
  • the method for fabricating the array substrate of the present application forms a flat layer and a pixel defining region through a mask process, and then forms a supporting layer, which saves the via hole and the pixel defining region of the flat layer by the two mask processes in the prior art.
  • a reticle saves processing and cost.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present application.
  • 2 to 7 are schematic cross-sectional views showing respective steps of a method for fabricating an array substrate of the present application.
  • the method for fabricating the array substrate according to the embodiment of the present application for forming the low-temperature polysilicon substrate may be, but not limited to, an OLED liquid crystal display such as a mobile phone, a computer, a display, or an e-reader, which is not specifically limited in the embodiment of the present application.
  • the method for fabricating an array substrate according to the present application includes:
  • step S1 the circuit thin film transistor 11 and the pixel thin film transistor 12 are formed on the substrate 10.
  • the circuit thin film transistors 11 each include a semiconductor layer 111, a gate electrode 112, a source electrode 113, and a drain electrode 114.
  • the pixel thin film transistor 12 includes a semiconductor layer 121, a gate electrode 122, a source electrode 123, and a drain electrode 124.
  • the step includes, in the first step, defining a circuit area and a pixel area (not shown) in the pixel unit on the substrate 10.
  • the circuit thin film transistor 11 and the pixel thin film transistor 12 are respectively formed corresponding to the circuit region and the pixel region; wherein the gate 112 of the circuit thin film transistor 11 is electrically connected to the source electrode 123 of the pixel thin film transistor 12 And one of the drain electrodes 124.
  • the formation of the circuit thin film transistor 11 and the pixel thin film transistor 12 uses a conventional patterning patterning process, such as film formation, exposure, development, etching, etc., and will not be described herein.
  • the circuit thin film transistor 11 and the pixel thin film transistor 12 formed on the substrate 10 are used to control the same pixel, wherein the number of the circuit thin film transistors 11 is at least one and/or the number of the pixel thin film transistors is 12.
  • the circuit thin film transistor 11 is one
  • the pixel thin film transistor 12 is plural (including two or more)
  • the pixel thin film transistor 12 is One or more circuit thin film transistors 11 (including two or more); or a plurality of circuit thin film transistors 11 and pixel thin film transistors 12.
  • the pixel in this embodiment is described by taking only one circuit thin film transistor 11 and one pixel thin film transistor 12 as an example.
  • an insulating layer 13 covering the circuit thin film transistor 11 and the pixel thin film crystal 12 and a flat layer 14 covering the insulating layer 13 are formed.
  • a PV material layer is formed on the circuit thin film transistor 11 and the pixel thin film crystal 12, and the insulating layer 13 is formed by patterning a PV material layer.
  • the flat layer 14 is formed by coating on the insulating layer 13, and the flat layer 14 is planar away from the surface of the substrate 10.
  • step S3 the flat layer 14 is patterned by a halftone mask 20 having a semi-permeable film, and a pixel defining region 141 and a hole defining region 142 are formed on the flat layer 14. Specifically include:
  • the halftone mask 20 including a light shielding area 21, a full transmission area 22, and a semi-transmissive area 23 is provided.
  • the halftone mask 20 defines a pattern of the pixel defining area and the hole defining area on the flat layer 14; wherein the semi-permeable area 23 corresponds to a position to form the pixel definition; and the full transparent area 22 corresponds to a position Hole definition area.
  • the halftone mask is removed and the pixel defining region 141 and the hole defining region 142 are formed on the flat layer 14 by development.
  • the hole defining region 142 penetrates the flat layer 14 and exposes the insulating layer. That is to say, the pixel defining region 141 and the hole defining region 142 are formed by a mask process, which saves a mask process compared to the conventional manufacturing method.
  • the pixel definition area 141 bit orthographic projection partially covers the pixel thin film transistor 12.
  • step S4 the hole defining region 142 is etched to form a via 143 that communicates with one of the source 123 and the drain electrode 124 of the pixel thin film transistor 12.
  • the via hole 143 penetrating the exposed source 123 of the insulating layer 13 is formed by dry etching the insulating layer 13 corresponding to the hole defining region 142.
  • a pixel electrode 15 electrically connected to one of the source electrode 123 and the drain electrode 124 of the pixel thin film transistor 12 is formed on the pixel defining region 141; specifically, by a patterning process
  • the pixel electrode material layer patterned in the flat layer 14 and the pixel defining region 141 constitutes the pixel electrode 15.
  • the pixel electrode 15 is electrically connected to the source electrode 123 of the pixel thin film transistor 12 through the via hole 143.
  • the pixel electrode 15 covers the pixel defining region 141 and the inside of the via 143 and the source electrode 123.
  • a support layer 17 is formed on the flat layer 14. Specifically include: An organic insulating layer is formed on the flat layer 14, and the support layer 17 is formed by patterning the organic insulating layer by a patterning patterning process.
  • the patterning process in the step of patterning the organic insulating layer to form the photomask in the supporting layer 17 is a halftone mask mask, or may be formed by using a photoresist layer mask.
  • the support layer 17 covers both side boundaries of the pixel electrode 15.
  • the method for fabricating the array substrate of the present application forms a flat layer and a pixel defining region through a mask process, and then forms a supporting layer, which saves the via hole and the pixel defining region of the flat layer by the two mask processes in the prior art.
  • a reticle saves processing and cost.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板制作方法，包括在基板（10）上形成电路薄膜晶体管（11）与像素薄膜晶体管（12）；形成覆盖电路薄膜晶体管（11）及像素薄膜晶体管（12）的绝缘层（13）及覆盖绝缘层（13）的平坦层（14）；通过带有半透膜的半色调掩膜（20）图案化平坦层（14），在平坦层（14）上形成像素定义区（141）及孔定义区（142）；蚀刻孔定义区（142）形成与像素薄膜晶体管（12）的源电极（123）和漏电极（124）中之一连通的过孔（143）；在像素定义区（141）上形成电连接到像素薄膜晶体管（12）的源电极（123）和漏电极（124）中之一的像素电极（15）；在平坦层（14）上形成支撑层（17）。

Description

阵列基板制作方法 技术领域
本发明涉及液晶面板制造技术领域，尤其涉及一种阵列基板制作方法。
背景技术
现有低温多晶硅基板的氧化物半导体TFT(Thin Film Transistor，薄膜晶体管)器件在制作过程中，制程均是PV(passivation)完后进行PNL(planarization，平坦层)的成膜图案化制作，然后进行PE(pixel electrode)的成膜图案化制作，再下一步进行PDL(pixel design layer，像素定义层)的成膜图案化制作，三道制程需要三道光罩，光罩次数多会增加生产成本。
发明内容
基于上述问题，本申请提供一种阵列基板制作方法，减小阵列基板光罩次数，节省生产成本。
本申请所述的阵列基板制作方法，包括，在基板上形成电路薄膜晶体管与像素薄膜晶体管；其中，所述电路薄膜晶体管及像素薄膜晶体管均包括半导体层、栅电极、源电极和漏电极；
形成覆盖所述电路薄膜晶体管及像素薄膜晶体管的绝缘层及覆盖所述绝缘层的平坦层；
通过带有半透膜的半色调掩膜图案化所述平坦层，在所述平坦层上形成像素定义区及孔定义区；
蚀刻所述孔定义区形成与所述像素薄膜晶体的源电极和漏电极中之一连通的过孔；
在像素定义区上形成电连接到所述像素薄膜晶体管的源电极和漏电极中之一的像素电极；
在所述平坦层上形成支撑层。
其中，所述步骤通过带有半透膜的半色调掩膜图案化所述平坦层，在所述平坦层上形成像素定义区及孔定义区，包括：提供包括遮光区、全透区及半透区的所述半色调掩膜，
光罩所述半色调掩膜在所述平坦层上定义出所述像素定义区及孔定义区的图案；其中半透区对应位置形成所述像素定义；
去除半色调掩膜并通过显影在所述平坦层上形成所述像素定义区及孔定义区。
其中，所述步骤蚀刻所述孔定义区形成与所述像素薄膜晶体的源电极和漏电极中之一连通的过孔；包括干蚀刻所述孔定义区对应的所述绝缘层，形成贯穿所述绝缘层的所述过孔。
其中，所述像素电极由覆盖像素定义区及所述过孔电连接所述像素薄膜晶体管的源和漏电极中之一。
其中，所述步骤在所述平坦层上形成覆盖所述像素电极边界的支撑层包括：
在所述平坦层上形成有机绝缘层，
通过图案化构图工艺图案化所述有机绝缘层形成所述支撑层。
其中，所述步骤在像素定义区上形成电连接到所述像素薄膜晶体管的源电极和漏电极中之一的像素电极，是通过图案化构图工艺图案化形成于所述平坦层及像素定义区内的像素电极材料层构成。
其中，所述图案化构图工艺图案化所述有机绝缘层形成所述支撑层中的光罩为半色调掩膜光罩方式。
其中，所述步骤在基板上形成电路薄膜晶体管与像素薄膜晶体管；包括：
在所述基板上定义电路区域和像素区域；
对应所述电路区域和像素区域分别形成所述电路薄膜晶体管与像素薄膜晶体管；其中，所述电路薄膜晶体管的栅极电连接所述像素薄膜晶体管的源电极与漏电极中的之一。
其中，所述像素定义区位正投影部分覆盖所述像素薄膜晶体管。
其中，所述支撑层覆盖所述像素电极两侧边界。
其中，所述在基板上形成的电路薄膜晶体管与像素薄膜晶体管用于控制同一个像素发光，其中，电路薄膜晶体管个数为至少一个和/或像素薄膜晶体管个数为至少一个。
本申请阵列基板制作方法在通过一道光罩工艺形成平坦层及像素定义区，然后再形成支撑层，相较于现有技术通过两道光罩工艺分别制作平坦层的过孔及像素定义区节省了一道光罩，进而节省了加工流程及成本。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例的阵列基板制作方法的流程图。
图2至图7是本申请阵列基板制作方法的各个步骤截面示意图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述。
本申请实施例涉及的阵列基板制作方法用于形成低温多晶硅基板可以为但不限于手机、电脑、显示器或电子阅读器等OLED液晶显示器中，本申请实施例此不作具体限定。
本申请所述的阵列基板制作方法，包括：
请参阅图1与图2，步骤S1，在基板10上形成电路薄膜晶体管11与像素薄膜晶体管12。所述电路薄膜晶体管11均包括半导体层111、栅电极112、源电极113和漏电极114；所述像素薄膜晶体管12包括半导体层121、栅电极122、源电极123和漏电极124。
具体的，本步骤包括，第一步，在所述基板10上的像素单元中定义电路区域和像素区域(图未示)。第二步，对应所述电路区域和像素区域分别形成所述电路薄膜晶体管11与像素薄膜晶体管12；其中，所述电路薄膜晶体管11的栅极112电连接所述像素薄膜晶体管12的源电极123与漏电极124中的之一。本步骤中，电路薄膜晶体管11与像素薄膜晶体管12的形成使用传统的图案化构图工艺，如成膜、曝光、显影、蚀刻等，在此不做赘述。需要说明的是，所述在基板10上形成的电路薄膜晶体管11与像素薄膜晶体管12是用于控制同一个像素，其中，电路薄膜晶体管11个数为至少一个和/或像素薄膜晶体管12个数为至少一个，也就是说根据设计需要，电路薄膜晶体管11为一个，像素薄膜晶体管12为多个(包括两个及两个以上)，或者像素薄膜晶体管12为 一个、电路薄膜晶体管11为多个(包括两个及两个以上)；或者电路薄膜晶体管11与像素薄膜晶体管12均为多个。本实施例中的像素仅以一个电路薄膜晶体管11和一个像素薄膜晶体管12为例进行说明制造方法。
请参阅图3，步骤S2，形成覆盖所述电路薄膜晶体管11及像素薄膜晶体12的绝缘层13及覆盖所述绝缘层13的平坦层14。具体的，在所述电路薄膜晶体管11及像素薄膜晶体12上形成PV材料层，通过图案化PV材料层形成所述绝缘层13。在所述绝缘层13上涂布形成所述平坦层14，所述平坦层14远离基板10的表面为平面。
请参阅图4，步骤S3，通过带有半透膜的半色调掩膜20图案化所述平坦层14，在所述平坦层14上形成像素定义区141及孔定义区142。具体包括：
提供包括遮光区21、全透区22及半透区23的所述半色调掩膜20，
光罩所述半色调掩膜20在所述平坦层14上定义出所述像素定义区及孔定义区的图案；其中半透区23对应位置形成所述像素定义；全透区22对应位置形成孔定义区。
去除半色调掩膜并通过显影在所述平坦层14上形成所述像素定义区141及孔定义区142。其中孔定义区142贯穿所述平坦层14并露出所述绝缘层。也就是说通过一道光罩工艺形成像素定义区141及孔定义区142，相较于传统的制造方法，节省了一道光罩工艺。所述像素定义区141位正投影部分覆盖所述像素薄膜晶体管12。
请参阅图5，步骤S4，蚀刻所述孔定义区142形成与所述像素薄膜晶体管12的源极123和漏电极124中之一连通的过孔143。具体的，通过干蚀刻所述孔定义区142对应的所述绝缘层13，形成贯穿所述绝缘层13的露出源极123的所述过孔143。
请参阅图6与图7，步骤S5，在像素定义区141上形成电连接到所述像素薄膜晶体管12的源电极123和漏电极124中之一的像素电极15；具体是通过图案化构图工艺图案化形成于所述平坦层14及像素定义区141内的像素电极材料层构成像素电极15。所述像素电极15通过所述过孔143电连接到所述像素薄膜晶体管12的源电极123。具体为所述像素电极15覆盖像素定义区141及过孔143内部与源电极123。
请参阅图7，步骤S6，在所述平坦层14上形成支撑层17。具体包括：在 所述平坦层14上形成有机绝缘层，通过图案化构图工艺图案化所述有机绝缘层形成所述支撑层17。本步骤中所述图案化构图工艺图案化所述有机绝缘层形成所述支撑层17中的光罩为半色调掩膜光罩方式，也可以是采用光阻层光罩形成。所述支撑层17覆盖所述像素电极15两侧边界。
需要说明的是，本申请制造方法中是以阵列基板中的一个电路薄膜晶体管11、一个像素薄膜晶体管12对应的结构为例进行说明，阵列基板中的所有电路薄膜晶体管、像素薄膜晶体管及像素电极均可通过本方法实现。
本申请阵列基板制作方法在通过一道光罩工艺形成平坦层及像素定义区，然后再形成支撑层，相较于现有技术通过两道光罩工艺分别制作平坦层的过孔及像素定义区节省了一道光罩，进而节省了加工流程及成本。
以上所述是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。

Claims (11)

  1. 一种阵列基板制作方法，其特征在于，包括，在基板上形成电路薄膜晶体管与像素薄膜晶体管；其中，所述电路薄膜晶体管及像素薄膜晶体管均包括半导体层、栅电极、源电极和漏电极；
    形成覆盖所述电路薄膜晶体管及像素薄膜晶体管的绝缘层及覆盖所述绝缘层的平坦层；
    通过带有半透膜的半色调掩膜图案化所述平坦层，在所述平坦层上形成像素定义区及孔定义区；
    蚀刻所述孔定义区形成与所述像素薄膜晶体的源电极和漏电极中之一连通的过孔；
    在像素定义区上形成电连接到所述像素薄膜晶体管的源电极和漏电极中之一的像素电极；
    在所述平坦层上形成支撑层。
  2. 如权利要求1所述的阵列基板制作方法，其特征在于，所述步骤通过带有半透膜的半色调掩膜图案化所述平坦层，在所述平坦层上形成像素定义区及孔定义区，包括：提供包括遮光区、全透区及半透区的所述半色调掩膜，
    光罩所述半色调掩膜在所述平坦层上定义出所述像素定义区及孔定义区的图案；其中半透区对应位置形成所述像素定义；
    去除半色调掩膜并通过显影在所述平坦层上形成所述像素定义区及孔定义区。
  3. 如权利要求2所述的阵列基板制作方法，其特征在于，所述步骤蚀刻所述孔定义区形成与所述像素薄膜晶体的源电极和漏电极中之一连通的过孔；包括干蚀刻所述孔定义区对应的所述绝缘层，形成贯穿所述绝缘层的所述过孔。
  4. 如权利要求1所述的阵列基板制作方法，其特征在于，所述像素电极由覆盖像素定义区及所述过孔电连接所述像素薄膜晶体管的源和漏电极中之一。
  5. 如权利要求1所述的阵列基板制作方法，其特征在于，所述步骤在所述平坦层上形成覆盖所述像素电极边界的支撑层包括：
    在所述平坦层上形成有机绝缘层，
    通过图案化构图工艺图案化所述有机绝缘层形成所述支撑层。
  6. 如权利要求1所述的阵列基板制作方法，其特征在于，所述步骤在像素定义区上形成电连接到所述像素薄膜晶体管的源电极和漏电极中之一的像素电极，是通过图案化构图工艺图案化形成于所述平坦层及像素定义区内的像素电极材料层构成。
  7. 如权利要求5所述的阵列基板制作方法，其特征在于，所述图案化构图工艺图案化所述有机绝缘层形成所述支撑层中的光罩为半色调掩膜光罩方式。
  8. 如权利要求1所述的阵列基板制作方法，其特征在于，所述步骤在基板上形成电路薄膜晶体管与像素薄膜晶体管；包括：
    在所述基板上定义电路区域和像素区域；
    对应所述电路区域和像素区域分别形成所述电路薄膜晶体管与像素薄膜晶体管；其中，所述电路薄膜晶体管的栅极电连接所述像素薄膜晶体管的源电极与漏电极中的之一。
  9. 如权利要求1所述的阵列基板制作方法，其特征在于，所述像素定义区位正投影部分覆盖所述像素薄膜晶体管。
  10. 如权利要求1所述的阵列基板制作方法，其特征在于，所述支撑层覆盖所述像素电极两侧边界。
  11. 如权利要求1-10任一项所述的阵列基板制作方法，其特征在于，所述在基板上形成的电路薄膜晶体管与像素薄膜晶体管用于控制同一个像素发光，其中，电路薄膜晶体管个数为至少一个和/或像素薄膜晶体管个数为至少一个。
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