WO2018119652A1 - Procédé de fabrication de substrat de matrice - Google Patents

Procédé de fabrication de substrat de matrice Download PDF

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Publication number
WO2018119652A1
WO2018119652A1 PCT/CN2016/112346 CN2016112346W WO2018119652A1 WO 2018119652 A1 WO2018119652 A1 WO 2018119652A1 CN 2016112346 W CN2016112346 W CN 2016112346W WO 2018119652 A1 WO2018119652 A1 WO 2018119652A1
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WO
WIPO (PCT)
Prior art keywords
pixel
thin film
film transistor
layer
array substrate
Prior art date
Application number
PCT/CN2016/112346
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English (en)
Chinese (zh)
Inventor
洪日
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to CN201680044134.0A priority Critical patent/CN108064415A/zh
Priority to PCT/CN2016/112346 priority patent/WO2018119652A1/fr
Publication of WO2018119652A1 publication Critical patent/WO2018119652A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of manufacturing liquid crystal panels, and in particular, to a method for fabricating an array substrate.
  • an oxide semiconductor TFT (Thin Film Transistor) device is fabricated by patterning PNL (planarization) after PV (passivation) is completed.
  • PNL planarization
  • PV passivation
  • PE pixel electrode
  • PDL pixel definition layer
  • the present application provides a method for fabricating an array substrate, which reduces the number of masks of the array substrate and saves production costs.
  • the method for fabricating an array substrate according to the present invention includes: forming a thin film transistor and a pixel thin film transistor on a substrate; wherein the circuit thin film transistor and the pixel thin film transistor each include a semiconductor layer, a gate electrode, a source electrode, and a drain electrode;
  • a support layer is formed on the flat layer.
  • the step of patterning the flat layer by a halftone mask with a semi-permeable film, forming a pixel defining area and a hole defining area on the flat layer including: providing a light shielding area, a full transparent area, and a half The halftone mask of the transmissive region,
  • a mask of the halftone mask defining a pattern of the pixel defining area and the hole defining area on the flat layer; wherein the corresponding position of the semi-permeable area forms the pixel definition;
  • the halftone mask is removed and the pixel definition area and the hole definition area are formed on the flat layer by development.
  • the step of etching the hole defining region to form a via that communicates with one of a source electrode and a drain electrode of the pixel thin film crystal; comprising: dry etching the insulating layer corresponding to the hole defining region to form a through-hole The via of the insulating layer.
  • the pixel electrode is electrically connected to one of a source and a drain electrode of the pixel thin film transistor by covering a pixel defining region and the via hole.
  • step of forming a support layer covering the boundary of the pixel electrode on the flat layer comprises:
  • the support layer is formed by patterning the organic insulating layer by a patterning patterning process.
  • the step of forming a pixel electrode electrically connected to one of the source electrode and the drain electrode of the pixel thin film transistor on the pixel defining region is formed in the flat layer and the pixel defining region by patterning a patterning process
  • the pixel electrode material layer is formed inside.
  • the patterned patterning process patterns the organic insulating layer to form a reticle in the supporting layer as a halftone mask reticle mode.
  • the circuit thin film transistor and the pixel thin film transistor are respectively formed corresponding to the circuit region and the pixel region; wherein a gate of the circuit thin film transistor is electrically connected to one of a source electrode and a drain electrode of the pixel thin film transistor.
  • the pixel definition area orthographic projection part covers the pixel thin film transistor.
  • the support layer covers both sides of the pixel electrode.
  • the circuit thin film transistor and the pixel thin film transistor formed on the substrate are used to control the same pixel to emit light, wherein the number of circuit thin film transistors is at least one and/or the number of pixel thin film transistors is at least one.
  • the method for fabricating the array substrate of the present application forms a flat layer and a pixel defining region through a mask process, and then forms a supporting layer, which saves the via hole and the pixel defining region of the flat layer by the two mask processes in the prior art.
  • a reticle saves processing and cost.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present application.
  • 2 to 7 are schematic cross-sectional views showing respective steps of a method for fabricating an array substrate of the present application.
  • the method for fabricating the array substrate according to the embodiment of the present application for forming the low-temperature polysilicon substrate may be, but not limited to, an OLED liquid crystal display such as a mobile phone, a computer, a display, or an e-reader, which is not specifically limited in the embodiment of the present application.
  • the method for fabricating an array substrate according to the present application includes:
  • step S1 the circuit thin film transistor 11 and the pixel thin film transistor 12 are formed on the substrate 10.
  • the circuit thin film transistors 11 each include a semiconductor layer 111, a gate electrode 112, a source electrode 113, and a drain electrode 114.
  • the pixel thin film transistor 12 includes a semiconductor layer 121, a gate electrode 122, a source electrode 123, and a drain electrode 124.
  • the step includes, in the first step, defining a circuit area and a pixel area (not shown) in the pixel unit on the substrate 10.
  • the circuit thin film transistor 11 and the pixel thin film transistor 12 are respectively formed corresponding to the circuit region and the pixel region; wherein the gate 112 of the circuit thin film transistor 11 is electrically connected to the source electrode 123 of the pixel thin film transistor 12 And one of the drain electrodes 124.
  • the formation of the circuit thin film transistor 11 and the pixel thin film transistor 12 uses a conventional patterning patterning process, such as film formation, exposure, development, etching, etc., and will not be described herein.
  • the circuit thin film transistor 11 and the pixel thin film transistor 12 formed on the substrate 10 are used to control the same pixel, wherein the number of the circuit thin film transistors 11 is at least one and/or the number of the pixel thin film transistors is 12.
  • the circuit thin film transistor 11 is one
  • the pixel thin film transistor 12 is plural (including two or more)
  • the pixel thin film transistor 12 is One or more circuit thin film transistors 11 (including two or more); or a plurality of circuit thin film transistors 11 and pixel thin film transistors 12.
  • the pixel in this embodiment is described by taking only one circuit thin film transistor 11 and one pixel thin film transistor 12 as an example.
  • an insulating layer 13 covering the circuit thin film transistor 11 and the pixel thin film crystal 12 and a flat layer 14 covering the insulating layer 13 are formed.
  • a PV material layer is formed on the circuit thin film transistor 11 and the pixel thin film crystal 12, and the insulating layer 13 is formed by patterning a PV material layer.
  • the flat layer 14 is formed by coating on the insulating layer 13, and the flat layer 14 is planar away from the surface of the substrate 10.
  • step S3 the flat layer 14 is patterned by a halftone mask 20 having a semi-permeable film, and a pixel defining region 141 and a hole defining region 142 are formed on the flat layer 14. Specifically include:
  • the halftone mask 20 including a light shielding area 21, a full transmission area 22, and a semi-transmissive area 23 is provided.
  • the halftone mask 20 defines a pattern of the pixel defining area and the hole defining area on the flat layer 14; wherein the semi-permeable area 23 corresponds to a position to form the pixel definition; and the full transparent area 22 corresponds to a position Hole definition area.
  • the halftone mask is removed and the pixel defining region 141 and the hole defining region 142 are formed on the flat layer 14 by development.
  • the hole defining region 142 penetrates the flat layer 14 and exposes the insulating layer. That is to say, the pixel defining region 141 and the hole defining region 142 are formed by a mask process, which saves a mask process compared to the conventional manufacturing method.
  • the pixel definition area 141 bit orthographic projection partially covers the pixel thin film transistor 12.
  • step S4 the hole defining region 142 is etched to form a via 143 that communicates with one of the source 123 and the drain electrode 124 of the pixel thin film transistor 12.
  • the via hole 143 penetrating the exposed source 123 of the insulating layer 13 is formed by dry etching the insulating layer 13 corresponding to the hole defining region 142.
  • a pixel electrode 15 electrically connected to one of the source electrode 123 and the drain electrode 124 of the pixel thin film transistor 12 is formed on the pixel defining region 141; specifically, by a patterning process
  • the pixel electrode material layer patterned in the flat layer 14 and the pixel defining region 141 constitutes the pixel electrode 15.
  • the pixel electrode 15 is electrically connected to the source electrode 123 of the pixel thin film transistor 12 through the via hole 143.
  • the pixel electrode 15 covers the pixel defining region 141 and the inside of the via 143 and the source electrode 123.
  • a support layer 17 is formed on the flat layer 14. Specifically include: An organic insulating layer is formed on the flat layer 14, and the support layer 17 is formed by patterning the organic insulating layer by a patterning patterning process.
  • the patterning process in the step of patterning the organic insulating layer to form the photomask in the supporting layer 17 is a halftone mask mask, or may be formed by using a photoresist layer mask.
  • the support layer 17 covers both side boundaries of the pixel electrode 15.
  • the method for fabricating the array substrate of the present application forms a flat layer and a pixel defining region through a mask process, and then forms a supporting layer, which saves the via hole and the pixel defining region of the flat layer by the two mask processes in the prior art.
  • a reticle saves processing and cost.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un substrat de matrice. Ledit procédé comprend : la formation d'un transistor en couches minces de circuit (11) et d'un transistor en couches minces de pixel (12) sur un substrat (10) ; la formation d'une couche isolante (13) qui recouvre le transistor en couches minces de circuit (11) et le transistor en couches minces de pixel (12) et d'une couche plate (14) qui recouvre la couche isolante (13) ; la formation de motifs sur la couche plate (14) au moyen d'un masque atténué ("en demi-ton") (20) qui comporte un film semi-transparent, et la formation d'une région de définition de pixel (141) et d'une région de définition de trou (142) sur la couche plate (14) ; la gravure de la région de définition de trou (142) pour former un trou d'interconnexion (143) en communication avec une électrode de source (123) ou une électrode de drain (124) du transistor en couches minces de pixel (12) ; la formation, sur la région de définition de pixel (141), d'une électrode de pixel (15) connectée électriquement à l'électrode de source (123) ou l'électrode de drain (124) du transistor en couches minces de pixel (12) ; et la formation d'une couche de support (17) sur la couche plate (14).
PCT/CN2016/112346 2016-12-27 2016-12-27 Procédé de fabrication de substrat de matrice WO2018119652A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201680044134.0A CN108064415A (zh) 2016-12-27 2016-12-27 阵列基板制作方法
PCT/CN2016/112346 WO2018119652A1 (fr) 2016-12-27 2016-12-27 Procédé de fabrication de substrat de matrice

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/112346 WO2018119652A1 (fr) 2016-12-27 2016-12-27 Procédé de fabrication de substrat de matrice

Publications (1)

Publication Number Publication Date
WO2018119652A1 true WO2018119652A1 (fr) 2018-07-05

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CN (1) CN108064415A (fr)
WO (1) WO2018119652A1 (fr)

Citations (5)

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Publication number Priority date Publication date Assignee Title
KR20040060598A (ko) * 2002-12-30 2004-07-06 엘지.필립스 엘시디 주식회사 액정 표시 장치용 어레이 기판의 제조 방법
US20090085040A1 (en) * 2004-05-27 2009-04-02 Byung Chul Ahn Liquid crystal display device and fabricating method thereof
CN101556417A (zh) * 2008-04-11 2009-10-14 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板结构及其制造方法
CN102543867A (zh) * 2012-03-08 2012-07-04 南京中电熊猫液晶显示科技有限公司 一种金属氧化物薄膜晶体管阵列基板的制造方法
CN105068373A (zh) * 2015-09-11 2015-11-18 武汉华星光电技术有限公司 Tft基板结构的制作方法

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KR20140108025A (ko) * 2013-02-28 2014-09-05 삼성디스플레이 주식회사 유기발광 디스플레이 장치 및 그 제조방법
CN103151305B (zh) * 2013-02-28 2015-06-03 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板、制备方法以及显示装置
CN103984147A (zh) * 2014-05-04 2014-08-13 深圳市华星光电技术有限公司 阵列面板及其制作方法
CN104538357B (zh) * 2015-01-13 2018-05-01 合肥京东方光电科技有限公司 制作阵列基板的方法和阵列基板
CN105390505B (zh) * 2015-11-05 2018-09-18 昆山龙腾光电有限公司 薄膜晶体管阵列基板及其制作方法
CN105470282B (zh) * 2015-11-20 2020-03-31 Tcl集团股份有限公司 一种无像素bank的TFT-OLED及制备方法
CN105336763B (zh) * 2015-11-26 2019-08-02 Tcl集团股份有限公司 一种发光显示器及其制备方法
CN105549269A (zh) * 2016-02-18 2016-05-04 深圳市华星光电技术有限公司 配向膜厚度均一性的优化方法及液晶显示面板
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040060598A (ko) * 2002-12-30 2004-07-06 엘지.필립스 엘시디 주식회사 액정 표시 장치용 어레이 기판의 제조 방법
US20090085040A1 (en) * 2004-05-27 2009-04-02 Byung Chul Ahn Liquid crystal display device and fabricating method thereof
CN101556417A (zh) * 2008-04-11 2009-10-14 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板结构及其制造方法
CN102543867A (zh) * 2012-03-08 2012-07-04 南京中电熊猫液晶显示科技有限公司 一种金属氧化物薄膜晶体管阵列基板的制造方法
CN105068373A (zh) * 2015-09-11 2015-11-18 武汉华星光电技术有限公司 Tft基板结构的制作方法

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