WO2018113346A1 - 接口防护电路及设备接口 - Google Patents

接口防护电路及设备接口 Download PDF

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Publication number
WO2018113346A1
WO2018113346A1 PCT/CN2017/100934 CN2017100934W WO2018113346A1 WO 2018113346 A1 WO2018113346 A1 WO 2018113346A1 CN 2017100934 W CN2017100934 W CN 2017100934W WO 2018113346 A1 WO2018113346 A1 WO 2018113346A1
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WIPO (PCT)
Prior art keywords
interface
protection circuit
tvs tube
capacitor
resistor
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PCT/CN2017/100934
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English (en)
French (fr)
Inventor
昝超
唐启明
周广荣
晏君
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华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP17883231.7A priority Critical patent/EP3471230A4/en
Priority to KR1020197002212A priority patent/KR20190022712A/ko
Priority to JP2019527944A priority patent/JP6974462B2/ja
Publication of WO2018113346A1 publication Critical patent/WO2018113346A1/zh
Priority to US16/360,343 priority patent/US11509134B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/20—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage
    • H02H3/202—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage for dc systems
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/044—Physical layout, materials not provided for elsewhere

Definitions

  • the present invention relates to the field of circuit technologies, and in particular, to an interface protection circuit and a device interface.
  • connection port can be generally set in each device, and a connection port of the two devices is connected through the connection component to realize a connection between the two devices, wherein the connection component can be a connection line.
  • the connecting member may be a component that connects the TV to the set top box, a component that connects the computer to the display, and the like.
  • the transmission rate of data signals between devices is getting higher and higher.
  • the transmission rate of the data signal between the devices is high, when the device is connected through the connection port, a large surge occurs in the circuit, and the generated surge may cause damage to the interface chip in the device.
  • a Transient Voltage Suppressor (TVS) is usually disposed in the device, and the interface chip is protected by the TVS tube.
  • the power of the TVS tube is generally increased.
  • the power of the TVS tube is high, the TVS tube generates a high parasitic capacitance, and the parasitic capacitance adversely affects the quality of the data signal transmitted between the devices, resulting in poor quality of the data signal transmitted between the devices.
  • the embodiment of the invention provides an interface protection circuit, which improves the protection capability of the interface chip under the premise of ensuring the quality of the data signal transmitted between the devices.
  • an embodiment of the present invention provides an interface protection circuit including a capacitor and a TVS tube.
  • the first end of the capacitor is connected to the connection port, the second end of the capacitor is respectively connected to the first end of the TVS tube and the interface chip, and the second end of the TVS tube is grounded.
  • the capacitor can first filter out the DC portion of the surge, thereby reducing the energy of the surge.
  • the protection capability of the interface chip can be improved without increasing the power of the interface protection circuit, thereby improving the protection capability of the interface chip under the premise of ensuring the quality of the data signal transmitted between the devices.
  • the capacitor can reduce the energy of the surge, the energy of the surge flowing to the TVS tube is reduced, thereby protecting the TVS tube and improving the reliability of the interface protection circuit.
  • the interface protection circuit further includes a resistor, and the resistor is connected in series with the capacitor and the interface chip.
  • a resistor may be disposed between the first end of the TVS tube and the interface chip.
  • the resistor It is connected in series with the interface chip so that the resistor can be divided with the interface chip; when a large surge occurs in the circuit, the resistor can reduce the surge voltage across the interface chip, thereby reducing the impact of the surge on the interface chip.
  • a resistor can be disposed between the connection port and the first end of the capacitor.
  • the resistor and the capacitor can reduce the voltage generated by the surge at both ends of the TVS tube, thereby improving the protection effect on the TVS tube, thereby improving the reliability of the protection circuit. Sex.
  • a resistor may be disposed between the second end of the capacitor and the first end of the TVS tube.
  • the resistor and the capacitor can reduce the voltage generated by the surge at both ends of the TVS tube, thereby improving the protection effect on the TVS tube, thereby improving the reliability of the protection circuit. Sex.
  • the size of the capacitor is inversely related to the frequency of the data signal transmitted by the connection port.
  • the capacitance of the capacitor can be greater than 0.1 nanofarads and less than 1 microfarad.
  • the resistance of the resistor is between the first resistance value and the second resistance value, and the first resistance value is greater than the second resistance value.
  • the first resistance is greater than 1 ohm and the second resistance is less than 200 ohms.
  • the frequency of the data signal transmitted in the circuit is greater than 500 MHz.
  • the frequency of the data signal is large, most of the energy of the data signal is an AC component, so that in the process of stably transmitting the data signal to the interface chip at the connection port, the influence of the capacitance on the data signal can be made small.
  • the clamping voltage of the TVS tube is greater than the maximum voltage of the data signal transmitted by the connection port.
  • the TVS tube can be a one-way TVS tube or a two-way TVS tube.
  • the TVS tube is a unidirectional TVS tube; correspondingly, the negative pole of the TVS tube is connected to the connection port.
  • the embodiment of the present invention further provides a device interface, where the device interface includes an interface chip and the interface protection circuit of any one of the first aspects.
  • the interface protection circuit and the device interface provided by the embodiment of the invention are provided with a capacitor and a TVS tube in the interface protection circuit, and the capacitor is located between the connection port and the TVS tube.
  • the protection capability of the interface chip can be improved without increasing the power of the interface protection circuit, thereby improving the protection capability of the interface chip under the premise of ensuring the quality of the data signal transmitted between the devices.
  • the capacitor can reduce the energy of the surge, the energy of the surge flowing to the TVS tube is reduced, thereby protecting the TVS tube and improving the reliability of the interface protection circuit.
  • FIG. 1 is a schematic diagram of an application scenario of an interface protection circuit provided by the present invention.
  • FIG. 2 is a schematic structural view 1 of an interface protection circuit provided by the present invention.
  • FIG. 3 is a schematic structural view 2 of an interface protection circuit provided by the present invention.
  • FIG. 4 is a schematic structural view 3 of an interface protection circuit provided by the present invention.
  • FIG. 5 is a schematic structural diagram 4 of an interface protection circuit provided by the present invention.
  • FIG. 6 is a schematic structural diagram 5 of an interface protection circuit provided by the present invention.
  • FIG. 7 is a schematic structural diagram of a device interface provided by the present invention.
  • FIG. 1 is a schematic diagram of an application scenario of an interface protection circuit according to the present invention.
  • the first device 101, the second device 102, and the connection component 103 are included.
  • the first device 101 is provided with a first interface chip, a first interface protection circuit, and a connection port A.
  • the second device 102 is provided with a second interface chip, a second interface protection circuit, and a connection port D.
  • the connection member 103 is provided with a connection port B and a connection port C.
  • the first device 101 can be a computer, and correspondingly, the second device 102 can be a display.
  • the first device 101 can be a television.
  • the second device 102 can be a set top box.
  • the connecting component 103 can be an integrated device with the first device 101 or the second device 102.
  • the connecting component 103 and the first device 101 can be removable disks.
  • the connecting member 103 may be a connecting line or the like.
  • the first device 101 and the second device 102 can be connected by the connection unit 103.
  • the connection port A of the first device 101 and the connection port B of the connection component 103 may be connected, and the connection port D and the connection component of the second device 102 may be connected.
  • the connection port C of 103 is connected.
  • the first device 101 and the second device 102 may pass through the first interface chip, the first protection circuit, the connection component 103, the second interface protection circuit, and the The two interface chips implement communication.
  • the second interface protection circuit can protect the second interface chip.
  • the first interface protection circuit can An interface chip is used for protection.
  • FIG. 2 is a schematic structural diagram 1 of an interface protection circuit provided by the present invention.
  • the interface protection circuit is disposed in the protected device.
  • the circuit can include a capacitor 201 and a TVS tube 202.
  • the first end of the capacitor 201 is connected to the connection port of the protected device, and the second end of the capacitor 201 is respectively connected to the first end of the TVS tube 202 and the interface chip of the protected device; the second end of the TVS tube 202 is grounded.
  • the TVS tube 202 in this application may be a one-way TVS tube or a two-way TVS tube.
  • the TVS tube 202 shown in FIG. 2 is a unidirectional TVS tube.
  • the TVS tube 202 is a unidirectional TVS tube, the negative pole of the TVS tube 202 is connected to the connection port.
  • the TVS tube 202 is a bidirectional TVS tube, any one of the TVS tubes 202 can be connected to the connection port.
  • the size of the capacitor 201 is related to the frequency of the data signal transmitted by the connection port. The higher the frequency of the data signal, the smaller the capacitance of the capacitor 201.
  • the capacitance of the capacitor 201 can be 0.1 nanofarad to 1 microfarad, in this way, not only can the capacitor effectively filter out the DC part of the surge, but also ensure that the capacitance has less influence on the data signal transmitted by the connection port.
  • the size of the capacitor 201 can be matched with the frequency of the data signal transmitted by the connection port. The rate is inverse.
  • the data signal transmitted by the connection port may be sent by the connection port to the interface chip, or may be sent by the interface chip to the connection port.
  • the clamping voltage of the TVS tube 202 is greater than the maximum voltage of the data signal transmitted by the connection port.
  • the impedance of the TVS tube 202 becomes instantaneously small, causing the TVS tube 202 to be turned on.
  • the impedance of the TVS tube 202 instantaneously becomes large, rendering the TVS tube 202 non-conductive.
  • the protected device may generate large surges in various scenarios, for example, when the protected device is connected with other devices, when the protected circuit and other devices start to transmit data signals, and the like.
  • the surge first passes through the capacitor 201, and the capacitor 201 can filter out the DC portion of the surge, thereby reducing the energy of the surge.
  • the capacitor 201 filters out the DC portion of the surge, the energy of the surge is still high, so that the voltage generated by the surge at both ends of the TVS tube is greater than the clamp voltage of the TVS tube 202, thus causing the impedance of the TVS tube 202 to be instantaneous. It becomes very small, making the TVS tube 202 conductive.
  • the surge flows to the TVS tube 202 without flowing to the interface chip.
  • the surge is grounded through the TVS tube 202, causing most of the energy of the surge to be grounded so that the TVS tube 202 clamps the voltage across the TVS tube 202 to a lower voltage. Since the interface chip and the TVS tube 202 are connected in parallel, the voltage across the interface chip is equal to the voltage across the TVS tube.
  • the surge in the protected device disappears. Since the frequency of the data signal transmitted by the connection port is high, for example, the frequency of the data signal is usually greater than 500 MHz, so that most of the energy of the data signal is an AC component, and when the AC component passes through the capacitor 201, the capacitor 201 has no filtering effect on the AC component. This allows the data signal to pass through the capacitor 202 more completely. Since the maximum voltage of the data signal is smaller than the clamp voltage of the TVS tube 202, the impedance of the TVS tube is instantaneously increased, so that the TVS is in a non-conducting state.
  • the interface protection circuit provided by the embodiment of the invention has a capacitor and a TVS tube disposed in the interface protection circuit, and the capacitor is located between the connection port and the TVS tube.
  • the protection capability of the interface chip can be improved without increasing the power of the interface protection circuit, thereby improving the protection capability of the interface chip under the premise of ensuring the quality of the data signal transmitted between the devices.
  • the capacitor can reduce the energy of the surge, the energy of the surge flowing to the TVS tube is reduced, thereby protecting the TVS tube and improving the reliability of the interface protection circuit.
  • a resistor may be disposed in the interface protection circuit, and the resistor is connected in series with the capacitor and the interface chip. In this way, the resistor can be divided with the interface chip, thereby reducing the influence of the surge on the interface chip, and further enhancing the protection effect of the interface protection circuit on the interface chip.
  • the interface protection circuit has different protection effects on the interface chip.
  • the interface protection circuit including the resistor will be described in detail in conjunction with the embodiment shown in FIGS. 3 to 5.
  • FIG. 3 is a schematic structural diagram 2 of an interface protection circuit provided by the present invention.
  • the interface protection circuit further includes a resistor 203 disposed between the first end of the TVS tube 202 and the interface chip.
  • the resistance of the resistor 203 is too small, the protection effect of the resistor on the interface chip is not obvious.
  • the resistance of the resistor 203 is too large, the resistance of the resistor 203 to the data signal transmitted by the connection port is large.
  • electric The resistance of the resistor 203 is generally between the first resistance value and the second resistance value, and the first resistance value is greater than the second resistance value.
  • the first resistance is greater than 1 ohm and the second resistance is less than 200 ohms.
  • the resistance of the resistor 203 may be 50 ohms.
  • the capacitor 201 When a large surge occurs in the protected circuit, the capacitor 201 first filters out the DC portion of the surge to reduce the energy of the surge.
  • the surge through capacitor 201 is grounded through the turned-on TVS tube 202 such that the TVS tube 202 clamps the voltage across the TVS tube 202 to a low voltage. Since the interface chip and the resistor 203 are connected in series, the sum of the voltage across the interface chip and the voltage across the resistor 203 is equal to the voltage across the TVS tube 202. Since the resistor 203 can be divided with the interface chip, the surge voltage across the interface chip can be reduced, and the influence of the surge on the interface chip can be further reduced.
  • the process of processing the data information by the capacitor 201 and the TVS tube 202 can refer to the embodiment shown in FIG. 2, after the data signal passes through the capacitor 201, since the TVS tube is not conductive. Therefore, the data signal passing through the capacitor 201 passes through the resistor 203 and then flows to the interface chip. Since the resistance of the resistor is less than the second resistance, the effect of the resistor on the data signal is small.
  • the resistor 203 can be divided with the interface chip when the data signal transmitted by the connection port generates a large surge. To reduce the surge voltage across the interface chip, thereby reducing the impact of surge on the interface chip. In the process of stable operation of the protected circuit, since the resistance of the resistor is less than the second resistance, the influence of the resistor on the data signal is small.
  • FIG. 4 is a schematic structural diagram 3 of an interface protection circuit provided by the present invention. On the basis of the embodiment shown in Fig. 2, please refer to Fig. 4.
  • the interface protection circuit further includes a resistor 203 disposed between the connection port and the first end of the capacitor 201.
  • the surge When a large surge occurs in the protected device, the surge is grounded through the resistor 203, the capacitor 201, and the TVS tube 202 (see the embodiment shown in FIG. 2 for specific reasons). Before the surge flows to the TVS tube 202, the surge first passes through the resistor 203, thereby reducing the energy of the surge flowing to the capacitor 201. The capacitor 201 further reduces the energy of the surge flowing to the TVS tube 202 by filtering out the DC portion of the surge.
  • the protection capability of the interface chip can be improved without increasing the power of the TVS tube, thereby improving the protection capability of the interface chip under the premise of ensuring the quality of the data signal transmitted between the devices. In this way, both the resistor 203 and the capacitor 202 can better protect the TVS tube, further improving the reliability of the protection circuit.
  • the processing of the data information by the capacitor 201 and the TVS tube 202 can refer to the embodiment shown in FIG. 2.
  • the data signal transmitted by the connection port flows through the resistor 203 and flows to the interface chip. Since the resistance of the resistor is less than the second resistance value, the resistance has less influence on the data signal.
  • resistor 203 is disposed between the connection port and the first end of capacitor 201.
  • the resistor 203 and the capacitor 201 can reduce the energy of the surge flowing to the TVS tube 202, improve the protection of the TVS tube, and thereby improve the reliability of the protection circuit.
  • the resistance of the resistor is less than the second resistance, the influence of the resistor on the data signal is small.
  • FIG. 5 is a schematic structural diagram 4 of an interface protection circuit provided by the present invention. On the basis of the embodiment shown in Fig. 2, please refer to Fig. 5.
  • the interface protection circuit further includes a resistor 203, and the resistor 203 is disposed at the second end of the capacitor and the TVS tube Between one end.
  • two TVS tubes may be disposed in the interface protection circuit.
  • a TVS tube can be disposed between the resistor 203 and the interface chip.
  • FIG. 6 refers to the embodiment shown in FIG. 6.
  • FIG. 6 is a schematic structural diagram 5 of an interface protection circuit provided by the present invention.
  • the interface protection circuit further includes a TVS tube 204.
  • One end of the TVS tube 204 is disposed between the resistor 203 and the interface chip, and the other end of the TVS tube 204 is grounded.
  • the characteristics of the TVS tube 204 may be the same as those of the TVS tube 203.
  • the TVS tube 204 can further reduce the surge voltage across the interface chip, thereby improving the protection of the interface chip. Further, when one TVS tube fails, another TVS tube can also protect the interface chip and improve the reliability of the interface chip protection.
  • the position of the TVS tube in the interface protection circuit and the number of the TVS tube in the interface protection circuit can be set according to actual needs, which is not specifically limited in the embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a device interface provided by the present invention.
  • the device interface includes an interface chip 701 and an interface protection circuit 702 shown in any of the embodiments of FIG. 2-6.
  • the device interface described in the embodiment of FIG. 7 may be disposed in a communication device, and the communication device may be a computer, a television, a display screen, a set top box, or the like.
  • the surge when a surge occurs in the circuit, the surge first passes through the interface protection circuit 702 and then flows to the interface chip 701, so that the interface protection circuit 702 can protect the interface chip 701.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Protection Of Static Devices (AREA)

Abstract

一种接口防护电路及设备接口，该接口防护电路包括：电容（201）和瞬变电压抑制器TVS管（202）。电容的第一端与连接端口连接，电容的第二端分别与TVS管的第一端及接口芯片连接；TVS管的第二端接地。在对接口芯片进行相同保护的前提下，提高了设备间传输的数据信号的质量。

Description

接口防护电路及设备接口
本申请要求于2016年12月23日提交中国专利局、申请号为201611207683.3、发明名称为“接口防护电路及设备接口”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电路技术领域，尤其涉及一种接口防护电路及设备接口。
背景技术
为了便于两个设备间的通信，通常可以在各设备中设置连接端口，并通过连接部件连接两个设备的连接端口，以实现两个设备之间的连接，其中，连接部件可以为连接线。连接部件可以为实现电视与机顶盒连接的部件、电脑与显示器连接的部件等。
随着电子技术的不断发展，设备之间的数据信号的传输速率越来越高。当设备之间的数据信号的传输速率较高时，在通过连接端口对设备进行连接时，电路中会产生较大的浪涌，产生的浪涌可能对设备中的接口芯片造成损害。在现有技术中，为了减少浪涌对接口芯片的损害，通常在设备中设置瞬变电压抑制器(Transient Voltage Suppressor，简称TVS)，通过TVS管对接口芯片进行保护。目前，为了提高TVS管对接口芯片的防护能力，通常提高TVS管的功率。当TVS管的功率较高时，TVS管则产生较高的寄生电容，寄生电容对设备间传输的数据信号的质量造成不良影响，导致设备间传输的数据信号的质量较差。
发明内容
本发明实施例提供一种接口防护电路，在保证设备间传输的数据信号的质量的前提下，提升了对接口芯片的防护能力。
第一方面，本发明实施例提供一种接口防护电路，该接口防护电路包括电容和TVS管。电容的第一端与连接端口连接，电容的第二端分别与TVS管的第一端及接口芯片连接，TVS管的第二端接地。
当电路中产生较大浪涌时，电容可以先滤除浪涌中的直流部分，进而降低浪涌的能量。在上述过程中，无需提高接口防护电路的功率即可提升对接口芯片的防护能力，进而实现在保证设备间传输的数据信号的质量的前提下，提升了对接口芯片的防护能力。进一步的，由于电容可以降低浪涌的能量，使得流向TVS管的浪涌的能量减少，进而可以对TVS管起到保护作用，提高了接口防护电路的可靠性。
在一种可能的实施方式中，接口防护电路还包括电阻，电阻与电容和接口芯片串联。
可选的，电阻可以设置于TVS管的第一端与接口芯片之间。在该种实现方式中，电阻 与接口芯片串联，以使电阻可以与接口芯片分压；当电路中产生较大的浪涌时，电阻可以降低接口芯片两端的浪涌电压，进而降低浪涌对接口芯片的影响。
可选的，电阻可以设置于连接端口与电容第一端之间。在该种可行的实现方式中，当电路中产生较大的浪涌时，电阻和电容可以降低TVS管两端浪涌产生的电压，提高了对TVS管的保护作用，进而提高防护电路的可靠性。
可选的，电阻可以设置于电容的第二端与TVS管的第一端之间。在该种可行的实现方式中，当电路中产生较大的浪涌时，电阻和电容可以降低TVS管两端浪涌产生的电压，提高了对TVS管的保护作用，进而提高防护电路的可靠性。
在另一种可能的实施方式中，电容的大小与连接端口传输的数据信号的频率成反向关系。可选的，电容的电容值可以大于0.1纳法，且小于1微法。通过设置合理的电容值，不但可以使得电容能够有效滤除浪涌中的直流部分，还可以保证电容对连接端口传输的数据信号的影响较小。
在另一种可能的实施方式中，电阻的阻值在第一阻值和第二阻值之间，第一阻值大于第二阻值。可选的，第一阻值大于1欧姆，第二阻值小于200欧姆。通过设置合理的电阻阻值，可以使得电阻既可以起到对接口芯片的防护作用，又可以使得电阻对连接端口传输的数据信号的影响较小。
在另一种可能的实施方式中，电路中传输的数据信号的频率大于500MHz。当数据信号的频率较大时，数据信号的大部分能量为交流分量，这样，在连接端口稳定向接口芯片发送数据信号的过程中，可以使得电容对数据信号的影响较小。
在另一种可能的实施方式中，TVS管的钳位电压大于连接端口传输的数据信号的最大电压。可选的，TVS管可以为单向TVS管，也可以为双向TVS管。当TVS管为单向TVS管；相应的，TVS管的负极与连接端口连接。
第二方面，本发明实施例还提供一种设备接口，该设备接口包括接口芯片和第一方面任一项的接口防护电路。
本发明实施例提供的接口防护电路及设备接口，在接口防护电路中设置有电容和TVS管，且电容位于连接端口与TVS管之间。在上述过程中，无需提高接口防护电路的功率即可提升对接口芯片的防护能力，进而实现在保证设备间传输的数据信号的质量的前提下，提升了对接口芯片的防护能力。进一步的，由于电容可以降低浪涌的能量，使得流向TVS管的浪涌的能量减少，进而可以对TVS管起到保护作用，提高了接口防护电路的可靠性。
附图说明
图1为本发明提供的接口防护电路的应用场景示意图；
图2为本发明提供的接口防护电路的结构示意图一；
图3为本发明提供的接口防护电路的结构示意图二；
图4为本发明提供的接口防护电路的结构示意图三；
图5为本发明提供的接口防护电路的结构示意图四；
图6为本发明提供的接口防护电路的结构示意图五；
图7为本发明提供的设备接口的结构示意图。
具体实施方式
图1为本发明提供的接口防护电路的应用场景示意图，请参见图1，包括第一设备101、第二设备102、及连接部件103。第一设备101中设置有第一接口芯片、第一接口防护电路和连接端口A。第二设备102中设置有第二接口芯片、第二接口防护电路和连接端口D。连接部件103中设置有连接端口B和连接端口C。可选的，第一设备101可以为电脑，相应的，第二设备102可以为显示器。可选的，第一设备101可以为电视，相应的，第二设备102可以为机顶盒。当然，连接部件103可以和第一设备101或第二设备102为一体设备，当连接部件103和第一设备101为一体设备时，连接部件103和第一设备101可以为可移动磁盘。可选的，连接部件103可以为连接线等。
第一设备101和第二设备102可以通过连接部件103实现连接。当需要实现第一设备101和第二设备102之间的连接时，可以将第一设备101的连接端口A和连接部件103的连接端口B连接，将第二设备102的连接端口D和连接部件103的连接端口C连接。
在第一设备101和第二设备102通过连接部件103实现连接之后，第一设备101和第二设备102可以通过第一接口芯片、第一防护电路、连接部件103、第二接口防护电路及第二接口芯片实现通信。在第一设备101向第二设备102发送数据时，第二接口防护电路可以对第二接口芯片进行保护，在第二设备102向第一设备101发送数据时，第一接口防护电路可以对第一接口芯片进行保护。
还需要说明的是，每一个设备中的接口防护电路的结构类似。下面，以任意一个设备中的接口防护电路的结构为例，通过具体实施例，对本申请所示的接口防护电路进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。
图2为本发明提供的接口防护电路的结构示意图一。该接口防护电路设置在被保护设备中。请参见图2，该电路可以包括电容201和TVS管202。其中，电容201的第一端与被保护设备的连接端口连接，电容201的第二端分别与TVS管202的第一端及被保护设备的接口芯片连接；TVS管202的第二端接地。
可选的，本申请中的TVS管202可以为单向TVS管，也可以为双向TVS管。需要说明的是，图2中所示的TVS管202为单向TVS管，当TVS管202为单向TVS管时，TVS管202的负极与连接端口连接。当TVS管202为双向TVS管时，TVS管202的任意一极均可以与连接端口连接。
可选的，电容201的大小与连接端口传输的数据信号的频率有关，数据信号的频率越高，电容201的容值可以越小，可选的，电容201的电容值可以在0.1纳法至1微法之间，这样，不但可以使得电容能够有效滤除浪涌中的直流部分，还可以保证电容对连接端口传输的数据信号的影响较小。可选的，电容201的大小可以与连接端口传输的数据信号的频 率成反向关系。可选的，连接端口传输的数据信号可能是连接端口发送至接口芯片的，也可能是接口芯片发送至连接端口的。
在本申请中，TVS管202的钳位电压大于连接端口传输的数据信号的最大电压。其中，当TVS管202两端的电压大于钳位电压时，TVS管202的阻抗瞬间变小，使得TVS管202导通。当TVS管202两端的电压小于钳位电压时，TVS管202的阻抗瞬间变大，使得TVS管202不导通。
下面，对图2实施例所示的接口防护电路的工作过程进行详细说明。
在实际应用过程中，被保护设备在多种场景下都可能产生较大浪涌，例如，在被保护设备和其它设备连接时、在被保护电路和其它设备开始传输数据信号时等。当被保护设备中产生较大的浪涌时，浪涌先经过电容201，电容201可以滤除浪涌中直流部分，进而降低浪涌的能量。在电容201滤除浪涌中的直流部分之后，浪涌的能量仍然较高，使得浪涌在TVS管两端产生的电压大于TVS管202的钳位电压，因此，使得TVS管202的阻抗瞬间变的非常小，使得TVS管202导通。由于TVS管202和接口芯片并联，且TVS管202的阻抗非常小，使得浪涌流向TVS管202，而不流向接口芯片。在浪涌流向TVS管之后，浪涌通过TVS管202接地，使得浪涌的大部分能量接地，以使TVS管202将TVS管202两端的电压钳制到一个较低的电压。由于接口芯片和TVS管202并联，因此，接口芯片两端的电压等于TVS管两端的电压。
在被保护电路稳定工作的过程中，被保护设备中的浪涌消失。由于连接端口传输的数据信号的频率较高，例如，数据信号的频率通常大于500MHz，使得数据信号的大部分能量为交流分量，在交流分量经过电容201时，电容201对交流分量没有过滤作用，使得数据信号可以较完整的通过电容202。由于数据信号的最大电压小于TVS管202的钳位电压，因此，TVS管的阻抗瞬间变大，使得TVS处于不导通状态。
本发明实施例提供的接口防护电路，在接口防护电路中设置有电容和TVS管，且电容位于连接端口与TVS管之间。在上述过程中，无需提高接口防护电路的功率即可提升对接口芯片的防护能力，进而实现在保证设备间传输的数据信号的质量的前提下，提升了对接口芯片的防护能力。进一步的，由于电容可以降低浪涌的能量，使得流向TVS管的浪涌的能量减少，进而可以对TVS管起到保护作用，提高了接口防护电路的可靠性。
在图2所示实施例的基础上，可选的，还可以在接口防护电路中设置电阻，并将电阻与电容和接口芯片串联。这样，电阻可以和接口芯片进行分压，进而降低浪涌对接口芯片的影响，进一步增强了接口防护电路对接口芯片的防护作用。
在实际应用过程中，当电阻在接口防护电路中的设置位置不同时，接口防护电路对接口芯片的防护作用也不相同。下面，结合图3-图5所示的实施例，对包括电阻的接口防护电路进行详细说明。
图3为本发明提供的接口防护电路的结构示意图二。在图2所示实施例的基础上，请参见图3。接口防护电路中还包括电阻203，电阻203设置于TVS管202的第一端与接口芯片之间。
在实际应用过程中，当电阻203的阻值过小时，电阻对接口芯片的防护作用不明显。当电阻203的阻值过大时，电阻203对连接端口传输的数据信号的干扰较大。可选的，电 阻203的阻值通常在第一阻值和第二阻值之间，第一阻值大于第二阻值。可选的，第一阻值大于1欧姆，第二阻值小于200欧姆。可选的，电阻203的阻值可以为50欧姆。
下面，对图3实施例所示的接口防护电路的工作过程进行详细说明。
当被保护电路中产生较大的浪涌时，电容201先滤除浪涌的直流部分，以降低浪涌的能量。经过电容201的浪涌经过导通的TVS管202接地，以使TVS管202将TVS管202两端的电压钳制到一个低电压。由于接口芯片和电阻203串联，因此，接口芯片两端的电压和电阻203两端的电压之和等于TVS管202两端的电压。由于电阻203可以与接口芯片分压，因此，可以降低接口芯片两端的浪涌电压，进一步降低浪涌对接口芯片的影响。
在连接端口稳定向接口芯片发送数据信号的过程中，电容201和TVS管202对数据信息的处理过程可以参考图2所示的实施例，在数据信号经过电容201之后，由于TVS管不导通，因此，经过电容201的数据信号经过电阻203之后流向接口芯片。由于电阻的阻值小于第二阻值，因此，电阻对数据信号的影响较小。
在图3所示的实施例中，通过将电阻203设置在TVS管202和接口芯片之间，这样，当连接端口发送的数据信号产生较大的浪涌时，电阻203可以与接口芯片分压，以降低接口芯片两端的浪涌电压，进而降低浪涌对接口芯片的影响。在被保护电路稳定工作的过程中，由于电阻的阻值小于第二阻值，使得电阻对数据信号的影响较小。
图4为本发明提供的接口防护电路的结构示意图三。在图2所示实施例的基础上，请参见图4。接口防护电路中还包括电阻203，电阻203设置于连接端口与电容201第一端之间。
需要说明的是，图4实施例中所示的电阻的特性与图3实施例所示的电阻的特性类似，此处不再进行赘述。
下面，对图4实施例所示的接口防护电路的工作过程进行详细说明。
当被保护设备中产生较大的浪涌时，浪涌会经过电阻203、电容201及TVS管202接地(具体原因可参见图2所示的实施例)。在浪涌流向TVS管202之前，浪涌先经过电阻203，进而降低流向电容201的浪涌的能量。电容201通过滤除浪涌中的直流部分，进一步降低流向TVS管202的浪涌的能量。在上述过程中，无需提高TVS管的功率即可提升对接口芯片的防护能力，进而实现在保证设备间传输的数据信号的质量的前提下，提升了对接口芯片的防护能力。这样，电阻203和电容202均可以对TVS管起到更好的保护作用，进一步提高防护电路的可靠性。
在被保护电路稳定工作的过程中，电容201和TVS管202对数据信息的处理过程可以参考图2所示的实施例。具体的，连接端口传输的数据信号经过电阻203之后流向接口芯片，由于电阻的阻值小于第二阻值，因此，电阻对数据信号的影响较小。
在图4所示的实施例中，通过将电阻203设置在连接端口与电容201第一端之间。这样，当被保护设备中产生较大的浪涌时，电阻203和电容201可以降低流向TVS管202的浪涌的能量，提高了对TVS管的保护作用，进而提高防护电路的可靠性。在被保护电路稳定工作的过程中，由于电阻的阻值小于第二阻值，使得电阻对数据信号的影响较小。
图5为本发明提供的接口防护电路的结构示意图四。在图2所示实施例的基础上，请参见图5。接口防护电路中还包括电阻203，电阻203设置于电容的第二端与TVS管的第 一端之间。
需要说明的是，图5实施例中所示的电阻的特性与图3实施例所示的电阻的特性类似，此处不再进行赘述。
还需要说明的是，图5实施例所示的接口防护电路的工作过程及和达到的有益效果可以参见图4所示的实施例，此处不再进行赘述。
在上述任意一个实施例的基础上，可选的，为了进一步提高接口防护电路对接口芯片的防护作用，可以在接口防护电路中设置两个TVS管。以图3实施例所示的接口防护电路为例，可以在电阻203与接口芯片之间再设置一个TVS管，具体的，请参见图6所示的实施例。
图6为本发明提供的接口防护电路的结构示意图五。在图3所示实施例的基础上，请参见图6，接口防护电路还包括TVS管204，TVS管204的一端设置在电阻203和接口芯片之间，TVS管204的另一端接地。
可选的，TVS管204的特性可以和TVS管203的特性相同。
TVS管204可以进一步的降低接口芯片两端的浪涌电压，进而提高了对接口芯片的保护作用。进一步的，当一个TVS管出现故障时，另一个TVS管还可以对接口芯片起到保护作用，提高了对接口芯片保护的可靠性。
当然，在实际应用过程中，还可以根据实际需要设置TVS管在接口防护电路中的位置、及接口防护电路中TVS管的个数，本发明实施例对此不作具体限定。
图7为本发明提供的设备接口的结构示意图。请参见图7，该设备接口包括接口芯片701和图2-图6任一实施例所示的接口防护电路702。
可选的，图7实施例中所述的设备接口可以设置在通信设备中，该通信设备可以为电脑、电视、显示屏、机顶盒等。在实际应用的过程中，当电路中产生浪涌时，浪涌首先经过接口防护电路702，然后再流向接口芯片701，以使接口防护电路702可以对接口芯片701起到防护作用。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (13)

  1. 一种接口防护电路，其特征在于，包括：电容和瞬变电压抑制器TVS管，其中，
    所述电容的第一端与被保护设备的连接端口连接，所述电容的第二端分别与所述TVS管的第一端及所述被保护电路的接口芯片连接；
    所述TVS管的第二端接地。
  2. 根据权利要求1所述的接口防护电路，其特征在于，所述接口防护电路还包括电阻，所述电阻与所述电容和所述接口芯片串联。
  3. 根据权利要求2所述的接口防护电路，其特征在于，所述电阻设置于所述TVS管的第一端与所述接口芯片之间。
  4. 根据权利要求2所述的接口防护电路，其特征在于，所述电阻设置于所述连接端口与所述电容第一端之间。
  5. 根据权利要求2所述的接口防护电路，其特征在于，所述电阻设置于所述电容的第二端与所述TVS管的第一端之间。
  6. 根据权利要求1-5任一项所述的接口防护电路，其特征在于，所述电容的大小与所述连接端口传输的数据信号的频率成反向关系。
  7. 根据权利要求1-5任一项所述的接口防护电路，其特征在于，所述电阻的阻值在第一阻值和第二阻值之间，所述第一阻值大于所述第二阻值。
  8. 根据权利要求7所述的接口防护电路，其特征在于，所述第一阻值大于1欧姆，所述第二阻值小于200欧姆。
  9. 根据权利要求1-5任一项所述的接口防护电路，其特征在于，所述连接端口传输的数据信号的频率大于500MHz。
  10. 根据权利要求1-5任一项所述的接口防护电路，其特征在于，所述TVS管的钳位电压大于所述连接端口传输的数据信号的最大电压。
  11. 根据权利要求1-5任一项所述的接口防护电路，其特征在于，所述TVS管为单向TVS管；相应的，所述TVS管的负极与所述连接端口连接。
  12. 根据权利要求1-5任一项所述的接口防护电路，其特征在于，所述电容的电容值大于0.1纳法，且小于1微法。
  13. 一种设备接口，其特征在于，包括接口芯片和权利要求1-12任一项所述的接口防护电路。
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