WO2018099250A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2018099250A1
WO2018099250A1 PCT/CN2017/109897 CN2017109897W WO2018099250A1 WO 2018099250 A1 WO2018099250 A1 WO 2018099250A1 CN 2017109897 W CN2017109897 W CN 2017109897W WO 2018099250 A1 WO2018099250 A1 WO 2018099250A1
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Prior art keywords
substrate
layer
electrode layer
array substrate
insulating layer
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English (en)
French (fr)
Inventor
曹可
杨成绍
马骏
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US16/065,942 priority Critical patent/US10546884B2/en
Publication of WO2018099250A1 publication Critical patent/WO2018099250A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a method of fabricating the same, and a display device.
  • the liquid crystal display panel generally includes an array substrate and a counter substrate provided to the cartridge, and a liquid crystal layer disposed between the array substrate and the opposite substrate.
  • the array substrate includes a thin film transistor arranged in an array, a flat layer disposed on the thin film transistor, an electrode structure disposed on the flat layer, and an insulating layer disposed on the flat layer and the electrode structure.
  • the flat layer can be made of an organic film, and when the flat layer is an organic film, the organic film can be made flatter and lower in cost and simple in process, compared to a film layer made of an inorganic material.
  • At least one embodiment of the present disclosure provides an array substrate, a method of fabricating the same, and a display device.
  • At least one embodiment of the present disclosure provides an array substrate including a base substrate, a flat layer, a first electrode layer, and an insulating layer.
  • a flat layer disposed on the base substrate; a first electrode layer disposed on a side of the flat layer away from the substrate; an insulating layer disposed on a side of the flat layer and the first electrode layer away from the substrate, and insulating
  • the layer includes a plurality of first pore structures.
  • the shape of the first pore structure includes an elliptical shape.
  • a long axis direction of each two adjacent first pore structures is perpendicular to each other.
  • the shape of the first pore structure includes a rectangle.
  • a longitudinal direction of each two adjacent first pore structures is perpendicular to each other.
  • the array substrate further includes: a second electrode layer disposed on a side of the insulating layer away from the first electrode layer, and including a plurality of openings, An orthographic projection of the second electrode layer on the substrate substrate at least partially overlapping an orthographic projection of the first electrode layer on the substrate substrate, the first electrode layer and the second electrode layer An orthographic projection of the first aperture structure on the substrate substrate falls into an orthographic projection of the opening on the substrate substrate on a region of the substrate substrate where the orthographic projection overlaps.
  • the first electrode layer includes a plurality of second pore structures on the first electrode layer and the second electrode layer on the base substrate The overlapping regions are orthographically projected, and the second aperture structure coincides with the orthographic projection of the first aperture structure on the substrate.
  • the plurality of first pore structures and the plurality of second pore structures are formed by the same patterning process.
  • the array substrate further includes a thin film transistor between the substrate and the flat layer.
  • the flat layer and the insulating layer have different thermal expansion coefficients.
  • a material of the flat layer includes an organic material
  • a material of the insulating layer includes an inorganic material
  • At least one embodiment of the present disclosure also provides a display device comprising the array substrate of any of the above.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate, including forming a planarization layer on a substrate; forming a first electrode layer on a side of the planarization layer away from the substrate substrate; and a planarization layer and a first electrode layer An insulating layer is formed on a side away from the substrate substrate, and the insulating layer is patterned to form a plurality of first pore structures.
  • the manufacturing method further includes: forming a second electrode layer on a side of the insulating layer away from the substrate substrate, wherein the second electrode layer is An orthographic projection on the substrate substrate at least partially overlapping an orthographic projection of the first electrode layer on the substrate substrate, the second electrode layer including a plurality of openings, the first electrode layer and the Depicting an area where the orthographic projection of the second electrode layer on the substrate substrate overlaps, the first pore structure being at the substrate base The orthographic projection of the plate falls into the orthographic projection of the opening on the substrate.
  • the manufacturing method further includes: patterning the insulating layer and the first electrode layer by using a single patterning process to be in the first electrode layer A second pore structure having the same shape as the first pore structure is formed thereon.
  • the flat layer and the insulating layer have different thermal expansion coefficients.
  • the material of the planar layer includes an organic material
  • the material of the insulating layer includes an inorganic material
  • 1a is a schematic view showing a portion of a film layer in an array substrate
  • 1b is a schematic view showing the fracture of an insulating layer in an array substrate
  • 1c is a schematic diagram of a flat layer fracture in an array substrate
  • FIG. 2 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure
  • 3a is a schematic diagram of a principle of preventing fracture of an array substrate by an array substrate according to an embodiment of the present disclosure
  • 3b is a schematic diagram of a principle of preventing fracture of an array substrate by an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a fracture principle of an array substrate termination film layer according to an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a principle of preventing fracture of an array substrate by an array substrate according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a fracture principle of an array substrate termination film layer according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • a flat layer for example, an organic film layer
  • an insulating layer for example, an inorganic film layer
  • the array substrate includes a flat layer 101, a first electrode layer 102, and an insulating layer 103. Since the flat layer 101 and the insulating layer 103 have different expansion coefficients, for example, the material of the flat layer 101 includes an organic material such as polyimide or the like; and the material of the insulating layer 103 includes an oxide, a nitride, or an oxynitride. material. That is, the organic film layer and the inorganic film layer have different expansion coefficients. The difference in the shape of the flat layer 101 and the insulating layer 103 is large in a high temperature and low temperature environment.
  • the deformation amount of the flat layer 101 is larger than the deformation amount generated by the insulating layer 103, and the internal stress is in the flat layer 101. Under the influence of the action, the insulating layer 103 is prone to breakage.
  • FIG. 1b is a schematic view showing the fracture of the insulating layer in the array substrate.
  • the insulating layer 103 is prone to fracture when the array substrate is subjected to external slight force and internal stress generated by the expansion of the flat layer 101. Caused serious bad.
  • FIG. 1c is a schematic diagram of a flat layer fracture in an array substrate.
  • the crack is used as a release port to cause cracks.
  • the external vibration and the bending of the glass substrate also cause the crack to further extend, eventually leading to the flat layer 101 being completely broken, resulting in serious defects, thereby affecting the display effect of the display area.
  • Embodiments of the present disclosure provide an array substrate, a method of fabricating the same, and a display device.
  • Array substrate The substrate includes a flat layer disposed on the base substrate, a first electrode layer disposed on a side of the flat layer away from the substrate, and an insulation disposed on a side of the flat layer and the first electrode layer away from the substrate Floor.
  • the insulating layer includes a plurality of first pore structures.
  • the array substrate can reduce the contact area between the insulating layer and the flat layer by providing a plurality of first pore structures on the insulating layer and can release the internal stress of the flat layer at a position corresponding to the pore structure, thereby making the insulating layer and The difference in the shape variables of the flat layer is reduced, which in turn reduces the probability of film fracture.
  • the plurality of first pore structures can also buffer the fracture stress, and the fracture structure can be terminated by the pore structure during the fracture, and finally the fracture effect is reduced to Lowest and increase yield.
  • the array substrate includes a base substrate 100 , a flat layer 101 , a first electrode layer 102 , and an insulating layer 103 .
  • the flat layer 101 is disposed on the base substrate 100; the first electrode layer 102 is disposed on a side of the flat layer 101 away from the base substrate 100; and the insulating layer 103 is disposed on the flat layer 101 and the first electrode layer 102 away from the base substrate 100.
  • the insulating layer 103 includes a plurality of first pore structures 210.
  • a plurality of first pore structures 210 may be formed by patterning the insulating layer 130.
  • the plurality of first pore structures 210 formed on the insulating layer 103 can reduce the contact area of the insulating layer 103 and the flat layer 101 as a whole, that is, the insulating layer 103 and the flat layer.
  • 101 is not in contact at a position having the first pore structure 210, and the plurality of first pore structures 210 may expose a portion of the flat layer 101 or the flat layer 101 and the first electrode layer 102 such that the flat layer 101 changes in temperature when the temperature changes greatly
  • the generated stress can be released at the position of the plurality of first pore structures 210 such that the difference in the shape of the flat layer 101 and the insulating layer 103 is reduced, thereby reducing the probability of occurrence of film breakage.
  • the plurality of first pore structures 210 may also buffer the fracture stress.
  • the insulation layer 103 is partially broken, when the fractured crack extends to one or more of the plurality of first pore structures 210, the one or more The first pore structure 210 allows the crack to stop extending and diffuse, so that the plurality of first pore structures 210 can be used to terminate the fracture process, ultimately minimizing the effects of fracture.
  • the array substrate provided in the first embodiment may further include a thin film transistor 110 between the base substrate 100 and the flat layer 101.
  • the thin film transistor 110 includes a gate electrode 111, a gate insulating layer 112, an active layer 113, a source electrode 114, and a drain electrode 115.
  • a bottom gate type thin film transistor is taken as an example, and the embodiment of the present disclosure includes but is not limited thereto, and the thin film transistor may also be a top gate type thin film transistor or a double gate type thin film transistor.
  • the array substrate provided in the first embodiment may further include a passivation layer 116 disposed on the source 114 and the drain 115 of the thin film transistor 110 for preventing the oxygen element or the like in the planar layer 101 from being opposite to the source 114 and Corrosion of the drain 115.
  • a passivation layer 116 disposed on the source 114 and the drain 115 of the thin film transistor 110 for preventing the oxygen element or the like in the planar layer 101 from being opposite to the source 114 and Corrosion of the drain 115.
  • the flat layer 101 and the insulating layer 103 have different coefficients of thermal expansion.
  • the material of the flat layer 101 includes an organic material such as polyimide or the like, and the embodiment is not limited thereto.
  • the material of the insulating layer 103 includes an inorganic material such as an oxide, a nitride or an oxynitride, and the embodiment is not limited thereto.
  • the coefficient of thermal expansion of the flat layer 101 is greater than the coefficient of thermal expansion of the insulating layer 103, and the flat layer 101 generates a deformation amount larger than that of the insulating layer 103.
  • FIG. 3a is a schematic view showing the principle of preventing the film layer from breaking in the array substrate provided in the embodiment.
  • a plurality of layers are disposed on the insulating layer 103.
  • a pore structure 210 exposes a portion of the flat layer 101.
  • the internal stress generated by the flat layer 101 due to thermal expansion can be released at the position of the first pore structure 210 to prevent the internal stress from being generated on the insulating layer 103.
  • Influence, and the plurality of first pore structures 210 provide a larger deformation space for the expansion of the flat layer 101, thereby reducing the probability of occurrence of film breakage.
  • the flat layer 101 can generate more thermal expansion deformation at the position of the first pore structure 210, thereby releasing internal stress and reducing aggregation of internal stress thereof, thereby preventing generation of fission plastic deformation. It should be noted that when the temperature is lowered, the flat layer will shrink. Similarly, the flat layer can generate more cold shrinkage deformation at the position of the first pore structure, reducing the accumulation of internal stress, thereby preventing fission. The generation of plastic deformation.
  • the array substrate provided by the embodiment of the present disclosure is also applicable to the case where the deformation of the flat layer and the insulating layer is inconsistent due to other environmental factors (for example, humidity, pH, etc.), and the embodiment of the present disclosure is not limited herein.
  • FIG. 3b shows another schematic diagram of the principle of preventing the film layer from breaking in the array substrate provided by the embodiment.
  • the position of the first electrode layer 102 is disposed between the insulating layer 103 and the flat layer 101. Since the ductility of the first electrode layer 102 is good, the flat layer 101 is thermally expanded due to the temperature rise. The generated internal stress can still be released at the position of the first pore structure 210 to avoid The internal stress affects the insulating layer 103, and the first electrode layer 102 can bulge upward as the flat layer 101 expands. At this time, the plurality of first pore structures 210 provide a larger expansion for the flat layer 101. Deformation space, thereby reducing the probability of film breakage.
  • the flat layer when the temperature is lowered, the flat layer will shrink. Similarly, the flat layer can generate more cold shrinkage deformation at the position of the first pore structure, reducing the accumulation of internal stress, thereby preventing fission. The generation of plastic deformation.
  • the array substrate provided by the embodiment of the present disclosure is also applicable to the case where the deformation of the flat layer and the insulating layer is inconsistent due to other environmental factors (for example, humidity, pH, etc.), and the embodiment of the present disclosure is not limited herein.
  • FIG. 4 is a schematic diagram showing the principle of breaking the film layer of the array substrate provided by the embodiment.
  • the one or more extensions of the crack 300 can be stopped by the one or more first pore structures 210, causing the crack 300 to stop extending and diffuse, so that the plurality of first pore structures 210 can be used to terminate the fracture process, and finally Minimize the effects of fracture.
  • the plurality of first pore structures may be formed by etching the insulating layer; the etching process may be performed by plasma etching or wet etching, etc., and the embodiment of the present disclosure is not limited herein.
  • the substrate may be made of glass, polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, or polyethylene terephthalate.
  • the one or more materials of the diol ester and the polyethylene naphthalate are made, and the embodiments of the present disclosure are not limited herein.
  • the first electrode layer may be a transparent conductive layer.
  • the selected material includes a transparent conductive oxide, for example, may include indium tin oxide (ITO) or indium zinc oxide (A combination or at least one of IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), and aluminum zinc oxide (AZO) is not limited herein.
  • the first electrode layer can also be a metal layer.
  • the first electrode layer may be a pixel electrode or an anode.
  • the array substrate provided in this embodiment can be used in a liquid crystal display device; when the first electrode layer is an anode, the array substrate provided in this embodiment can be used in an organic light emitting diode (OLED) display device.
  • the first electrode layer may also be a common electrode, and the embodiment of the present disclosure is not limited herein.
  • the active layer may include polysilicon.
  • polysilicon can be crystallized by making amorphous silicon to make.
  • amorphous silicon can be crystallized by various suitable methods, including rapid thermal annealing, solid phase crystallization, excimer laser annealing, metal induced crystallization, metal induced lateral crystallization, or sequential Lateral crystallization method, etc.
  • the embodiment is not limited thereto, and the active layer may also be other materials.
  • materials for forming the source and the drain may include from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni). Selection of groups consisting of ruthenium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu) At least one of them may be formed in a single layer or a plurality of layers, and the embodiment is not limited thereto.
  • the material of the gate may include a metal oxide material, for example, may include one or more combinations of the group consisting of indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, indium gallium oxide, and aluminum zinc oxide.
  • the embodiment is not limited thereto, and may further include a combination of one or more of metal materials such as molybdenum, titanium, aluminum, and copper.
  • the material of the gate insulating layer may be silicon nitride, silicon oxide, or a combination of the two, and the embodiment is not limited thereto.
  • the array substrate further includes a second electrode layer 104 disposed on a side of the insulating layer 103 away from the first electrode layer 102. And including a plurality of openings 230. As shown in FIG. 5, the opening 230 is located at the position of the dashed box of the same layer of the second electrode layer 104.
  • the orthographic projection of the second electrode layer 104 on the substrate substrate 100 at least partially overlaps the orthographic projection of the first electrode layer 102 on the substrate substrate 100, the first electrode layer 102 and the second electrode layer 104 being on the base substrate
  • the orthographic projection of each of the first aperture structures 210 on the base substrate 100 falls into the orthographic projection of each opening 230 on the base substrate 100, for example, each opening 230 is parallel
  • the minimum dimension of the cross section of the plane of the substrate substrate 100 is greater than the maximum dimension of the cross section of each of the first aperture structures 210 along the plane parallel to the substrate 100.
  • the embodiment is not limited thereto, and each opening may also be included.
  • the minimum dimension of the cross section 230 along the plane parallel to the substrate substrate 100 is equal to the case where the first pore structure 210 is along the largest dimension of the cross section parallel to the plane of the substrate substrate 100.
  • an orthographic projection of each of the first pore structures 210 on the substrate substrate 100 falls into each of the openings 230 on the substrate.
  • the orthographic projection on the substrate 100 can prevent the second electrode layer 104 from being electrically connected to the first electrode layer 102 when the second electrode layer 104 is formed, and ensure that the insulating layer 103 is in the second electrode layer 104 and the first electrode layer 102. It has a good insulation effect.
  • the above-mentioned area where the first electrode layer and the second electrode layer overlap with each other on the base substrate is in the first electrode layer and/or the When the two electrode layers are slit electrode layers, they are regions surrounded by the first electrode layer and the second electrode layer, and include slits of the first electrode layer and/or the second electrode layer.
  • the second electrode layer may be a slit electrode, whereby the second electrode layer may generate a transverse electric field with the first electrode layer to drive the liquid crystal molecules to deflect.
  • the plurality of first pore structures described above are different from the via holes formed on the insulating layer.
  • the array substrate further includes a common electrode line 117 disposed on the base substrate 100.
  • a via 118 may be formed in the insulating layer 103 to electrically connect the second electrode layer 104 and the common electrode line 117.
  • the plurality of first pore structures 210 in this embodiment are not used for electrical connection, that is, a conductive layer or a portion of the conductive layer is not included in each of the first pore structures 210.
  • the plurality of first pore structures 210 in the embodiment may be disposed not only in a region where the flat layer 101 and the insulating layer 103 are in direct contact, but also in the presence of the first electrode layer 102 between the flat layer 101 and the insulating layer 103. region.
  • the second electrode layer 104 may also be a transparent conductive layer.
  • the selected material includes a metal oxide, for example, may include indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, indium gallium oxide, and aluminum zinc oxide.
  • the combination of the present disclosure or at least one of the embodiments of the present disclosure is not limited herein.
  • the first electrode layer can also be a metal layer.
  • the first electrode layer 102 includes a plurality of second pore structures 220, and the orthographic projections of the first electrode layer 102 and the second electrode layer 104 on the substrate substrate 100 The overlapping regions, the plurality of second pore structures 220 coincide with the orthographic projection of the plurality of first pore structures 210 on the substrate substrate 100. As shown in FIG. 5, the second pore structure 220 is located at the position of the dashed box of the same layer of the first electrode layer 102.
  • the plurality of second pore structures 220 disposed in the first electrode layer 102 may reduce the contact area of the flat layer 101 and the first electrode layer 102 as a whole, such that The difference between the two shape variables is reduced, and the probability of occurrence of film fracture is reduced.
  • the plurality of second pore structures 220 can also buffer the fracture stress, and can effectively terminate the fracture process at the time of fracture, and finally minimize the influence of the fracture.
  • the plurality of second pore structures 220 may also provide a larger deformation space for the expansion deformation or shrinkage deformation of the flat layer.
  • the orthogonal projection of the plurality of second pore structures and the plurality of first pore structures on the substrate substrate refers to a cross section of each of the second pore structures along a plane parallel to the substrate substrate.
  • the shape and size are equal to the shape and size of each first aperture structure along a cross-section parallel to the plane of the substrate substrate, and embodiments of the present disclosure include, but are not limited to.
  • the plurality of second pore structures may also be combined with the plurality of first holes The gap structure does not completely overlap on the base substrate.
  • the plurality of second pore structures 220 may be formed by etching, including plasma etching or wet etching, etc., and the embodiments of the present disclosure are not limited herein.
  • the first pore structure 210 and the second pore structure 220 may be formed by the same patterning process, that is, each of the first pore structures 210 and each of the second pore structures 220
  • the shape and size are the same, that is, in the region where the first electrode layer 102 and the second electrode layer 104 are orthographically projected on the base substrate, each of the second pore structures 220 is lining with each of the first pore structures 210.
  • the orthographic projections on the base substrate 100 are completely coincident. Forming the first pore structure 210 and the second pore structure 220 by a uniform patterning process can reduce the patterning step and save cost.
  • first pore structure 210 and the second pore structure 220 can also be formed by a two-step patterning process. It should be noted that when a plurality of first pore structures and a plurality of second pore structures are simultaneously etched using one etching process, the etching rate may be etched due to the consumption of the etching gas or the etching solution during the etching process. It will decrease as the etching progresses, resulting in the size of each second pore structure being slightly smaller than the first pore structure. However, embodiments in accordance with the present disclosure are not limited thereto, and each second pore structure may also be slightly larger in size than the first pore structure.
  • FIG. 6 is a schematic view showing the principle of preventing the film layer from breaking in the array substrate provided in the embodiment. As shown in FIG. 6, the position of the first electrode layer 102 exists between the insulating layer 103 and the flat layer 101, due to the first electrode.
  • the layer 102 has a plurality of second pore structures 220, and the plurality of second pore structures 220 and the plurality of first pore structures 210 may expose a portion of the flat layer 101, and the internal stress generated by the flat layer 101 due to thermal expansion when the temperature is raised
  • the release may be performed at the positions of the first pore structure 210 and the second pore structure 220 to prevent its internal stress from affecting the insulating layer 103, and the plurality of first pore structures 210 provide a larger expansion for the flat layer 101. Deformation space, thereby reducing the probability of film breakage.
  • the flat layer 101 can generate more thermal expansion deformation at the position of the first pore structure 210, thereby releasing internal stress and reducing aggregation of internal stress thereof, thereby preventing generation of fission plastic deformation. It should be noted that when the temperature is lowered, the flat layer will shrink. Similarly, the flat layer can generate more cold shrinkage deformation at the position of the first pore structure, reducing the accumulation of internal stress, thereby preventing fission. The generation of plastic deformation.
  • the array substrate provided by the embodiment of the present disclosure is also applicable to the case where the deformation of the flat layer and the insulating layer is inconsistent due to other environmental factors (for example, humidity, pH, etc.), and the embodiment of the present disclosure is not limited herein.
  • the shapes of the plurality of first pore structures 210 and the plurality of second pore structures 220 include an elliptical shape, and in addition, a plurality of first pore junctions.
  • the shape of the plurality of second pore structures may also be a pattern having a long axis or a long side, such as a rectangle, an elongated shape, or the like.
  • FIG. 7 only shows the shape and arrangement state of the insulating layer 103 and the pore structure left after etching thereon.
  • the embodiments of the present disclosure include but are not limited thereto, and the shapes of the plurality of first pore structures and the plurality of second pore structures may also be square, circular, or the like.
  • each two adjacent first pore structures 210 or every two adjacent second pore structures 220 are perpendicular to each other. That is, when the shape of the first pore structure 210 is elliptical, the long axis directions of each two adjacent first pore structures 210 or each two adjacent second pore structures 220 are perpendicular to each other; When the shape of the pore structure 210 is a rectangle, the longitudinal direction of each two adjacent first pore structures 210 or every two adjacent second pore structures 220 are perpendicular to each other.
  • the long axis direction of the hollow elliptical first pore structure 210 or the second pore structure 220 is easy to be broken first, and the crack will extend along the long axis direction thereof in the crack.
  • the fracture Upon reaching the short axis of the elliptical first pore structure 210 or the second pore structure 220, the fracture will stay due to the buffering action in the short axis direction.
  • the crack between each two adjacent first pore structures 210 or each two adjacent second pore structures 220 is small, and does not continue to fracture under the buffer of the short axis, thus The purpose of preventing breakage can be achieved.
  • etching the insulating layer 103 or the first electrode layer 102 corresponds to reducing the contact area of the insulating layer 103 or the first electrode layer 102 with the flat layer 101 as a whole, that is, reducing the two layers.
  • the relative shape variable is different, so it is not easy to break.
  • An embodiment of the present disclosure further provides a method for fabricating an array substrate.
  • the specific steps are as shown in FIG. 8 and include:
  • the contact area between the insulating layer and the flat layer can be reduced as a whole, and a part of the flat layer or The flat layer and the first electrode layer, so that the stress generated by the flat layer when the temperature changes greatly can be released at the position of the plurality of first pore structures, so that the difference in the shape of the flat layer and the insulating layer is reduced, thereby reducing The probability of film breakage occurs.
  • the fracture stress can also be buffered by patterning the insulating layer and forming a plurality of first pore structures.
  • the One or more first pore structures can make the The crack stops extending and diffuses, so that the first fracture structure can be terminated by a plurality of first pore structures, and finally the impact of the fracture is minimized.
  • the flat layer and the insulating layer have different thermal expansion coefficients.
  • the material of the flat layer includes an organic material such as polyimide or the like, and the embodiment is not limited thereto.
  • the material of the insulating layer includes an inorganic material such as an oxide, a nitride or an oxynitride, and the embodiment is not limited thereto.
  • the coefficient of thermal expansion of the flat layer is greater than the coefficient of thermal expansion of the insulating layer, and the flat layer produces a deformation larger than that of the insulating layer.
  • Patterning and etching a plurality of first pore structures on the insulating layer can reduce the contact area between the insulating layer and the flat layer as a whole, so that the difference between the shape variables is reduced, and the probability of occurrence of film breakage is reduced.
  • the plurality of first pore structures can buffer the fracture stress, so that the flat layer does not generate excessive internal stress due to deformation when the temperature changes greatly, and can be terminated by using the plurality of first pore structures when the fracture occurs.
  • the fracture process eventually minimizes the effects of fracture and increases yield.
  • the step of patterning the insulating layer to form the plurality of first pore structures may employ an etching process, such as plasma etching or wet etching, etc., and embodiments of the present disclosure are not limited thereto.
  • the method for fabricating the array substrate further includes: forming a second electrode layer on a side of the insulating layer away from the substrate substrate, the second electrode layer includes a plurality of openings, and the second electrode layer is on the substrate.
  • the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first electrode layer on the substrate, each of the first pore structures in a region where the front projections of the first electrode layer and the second electrode layer on the substrate substrate overlap
  • the orthographic projection on the substrate substrate falls into the orthographic projection of each opening on the substrate.
  • the minimum dimension of each opening along a cross section parallel to the plane of the substrate substrate is greater than the maximum dimension of each first aperture structure along a cross section parallel to the plane of the substrate substrate, and the embodiment is not limited thereto, and may also be The minimum dimension including the cross-section of each opening along a plane parallel to the substrate substrate is equal to the maximum dimension of each first aperture structure along a cross-section parallel to the plane of the substrate substrate.
  • the method for fabricating the array substrate provided in the first embodiment may further include: patterning the insulating layer and the first electrode layer by using a single patterning process to form the same shape as the first pore structure on the first electrode layer. Second pore structure. Patterning the insulating layer and the first electrode layer using a single patterning process The patterning step can be reduced and the cost can be saved.
  • the embodiment is not limited thereto, and the first pore structure and the second pore structure may also be formed by two patterning processes.
  • the first electrode layer may be a transparent conductive layer, for example, may be made of a transparent conductive oxide, for example, indium tin oxide, indium zinc oxide, zinc oxide, oxidation. A combination or at least one of indium, indium gallium oxide, and aluminum zinc oxide.
  • the plurality of second pore structures disposed in the first electrode layer can reduce the contact area of the flat layer and the first electrode layer as a whole, so that the difference in shape variables is reduced, and the probability of occurrence of film breakage is reduced; The second pore structure can also buffer the fracture stress and effectively terminate the fracture process at the time of fracture, and finally minimize the impact of the fracture.
  • the plurality of second pore structures may also provide a larger deformation space for the expansion deformation or shrinkage deformation of the flat layer.
  • the same shape of the plurality of second pore structures and the plurality of first pore structures on the base substrate refers to the orthographic projection of the first electrode layer and the second electrode layer on the base substrate.
  • the overlapping regions, the shape and size of each second pore structure along a cross section parallel to the plane of the substrate substrate is equal to the shape and size of each first pore structure along a cross section parallel to the plane of the substrate substrate, the present disclosure Embodiments include but are not limited to.
  • the plurality of second pore structures may also not completely coincide with the plurality of first pore structures on the substrate.
  • FIG. 9 is a schematic diagram of a three-dimensional film layer of an array substrate fabricated by using the method for fabricating an array substrate provided in an example of the embodiment.
  • the insulating layer 103 is patterned to form a plurality of first pore structures 210; after the etching of the insulating layer 103 is completed, the first electrode layer 102 may also be patterned to form a plurality of second pore structures 220, of course, the first pores
  • the structure 210 and the second pore structure 220 may be formed by the same patterning process, and embodiments of the present disclosure are not limited thereto.
  • the flat layer 101 may be exposed, and the exposed flat layer 101 may be directly covered by the alignment film during the subsequent fabrication of the array substrate.
  • a part of the film layer of the array substrate in FIG. 9 includes a flat layer 101, a first electrode layer 102, an insulating layer 103 and a second electrode layer 104.
  • each film layer in the figure is schematic. Displaced, in fact, the positional relationship of each film layer is as shown in Fig. 2 or 5.
  • the expansion of the flat layer 101 is provided at a high temperature to provide a larger deformation space, that is, the flat layer 101 can be
  • the first pore structure 210 and the second pore structure 220 generate more elastic deformation, thereby releasing internal stress and reducing the accumulation of internal stress, thereby preventing the generation of fission plastic deformation.
  • the shapes of the first pore structure and the second pore structure include an elliptical shape, and the embodiment of the present disclosure is not limited thereto, and may also be a rectangle or the like. A graphic with a long axis or a long side is sufficient.
  • the major axis or the long side direction of each two adjacent first pore structures or every two adjacent second pore structures are perpendicular to each other. That is, when the shape of the first pore structure is elliptical, the major axis directions of each two adjacent first pore structures or every two adjacent second pore structures are perpendicular to each other; when the first pore structure When the shape is a rectangle, the longitudinal direction of each two adjacent first pore structures or every two adjacent second pore structures is perpendicular to each other.
  • the selection of the shape formed by the patterning of the first pore structure and the second pore structure and the arrangement state thereof can effectively terminate the film fracture.
  • the method for fabricating the array substrate provided in this embodiment further includes forming a thin film transistor between the substrate and the planar layer.
  • a gate electrode is formed on a base substrate, and a gate insulating layer is formed on the gate electrode to be insulated from the subsequent film layer.
  • Forming an active layer on the gate insulating layer for example, the active layer includes a channel region, a source contact region electrically connected to the source, and a contact region electrically connected to the drain; here, the source of the active layer
  • the contact region and the drain contact region are electrically connected to the subsequently formed source and drain, respectively.
  • a source and a drain are formed on the active layer.
  • the present embodiment is exemplified by a bottom gate thin film transistor, and is not limited thereto, and may be a top gate thin film transistor or a double gate thin film transistor.
  • An embodiment of the present disclosure further provides a display device including any of the above array substrates, which can effectively reduce the probability of film fracture, minimize the impact of fracture, and improve the yield.
  • the display device includes a liquid crystal display device, an organic light emitting diode display device, and the like, and the embodiment is not limited thereto.
  • the display device can be widely applied to a variety of display terminals, including but not limited to mobile phones, notebooks, tablet computers, advertisement display boards, digital photo frames, POS machines, game terminals, and the like.

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Abstract

一种阵列基板及其制作方法、显示装置。该阵列基板通过对绝缘层(103)刻蚀出多个第一孔隙结构(210)，可以减小绝缘层(103)与平坦层(101)的接触面积并使平坦层(101)可在孔隙结构(210)对应的位置释放其内部应力，从而使得绝缘层(103)和平坦层(101)的形变量差异减小，进而可降低发生膜层断裂的几率；另外，多个第一孔隙结构(210)还可以缓冲断裂应力，在断裂时能够利用第一孔隙结构(210)终止断裂进程，最终将断裂影响降到最低，提高良率。

Description

阵列基板及其制作方法、显示装置
交叉引用
本申请要求于2016年12月02日提交的申请号为201611094764.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开实施例涉及一种阵列基板及其制作方法、显示装置。
背景技术
随着显示技术的不断发展，液晶显示器(Liquid Crystal Display,LCD)因其响应速度快、集成度高、功耗小等优点，已成为主流的显示装置。液晶显示面板通常包括对盒设置的阵列基板和对置基板以及设置在阵列基板与对置基板之间的液晶层组成。
通常，阵列基板包括呈阵列排布的薄膜晶体管、设置在薄膜晶体管上的平坦层、设置在平坦层上的电极结构以及设置在平坦层和电极结构上的绝缘层。平坦层可采用有机膜制作，并且当平坦层为有机膜时，相对于采用无机材料制作的膜层，有机膜可以制作得更加平坦并且成本较低、工艺简单。
发明内容
本公开的至少一个实施例提供一种阵列基板及其制作方法、显示装置。
本公开的至少一个实施例提供一种阵列基板，其包括衬底基板、平坦层、第一电极层和绝缘层。平坦层，设置在衬底基板上；第一电极层，设置在平坦层远离衬底基板的一侧；绝缘层，设置在平坦层和第一电极层远离衬底基板的一侧，并且，绝缘层包括多个第一孔隙结构。
例如，在本公开一实施例提供的阵列基板中，所述第一孔隙结构的形状包括椭圆形。
例如，在本公开一实施例提供的阵列基板中，每两个相邻的所述第一孔隙结构的长轴方向互相垂直。
例如，在本公开一实施例提供的阵列基板中，所述第一孔隙结构的形状包括长方形。
例如，在本公开一实施例提供的阵列基板中，每两个相邻的所述第一孔隙结构的长边方向互相垂直。
例如，在本公开一实施例提供的阵列基板中，该阵列基板还包括：第二电极层，设置在所述绝缘层的远离所述第一电极层的一侧，且包括多个开口，所述第二电极层在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影至少部分重叠，在所述第一电极层和所述第二电极层在所述衬底基板上的正投影重叠的区域，所述第一孔隙结构在所述衬底基板上的正投影落入所述开口在所述衬底基板上的正投影。
例如，在本公开一实施例提供的阵列基板中，所述第一电极层包括多个第二孔隙结构，在所述第一电极层和所述第二电极层在所述衬底基板上的正投影重叠的区域，所述第二孔隙结构与所述第一孔隙结构在所述衬底基板上的正投影重合。
例如，在本公开一实施例提供的阵列基板中，所述多个第一孔隙结构与所述多个第二孔隙结构经同一图案化工艺形成。
例如，在本公开一实施例提供的阵列基板中，该阵列基板还包括位于所述衬底基板和所述平坦层之间的薄膜晶体管。
例如，在本公开一实施例提供的阵列基板中，所述平坦层和所述绝缘层的热膨胀系数不同。
例如，在本公开一实施例提供的阵列基板中，所述平坦层的材料包括有机材料，所述绝缘层的材料包括无机材料。
本公开至少一个实施例还提供一种显示装置，包括上述任一项所述的阵列基板。
本公开的至少一个实施例提供一种阵列基板的制作方法，包括在衬底基板上形成平坦层；在平坦层远离衬底基板的一侧形成第一电极层；在平坦层和第一电极层远离衬底基板的一侧形成绝缘层，以及图案化绝缘层以形成多个第一孔隙结构。
例如，在本公开一实施例提供的阵列基板的制作方法中，该制作方法还包括：在所述绝缘层远离所述衬底基板的一侧形成第二电极层，所述第二电极层在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影至少部分重叠，所述第二电极层包括多个开口，在所述第一电极层和所述第二电极层在所述衬底基板上的正投影重叠的区域，所述第一孔隙结构在所述衬底基 板上的正投影落入所述开口在所述衬底基板上的正投影。
例如，在本公开一实施例提供的阵列基板的制作方法中，该制作方法还包括：利用一次图案化工艺图案化所述绝缘层和所述第一电极层，以在所述第一电极层上形成与所述第一孔隙结构形状相同的第二孔隙结构。
例如，在本公开一实施例提供的阵列基板的制作方法中，所述平坦层和所述绝缘层的热膨胀系数不同。
例如，在本公开一实施例提供的阵列基板的制作方法中，所述平坦层的材料包括有机材料，所述绝缘层的材料包括无机材料。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1a为一种阵列基板中部分膜层示意图；
图1b为一种阵列基板中绝缘层断裂示意图；
图1c为一种阵列基板中平坦层断裂示意图；
图2为本公开一实施例提供的一种阵列基板截面示意图；
图3a为本公开一实施例提供的一种阵列基板防止膜层断裂原理示意图；
图3b为本公开一实施例提供的一种阵列基板防止膜层断裂原理示意图；
图4为本公开一实施例提供的一种阵列基板终止膜层断裂原理示意图；
图5为本公开一实施例提供的一种阵列基板截面示意图；
图6为本公开一实施例提供的一种阵列基板防止膜层断裂原理示意图；
图7为本公开一实施例提供的一种阵列基板终止膜层断裂原理示意图；
图8为本公开一实施例提供的一种阵列基板制作方法的流程图；以及
图9为本公开一实施例提供的一种阵列基板的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所 有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在研究中，本申请的发明人发现：阵列基板上的平坦层(例如有机膜层)和平坦层上绝缘层(例如无机膜层)由于具有不同的膨胀系数，在高温和低温的环境中，两者的形变量差异较大，从而导致平坦层和绝缘层会在外力的影响下容易发生断裂，进而导致严重不良。
图1a为一种阵列基板中的部分膜层示意图，如图1a所示，阵列基板包括平坦层101、第一电极层102和绝缘层103。由于平坦层101和绝缘层103具有不同的膨胀系数，例如，平坦层101的材料包括有机材料，例如聚酰亚胺等材料；而绝缘层103的材料包括氧化物、氮化物或氮氧化合物等材料。也就是说，有机膜层与无机膜层具有不同的膨胀系数。在高温以及低温环境中平坦层101和绝缘层103的形变量差异大，例如，温度变化较大时，平坦层101膨胀产生的形变量大于绝缘层103产生的形变量，在平坦层101内部应力作用的影响下，绝缘层103容易产生断裂现象。
图1b为一种阵列基板中绝缘层断裂示意图，如图1b所示，在阵列基板受到外界轻微力以及平坦层101膨胀产生的内部应力的共同作用下，绝缘层103会很容易出现断裂现象，导致严重不良。
图1c为一种阵列基板中平坦层断裂示意图，如图1c所示，当绝缘层103在底部平坦层101的内应力作用下断裂后，一方面，由于应力会以此裂痕作为释放口使裂痕继续延伸；另一方面，外界的震动和玻璃衬底基板的弯曲也会使裂痕进一步出现延伸现象，最终导致平坦层101彻底断裂，导致严重不良，从而影响显示区域的显示效果。
本公开实施例提供一种阵列基板及其制作方法以及显示装置。该阵列基板 包括衬底基板、设置在衬底基板上的平坦层、设置在平坦层上远离衬底基板一侧的第一电极层、以及设置在平坦层和第一电极层远离衬底基板一侧的绝缘层。绝缘层包括多个第一孔隙结构。由此，该阵列基板通过在绝缘层上设置多个第一孔隙结构可以减小绝缘层与平坦层的接触面积并使平坦层可在孔隙结构对应的位置释放其内部应力，从而使得绝缘层和平坦层的形变量差异减小，进而可降低发生膜层断裂的几率；另外，多个第一孔隙结构还可以缓冲断裂应力，在断裂时能够利用孔隙结构终止断裂进程，最终将断裂影响降到最低，并提高良率。
下面结合附图对本公开实施例提供的阵列基板及其制作方法以及显示装置进行说明。
本公开一实施例提供一种阵列基板，如图2所示，该阵列基板包括衬底基板100、平坦层101、第一电极层102和绝缘层103。平坦层101设置在衬底基板100上；第一电极层102设置在平坦层101远离衬底基板100的一侧；绝缘层103设置在平坦层101和第一电极层102远离衬底基板100的一侧。并且，如图2所示，绝缘层103包括多个第一孔隙结构210。例如，可通过对绝缘层130进行图案化工艺以形成多个第一孔隙结构210。
由此，在本实施例提供的阵列基板中，在绝缘层103上形成的多个第一孔隙结构210可整体减小绝缘层103与平坦层101的接触面积，即，绝缘层103和平坦层101在具有第一孔隙结构210的位置处不接触，多个第一孔隙结构210可暴露出部分平坦层101或平坦层101和第一电极层102，从而使得平坦层101在温度变化较大时产生的应力可以在多个第一孔隙结构210的位置处释放，使得平坦层101和绝缘层103的形变量差异减小，进而可降低发生膜层断裂的几率。另外，多个第一孔隙结构210还可以缓冲断裂应力，当绝缘层103发生局部断裂时，当断裂的裂缝延伸到多个第一孔隙结构210中的一个或多个时，该一个或多个第一孔隙结构210可使该裂缝停止继续延伸，扩散，从而可利用多个第一孔隙结构210终止断裂进程，最终将断裂影响降到最低。
例如，本实施例一示例提供的阵列基板还可包括位于衬底基板100和平坦层101之间的薄膜晶体管110。如图2所示，薄膜晶体管110包括栅极111、栅极绝缘层112、有源层113、源极114和漏极115。例如，本实施例以底栅型薄膜晶体管为例，本公开实施例包括但不限于此，薄膜晶体管还可以是顶栅型薄膜晶体管或双栅型薄膜晶体管。
例如，本实施例一示例提供的阵列基板还可包括设置在薄膜晶体管110的源极114和漏极115上的钝化层116，用于防止平坦层101中的氧元素等对源极114和漏极115的腐蚀。
例如，在本实施例一示例提供的阵列基板中，平坦层101和绝缘层103的热膨胀系数不同。例如，平坦层101的材料包括有机材料，例如聚酰亚胺等材料，本实施例不限于此。例如，绝缘层103的材料包括无机材料，例如氧化物、氮化物或氮氧化合物等材料，本实施例不限于此。例如，在高温时，平坦层101的热膨胀系数大于绝缘层103的热膨胀系数，平坦层101会产生大于绝缘层103的形变量，因此，平坦层101中产生的内应力会作用于绝缘层103，使绝缘层103容易产生断裂现象。另一方面，外界的震动和阵列基板的弯曲会进一步导致绝缘层103出现断裂现象，甚至平坦层101也随之彻底断裂。因此，通过在绝缘层103设置多个第一孔隙结构210，一方面可以使得平坦层101和绝缘层103形变量差异减小，降低发生膜层断裂的几率；另一方面可以缓冲断裂应力，并在断裂时终止断裂进程，最终将断裂影响降到最低，并提高良率。
例如，图3a示出了本实施例提供的阵列基板防止膜层断裂原理示意图，如图3a所示，在绝缘层103与平坦层101直接接触的位置，由于绝缘层103上设置的多个第一孔隙结构210暴露出了部分平坦层101，当温度升高时，平坦层101由于热膨胀而产生的内应力可以在第一孔隙结构210的位置进行释放，以避免其内应力对绝缘层103产生影响，并且，多个第一孔隙结构210为平坦层101的膨胀提供了更大的形变空间，从而降低发生膜层断裂的几率。也就是说，平坦层101可以在第一孔隙结构210的位置处产生更多的热膨胀形变，进而释放内部应力，减小其内部应力的聚集，从而防止裂变式塑性形变的产生。需要说明的是，当温度降低时，平坦层会产生收缩，同样地，平坦层可以在第一孔隙结构的位置处产生更多的冷收缩形变，减小其内部应力的聚集，从而防止裂变式塑性形变的产生。当然，本公开实施例提供的阵列基板还可适用于因为其他环境因素(例如，湿度，酸碱度等)而导致的平坦层和绝缘层产生形变不一致的情形，本公开实施例在此不作限制。
例如，图3b示出了另一种本实施例提供的阵列基板防止膜层断裂原理示意图。如图3b所示，在绝缘层103与平坦层101之间设置有第一电极层102的位置，由于第一电极层102的延展性较好，当温度升高时，平坦层101由于热膨胀而产生的内应力仍然可以在第一孔隙结构210的位置进行释放，以避免 其内应力对绝缘层103产生影响，并且第一电极层102可随着平坦层101的膨胀而向上鼓起，此时，多个第一孔隙结构210为平坦层101的膨胀提供了更大的形变空间，从而降低发生膜层断裂的几率。需要说明的是，当温度降低时，平坦层会产生收缩，同样地，平坦层可以在第一孔隙结构的位置处产生更多的冷收缩形变，减小其内部应力的聚集，从而防止裂变式塑性形变的产生。当然，本公开实施例提供的阵列基板还可适用于因为其他环境因素(例如，湿度，酸碱度等)而导致的平坦层和绝缘层产生形变不一致的情形，本公开实施例在此不作限制。
例如，图4示出了本实施例提供的阵列基板终止膜层断裂原理示意图，如图4所示，即使当绝缘层103上产生了裂缝300，当裂缝300延伸到多个第一孔隙结构210的一个或多个时，裂缝300的延伸可被该一个或多个第一孔隙结构210中止，使该裂缝300停止继续延伸，扩散，从而可利用多个第一孔隙结构210终止断裂进程，最终将断裂影响降到最低。
例如，在本实施例一示例提供的阵列基板中，多个第一孔隙结构可以通过刻蚀绝缘层形成；刻蚀工艺可采用等离子刻蚀或湿刻等，本公开实施例在此不作限制。
例如，在本实施例一示例提供的阵列基板中，衬底基板可以由玻璃、聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯中的一种或多种材料制成，本公开实施例在此不作限制。
例如，在本实施例一示例提供的阵列基板中，第一电极层可为透明导电层，例如，选用的材料包括透明导电氧化物，例如，可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铟镓(IGO)和氧化铝锌(AZO)中的组合或至少一种，本公开实施例在此不作限制。当然，第一电极层也可为金属层。
例如，在本实施例一示例提供的阵列基板中，第一电极层可为像素电极也可为阳极。当第一电极层为像素电极时，本实施例提供的阵列基板可用于液晶显示装置；当第一电极层为阳极时，本实施例提供的阵列基板可用于有机发光二极管(OLED)显示装置。另外，第一电极层也可为公共电极，本公开实施例在此不作限制。
例如，有源层可以包括多晶硅。例如，多晶硅可以通过使非晶硅结晶化形 成。例如，可以通过利用各种合适的方法使非晶硅结晶化，包括快速热退火方法、固相结晶化方法、准分子激光退火方法、金属诱导结晶化方法、金属诱导横向结晶化方法或循序性侧向结晶方法等。本实施例不限于此，有源层还可以是其他材料。
例如，用于形成源极和漏极的材料可以包括从由铝(Al)、铂(Pt)、钯(Pd)、银(Ag)、镁(Mg)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、锂(Li)、钙(Ca)、钼(Mo)、钛(Ti)、钨(W)和铜(Cu)组成的组中选择的至少一种，并且可以形成单层或多层，本实施例不限于此。
例如，栅极的材料可以包括金属氧化物材料，例如可以包括由氧化铟锡、氧化铟锌、氧化锌、氧化铟、氧化铟镓和氧化铝锌构成的组中的一种或多种组合，本实施例不限于此，还可以包括钼、钛、铝、铜等金属材料中的一种或多种的组合等。
例如，栅极绝缘层的材质可以是氮化硅、氧化硅或两者的组合，本实施例不限于此。
本公开一实施例提供另一种阵列基板，如图5所示，该阵列基板还包括第二电极层104，第二电极层104设置在绝缘层103的远离第一电极层的102一侧，且包括多个开口230。如图5所示，开口230位于第二电极层104同层的虚线方框位置处。例如，第二电极层104在衬底基板100上的正投影与第一电极层102在衬底基板100上的正投影至少部分重叠，第一电极层102和第二电极层104在衬底基板100上的正投影重叠的区域内，每个第一孔隙结构210在衬底基板100上的正投影落入每个开口230在衬底基板100上的正投影，例如，每个开口230沿平行于衬底基板100所在平面的横截面的最小尺寸大于每个第一孔隙结构210沿平行于衬底基板100所在平面的横截面的最大尺寸，本实施例不限于此，还可以包括每个开口230沿平行于衬底基板100所在平面的横截面的最小尺寸等于第一孔隙结构210沿平行于衬底基板100所在平面的横截面的最大尺寸的情况。在第一电极层102和第二电极层104在衬底基板100上的正投影重叠的区域，每个第一孔隙结构210在衬底基板100上的正投影落入每个开口230在衬底基板100上的正投影，在形成第二电极层104时，可以防止第二电极层104与第一电极层102产生电连接，保证绝缘层103在第二电极层104与第一电极层102之间起到良好的绝缘效果。需要说明的是，上述的第一电极层和第二电极层在衬底基板上的正投影重叠的区域在第一电极层和/或第 二电极层为狭缝电极层时，为第一电极层和第二电极层围成的区域，其包括第一电极层和/或第二电极层的缝隙。
例如，当本实施例提供的阵列基板应用于液晶显示装置时，第二电极层可为狭缝电极，由此，第二电极层可与第一电极层产生横向电场以驱动液晶分子偏转。
需要说明的是，上述的多个第一孔隙结构不同于形成在绝缘层上的过孔。例如，如图5所示，该阵列基板还包括设置在衬底基板100上的公共电极线117。为了将绝缘层103上的第二电极层104与公共电极线117相连，可在绝缘层103上开设过孔118从而将第二电极层104与公共电极线117进行电性连接。而本实施例中的多个第一孔隙结构210并不用于电性连接，也就是说，在各第一孔隙结构210中不包括导电层或导电层的一部分。另外，本实施例中的多个第一孔隙结构210不仅可设置在平坦层101和绝缘层103直接接触的区域，还可设置在平坦层101和绝缘层103之间存在第一电极层102的区域。
例如，第二电极层104也可为透明导电层，例如，选用的材料包括金属氧化物，例如，可以包括氧化铟锡、氧化铟锌、氧化锌、氧化铟、氧化铟镓和氧化铝锌中的组合或至少一种，本公开实施例在此不作限制。当然，第一电极层也可为金属层。
例如，在本实施例一示例提供的阵列基板中，第一电极层102包括多个第二孔隙结构220，且在第一电极层102和第二电极层104在衬底基板100上的正投影重叠的区域，多个第二孔隙结构220与多个第一孔隙结构210在衬底基板100上的正投影重合。如图5所示，第二孔隙结构220位于第一电极层102同层的虚线方框位置处。由于平坦层101与第一电极层102的热膨胀系数也有差异，设置在第一电极层102中的多个第二孔隙结构220可以整体减小平坦层101与第一电极层102的接触面积，使得两者形变量差异减小，降低发生膜层断裂的几率；另外，多个第二孔隙结构220也可以缓冲断裂应力，并在断裂时能够有效终止断裂进程，最终将断裂影响降到最低。另一方面，多个第二孔隙结构220还可为平坦层的膨胀变形或收缩变形提供更大的形变空间。需要说明的是，上述的多个第二孔隙结构与多个第一孔隙结构在衬底基板上的正投影重合指的是每个第二孔隙结构沿平行于衬底基板所在平面的横截面的形状和尺寸等于每个第一孔隙结构沿平行于衬底基板所在平面的横截面的形状和尺寸，本公开实施例包括但不限于此。例如，多个第二孔隙结构还可以与多个第一孔 隙结构在衬底基板上不完全重合。
例如，在本实施例一示例提供的阵列基板中，多个第二孔隙结构220可以通过刻蚀形成，包括等离子刻蚀或湿刻等，本公开实施例在此不作限制。
例如，在本实施例一示例提供的阵列基板中，第一孔隙结构210与第二孔隙结构220可经同一图案化工艺形成，即，每个第一孔隙结构210与每个第二孔隙结220的形状以及尺寸相同，也就是说，在第一电极层102和第二电极层104在衬底基板上正投影重叠的区域，每个第二孔隙结构220与每个第一孔隙结构210在衬底基板100上的正投影完全重合。利用统一图案化工艺形成第一孔隙结构210与第二孔隙结构220，可以减少图案化步骤，节省成本。当然，第一孔隙结构210与第二孔隙结构220也可以经两步图案化工艺形成。需要说明的是，当使用一次刻蚀工艺同时刻蚀多个第一孔隙结构和多个第二孔隙结构时，由于刻蚀气体或刻蚀液在刻蚀过程中的消耗，其刻蚀速率可能会随着刻蚀的进行而下降，从而导致各第二孔隙结构的尺寸会略小于第一孔隙结构。然而，根据本公开的实施例并不限制于此，各第二孔隙结构的尺寸也可以略大于第一孔隙结构。
例如，图6示出了本实施例提供的阵列基板防止膜层断裂原理示意图，如图6所示，在绝缘层103与平坦层101之间存在第一电极层102的位置，由于第一电极层102具有多个第二孔隙结构220，多个第二孔隙结构220和多个第一孔隙结构210可暴露出部分平坦层101，当温度升高时，平坦层101由于热膨胀而产生的内应力可以在第一孔隙结构210和第二孔隙结构220的位置进行释放，以避免其内应力对绝缘层103产生影响，并且，多个第一孔隙结构210为平坦层101的膨胀提供了更大的形变空间，从而降低发生膜层断裂的几率。也就是说，平坦层101可以在第一孔隙结构210的位置处产生更多的热膨胀形变，进而释放内部应力，减小其内部应力的聚集，从而防止裂变式塑性形变的产生。需要说明的是，当温度降低时，平坦层会产生收缩，同样地，平坦层可以在第一孔隙结构的位置处产生更多的冷收缩形变，减小其内部应力的聚集，从而防止裂变式塑性形变的产生。当然，本公开实施例提供的阵列基板还可适用于因为其他环境因素(例如，湿度，酸碱度等)而导致的平坦层和绝缘层产生形变不一致的情形，本公开实施例在此不作限制。
例如，在本实施例一示例提供的阵列基板中，如图7所示，多个第一孔隙结构210和多个第二孔隙结构220的形状包括椭圆形，另外，多个第一孔隙结 构和多个第二孔隙结构的形状还可以是具有长轴或长边的图形，例如长方形、长条形等。需要说明的是，图7仅示意出了绝缘层103以及其上刻蚀后留下的孔隙结构的形态和排布状态。需要说明的是，本公开实施例包括但不限于此，多个第一孔隙结构和多个第二孔隙结构的形状也可为正方形、圆形等形状。
例如，如图7所示，每两个相邻的第一孔隙结构210或每两个相邻的第二孔隙结构220的长轴或长边方向互相垂直。也就是说，当第一孔隙结构210的形状为椭圆形时，每两个相邻的第一孔隙结构210或每两个相邻的第二孔隙结构220的长轴方向互相垂直；当第一孔隙结构210的形状为长方形时，每两个相邻的第一孔隙结构210或每两个相邻的第二孔隙结构220的长边方向互相垂直。根据材料结构力学原理，在内、外应力下，中空的椭圆形第一孔隙结构210或第二孔隙结构220的长轴方向容易首先发生断裂，并且裂痕会沿着其长轴方向延伸，在裂痕到达椭圆形第一孔隙结构210或第二孔隙结构220的短轴上时，由于短轴方向的缓冲作用，断裂会停留下来。从整体上看，每两个相邻的第一孔隙结构210或每两个相邻的第二孔隙结构220之间的裂痕很小，并且在短轴的缓冲作用下不会产生继续断裂，因此可以达到阻止断裂的目的。另一方面，对绝缘层103或第一电极层102的刻蚀，相当于在整体上减小了绝缘层103或第一电极层102与平坦层101的接触面积，即减小了两膜层的相对形变量差异，因此不容易发生断裂。
本公开一实施例还提供了一种阵列基板的制作方法，具体步骤如图8所示，包括：
S01：在衬底基板上形成平坦层。
S02：在平坦层远离衬底基板的一侧形成第一电极层。
S03：在平坦层和第一电极层远离衬底基板的一侧形成绝缘层。
S04：图案化绝缘层以形成多个第一孔隙结构。
由此，在本实施例提供的阵列基板的制作方法中，通过图案化绝缘层并形成多个第一孔隙结构可整体减小绝缘层与平坦层的接触面积，还可暴露出部分平坦层或平坦层和第一电极层，从而使得平坦层在温度变化较大时产生的应力可以在多个第一孔隙结构的位置处释放，使得平坦层和绝缘层的形变量差异减小，进而可降低发生膜层断裂的几率。另外，通过图案化绝缘层并形成多个第一孔隙结构还可以缓冲断裂应力，当绝缘层发生局部断裂时，当断裂的裂缝延伸到多个第一孔隙结构中的一个或多个时，该一个或多个第一孔隙结构可使该 裂缝停止继续延伸，扩散，从而可利用多个第一孔隙结构终止断裂进程，最终将断裂影响降到最低。
例如，在本实施例一示例提供的阵列基板的制作方法中，平坦层和绝缘层的热膨胀系数不同。例如，平坦层的材料包括有机材料，例如聚酰亚胺等材料，本实施例不限于此。例如，绝缘层的材料包括无机材料，例如氧化物、氮化物或氮氧化合物等材料，本实施例不限于此。例如，在高温时，平坦层的热膨胀系数大于绝缘层的热膨胀系数，平坦层会产生大于绝缘层的形变量，因此，平坦层中产生的内应力会作用于绝缘层，使绝缘层容易产生断裂现象。外界的震动和阵列基板的弯曲会进一步导致绝缘层的断裂，甚至平坦层彻底断裂。对绝缘层图案化刻蚀出多个第一孔隙结构，一方面，可以相当于整体减小了绝缘层与平坦层的接触面积，使得两者形变量差异减小，降低发生膜层断裂的几率；另一方面，多个第一孔隙结构可以缓冲断裂应力，使平坦层在温度变化较大时，不会因为形变而产生过多的内应力，在断裂时能够利用多个第一孔隙结构终止断裂进程，最终将断裂影响降到最低，并提高良率。
例如，图案化绝缘层以形成多个第一孔隙结构的步骤可采用刻蚀工艺，例如，等离子刻蚀或湿刻等，本公开实施例不限于此。
例如，本实施例一示例提供的阵列基板的制作方法，还包括：在绝缘层远离衬底基板的一侧形成第二电极层，第二电极层包括多个开口，第二电极层在衬底基板上的正投影与第一电极层在衬底基板上的正投影至少部分重叠，在第一电极层和第二电极层在衬底基板上的正投影重叠的区域，每个第一孔隙结构在衬底基板上的正投影落入每个开口在衬底基板上的正投影。例如，每个开口沿平行于衬底基板所在平面的横截面的最小尺寸大于每个第一孔隙结构沿平行于衬底基板所在平面的横截面的最大尺寸，本实施例不限于此，还可以包括每个开口沿平行于衬底基板所在平面的横截面的最小尺寸等于每个第一孔隙结构沿平行于衬底基板所在平面的横截面的最大尺寸的情况。每个第一孔隙结构在衬底基板上的正投影落入每个开口在衬底基板上的正投影，在形成第二电极层时，可以防止第二电极层与第一电极层产生电连接的现象，保证绝缘层在第二电极层与第一电极层之间起到良好的绝缘效果。
例如，本实施例一示例提供的阵列基板的制作方法，还可包括：利用一次图案化工艺图案化绝缘层和第一电极层，以在第一电极层上形成与第一孔隙结构形状相同的第二孔隙结构。利用一次图案化工艺图案化绝缘层和第一电极层 可以减少图案化步骤，节省成本。本实施例不限于此，第一孔隙结构与第二孔隙结构也可以经两次图案化工艺形成。
由于平坦层与第一电极层的膨胀系数也有差异，例如，第一电极层可为透明导电层，例如，可采用透明导电氧化物制作，例如，氧化铟锡、氧化铟锌、氧化锌、氧化铟、氧化铟镓和氧化铝锌中的组合或至少一种。设置在第一电极层中的多个第二孔隙结构可以整体减小平坦层与第一电极层的接触面积，使得两者形变量差异减小，降低发生膜层断裂的几率；另外，多个第二孔隙结构也可以缓冲断裂应力，并在断裂时能够有效终止断裂进程，最终将断裂影响降到最低。另一方面，多个第二孔隙结构还可为平坦层的膨胀变形或收缩变形提供更大的形变空间。需要说明的是，上述的多个第二孔隙结构与多个第一孔隙结构在衬底基板上的形状相同是指的是在第一电极层和第二电极层在衬底基板上的正投影重叠的区域，每个第二孔隙结构沿平行于衬底基板所在平面的横截面的形状和尺寸等于每个第一孔隙结构沿平行于衬底基板所在平面的横截面的形状和尺寸，本公开实施例包括但不限于此。例如，多个第二孔隙结构还可以与多个第一孔隙结构在衬底基板上不完全重合。
图9为采用本实施例一示例提供的阵列基板的制作方法所制作的阵列基板的立体膜层示意图，如图9所示，可在第二电极层104的多个开口230的区域内，对绝缘层103进行图案化以形成多个第一孔隙结构210；绝缘层103刻蚀完成后，还可对第一电极层102进行图案化以形成多个第二孔隙结构220，当然，第一孔隙结构210与第二孔隙结构220可以经同一图案化工艺形成，本公开实施例不限于此。当绝缘层103和第一电极层102刻蚀完成后可以暴露出平坦层101，暴露的平坦层101可以在后续制造阵列基板的过程中被配向膜直接覆盖。需要说明的是，图9中阵列基板的部分膜层包括平坦层101、第一电极层102、绝缘层103和第二电极层104，为了表示的更清楚，图中的每一膜层示意图是错开表示的，实际上每一膜层的位置关系如图2或5所示。对绝缘层103和第一电极层102刻蚀形成第一孔隙结构210和第二孔隙结构220后，在高温情况下为平坦层101的膨胀提供了更大的形变空间，即平坦层101可以在第一孔隙结构210和第二孔隙结构220处产生更多的弹性形变，进而释放内部应力，减小其内部应力的聚集，从而防止裂变式塑性形变的产生。
例如，在本实施例一示例提供的阵列基板的制作方法中，第一孔隙结构和第二孔隙结构的形状包括椭圆形，本公开实施例不限于此，还可以是长方形等 具有长轴或长边的图形即可。
例如，在本实施例一示例提供的阵列基板的制作方法中，每两个相邻的第一孔隙结构或每两个相邻的第二孔隙结构的长轴或长边方向互相垂直。也就是说，当第一孔隙结构的形状为椭圆形时，每两个相邻的第一孔隙结构或每两个相邻的第二孔隙结构的长轴方向互相垂直；当第一孔隙结构的形状为长方形时，每两个相邻的第一孔隙结构或每两个相邻的第二孔隙结构的长边方向互相垂直。对第一孔隙结构和第二孔隙结构图案化形成的形状的选取以及其排布状态可以有效终止膜层断裂。
例如，本实施例提供的阵列基板的制作方法还包括在衬底基板与平坦层之间形成薄膜晶体管。例如，在衬底基板上形成栅极，在栅极上形成栅极绝缘层以与后续膜层绝缘。在栅极绝缘层上形成有源层，例如，有源层包括沟道区域、与源极电连接的源极接触区域和与漏极电连接的接触区域；在此，有源层的源极接触区域和漏极接触区域分别与后续形成的源极和漏极电连接。在有源层上形成源极和漏极。例如，本实施例以底栅型薄膜晶体管为例，不限于此，还可以是顶栅型薄膜晶体管或双栅型薄膜晶体管。
本公开一实施例还提供一种显示装置，该显示装置包括上述任一项阵列基板，可以有效减小膜层断裂几率，将断裂影响降到最低，并且提高良率。
例如，该显示装置包括液晶显示装置、有机发光二极管显示装置等，本实施例不限于此。
例如，该显示装置可以广泛应用于多种显示终端，包括但不限于手机、笔记本、平板电脑、广告展示牌、数码相框、POS机、游戏终端等。
有以下几点需要说明：
(1)除非另作定义，本公开实施例以及附图中，同一标号代表同一含义。
(2)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或衬底基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到 变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种阵列基板，包括：
    衬底基板；
    平坦层，设置在所述衬底基板上；
    第一电极层，设置在所述平坦层远离所述衬底基板的一侧；
    绝缘层，设置在所述平坦层和所述第一电极层远离所述衬底基板的一侧，
    其中，所述绝缘层包括多个第一孔隙结构。
  2. 根据权利要求1所述的阵列基板，其中，所述第一孔隙结构的形状包括椭圆形。
  3. 根据权利要求2所述的阵列基板，其中，每两个相邻的所述第一孔隙结构的长轴方向互相垂直。
  4. 根据权利要求1所述的阵列基板，其中，所述第一孔隙结构的形状包括长方形。
  5. 根据权利要求4所述的阵列基板，其中，每两个相邻的所述第一孔隙结构的长边方向互相垂直。
  6. 根据权利要求1-5中任一项所述的阵列基板，还包括：
    第二电极层，设置在所述绝缘层的远离所述第一电极层的一侧，且包括多个开口，
    其中，所述第二电极层在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影至少部分重叠，所述第一电极层和所述第二电极层在所述衬底基板上的正投影重叠的区域内，所述第一孔隙结构在所述衬底基板上的正投影落入所述开口在所述衬底基板上的正投影。
  7. 根据权利要求6所述的阵列基板，其中，所述第一电极层包括多个第二孔隙结构，所述第一电极层和所述第二电极层在所述衬底基板上的正投影重叠的区域内，所述第二孔隙结构与所述第一孔隙结构在所述衬底基板上的正投影重合。
  8. 根据权利要求7所述的阵列基板，其中，所述多个第一孔隙结构与所述多个第二孔隙结构经同一图案化工艺形成。
  9. 根据权利要求1-5中任一项所述的阵列基板，还包括位于所述衬底基板和所述平坦层之间的薄膜晶体管。
  10. 根据权利要求1-5中任一项所述的阵列基板，其中，所述平坦层和所述绝缘层的热膨胀系数不同。
  11. 根据权利要求1-5中任一项所述的阵列基板，其中，所述平坦层的材料包括有机材料，所述绝缘层的材料包括无机材料。
  12. 一种显示装置，包括根据权利要求1-11中任一项所述的阵列基板。
  13. 一种阵列基板的制作方法，包括：
    在衬底基板上形成平坦层；
    在所述平坦层远离所述衬底基板的一侧形成第一电极层；
    在所述平坦层和所述第一电极层远离所述衬底基板的一侧形成绝缘层，以及
    图案化所述绝缘层以形成多个第一孔隙结构。
  14. 根据权利要求13所述的制作方法，还包括：
    在所述绝缘层远离所述衬底基板的一侧形成第二电极层，所述第二电极层在所述衬底基板上的正投影与所述第一电极层在所述衬底基板上的正投影至少部分重叠，
    其中，所述第二电极层包括多个开口，在所述第一电极层和所述第二电极层在所述衬底基板上的正投影重叠的区域内，所述第一孔隙结构在所述衬底基板上的正投影落入所述开口在所述衬底基板上的正投影。
  15. 根据权利要求13所述的制作方法，还包括：
    利用一次图案化工艺图案化所述绝缘层和所述第一电极层，以在所述第一电极层上形成与所述第一孔隙结构形状相同的第二孔隙结构。
  16. 根据权利要求13所述的制作方法，其中，所述平坦层和所述绝缘层的热膨胀系数不同。
  17. 根据权利要求13-16中任一项所述的制作方法，其中，所述平坦层的材料包括有机材料，所述绝缘层的材料包括无机材料。
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CN107170760B (zh) * 2017-05-31 2019-12-20 京东方科技集团股份有限公司 显示基板的制备方法、显示基板和显示装置
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