WO2018095440A1 - 一种基极多晶硅自对准套准结构及其制备方法 - Google Patents

一种基极多晶硅自对准套准结构及其制备方法 Download PDF

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WO2018095440A1
WO2018095440A1 PCT/CN2017/119752 CN2017119752W WO2018095440A1 WO 2018095440 A1 WO2018095440 A1 WO 2018095440A1 CN 2017119752 W CN2017119752 W CN 2017119752W WO 2018095440 A1 WO2018095440 A1 WO 2018095440A1
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sio
protective layer
layer
base
base polysilicon
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French (fr)
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刘洪军
应贤炜
赵杨杨
盛国兴
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中国电子科技集团公司第五十五研究所
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Priority to US16/462,942 priority Critical patent/US11011472B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors

Definitions

  • the invention relates to semiconductor microelectronics design and manufacture, in particular to a base polysilicon self-aligned register structure and a preparation method thereof.
  • bipolar transistors are mainly used in high-speed drive circuits, high-frequency signal reception and amplification.
  • Si-based bipolar transistor devices have low phase noise at low frequencies, they still have an irreplaceable advantage over GaAs and GaN-based materials.
  • the noise performance of silicon bipolar transistors is closely related to their frequency performance. The higher the frequency performance, the better. Therefore, the main purpose of silicon bipolar transistors is to improve the cut-off frequency of the devices.
  • the measures are as follows: 1) Thin base technology, 2 In-situ doped polysilicon emitter technology, 3) dual polysilicon self-alignment technology.
  • the dual polysilicon self-alignment technology means that the base and emitter of the bipolar transistor are both polysilicon technology, which is characterized by the use of the base polysilicon side wall self-alignment technology to form the emitter polysilicon and control the emitter effectively. Width, which can significantly reduce the parasitic parameters between the device's intrinsic junctions, this technology increases the cut-off frequency of silicon-based bipolar transistors from the conventional 10GHz to more than 20GHz.
  • the process cannot measure and judge the registration of the two, and when SiO 2
  • the size of the protective layer is controlled at 0.6-0.7 ⁇ m, so that the distance between SiO 2 and the base polysilicon is only 0.15-0.2 ⁇ m. Therefore, the registration requirement is very high, and the registration is not good, which will make SiO 2 not protect the intrinsic area or The base polysilicon overlaps, and these bias factors will directly affect the electrical parameter consistency of the device.
  • the present invention provides a base polysilicon self-aligned register structure, the base polysilicon self-aligned register structure achieves a very high registration requirement, and ensures electrical parameters of the device. Consistency.
  • the invention also provides a method for preparing a base polysilicon self-aligned register structure.
  • a base polysilicon self-aligned registration structure comprising a silicon substrate having a SiO 2 medium having a local oxidation region, having SiO 2 in an intermediate portion above the silicon substrate dielectric protective layer, a base polysilicon layer is SiO 2 dielectric protective layer right and left sides, and the SiO 2 protective layer dielectric adjacent the base polysilicon layer are equal and symmetrical spacing, the pitch size equal to the thickness of the base electrode polysilicon layer.
  • the silicon substrate between the SiO 2 dielectric protective layer and the adjacent base polysilicon layer is slightly etched through a depth of 0.1-0.2 ⁇ m. That is, the silicon substrate at the position of the SiO 2 dielectric protective layer and the adjacent base polysilicon layer at both sides is lightly engraved, and the depth is 0.1-0.2 ⁇ m, which can effectively control the high concentration base to the intrinsic region. The length of the diffusion.
  • the method for preparing a base polysilicon self-aligned register structure comprises the following steps:
  • step (3) depositing a base polysilicon layer on the basis of the step (2);
  • the thickness of the SiO 2 dielectric protective layer formed by the oxidation in the step (1) is
  • the thickness of the polysilicon layer in step (1) is the thickness of the polysilicon layer in step (1)
  • the wet etching as described in step (2) removes the thickness to SiO 2 dielectric protective layer.
  • the thickness of the base polysilicon layer in step (3) is the thickness of the base polysilicon layer in step (3).
  • a photoresist having a thickness of 0.8-1.2 ⁇ m is spin-coated on the base polysilicon layer, and a photoresist having a thickness of 0.4-0.6 ⁇ m is etched back.
  • step (5) terminating in said dielectric SiO 2 protective layer, a light cut of the silicon substrate between the polysilicon electrode layer of SiO 2 on both sides of the base protective layer and the dielectric, the polysilicon layer between the electrode layer and the SiO 2 dielectric protective group
  • the silicon substrate is slightly pasted to a depth of 0.1-0.2 ⁇ m and has a width equal to the thickness of the remaining remaining base polysilicon layer.
  • the diffusion length of the high-concentration base to the intrinsic region can be effectively controlled by the light over-etching method, and the thin layer of SiO 2 can be used as a light With a degree of reference, it is possible to reduce the capacitance and improve the yield.
  • the base polysilicon self-aligned register structure of the present invention achieves a very high registration requirement of the base polysilicon and the SiO 2 dielectric protective layer, and the SiO 2 dielectric protective layer can realize the selective etch stop layer, eliminating the Physical or chemical damage to the intrinsic region when etched onto the surface of the silicon substrate when the base polysilicon is formed.
  • the termination position of the SiO 2 dielectric protective layer is just in the middle position of the base polysilicon, achieving extremely high registration requirements and ensuring the consistency of the electrical parameters of the device.
  • the silicon substrate between the SiO 2 dielectric protective layer and the base polysilicon can effectively control the diffusion length of the high concentration base to the intrinsic region by the light over-etching method, and the thin layer SiO 2 can be used as a light over-etching degree. References to achieve reduced capacitance and improved yield.
  • the preparation method of the invention is simple and convenient, low in cost and short in time.
  • FIG. 1 is a schematic view showing a SiO 2 dielectric protective layer formed on a silicon substrate having a partial oxidation region, and a polysilicon layer is deposited;
  • FIG. 2 is a schematic view of removing a SiO 2 dielectric protective layer after photolithography and etching of a polysilicon layer;
  • Figure 3 is a schematic view of depositing a base polysilicon layer
  • Figure 4 is a schematic view of a spin-on photoresist
  • Figure 5 is a schematic view of a etch back photoresist
  • Figure 6 is a schematic view showing a polysilicon layer terminated with a SiO 2 dielectric protective layer
  • FIG. 7 is a schematic view showing a structure of removing a photoresist, forming a base polysilicon layer and a SiO 2 dielectric protective layer, and obtaining a base polysilicon self-aligned register;
  • 1 is a silicon substrate
  • 2 is a SiO 2 medium having a partial oxidation region
  • 3 is a SiO 2 dielectric protective layer
  • 4 is a polysilicon layer
  • 5 is a base polysilicon layer
  • 6 is a photoresist.
  • the thickness is oxidized to
  • the SiO 2 dielectric protective layer 3 is deposited on the SiO 2 dielectric protective layer 3 to a thickness of The polysilicon layer 4 is used to realize the damage-free protection of the intrinsic region of the device; as shown in FIG. 2, the polysilicon layer 4 is photolithographically and etched to terminate in the SiO 2 dielectric protective layer 2, and the SiO 2 without the polysilicon layer is removed by wet etching.
  • Dielectric protective layer 3 as shown in FIG.
  • the deposited base polysilicon layer 5 is grown to a thickness of Preferably, a boron-doped base polysilicon layer is used; as shown in FIG. 4, a photoresist 6 having a thickness of 0.8-1.2 ⁇ m is spin-coated on the base polysilicon layer 5; preferably, the thickness of the spin-on photoresist is 1 ⁇ m, as shown in FIG. Reprinting a photoresist 6 having a thickness of 0.4-0.6 ⁇ m, preferably etching a photoresist having a thickness of 0.6 ⁇ m; continuing to etch back the photoresist-free base polysilicon layer, so that the polysilicon layer on the SiO 2 dielectric protective layer 3 4 exposed; as shown in FIG.
  • the prepared base polysilicon self-aligned registration structure comprises a silicon substrate 1 having a SiO 2 dielectric 2 having a local oxidation region, and a SiO 2 dielectric protection layer 2 and a base polysilicon layer at an intermediate portion above the silicon substrate 1 5 is located on the left and right sides of the SiO 2 dielectric protective layer 3, and the SiO 2 dielectric protective layer 3 and the adjacent base polysilicon layers 5 are equally spaced and symmetric, and the pitch is equal to the thickness of the base polysilicon layer 5, SiO 2 medium
  • the termination position of the protective layer 3 is just in the middle of the base polysilicon 5; the silicon substrate at the position of the SiO 2 dielectric protective layer 3 and the adjacent base polysilicon layer 5 is lightly engraved, slightly engraved The depth is 0.1-0.2 ⁇ m and the width is equal to the thickness of the remaining remaining base polysilicon layer.
  • the base polysilicon self-aligned register structure realizes self-aligned registration of the base polysilicon and the SiO 2 dielectric protective layer in the

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Abstract

一种基极多晶硅自对准套准结构及其制备方法，该自对准套准结构包括具有局部氧化区的SiO 2介质（2）的硅衬底（1），在硅衬底（1）上方中间部位具有SiO 2介质保护层（3），基极多晶硅层（5）位于SiO 2介质保护层（3）左右两侧，且SiO 2介质保护层（3）与相邻的基极多晶硅层（5）间距相等且对称，间距大小与基极多晶硅层（5）的厚度相等。该基极多晶硅自对准套准结构，保证了器件电参数的一致性，消除了在形成基极多晶硅时，刻蚀至硅衬底表面时对本征区的物理或化学损伤，实现减小电容与提高成品率。

Description

一种基极多晶硅自对准套准结构及其制备方法 技术领域
本发明是涉及半导体微电子设计制造，具体涉及一种基极多晶硅自对准套准结构及其制备方法。
背景技术
在微波技术领域，双极型晶体管主要应用于高速驱动电路、高频信号接收与放大等领域。特别在低噪声放大器领域，由于Si基双极型晶体管器件在低频时相位噪声小，相对于GaAs、GaN基材料仍然具有不可替代的优势。硅双极型晶体管的噪声性能与其频率性能密切相关，频率性能越高越好，因此硅双极型晶体管在设计上主要目的是提高器件的截至频率，措施有：1)薄基区技术，2)原位掺杂多晶硅发射极技术，3)双多晶硅自对准技术等。其中，双多晶硅自对准技术是指双极型晶体管的基极和发射极都是采用多晶硅技术，特点是利用基极多晶硅的侧墙自对准技术形成发射极多晶硅，并控制发射极的有效宽度，这样可以大幅降低器件本征区结之间寄生参数，该技术把硅基双极型晶体管的截至频率从常规的10GHz左右提高到20GHz以上。
在双多晶硅自对准技术中，有个技术难点，就是基极多晶硅与硅衬底之间的本征区保护控制，本征区用于后续工艺的发射极多晶硅，若不用SiO 2保护层，基极多晶硅刻蚀终止于硅硅衬底时，工艺很难保证不损伤器件本征区；若用SiO 2保护层时，则两次光刻前后形成的基极多晶硅与SiO 2介质之间存在套准的问题。通常基极多晶硅之间距离在1μm左右，SiO 2保护层的尺寸大于1μm时，基极多晶硅于SiO 2保护层交叠，则工艺上无法测量和判断二者的套准情况，而当SiO 2保护层尺寸控制在0.6～0.7μm，使得SiO 2与基极多晶硅之间距离只有0.15～0.2μm，因此套准要求非常高，套准的不好，会使得SiO 2保护不了本征区或与基极多晶硅有交叠，这些套偏因素将直接影响器件的电参数一致性。
发明内容
发明目的：针对现有技术存在的问题，本发明提供一种基极多晶硅自对准套准结构，该基极多晶硅自对准套准结构实现了极高套准的要求，保证了器件电参数的一致性。本发明还提供了一种基极多晶硅自对准套准结构的制备方法。
技术方案：为了实现上述目的，如本发明所述的一种基极多晶硅自对准套准结构，包括具有局部氧化区的SiO 2介质的硅衬底，在硅衬底上方中间部位具有SiO 2介质保护层，基极多晶硅层位于SiO 2介质保护层左右两侧，且SiO 2介质保 护层与相邻的基极多晶硅层间距相等且对称，间距大小与基极多晶硅层的厚度相等。
作为优选，SiO 2介质保护层与相邻的基极多晶硅层之间的硅衬底轻微刻过0.1-0.2μm深度。即对SiO 2介质保护层与两侧相邻的基极多晶硅层间距位置处的的硅衬底进行轻刻，轻微刻过0.1-0.2μm深度，可以有效控制高浓度的基极向本征区的扩散长度。
如本发明所述的基极多晶硅自对准套准结构的制备方法，包括如下步骤：
(1)在具有局部氧化区的SiO 2介质的硅衬底上，氧化形成SiO 2介质保护层，在SiO 2介质保护层上淀积多晶硅层；
(2)对多晶硅层进行光刻和刻蚀终止于SiO 2介质保护层，湿法腐蚀去掉上面无多晶硅层的SiO 2介质保护层；
(3)在步骤(2)的基础上淀积基极多晶硅层；
(4)在基极多晶硅层上旋涂光刻胶，再回刻光刻胶和无光刻胶保护的基极多晶硅层，使得SiO 2介质保护层上的多晶硅层露出；
(5)继续回刻多晶硅层，终止于SiO 2介质保护层，SiO 2介质保护层终止位置刚好处在基极多晶硅的正中间位置；
(6)去除光刻胶，得到基极多晶硅自对准套准结构。
作为优选，步骤(1)所述氧化形成SiO 2介质保护层的厚度为
Figure PCTCN2017119752-appb-000001
作为优选，步骤(1)所述多晶硅层厚度为
Figure PCTCN2017119752-appb-000002
作为优选，步骤(2)所述湿法腐蚀去掉厚度为
Figure PCTCN2017119752-appb-000003
SiO 2介质保护层。
作为优选，步骤(3)所述基极多晶硅层的厚度为
Figure PCTCN2017119752-appb-000004
作为优选，步骤(4)所述在基极多晶硅层上旋涂厚度为0.8-1.2μm的光刻胶，再回刻厚度为0.4-0.6μm的光刻胶。
其中，步骤(5)所述终止于SiO 2介质保护层后，轻刻SiO 2介质保护层与两侧基极多晶硅层之间的硅衬底，SiO 2介质保护层与基极多晶硅层之间的硅衬底轻微刻过0.1-0.2μm深度，宽度与最终剩余的基极多晶硅层厚度相等。对于SiO 2介质保护层与两侧相邻基极多晶硅之间硅衬底通过轻过刻方法，可以有效控制高浓度的基极向本征区的扩散长度，并且薄层SiO 2的可以作为轻过刻程度的参照物，实现减小电容与提高成品率。
有益效果：与现有技术的相比，本发明具有如下优点：
1、本发明的基极多晶硅自对准套准结构实现了基极多晶硅与SiO 2介质保护层极高套准的要求，采用SiO 2介质保护层可以实现选择性刻蚀终止层，消除了 在形成基极多晶硅时，刻蚀至硅衬底表面时对本征区的物理或化学损伤。
2、SiO 2介质保护层终止位置刚好处在基极多晶硅的正中间位置，实现了极高套准的要求，保证了器件电参数的一致性。
3、SiO 2介质保护层与基极多晶硅之间硅衬底通过轻过刻方法，可以有效控制高浓度的基极向本征区的扩散长度，并且薄层SiO 2的可以作为轻过刻程度的参照物，实现减小电容与提高成品率。
4、本发明的制备方法简单方便、成本低、时间短。
附图说明
附图1为是在具有局部氧化区域的硅衬底上，氧化生长形成SiO 2介质保护层，淀积多晶硅层的示意图；
附图2是光刻和刻蚀多晶硅层后，去除SiO 2介质保护层的示意图；
附图3是淀积基极多晶硅层的示意图；
附图4是旋涂光刻胶的示意图；
附图5是回刻光刻胶的示意图；
附图6是刻多晶硅层，终止于SiO 2介质保护层的示意图；
附图7是去除光刻胶，形成了基极多晶硅层与SiO 2介质保护层，得到基极多晶硅自对准套准结构示意图；
图中的1是硅衬底、2是局部氧化区的SiO 2介质、3是SiO 2介质保护层、4是多晶硅层、5是基极多晶硅层、6是光刻胶。
具体实施方式
以下结合实施例和附图对本发明作进一步说明。
实施例
如图1所示，在形成基极多晶硅前，在具有局部氧化区的SiO 2介质2的硅衬底1上，氧化形成厚度为
Figure PCTCN2017119752-appb-000005
SiO 2介质保护层3，在SiO 2介质保护层3上淀积厚度为
Figure PCTCN2017119752-appb-000006
多晶硅层4来实现器件本征区的无损伤保护；如图2所示，对多晶硅层4进行光刻和刻蚀终止于SiO 2介质保护层2，湿法腐蚀去掉上面无多晶硅层的SiO 2介质保护层3；如图3所示，淀积基极多晶硅层5生长到厚度为
Figure PCTCN2017119752-appb-000007
优选掺硼的基极多晶硅层；如图4所示，在基极多晶硅层5上旋涂厚度为0.8-1.2μm的光刻胶6；优选旋涂光刻胶厚度1μm，如图5所示，回刻0.4-0.6μm厚度的光刻胶6，优选回刻0.6μm厚度的光刻胶；继续回刻无光刻胶保护的基极多晶硅层，使得SiO 2介质保护层3上的多晶硅层4露出；如图6所示，刻蚀剩余的多晶硅层4，终止于SiO 2介质保护层3；轻刻SiO 2介质保护层3与基极多晶硅层5之间的硅衬底1，轻微刻过0.1-0.2μm的硅衬底， 轻微刻过的硅衬底的宽度与最终剩余的基极多晶硅层厚度相等；如图7所示，去除剩余光刻胶，得到基极多晶硅自对准套准结构。
所制备得到的基极多晶硅自对准套准结构，包括具有局部氧化区的SiO 2介质2的硅衬底1，在硅衬底1上方中间部位具有SiO 2介质保护层2，基极多晶硅层5位于SiO 2介质保护层3左右两侧，且SiO 2介质保护层3与两侧相邻的基极多晶硅层5间距相等且对称，间距大小与基极多晶硅层5的厚度相等，SiO 2介质保护层3终止位置刚好处在基极多晶硅5的正中间位置；对SiO 2介质保护层3与两侧相邻的基极多晶硅层5间距位置处的的硅衬底进行轻刻，轻微刻过0.1-0.2μm深度，宽度与最终剩余的基极多晶硅层厚度相等。该基极多晶硅自对准套准结构在双多晶硅自对准双极型晶体管的工艺过程中，实现基极多晶硅与SiO 2介质保护层自对准套准。

Claims (10)

  1. 一种基极多晶硅自对准套准结构，其特征在于，包括具有局部氧化区的SiO 2介质的硅衬底，在硅衬底上方中间部位具有SiO 2介质保护层，基极多晶硅层位于SiO 2介质保护层左右两侧，且SiO 2介质保护层与两侧相邻的基极多晶硅层间距相等且对称，间距大小与基极多晶硅层的厚度相等。
  2. 根据权利要求1所述的基极多晶硅自对准套准结构，其特征在于，SiO 2介质保护层与两侧相邻的基极多晶硅层之间的硅衬底轻微刻过0.1-0.2μm深度。
  3. 一种基极多晶硅自对准套准结构的制备方法，其特征在于，包括如下步骤：
    (1)在具有局部氧化区的SiO 2介质的硅衬底上，氧化形成SiO 2介质保护层，在SiO 2介质保护层上淀积多晶硅层；
    (2)对多晶硅层进行光刻和刻蚀终止于SiO 2介质保护层，湿法腐蚀去掉上面无多晶硅层的SiO 2介质保护层；
    (3)在步骤(2)的基础上淀积基极多晶硅层；
    (4)在基极多晶硅层上旋涂光刻胶，再回刻光刻胶和无光刻胶保护的基极多晶硅层，使得SiO 2介质保护层上的多晶硅层露出；
    (5)继续回刻多晶硅层，终止于SiO 2介质保护层；
    (6)去除光刻胶，得到基极多晶硅自对准套准结构。
  4. 根据权利要求3所述的制备方法，其特征在于，步骤(1)所述氧化形成SiO 2介质保护层的厚度为
    Figure PCTCN2017119752-appb-100001
  5. 根据权利要求3所述的制备方法，其特征在于，步骤(1)所述多晶硅层厚度为
    Figure PCTCN2017119752-appb-100002
  6. 根据权利要求3所述的制备方法，其特征在于，步骤(2)所述湿法腐蚀去掉SiO 2介质保护层的厚度为
    Figure PCTCN2017119752-appb-100003
  7. 根据权利要求3所述的制备方法，其特征在于，步骤(3)所述基极多晶硅层的厚度为
    Figure PCTCN2017119752-appb-100004
  8. 根据权利要求3所述的制备方法，其特征在于，步骤(4)所述在基极多晶硅层上旋涂厚度为0.8-1.2μm的光刻胶，再回刻厚度为0.4-0.6μm的光刻胶。
  9. 根据权利要求3所述的制备方法，其特征在于，步骤(5)所述终止于SiO 2介质保护层后，轻刻SiO 2介质保护层与基极多晶硅层之间的硅衬底。
  10. 根据权利要求9所述的制备方法，其特征在于，步骤(5)所述硅衬底轻微刻过0.1-0.2μm深度，宽度与最终剩余的基极多晶硅层厚度相等。
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