WO2018076160A1 - Dac电容阵列及模数转换器、降低模数转换器功耗的方法 - Google Patents

Dac电容阵列及模数转换器、降低模数转换器功耗的方法 Download PDF

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WO2018076160A1
WO2018076160A1 PCT/CN2016/103185 CN2016103185W WO2018076160A1 WO 2018076160 A1 WO2018076160 A1 WO 2018076160A1 CN 2016103185 W CN2016103185 W CN 2016103185W WO 2018076160 A1 WO2018076160 A1 WO 2018076160A1
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Prior art keywords
capacitor
sub
capacitor array
dac
analog
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PCT/CN2016/103185
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English (en)
French (fr)
Inventor
范硕
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深圳市汇顶科技股份有限公司
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Priority to CN201680001422.8A priority Critical patent/CN106797220B/zh
Priority to PCT/CN2016/103185 priority patent/WO2018076160A1/zh
Priority to KR1020177029837A priority patent/KR101972689B1/ko
Priority to EP16898149.6A priority patent/EP3340472A4/en
Priority to US15/784,514 priority patent/US10079609B2/en
Publication of WO2018076160A1 publication Critical patent/WO2018076160A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/462—Details of the control circuitry, e.g. of the successive approximation register

Definitions

  • the embodiments of the present invention belong to the field of integrated circuits, and in particular, to a DAC capacitor array and an analog-to-digital converter, and a method for reducing power consumption of an analog-to-digital converter.
  • the successive approximation analog-to-digital converter converts the analog signal into a digital signal.
  • SAR ADC converts the analog signal into a digital signal.
  • it consists of a comparator, a register, and a digital-to-analog converter.
  • Converter, DAC the basic principle of converting analog signals into digital signals is: comparing the analog input signal to be converted with a reference signal, the reference signal is obtained by the output of a D/A converter, according to the two
  • the size determines whether to increase or decrease the digital signal input by the D/A converter, so that the reference signal is forced to the analog input signal.
  • the digital signal input to the D/A converter is analog.
  • the digital signal corresponding to the input signal. That is, the analog-to-digital conversion is realized by the way that the output of the DAC successively approaches the input voltage, and the successive approximation process can be referred to FIG.
  • SAR ADC As a key component of the interface between analog module and digital module, SAR ADC is widely used in mobile devices, wireless sensors and other devices. Due to the volume problem and battery life of the device, the analog-to-digital converter is required to have small size and low power consumption. Features are easy to integrate in the circuit of various devices.
  • Figure 3 shows one of the existing DAC capacitor arrays.
  • the capacitors in the capacitor column are not arranged in binary weight according to the capacitance.
  • Each branch is the same unit capacitor due to manufacturing error and capacitance.
  • the area is proportional, and all unit capacitors can reduce the manufacturing error of the unit capacitor.
  • all unit capacitors can reduce the size of the overall capacitor array and reduce power consumption.
  • this solution has a problem of excessive control of the branch, which directly leads to an increase in the size and power consumption of the circuit for control, so that the advantage brought by the reduction of the capacitance area is reduced or even disappeared.
  • FIG. 4 shows another existing DAC capacitor array.
  • the DAC capacitor array is arranged in a binary weighted arrangement according to the capacitance, except for the two unit capacitors on the right side.
  • the circuit power consumption can be effectively reduced by changing the reference voltage of the right unit capacitor.
  • the overall capacitance will be too large, which will increase the power consumption of the circuit and even offset the power consumption of the circuit which is reduced by changing the reference voltage of the right unit capacitor.
  • the embodiments of the present invention provide a DAC capacitor array and an analog-to-digital converter, and a method for reducing the power consumption of an analog-to-digital converter, so as to reduce the size of the overall capacitance in the SAR analog-to-digital converter, thereby reducing the mode.
  • the volume of the digital converter reduces the power consumption.
  • an embodiment of the present invention provides a DAC capacitor array for use in a SAR-type analog-to-digital converter.
  • the DAC capacitor array includes a plurality of sub-capacitor arrays connected in parallel, and each of the sub-capacitor arrays includes:
  • Capacitor group comprising N parallel capacitors, the N being a positive integer
  • One end of each capacitor in the capacitor group is commonly connected to an input end of the comparator, and an input source is connected through the main circuit switch;
  • each capacitor in the capacitor group is connected to a plurality of input sources through a corresponding multiple selection switch.
  • the DAC capacitor array further includes a symmetric capacitor array, and one end of each capacitor in the symmetric capacitor array is commonly connected to another input end of the comparator.
  • the capacitor group includes a high-position capacitor group, a low-position capacitor group, and a compensation capacitor, wherein the compensation capacitor is a unit capacitor, and the number of capacitors of the high-port capacitor group is P, the low-position
  • the number of capacitors of the capacitor group is M, and the P and M are positive integers smaller than the N, and specifically satisfy the following relationship:
  • N M+P+1.
  • the input source includes an analog input signal and a plurality of reference voltages, and the voltage value of the reference voltage ranges from 0 to V R , wherein the reference voltage connected to the high-position capacitor group includes 0. And V R , the reference voltage connected to the low sub-capacitor group includes The value of the V R is adjustable.
  • an embodiment of the present invention provides a SAR type analog-to-digital converter, the analog-to-digital converter including a comparator, a register connected to an output end of the comparator, and a DAC capacitor array connected to an input end of the comparator,
  • the DAC capacitor array comprises:
  • each of the sub-capacitor arrays comprising:
  • Capacitor group including a plurality of capacitors connected in parallel;
  • One end of each capacitor in the capacitor group is commonly connected to an input end of the comparator, and an input source is connected through the main circuit switch;
  • each capacitor in the capacitor group is connected to a plurality of input sources through a corresponding multiple selection switch.
  • the SAR type analog-to-digital converter further includes a symmetric capacitor array, and each of the symmetric capacitor arrays One end of the capacitor is commonly connected to the other input of the comparator.
  • the capacitor group includes a high-position capacitor group, a low-position capacitor group, and a compensation capacitor, wherein the compensation capacitor is a unit capacitor, and the number of capacitors of the high-port capacitor group is P, the low-position
  • the number of capacitors of the capacitor group is M, and the P and M are positive integers smaller than the N, and specifically satisfy the following relationship:
  • N M+P+1.
  • the input source includes an analog input signal and a plurality of reference voltages, and the voltage value of the reference voltage ranges from 0 to V R , wherein the reference voltage connected to the high-position capacitor group includes 0. And V R , the reference voltage connected to the low sub-capacitor group includes The value of the V R is adjustable.
  • the capacitance values of the capacitors in the high-position capacitor group are H P , H P-1 , . . . , H 2 , H 1 in the low-position capacitor group.
  • the capacitance values of the capacitors are L M , L M-1 ,..., L 2 , L 1 in sequence;
  • the value satisfies the equivalence ratio of the ratio of 2.
  • an embodiment of the present invention provides a method for reducing power consumption of a SAR analog-to-digital converter, including:
  • the DAC capacitor array is connected to one end of the comparator input terminal to access the reference voltage through the main circuit switch. And connecting the other end of the DAC capacitor array to the analog input signal through a corresponding multiple selection switch to complete sampling;
  • the main switch of the DAC capacitor array is turned off, and the multi-selection switch is disconnected from the analog input signal and connected to the reference voltage. Comparing a terminal voltage of the DAC capacitor array connected to the input end of the comparator with a voltage of the other input end of the comparator, determining a value of the highest bit according to the comparison result, and selecting a corresponding sub-capacitor array according to the value of the highest bit, The second highest bit and the lowest bit value are obtained in the selected sub-capacitor array.
  • selecting the corresponding sub-capacitor array according to the value of the highest bit includes:
  • the unselected sub-capacitor array is connected to the reference voltage 0 or the reference voltage V R .
  • the obtaining the value of the next highest bit and the lowest bit in the selected sub-capacitor array includes:
  • the DAC capacitor array and the analog-to-digital converter provided by the embodiments of the present invention and the method for reducing the power consumption of the analog-to-digital converter, the DAC capacitor array is optimized by adjusting the reference voltage of each capacitor connection of the DAC capacitor array, and the DAC capacitor array is reduced.
  • the overall capacitance size reduces the size of the SAR analog-to-digital converter, reduces power consumption, and reduces chip cost in chip manufacturing.
  • the voltage variation range across the capacitor is reduced, which in turn reduces the overall power consumption.
  • Figure 1 is a schematic diagram of the conversion of a SAR analog-to-digital converter.
  • FIG. 2 is a schematic diagram of a successive approximation process of a SAR type analog-to-digital converter.
  • FIG. 5 is a schematic diagram of a DAC capacitor array according to an embodiment of the present invention.
  • FIG. 6 is a diagram showing a DAC capacitor array for a four-bit SAR type analog-to-digital converter according to an embodiment of the present invention.
  • FIG. 7 is a diagram of a conversion process according to an embodiment of the present invention.
  • references to "an embodiment” herein mean that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the invention.
  • the appearances of the phrases in various places in the specification are not necessarily referring to the same embodiments, and are not exclusive or alternative embodiments that are mutually exclusive. Those skilled in the art will understand and implicitly understand that the embodiments described herein can be combined with other embodiments.
  • the DAC capacitor array provided in FIG. 5 for use in a SAR type analog to digital converter.
  • the DAC capacitor array provided by the embodiment of the present invention combines and changes two known DAC capacitor arrays described in the prior art, and proposes a DAC capacitor array arranged in a binary weighted arrangement manner and adopts
  • the DAC capacitor array between the DAC capacitor arrays of the unit capacitors includes a plurality of sub-capacitor arrays connected in parallel.
  • the DAC capacitor array provided by the embodiment of the present invention is divided into a plurality of identical sub-capacitors. Capacitor array section.
  • each of the sub-capacitor arrays includes:
  • Capacitor group comprising N parallel capacitors, the N being a positive integer
  • each capacitor in the capacitor group is commonly connected to an input end of the comparator, and an input source is connected through the main circuit switch for convenience of description, and one end of each capacitor commonly connected to the input end of the comparator is called a common end;
  • each capacitor in the capacitor group is connected to a plurality of input sources through corresponding multi-way selection switches, which is convenient for description.
  • the other end of each capacitor is called a free end, and the free end can be switched between multiple input sources. .
  • the SAR type analog-to-digital converter using the above capacitor array is a single-ended SAR type analog-to-digital converter having only one analog input and being sampled to the DAC capacitor array.
  • a symmetric capacitor array is further included, and one end of each capacitor in the symmetric capacitor array is commonly connected to another input end of the comparator.
  • the analog-to-digital converter including the symmetric capacitor array is a differential analog-to-digital converter, and correspondingly, two inputs V ip and V in , V ip and V in are respectively sampled onto two symmetric capacitor arrays, and The two input terminals of the comparator are respectively connected, wherein the capacitor array of the input V ip is connected to the positive phase input terminal of the comparator, and the capacitor array of the input V in is connected to the inverting input terminal of the comparator.
  • the capacitor group may be divided into a high-position capacitor group, a low-position capacitor group, and a compensation capacitor, wherein the compensation capacitor is a unit.
  • the number of capacitors of the high-position capacitor group is P
  • the number of capacitors of the low-port capacitor group is M
  • the P and M are smaller than the positive integer of the N, specifically, the value range of M It is 0 to N
  • the N, P, and M satisfy the following relationship:
  • N M+P+1.
  • capacitors are unit capacitors, and the non-unit capacitors are arranged in a binary weighted manner according to the size of the capacitors.
  • the capacitances in the sub-capacitor array may also be arranged in a binary weighted arrangement.
  • the input source comprises an analog input signal and a plurality of reference voltages, the voltage value of the reference voltage range of 0 ⁇ V R, the reference voltage wherein the upper sub-capacitor group are connected comprise 0 , And V R , the reference voltage connected to the low sub-capacitor group includes The value of the V R is adjustable.
  • the capacitance values of the capacitors in the high-position capacitor group are H P , H P-1 , . . . , H 2 , H 1 in the low-position capacitor group.
  • the capacitance values of the capacitors are L M , L M-1 , . . . , L 2 , L 1 in sequence; as an alternative to the embodiment, the capacitance bits are arranged from high to low, H P-1 V R , H 2 V R ,...,H 2 V R ,H 1 V R , The value satisfies the equivalence ratio of the ratio of 2.
  • the capacitance bits are arranged from high to low, H P-1 V R , H 2 V R , ..., H 2 V R , H 1 V R ,
  • the numerical value can also satisfy the equivalence relation that the ratio is an arbitrary positive integer, or the equivalence relation cannot be satisfied.
  • the DAC capacitor array used is divided into two identical sub-capacitor array portions, respectively sub-capacitors.
  • Array I and sub-capacitor array II, sub-capacitor array I and sub-capacitor array II can be similar to the unit capacitance in FIG. 3 of the background art.
  • the size of the reference voltage connected to the low sub-capacitor group affects the division of the high sub-capacitor group and the low sub-capacitor group in the sub-capacitor array and the values of the capacitors in the sub-capacitor array, or the high-sub capacitor in the sub-capacitor array.
  • the division of the group and the low sub-capacitor group will affect the magnitude of the reference voltage to which the low sub-capacitor bank is connected and the value of each capacitor in the sub-capacitor array.
  • the sub-capacitor array including four capacitors is shown in FIG. 6.
  • the high-port capacitor group includes C1 and C2
  • the low-port capacitor group includes C3, according to H P-1 V R , H 2 V R ,..., H 2 V R , H 1 V R
  • the value satisfies the equivalence ratio of the ratio of 2, at which point C1 will become C, C2 will become 2C, and C3 and C4 will remain unchanged.
  • the above values may not satisfy the equivalence relationship of the ratio of 2, or may satisfy the equivalence relationship of the ratios to other values.
  • the value of the reference voltage is different, which will affect the value of each capacitor in the sub-capacitor array.
  • the capacitance of the DAC capacitor array can be changed by adjusting the reference voltage, thereby reducing the unit capacitance of the DAC capacitor array.
  • the capacitances of the capacitors may be arranged in a binary manner or may not be arranged in a binary manner.
  • a SAR type analog to digital converter comprising the DAC capacitor array described in the above embodiments.
  • FIG. 7 a method for reducing power consumption of a SAR type analog-to-digital converter is provided.
  • C is the size of the capacitor and V is the magnitude of the voltage change on the capacitor.
  • the capacitance is determined by noise and matching. Noise means that the thermal noise of the resistor enters the capacitor through the sampling phase and is superimposed on the useful signal.
  • the matching refers to the difference between the size of the capacitor and the design size due to the limited precision in the manufacturing process, resulting in the ratio of any two capacitors.
  • the problem that the manufacturing value is different from the design value affects the accuracy of the ADC to some extent; the voltage is determined by the dynamic range of the ADC, specifically the input voltage range of the ADC.
  • a method for reducing power consumption of a SAR analog-to-digital converter includes:
  • sampling stage connecting the DAC capacitor array to one end of the comparator input terminal to access the reference voltage through the main circuit switch And the other end of the DAC capacitor array is connected to the analog input signal through a corresponding multi-path selection switch to complete sampling; specifically, the sampling may be an upper plate sampling or a lower plate sampling, wherein the upper pole
  • the sampling of the board means that the sampling signal is connected to the input of the comparator at the same time.
  • the sampling of the lower board means that the sampling signal and the input of the comparator are respectively connected to the two ends of the sampling capacitor.
  • the high order result of the SAR type analog-to-digital converter determines which sub-capacitor array is performed in the low-order conversion.
  • the DAC capacitor array includes a sub-capacitor array I and a sub-capacitor array II, specifically, if the highest bit is 1, Low level conversion In the sub-capacitor array I; otherwise, if the highest bit is 0, the low-order conversion is performed in the sub-capacitor array II.
  • the values of the remaining bits are determined according to the result of the upper two bits, there will be four sub-capacitor arrays. Specifically, one of the four sub-capacitor arrays is selected according to the result of the upper two bits to determine the digital signal to be output. The values of the rest of you.
  • the selecting the corresponding sub-capacitor array according to the value of the highest bit includes:
  • the unselected sub-capacitor array is connected to the reference voltage 0 or the reference voltage V R .
  • the high-order result of the SAR-type analog-to-digital converter also determines the reference voltage to which the capacitance of each sub-capacitor array is to be connected. Referring now to a specific example, referring to the DAC capacitor array for a four-bit SAR type analog-to-digital converter shown in FIG.
  • the DAC capacitor array includes a sub-capacitor array I and a sub-capacitor array II, specifically, if the highest bit is 1, Then the sub-capacitor array II will be connected to the reference voltage 0, while the low-order conversion is performed in the sub-capacitor array I; conversely, if the highest bit is 0, the capacitance in the sub-capacitor array I will be connected to the reference voltage V R while low The conversion is performed in the sub-capacitor array II.
  • the obtaining the second highest bit and the lowest bit value in the selected sub-capacitor array includes:
  • the DAC capacitor array can extend any number of sub-capacitor arrays, and the high bit value of the SAR-type analog-to-digital converter using the extended new DAC capacitor array determines which sub-capacitor array is converted in the low-order array.
  • the method for reducing the power consumption of the SAR analog-to-digital converter described in the above embodiments will be described in detail with reference to a specific example.
  • the four-bit SAR analog-to-digital converter uses the DAC capacitor array shown in Figure 6.
  • C1 and C5 are the highest bits in the sub-capacitor array, assuming that the dynamic range of the SAR-type mode converter is from V R to 0. .
  • the DAC capacitor array is divided into two identical sub-capacitor arrays, and the two identical sub-capacitor arrays can be viewed as the unit capacitor in Figure 3 in the background.
  • the free end of the DAC capacitor array shown in Figure 6 is connected to the analog signal V i through a multiplexer; meanwhile, the common terminal of the capacitor is connected to the reference voltage. And connected to the input of the comparator; the input voltage V i is sampled to the free end of each capacitor in the DAC capacitor array shown in FIG.
  • the point voltage V X of the common terminal can be obtained as:
  • V X V R -V i ;
  • V X ratio Large If V X ratio Large, then the free end of the sub-capacitor array II will be connected to the reference voltage 0, which is the reference ground. At this time, the common end point voltage is changed to V X V X ', can be obtained by charge conservation V X' is:
  • V X ratio Small If V X ratio Small, then the free ends of the sub-capacitor array I are all connected to the reference voltage V R . At this time, V X is changed to V X ', can be obtained by charge conservation V X' is:
  • the DAC capacitor array included is divided into four 10-bit capacitor arrays and referenced to the last 4-bit capacitor of each subsequent 10-bit capacitor array. The voltage was changed to the original 1/8. Specifically, that is, the DAC capacitor array is composed of four identical sub-capacitor arrays, and the high two-bit result of the SAR-type analog-to-digital converter determines that the lower 10 bits are performed in one of the four unit capacitor arrays.
  • the sub-capacitor arrays that calculate the lower 10 bits are not arranged in the traditional 2 9 C, 2 8 C, 2 7 C...2C, C, C manner, but in accordance with 2 6 C, 2 5 C, 2 4 C...C
  • the way, 4C, 2C, C, C are arranged.
  • the lower part 4C, 2C, C, C is connected according to the comparison result of the bit (corresponding to the bit ADC result) Or a reference voltage of zero.
  • Other capacitors are connected according to the comparison result of this bit (corresponding to the bit ADC result) Or a reference voltage of zero.
  • the capacitor arrangement in the high-precision SAR analog-to-digital converter can be optimized for different process parameters by calculation, thereby achieving the purpose of reducing power consumption and chip area.
  • the DAC capacitor array and the analog-to-digital converter provided by the embodiments of the present invention and the method for reducing the power consumption of the analog-to-digital converter can reduce the number of capacitors in the capacitor array and reduce the overall capacitance of the DAC capacitor array by optimizing the DAC capacitor array.
  • the size which reduces the size of the SAR analog-to-digital converter, reduces power consumption, and reduces chip cost in chip manufacturing.
  • the voltage variation range across the capacitor is reduced, which in turn reduces the overall power consumption.

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Abstract

一种DAC电容阵列及模数转换器、降低模数转换器功耗的方法，所述DAC电容阵列包括多个并联的子电容阵列，所述每个子电容阵列包括：电容组：包括N个并联的电容，所述N为正整数；主路开关及多个多路选择开关；所述电容组中各电容的一端共同连接于比较器的输入端，并通过所述主路开关连接一个输入源；所述电容组中各电容的另一端通过相应的多路选择开关连接于多个输入源。通过调整DAC电容阵列各电容连接的参考电压，对DAC电容阵列进行优化，可降低DAC电容阵列的整体电容大小，从而减小SAR型模数转化器的体积，降低功耗，同时在芯片制造中可降低芯片成本。

Description

DAC电容阵列及模数转换器、降低模数转换器功耗的方法 【技术领域】
本发明实施例属于集成电路领域，尤其涉及一种DAC电容阵列及模数转换器、降低模数转换器功耗的方法。
【背景技术】
逐次逼近型模数转换器(Successive Approximation Analog-to-digital converter，SAR ADC)可以将模拟信号转化为数字信号，参考图1，其由比较器、寄存器以及数模转化器(Digital-to-analog converter，DAC)组成，其将模拟信号转换为数字信号转换的基本原理是：将待转换的模拟输入信号与一个参考信号进行比较，参考信号由一个D/A转换器的输出获得，根据二者大小决定增大还是减小D/A转换器输入的数字信号，以使参考信号向模拟输入信号逼进，当参考信号与模拟输入信号相等时，向D/A转换器输入的数字信号就是模拟输入信号对应的数字信号。即通过DAC的输出逐次逼近输入电压的方式来实现模数转换，其逐次逼近过程可参考图2。
SAR型ADC作为模拟模块和数字模块之间接口的关键部件，广泛应用于移动设备、无线传感器等设备中，由于设备的体积问题以及续航问题，要求模数转换器具有体积小，低功耗的特点，便于集成在各种设备的电路中。
现有技术中有两类用于SAR型模数转化器的DAC电容阵列，如图3及图4所示，
其中图3所示为其中一种现有的DAC电容阵列，图示电容整列中各电容没有根据电容大小按照二进制加权排列，每个支路都是相同的单位电容，由于制造误差跟电容大小或面积成正比，全部采用单位电容可以降低对单位电容制造误差的要求。相对于根据电容大小按照二进制加权排列的电容阵列，全部采用单位电容可以降低整体电容阵列的大小，减小功耗。然而该方案存在控制支路过多的问题，直接导致用于控制的电路大小跟功耗都会增加，使得电容面积降低带来的优势降低甚至消失。
其中图4所示为另一种现有的DAC电容阵列，图示DAC电容阵列除了右侧的两个单位电容以外，其他电容根据电容大小按照二进制加权排列的方式排布。对于该DAC电容阵列，通过改变右侧单位电容的参考电压，可以有效降低电路功耗。然而如果按照二进制加权排列的方式排布的电容过多时，会导致整体电容的大小过大，增加电路功耗，甚至会抵消通过改变右侧单位电容的参考电压所降低的电路功耗。
【发明内容】
有鉴于此，本发明实施例提供一种DAC电容阵列及模数转换器、降低模数转换器功耗的方法，以减小SAR型模数转换器中整体电容的大小，从而达到减小模数转化器的体积，降低功耗的目的。
第一方面，本发明实施例提供一种DAC电容阵列，用于SAR型的模数转化器中，所述DAC电容阵列包括多个并联的子电容阵列，所述每个子电容阵列包括：
电容组：包括N个并联的电容，所述N为正整数；
主路开关及多个多路选择开关；
所述电容组中各电容的一端共同连接于比较器的输入端，并通过所述主路开关连接一个输入源；
所述电容组中各电容的另一端通过相应的多路选择开关连接于多个输入源。
进一步的，所述DAC电容阵列还包括一个对称电容阵列，所述对称电容阵列中各电容的一端共同连接于所述比较器的另一输入端。
进一步的，所述电容组包括高位子电容组、低位子电容组和一个补位电容，其中所述补位电容为单位电容，所述高位子电容组的电容个数为P，所述低位子电容组的电容个数为M，所述P和M为小于所述N的正整数，具体满足如下关系：
N＝M+P+1。
进一步的，所述输入源包括模拟输入信号和多个参考电压，所述参考电压的电压值范围为0～VR，其中，所述高位子电容组所连接的参考电压包括0，
Figure PCTCN2016103185-appb-000001
和VR，所述低位子电容组所连接的参考电压包括
Figure PCTCN2016103185-appb-000002
所述VR的值可调。
第二方面，本发明实施例提供一种SAR型模数转换器，所述模数转换器包括比较器，连接于比较器输出端的寄存器，以及连接于所述比较器的输入端的DAC电容阵列，其中，所述DAC电容阵列包括：
多个并联的子电容阵列，所述每个子电容阵列包括：
电容组：包括多个并联的电容；
主路开关及多个多路选择开关；
所述电容组中各电容的一端共同连接于比较器的输入端，并通过所述主路开关连接一个输入源；
所述电容组中各电容的另一端通过相应的多路选择开关连接于多个输入源。
进一步的，所述SAR型模数转换器还包括一个对称电容阵列，所述对称电容阵列中各 电容的一端共同连接于所述比较器的另一输入端。
进一步的，所述电容组包括高位子电容组、低位子电容组和一个补位电容，其中所述补位电容为单位电容，所述高位子电容组的电容个数为P，所述低位子电容组的电容个数为M，所述P和M为小于所述N的正整数，具体满足如下关系：
N＝M+P+1。
进一步的，所述输入源包括模拟输入信号和多个参考电压，所述参考电压的电压值范围为0～VR，其中，所述高位子电容组所连接的参考电压包括0，
Figure PCTCN2016103185-appb-000003
和VR，所述低位子电容组所连接的参考电压包括
Figure PCTCN2016103185-appb-000004
所述VR的值可调。
进一步的，按照电容位从高到低排布，所述高位子电容组中各电容的容值依次为HP，HP-1，…，H2，H1；所述低位子电容组中各电容的容值依次为LM，LM-1，…，L2，L1；其中：
Figure PCTCN2016103185-appb-000005
的数值满足比值为2的等比关系。
第三方面，本发明实施例提供一种降低SAR型模数转化器功耗的方法，包括：
采样阶段，将所述DAC电容阵列接入比较器输入端的一端通过主路开关接入参考电压
Figure PCTCN2016103185-appb-000006
并将所述DAC电容阵列的另一端通过相应的多路选择开关连接于模拟输入信号，完成采样；
转换阶段，将所述DAC电容阵列的主路开关断开，同时将所述多路选择开关与模拟输入信号断开后连接至参考电压
Figure PCTCN2016103185-appb-000007
将所述DAC电容阵列连接至比较器输入端的端电压与所述比较器另一输入端的电压进行比较，根据比较结果确定最高位的值，根据所述最高位的值选择对应的子电容阵列，并在选定的子电容阵列中获取次高位以及最低位的值。
进一步的，所述根据所述最高位的值选择对应的子电容阵列包括：
在选定子电容阵列后，将非选定的子电容阵列接入参考电压0或者参考电压VR。
进一步的，其特征在于，所述在选定的子电容阵列中获取次高位以及最低位的值包括：
根据所述DAC电容阵列连接至比较器输入端的端电压与所述比较器另一输入端的电压的比较结果调整所述选定的子电容阵列中各电容的参考电压为
Figure PCTCN2016103185-appb-000008
或
Figure PCTCN2016103185-appb-000009
其中M为所述选定的子电容阵列中低位子电容组的电容个数。
通过本发明实施例提供的DAC电容阵列及模数转换器、降低模数转换器功耗的方法，通过调整DAC电容阵列各电容连接的参考电压，对DAC电容阵列进行优化，降低DAC电容阵列的整体电容大小，从而减小SAR型模数转化器的体积，降低功耗，同时在芯片制造中可降低芯片成本。此外通过改变模拟信号与数字信号之间的转换过程，减小电容两端的电压变化范围，继而降低整体功耗。
【附图说明】
为了更清楚地说明本发明或现有技术中的方案，下面将对实施例或现有技术描述中所需要使用的附图作一个简单介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为SAR型模数转换器的转换原理图。
图2为SAR型模数转换器的逐次逼近过程示意图。
图3为现有技术中的一种DAC电容阵列。
图4为现有技术中的另一种DAC电容阵列。
图5为本发明实施例提供的DAC电容阵列。
图6为本发明实施例提供的用于四位SAR型模数转换器的DAC电容阵列。
图7为本发明实施例提供的转换过程图。
【具体实施方式】
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例，附图中给出了本发明的较佳实施例。本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例，相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本发明的说明书和权利要求书及上述附图中的术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本发明的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
在本发明实施例中，参考图5提供的DAC电容阵列，所述DAC电容阵列用于SAR型的模数转化器中。具体地，本发明实施例提供的DAC电容阵列，通过对背景技术中所述两种已知DAC电容阵列进行结合和改变，提出一种介于采用二进制加权排列的方式排列的DAC电容阵列与采用单位电容的DAC电容阵列之间的DAC电容阵列，该DAC电容阵列包括多个并联的子电容阵列，从图5中可以看到，本发明实施例提供的DAC电容阵列被分成多个相同的子电容阵列部分。可以把这些相同的子电容阵列类似作为背景技术图3当中的单位电容，而在每个子电容阵列的内部，各电容又是根据电容大小按照二进制加权排列的方式排布组成电容阵列。具体地，所述每个子电容阵列包括：
电容组：包括N个并联的电容，所述N为正整数；
主路开关及多个多路选择开关；
所述电容组中各电容的一端共同连接于比较器的输入端，并通过所述主路开关连接一个输入源，便于描述，将各电容共同连接于比较器的输入端的一端称为公共端；
所述电容组中各电容的另一端通过相应的多路选择开关连接于多个输入源，便于描述，将各电容的另一端称为自由端，自由端可在多个输入源之间切换连接。
采用上述电容阵列的SAR型模数转化器为单端SAR型模数转换器，其模拟输入只有一个，且被采样到所述DAC电容阵列。
在本发明实施例中，还包括一个对称电容阵列，所述对称电容阵列中各电容的一端共同连接于所述比较器的另一输入端。具体地，包含对称电容阵列的模数转换器为差分模数转化器，相应地有两路输入Vip跟Vin，Vip跟Vin会分别被采样到两个对称的电容阵列上，并分别接入比较器的两个输入端，其中输入Vip的电容阵列接入比较器正相输入端，输入Vin的电容阵列接入比较器反相输入端。
在本发明实施例中，所述子电容阵列包含的多个电容中，可将所述电容组划分为高位子电容组、低位子电容组和一个补位电容，其中所述补位电容为单位电容，所述高位子电容组的电容个数为P，所述低位子电容组的电容个数为M，所述P和M为小于所述N的正整数，具体地，M的取值范围为0～N，所述N，P，M满足如下关系：
N＝M+P+1。
其中三个电容为单位电容，非单位电容根据电容大小以二进制加权排列的方式排列。优选地，所述子电容阵列中的电容也可以不以二进制加权排列的方式排列。
在本发明实施例中，所述输入源包括模拟输入信号和多个参考电压，所述参考电压的电压值范围为0～VR，其中，所述高位子电容组所连接的参考电压包括0，
Figure PCTCN2016103185-appb-000010
和VR，所述低位子电容组所连接的参考电压包括
Figure PCTCN2016103185-appb-000011
所述VR的值可调。
进一步的，按照电容位从高到低排布，所述高位子电容组中各电容的容值依次为HP，HP-1，…，H2，H1；所述低位子电容组中各电容的容值依次为LM，LM-1，…，L2，L1；作为本实施例的一种可选方案，按照电容位从高到低排布，HP-1VR，H2VR，…，H2VR，H1VR，
Figure PCTCN2016103185-appb-000012
的数值满足比值为2的等比关系。在本实施例的其它可选实施例中，按照电容位从高到低排布，HP-1VR，H2VR，…，H2VR，H1VR，
Figure PCTCN2016103185-appb-000013
的数值也可以满足比值为任意正整数的等比关系，也可以不满足等比关系。
现以一个具体实例对上述实施例加以说明，参考图6，以4位的SAR型模数转换器为例，那么其采用的DAC电容阵列被分成两个相同子电容阵列部分，分别为子电容阵列I和子电容阵列II，可以把子电容阵列I和子电容阵列II类似作为背景技术图3当中的单位电容，在子电容阵列I和子电容阵列II的内部，其电容个数N＝4，相应的，低位子电容组的电容个数M的取值范围为0～2，高位子电容组的电容个数P＝N-M-1。
具体的，所述低位子电容组连接的参考电压的大小将影响到子电容阵列中高位子电容组和低位子电容组的划分以及子电容阵列中各电容的值，或者说子电容阵列中高位子电容组和低位子电容组的划分将影响到所述低位子电容组连接的参考电压的大小及子电容阵列中各电容的值。
比如图6中所示包含四个电容的子电容阵列，以子电容阵列I为例，如果取所述低位子电容组连接的参考电压为
Figure PCTCN2016103185-appb-000014
即M＝1，高位子电容组包括C1和C2，低位子电容组包括C3，根据HP-1VR，H2VR，…，H2VR，H1VR，
Figure PCTCN2016103185-appb-000015
Figure PCTCN2016103185-appb-000016
的数值满足比值为2的等比关系，此时C1将变为C，C2将变为2C，C3和C4将保持C不变。当然，以上数值也可以不满足比值为2的等比关系，或者可以满 足比值为其他数值的等比关系。可见参考电压取值不同，将影响子电容阵列中各电容的值，基于此原理，可以通过调整参考电压来改变DAC电容阵列的电容大小，从而达到减小DAC电容阵列单位电容的目的。
可选的，在子电容阵列I和子电容阵列II中，各电容的电容大小可以按照二进制方式排列，也可以不按二进制方式排列。
在本发明实施例中，提供一种SAR型模数转换器，所述SAR型模数转换器包括上述实施例中所述的DAC电容阵列。
在本发明实施例中，如图7所示，提供一种降低SAR型模数转换器功耗的方法。
可以知道，对于采用DAC电容阵列的SAR型模数转换器而言，当在DAC电容阵列中开关一个电容时，存在能量消耗，具体的，该能量消耗由以下公式决定：
E＝CV2
其中，C是电容的大小，V是该电容上电压变化量的大小。一般在SAR型ADC中，电容大小是由噪声和匹配来确定。噪声是指电阻热噪声经过采样阶段进入电容，叠加在有用信号上；而匹配是指由于制造过程中的精度有限，制造出的电容大小跟设计大小发生偏移，从而导致任意两个电容大小比例制造值跟设计值不一样的问题，一定程度上影响ADC的精度；电压由所述ADC的动态范围来确定，具体指ADC的输入电压范围。
在本发明实施例中，降低SAR型模数转换器功耗的方法包括：
S1、采样阶段，将所述DAC电容阵列接入比较器输入端的一端通过主路开关接入参考电压
Figure PCTCN2016103185-appb-000017
并将所述DAC电容阵列的另一端通过相应的多路选择开关连接于模拟输入信号，完成采样；具体的，所述采样可以是上极板采样，也可以是下极板采样，其中上极板采样是指采样信号跟比较器的输入同时接到比较器的一端，下极板采样是指采样信号跟比较器输入分别接到采样电容的两端
S2、转换阶段，将所述DAC电容阵列的主路开关断开，同时将所述多路选择开关与模拟输入信号断开后连接至参考电压
Figure PCTCN2016103185-appb-000018
将所述DAC电容阵列连接至比较器输入端的端电压与所述比较器另一输入端的电压进行比较，根据比较结果确定最高位的值。
S3、确定最高位的值后，根据所述最高位的值选择对应的子电容阵列，并在选定的子电容阵列中获取次高位以及最低位的值。
具体地，所述SAR型模数转换器的高位结果决定低位的转换在哪个子电容阵列当中进行。现以具体实例加以说明，参考图6所示用于四位SAR型模数转换器的DAC电容阵列，该DAC电容阵列包括子电容阵列I和子电容阵列II，具体地，如果最高位是1，低位转换 在子电容阵列I中进行；反之，如果最高位是0，低位转换在子电容阵列II中进行。
可选的，如果根据高两位的结果来确定其余各位的数值，将有四个子电容阵列，具体地，根据高两位的结果来选择四个子电容阵列中的一个来确定待输出的数字信号其余各位的数值。
可选的，所述根据所述最高位的值选择对应的子电容阵列包括：
在选定子电容阵列后，将非选定的子电容阵列接入参考电压0或者参考电压VR。
具体地，所述SAR型模数转换器的高位结果也会决定各子电容阵列的电容所要连接的参考电压。现以具体实例加以说明，参考图6所示用于四位SAR型模数转换器的DAC电容阵列，该DAC电容阵列包括子电容阵列I和子电容阵列II，具体地，如果最高位是1，那么子电容阵列II会被连接到参考电压0，同时低位转换在子电容阵列I中进行；反之，如果最高位是0，子电容阵列I中的电容会被连到参考电压VR，同时低位转换在子电容阵列II中进行。
可选的，所述在选定的子电容阵列中获取次高位以及最低位的值包括：
根据所述DAC电容阵列连接至比较器输入端的端电压与所述比较器另一输入端的电压的比较结果调整所述选定的子电容阵列中各电容的参考电压为
Figure PCTCN2016103185-appb-000019
或
Figure PCTCN2016103185-appb-000020
其中M为所述选定的子电容阵列中低位子电容组的电容个数。
可选地，所述DAC电容阵列可以扩展任意多个子电容阵列，采用扩展后新的DAC电容阵列的SAR型模数转换器的高位取值决定低位的转化在哪个子电容阵列中进行。
现以一具体实例对上述实施例所述的降低SAR型模数转换器功耗的方法进行详细说明，请一并参考图6所示DAC电容阵列，以四位SAR型模数转换器为例，该四位SAR型模数转换器采用图6所示的DAC电容阵列，阵列中，C1和C5是子电容阵列中的最高位，假设SAR型模式转换器的动态范围是从VR到0。
从图6中可以看到，DAC电容阵列分成两个相同的子电容阵列，可以把这两个相同的子电容阵列看做背景中图3中的单位电容。
具体地，所述四位SAR型模数转换器进行模数转换的处理过程为：
(1)在采样阶段，图6所示DAC电容阵列的自由端通过多路开关接入模拟信号Vi；同时，电容的公共端接参考电压
Figure PCTCN2016103185-appb-000021
并接到比较器的输入；输入电压Vi被采样到图6所示DAC电容阵列中各电容的自由端。
(2)在转换阶段，DAC电容阵列中各电容的自由端通过多路开关连接到参考电压
Figure PCTCN2016103185-appb-000022
公共端与参考电压
Figure PCTCN2016103185-appb-000023
断开，只接到比较器的输入端。
则根据公共端电荷守恒，可求得公共端的点电压VX为：
VX＝VR-Vi；
(3)比较VX跟
Figure PCTCN2016103185-appb-000024
大小，在本实施例中，C1和C2、C5和C6属于高位部分，C3和C4、C7和C8属于低位部分：
如果VX比
Figure PCTCN2016103185-appb-000025
大，那么子电容阵列II的自由端会全部连到参考电压0，即参考地。此时，公共端的点电压VX改变为VX'，通过电荷守恒可求得VX'为：
Figure PCTCN2016103185-appb-000026
之后求取次高位的值时，只会改变子电容阵列I中各电容自由端连接的参考电压；
如果VX比
Figure PCTCN2016103185-appb-000027
小，那么子电容阵列I的自由端会全部连到参考电压VR。此时，VX改变为VX'，通过电荷守恒可求得VX'为：
Figure PCTCN2016103185-appb-000028
之后求取次高位的值时，只会改变子电容阵列II中各电容自由端连接的参考电压。
(5)之后VX'再跟
Figure PCTCN2016103185-appb-000029
作比较，根据结果改变C1电容自由端连接的参考电压。如果
Figure PCTCN2016103185-appb-000030
C1电容连接地电压，如果
Figure PCTCN2016103185-appb-000031
C1电容连接参考电压VR，对C2重复以上步骤。
(6)之后，根据此时各电容公共端的点电压VX'跟
Figure PCTCN2016103185-appb-000032
的大小关系，改变C3自由端参考电压，跟C1，C2不同的是，此时C3会连接到参考电压
Figure PCTCN2016103185-appb-000033
或者
Figure PCTCN2016103185-appb-000034
同样地，对于C4也是如此。
同样地，以一款12位的SAR型模数转化器为例，其包含的DAC电容阵列被分为了4个10位的电容阵列，同时对于后每个10bit电容阵列的后面4位电容的参考电压，改为了原来的1/8。具体地，也就是说DAC电容阵列是由4个相同的子电容阵列组成，SAR型模数转换器的高两位结果决定低10位在这4个单位电容阵列的某一个中进行。计算低10位的子电容阵列不是按照传统的29C，28C，27C…2C，C，C的方式排布，而是按照26C，25C， 24C…C的方式，4C，2C，C，C排布。其中低位部分4C，2C，C，C根据该位的比较结果(对应该位ADC结果)连接
Figure PCTCN2016103185-appb-000035
或者0的参考电压。其他的电容，根据该位的比较结果(对应该位ADC结果)连接
Figure PCTCN2016103185-appb-000036
或者0的参考电压。
基于上述实施例提供的方法，可以通过计算，针对不同的工艺参数，优化高精度SAR型模数转换器中的电容排布，达到降低功耗跟芯片面积的目的。
通过本发明实施例提供的DAC电容阵列及模数转换器、降低模数转换器功耗的方法，通过对DAC电容阵列的优化，可以减少电容阵列中的电容数量，降低DAC电容阵列的整体电容大小，从而减小SAR型模数转化器的体积，降低功耗，在芯片制造中可降低芯片成本。此外通过改变模拟信号与数字信号之间的转换过程，减小电容两端的电压变化范围，继而降低整体功耗。
以上仅为本发明的实施例，但并不限制本发明的专利范围，尽管参照前述实施例对本发明进行了详细的说明，对于本领域的技术人员来而言，其依然可以对前述各具体实施方式所记载的技术方案进行修改，或者对其中部分技术特征进行等效替换。凡是利用本发明说明书及附图内容所做的等效结构，直接或间接运用在其他相关的技术领域，均同理在本发明专利保护范围之内。

Claims (12)

  1. 一种DAC电容阵列，所述DAC电容阵列用于SAR型模数转化器中，其特征在于，所述DAC电容阵列包括多个并联的子电容阵列，所述每个子电容阵列包括：
    电容组，其包括N个并联的电容，所述N为正整数；
    主路开关及多个多路选择开关；
    所述电容组中各电容的一端共同连接于比较器的输入端，并通过所述主路开关连接一个输入源；
    所述电容组中各电容的另一端通过相应的多路选择开关连接于多个输入源。
  2. 根据权利要求1所述的DAC电容阵列，其特征在于，还包括一个对称电容阵列，所述对称电容阵列中各电容的一端共同连接于所述比较器的另一输入端。
  3. 根据权利要求1或2所述的DAC电容阵列，其特征在于，所述电容组包括高位子电容组、低位子电容组和一个补位电容，其中所述补位电容为单位电容，所述高位子电容组的电容个数为P，所述低位子电容组的电容个数为M，所述P和M为小于所述N的正整数，具体满足如下关系：
    N＝M+P+1。
  4. 根据权利要求3所述的DAC电容阵列，其特征在于，所述输入源包括模拟输入信号和多个参考电压，所述参考电压的电压值范围为0～VR，其中，所述高位子电容组所连接的参考电压包括0，
    Figure PCTCN2016103185-appb-100001
    和VR，所述低位子电容组所连接的参考电压包括
    Figure PCTCN2016103185-appb-100002
    Figure PCTCN2016103185-appb-100003
    所述VR的值可调。
  5. 一种SAR型模数转换器，其特征在于，包括比较器，连接于比较器输出端的寄存器，以及连接于所述比较器的输入端的DAC电容阵列，其中，所述DAC电容阵列包括：
    多个并联的子电容阵列，所述每个子电容阵列包括：
    电容组：包括多个并联的电容；
    主路开关及多个多路选择开关；
    所述电容组中各电容的一端共同连接于比较器的输入端，并通过所述主路开关连接一个输入源；
    所述电容组中各电容的另一端通过相应的多路选择开关连接于多个输入源。
  6. 根据权利要求5所述的SAR型模数转换器，其特征在于，还包括一个对称电容阵 列，所述对称电容阵列中各电容的一端共同连接于所述比较器的另一输入端。
  7. 根据权利要求5或6所述的SAR型模数转换器，其特征在于，所述电容组包括高位子电容组、低位子电容组和一个补位电容，其中所述补位电容为单位电容，所述高位子电容组的电容个数为P，所述低位子电容组的电容个数为M，所述P和M为小于所述N的正整数，具体满足如下关系：
    N＝M+P+1。
  8. 根据权利要求7所述的SAR型模数转换器，其特征在于，所述输入源包括模拟输入信号和多个参考电压，所述参考电压的电压值范围为0～VR，其中，所述高位子电容组所连接的参考电压包括0，
    Figure PCTCN2016103185-appb-100004
    和VR，所述低位子电容组所连接的参考电压包括
    Figure PCTCN2016103185-appb-100005
    Figure PCTCN2016103185-appb-100006
    所述VR的值可调。
  9. 根据权利要求7所述的SAR型模数转换器，其特征在于，按照电容位从高到低排布，所述高位子电容组中各电容的容值依次为HP，HP-1，…，H2，H1；所述低位子电容组中各电容的容值依次为LM，LM-1，…，L2，L1；其中：
    HP-1VR，H2VR，…，H2VR，H1VR，
    Figure PCTCN2016103185-appb-100007
    的数值满足比值为2的等比关系。
  10. 一种降低SAR型模数转换器功耗的方法，其特征在于，包括：
    采样阶段，将所述DAC电容阵列接入比较器输入端的一端通过主路开关接入参考电压
    Figure PCTCN2016103185-appb-100008
    并将所述DAC电容阵列的另一端通过相应的多路选择开关连接于模拟输入信号，完成采样；
    转换阶段，将所述DAC电容阵列的主路开关断开，同时将所述多路选择开关与模拟输入信号断开后连接至参考电压
    Figure PCTCN2016103185-appb-100009
    将所述DAC电容阵列连接至比较器输入端的端电压与所述比较器另一输入端的电压进行比较，根据比较结果确定最高位的值，根据所述最高位的值选择对应的子电容阵列，并在选定的子电容阵列中获取次高位以及最低位的值。
  11. 根据权利要求10所述的降低SAR型模数转换器功耗的方法，其特征在于，所述根据所述最高位的值选择对应的子电容阵列包括：
    在选定子电容阵列后，将非选定的子电容阵列接入参考电压0或者参考电压VR。
  12. 根据权利要求10或11所述的降低SAR型模数转换器功耗的方法，其特征在于， 所述在选定的子电容阵列中获取次高位以及最低位的值包括：
    根据所述DAC电容阵列连接至比较器输入端的端电压与所述比较器另一输入端的电压的比较结果调整所述选定的子电容阵列中各电容的参考电压为
    Figure PCTCN2016103185-appb-100010
    或
    Figure PCTCN2016103185-appb-100011
    其中M为所述选定的子电容阵列中低位子电容组的电容个数。
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