WO2019019058A1 - 动态放大电路 - Google Patents

动态放大电路 Download PDF

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Publication number
WO2019019058A1
WO2019019058A1 PCT/CN2017/094529 CN2017094529W WO2019019058A1 WO 2019019058 A1 WO2019019058 A1 WO 2019019058A1 CN 2017094529 W CN2017094529 W CN 2017094529W WO 2019019058 A1 WO2019019058 A1 WO 2019019058A1
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Prior art keywords
transistor
signal
control signal
voltage
time
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PCT/CN2017/094529
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English (en)
French (fr)
Inventor
范硕
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2017/094529 priority Critical patent/WO2019019058A1/zh
Priority to EP17896327.8A priority patent/EP3461003B1/en
Priority to CN201780000805.8A priority patent/CN109643975B/zh
Priority to US16/110,127 priority patent/US10476443B2/en
Publication of WO2019019058A1 publication Critical patent/WO2019019058A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/297—Indexing scheme relating to amplifiers the loading circuit of an amplifying stage comprising a capacitor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/312—Indexing scheme relating to amplifiers the loading circuit of an amplifying stage comprising one or more switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/447—Indexing scheme relating to amplifiers the amplifier being protected to temperature influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45134—Indexing scheme relating to differential amplifiers the whole differential amplifier together with other coupled stages being fully differential realised
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45631—Indexing scheme relating to differential amplifiers the LC comprising one or more capacitors, e.g. coupling capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45726—Indexing scheme relating to differential amplifiers the LC comprising more than one switch, which are not cross coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • Embodiments of the present application relate to the field of circuits and, more particularly, to dynamic amplification circuits.
  • Dynamic Amplifier has low power consumption and no overshoot compared to traditional feedback-based op amp implementations.
  • the gain of a dynamic amplifier varies with, for example, semiconductor process, supply voltage, and temperature (Process, Voltage, Temperature, PVT), which limits its application to some extent.
  • the present application provides a dynamic amplification circuit that provides a relatively stable gain.
  • a dynamic amplification circuit comprising:
  • a first driving circuit configured to receive a first control signal, generate a first voltage signal and a second voltage signal, the first voltage signal changes with time, and the second voltage signal is a constant voltage
  • a second driving circuit configured to receive the first voltage signal and the second voltage signal to generate a first driving signal
  • a third driving circuit configured to receive the first control signal and the first driving signal to generate a second control signal
  • a dynamic amplifier DA comprising a first control switch, a second control switch and a transistor
  • the DA is configured to receive the first control signal and the second control signal, and respectively control the first control switch and the second control switch by using the first control signal and the second control signal Closing and disconnecting;
  • the first control signal is at a high level, the voltage value output by the first voltage signal is a first voltage value, and the voltage value output by the second voltage signal is a second voltage value.
  • Said second control signal is low level;
  • the first control signal In a second period of time after the first period of time, the first control signal is at a low level, and a voltage value output by the first voltage signal begins to increase, but is smaller than the second voltage value. Narrative a driving signal is low level, and the second control signal is high level;
  • the first control signal is a low level, and the voltage value output by the first voltage signal is greater than or equal to the second voltage value, the first The driving signal is at a high level, and the second control signal is at a low level;
  • the duration of the second period of time is inversely proportional to the transconductance of the transistor in the DA in the saturation region.
  • the dynamic amplifying circuit of the embodiment of the present application controls the voltage value of the output of the first voltage signal and the second voltage signal through the first control signal, and further controls the first voltage signal and the second voltage signal according to the first control signal.
  • the duration of the two time periods is inversely proportional to the transconductance of the transistor in the DA in the saturation region, so that the dynamic amplification circuit can still provide a relatively stable gain when the PVT changes.
  • the first driving circuit includes:
  • a first bias circuit configured to receive the first control signal to generate the first voltage signal
  • the first bias circuit includes a first transistor, a first current source and a first capacitor, a drain of the first transistor is connected to the first current source, and one end of the first capacitor is connected to a drain of the first transistor And connecting, by a first switching device, a gate of the first transistor, a source of the first transistor is connected to another end of the first capacitor, and a drain of the first transistor is used to output the first a voltage signal;
  • the second bias circuit includes a second transistor and a second current source, a drain of the second transistor is connected to the second current source, a drain of the second transistor and a gate of the second transistor Connecting, the drain of the second transistor is configured to output the second voltage signal;
  • the transistors of the first transistor and the second transistor have the same parameter, and the current value of the second current source is greater than the current value of the first current source.
  • the first control signal is further configured to control closing and opening of the first switching device
  • the first control signal is specifically used to:
  • the first switching device In the first period of time, the first switching device is controlled to be closed, and in the second period of time and the third period of time, the first switching device is controlled to be turned off.
  • the first transistor In conjunction with the first aspect, in a possible implementation of the first aspect, the first transistor The transistor parameters of the second transistor and the transistor of the DA are the same.
  • the first transistor and the second transistor are metal oxide semiconductor MOS transistors.
  • the first transistor and the transistor of the DA are supplied with current by a mirrored current source.
  • the second driving circuit includes a second capacitor, a first inverter, and a second inverter;
  • One end of the second capacitor receives the first voltage signal through a second switching device, and receives the second voltage signal through a third switching device, the other end of the second capacitor and the first inverter Input connection;
  • An input end and an output end of the first inverter are connected by a fourth switching device, and an output end of the first inverter is connected to an input end of the second inverter, the second inverter The output is for outputting the first drive signal.
  • the first control signal is further used to:
  • the first control signal is specifically used to:
  • the second driving circuit is a continuous time comparator, and the first input end of the connection time comparator is configured to receive the first voltage signal The second input of the connection time comparator is configured to receive the second voltage signal, and an output of the continuous time comparator is configured to output the first driving signal.
  • the third driving circuit includes a third inverter, a fourth inverter, and a summing circuit;
  • An input end of the third inverter is configured to receive the first control signal, and an output end of the third inverter is connected to a first input end of the summing circuit;
  • An input end of the fourth inverter is configured to receive the first driving signal, and an output end of the fourth inverter is connected to a second input end of the sourcing circuit;
  • An output of the summing circuit is for outputting the second control signal.
  • the DA further includes a third capacitor, one end of the third capacitor is connected to a negative pole of the power source, and the other end of the third capacitor is passed through
  • the first control switch is connected to the positive terminal of the power source, the other end of the capacitor is further connected to one end of the second control switch, and the other end of the second control switch is connected to the drain of the transistor;
  • the first control signal is specifically used to:
  • Controlling in the first period of time, that the first control switch is closed, and in the second time period and the third time period, controlling the first control switch to be turned off;
  • the second control signal is specifically used to:
  • the voltage value obtained by subtracting the threshold voltage of the second transistor from the second voltage value is the first voltage value minus the first A multiple of the voltage value obtained by the threshold voltage of a transistor.
  • the dynamic amplifying circuit of the embodiment of the present application controls the voltage value of the output of the first voltage signal and the second voltage signal through the first control signal, and further controls the first voltage signal and the second voltage signal according to the first control signal.
  • the duration of the two time periods is inversely proportional to the transconductance of the transistor in the DA in the saturation region, so that the dynamic amplification circuit can still provide a relatively stable gain when the PVT changes.
  • 1 is a schematic structural view of a conventional dynamic amplifying circuit.
  • FIG. 2 is a logic timing diagram of a conventional dynamic amplifying circuit.
  • 3 is an equivalent circuit diagram of a conventional dynamic amplifier circuit.
  • FIG. 4 is a schematic diagram of a dynamic amplification circuit in accordance with an embodiment of the present application.
  • FIG. 5 is a logic timing diagram of a dynamic amplification circuit in accordance with an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an example of a first driving circuit according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an example of a second driving circuit according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another example of a second driving circuit according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an example of a third driving circuit according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a conventional dynamic amplifier.
  • the dynamic amplifier 100 has a symmetrical structure, and the right half structure and the left half structure include devices and the parameters of the device are the same.
  • the left half structure is taken as an example.
  • the working state of the device in the right half structure is the same as the working state of the corresponding device in the left half structure, and details are not described herein again.
  • the dynamic amplifier 100 includes a transistor 110, a capacitor 120, a first control switch 130, and a second control switch 140.
  • the operating state of the dynamic amplifier 100 includes two phases:
  • the first control switch 130 is closed, the second control switch 140 is opened, the capacitor 120 is connected to the positive pole (V CC ) of the power source, and the capacitor is in a charged state;
  • the first control switch 130 is turned off, the second control switch 140 is closed, and the capacitor 120 is connected to the drain of the transistor 110 through the second control switch 140, and the capacitor is in a discharged state.
  • V out 140 is a logic timing diagram of the dynamic amplifier 100, in which For the timing of the first control switch 130, The timing for the output voltage of the second control switch timing, V out 140 of.
  • the first control switch 130 in the first phase (denoted as T R ), the first control switch 130 is closed, the second control switch 140 is open, the dynamic amplifier is in a reset state; in the second phase (denoted as T A The first control switch 130 is turned off, the second control switch 140 is closed, the dynamic amplifier is in an amplified state, and the duration of the dynamic amplification circuit in the amplified state is the duration T A of the second phase.
  • FIG. 3 is an equivalent circuit diagram of the dynamic amplifier shown in FIG. 1, wherein g m is a transconductance of the transistor 110, and C L is a capacitance value of the capacitor 120, which is obtained by FIG. 3, and an amplification factor of the dynamic amplifying circuit ( Gain) Av is shown in equation (1):
  • the embodiment of the present application provides a dynamic amplifying circuit by controlling the second stage.
  • the duration T A can provide a relatively stable gain.
  • the dynamic amplifying circuit 300 includes:
  • the first driving circuit 310 is configured to receive the first control signal, generate a first voltage signal and a second voltage signal, the first voltage signal changes with time, and the second voltage signal is a constant voltage;
  • the second driving circuit 320 is configured to receive the first voltage signal and the second voltage signal to generate a first driving signal
  • the third driving circuit 330 is configured to receive the first control signal and the first driving signal to generate a second control signal
  • a dynamic amplifier DA340 comprising a first control switch, a second control switch and a transistor
  • the DA is configured to receive the first control signal and the second control signal, and control the closing and opening of the first control switch and the second control switch by using the first control signal and the second control signal, respectively;
  • the first control signal and the second control signal respectively correspond to the control signal in FIG. with That is, the first control signal and the second control signal can be used as the control signal in FIG. with And for controlling the first control switch 130 and the second control switch 140 of the DA 100, respectively.
  • the DA 340 may be the DA 100 shown in FIG. 1 or may be other equivalent circuits.
  • the DA 340 may further include a third capacitor, and the third capacitor may correspond to the capacitor 120 in the DA 100 shown in FIG. 1 .
  • One end of the three capacitor is connected to the negative pole of the power source, the other end of the third capacitor is connected to the positive phase of the power supply through the first control switch, the other end of the capacitor is also connected to one end of the second control switch, and the other end of the second control switch is connected to the transistor The drain connection.
  • the first control signal is specifically used to:
  • Controlling by the first time period, that the first control switch is closed, and in the second time period and the third time period, controlling the first control switch to be turned off;
  • the second control signal is specifically used to:
  • the second control switch In the first period of time, the second control switch is controlled to be turned off, in the second period of time, the second control switch is controlled to be closed, and in the third period of time, the second control switch is controlled to be turned off.
  • the first control signal is at a high level, and the first voltage signal V output by the first driving circuit 1 is a first voltage value, the second voltage signal V 2 is a second voltage value, and the first voltage value is less than the second voltage value.
  • the second control signal output by the third driving circuit is at a low level.
  • the first driving signal may output a low level or a high level during the first time period
  • FIG. 5 only uses the first driving signal as a low level. For example, as long as the first control signal is at a high level and the second control signal is at a low level during the first time period.
  • the first control signal is a low level
  • the first voltage signal outputted by the first driving circuit starts to increase, but is still smaller than the second voltage value
  • the second voltage signal is still the second voltage value
  • the second driving circuit is configured according to the first voltage signal and the second voltage.
  • the first driving signal of the signal output is still at a low level
  • the third driving circuit changes from a low level to a high level according to the first control signal and the second control signal output by the first driving signal.
  • the first control signal is a low level
  • the first voltage signal output by the first driving circuit is greater than or equal to the second voltage value
  • the second driving The first driving signal outputted by the circuit changes from a low level to a high level
  • the second control signal outputted by the third driving circuit changes from a high level to a low level.
  • the first driving circuit of the embodiment of the present application may output the first voltage signal V 1 and the second voltage signal V 2 according to the first control signal, wherein, in the first time period, V 1 ⁇ V 2 , During the second time period, V 1 starts to increase, but is still smaller than V 2 . In the third time period, V 1 increases to be greater than or equal to V 2 , that is, the boundary between the second time period and the third time period is The time at which V 1 is equal to V 2 .
  • V 1 may increase to be equal to V 2 and then no longer increase, or may continue to increase to a certain voltage value after being equal to V 2 and then no longer increase, etc.
  • the embodiment of the present application does not limit the magnitude of the voltage value of the first voltage signal in the third time period, as long as the first driving signal is inverted when V 1 is equal to V 2 .
  • the second driving circuit is capable of outputting the first driving signal according to the first voltage signal and the second voltage signal that change with time, that is, when the voltage value of the first voltage signal is less than the voltage value of the second voltage signal, the output is low. And outputting a high level when the voltage value of the first voltage signal is greater than or equal to the voltage value of the second voltage signal.
  • the second drive circuit can be implemented with a comparator, and in particular, the comparator can be a continuous time comparator.
  • the third driving circuit outputs the second control signal according to the first control signal and the first driving signal, wherein the third driving circuit only needs to control when the first control signal and the first driving signal are both low
  • the second control signal outputs a high level, and when the first control signal and the first driving signal are in other states, the second control signal outputs a low level.
  • the third driving circuit can be implemented by a combination circuit of an inverter and an AND gate, for example, After the first control signal and the first driving signal are both inverted, the two inputs are input to the AND gate. At this time, the output of the AND gate can be controlled when both the first control signal and the first driving signal are low. The output of the terminal is high. In other states, the output of the AND gate outputs a low level.
  • equation (1) can be reduced to equation (2):
  • the gain of the dynamic amplifying circuit is only related to the capacitance value, and therefore, the gain of the dynamic amplifying circuit is relatively stable when the PVT changes.
  • the dynamic amplifying circuit of the embodiment of the present application controls the voltage value of the output of the first voltage signal and the second voltage signal by using the first control signal, and further controls the second time period according to the first voltage signal and the second voltage signal.
  • the duration T A is inversely proportional to the transconductance of the transistor in the DA in the saturation region, so that the dynamic amplification circuit can still provide a relatively stable gain when the PVT changes.
  • FIG. 9 to FIG. 9 are intended to help those skilled in the art to better understand the embodiments of the present application, and do not limit the scope of the embodiments of the present application. It will be obvious to those skilled in the art that various modifications and changes can be made without departing from the scope of the embodiments of the present application.
  • the voltage and current of a transistor operating in a saturation region have the following relationship:
  • I D is the drain current of the transistor
  • ⁇ is the carrier mobility
  • C ox is the gate oxide capacitance per unit area
  • W is the width of the gate
  • L is the length of the gate
  • V GS is the gate and The voltage difference of the source
  • V TH is the threshold voltage of the transistor, or the turn-on voltage of the gate and source
  • V ov is the overdrive voltage of the transistor.
  • the calculation formula of the transconductance g m of the transistor can be derived according to the formula (3), as shown in the formula (4):
  • the drain current I D is proportional to (V ov ) 2 , or, after the parameters of the transistor are determined, the voltage drop across the gate and source of the transistor is only related to the current flowing through the transistor.
  • g m is proportional to 2I D /V ov , or, after the parameters of the transistor are determined, the transconductance g m of the transistor is only related to the current flowing through the transistor.
  • I D is proportional to (V ov ) 2
  • g m is proportional to 2I D /V ov is an approximate proportional relationship, which may be slightly affected by factors such as process or environment of the transistor. Deviation, but the deviation is small, and within the acceptable range, it can be considered to be approximately proportional.
  • FIG. 6 is a schematic structural diagram of an example of a first driving circuit according to an embodiment of the present application.
  • FIG. 6 shows a possible implementation manner of the first driving circuit, or a preferred implementation manner, but the embodiment of the present application does not. It is to be understood that the various modifications and variations of the present invention are within the scope of the embodiments of the present application.
  • the first driving circuit 310 includes a first bias circuit 311 and a second bias circuit 312.
  • the first bias circuit 311 includes a first transistor 3111, a first current source 3112, a first capacitor 3113, and a first switching device 3114.
  • the drain (D pole) of the first transistor 3111 is connected to the first current source 3112, one end of the first capacitor 3113 is connected to the drain (D pole) of the first transistor 3111, and is connected to the first transistor 3111 through the first switching device 3114.
  • the gate (S pole), the source (S pole) of the first transistor 3111 is connected to the other end of the first capacitor 3113, and the drain (D pole) of the first transistor 3111 is used to output a first voltage signal.
  • the second bias circuit 312 includes a second transistor 3121 and a second current source 3122.
  • the drain (D pole) of the second transistor 3121 is connected to the second current source 3122, and the drain (D pole) of the second transistor 3121 is connected.
  • the gate (S pole) of the second transistor 3121 is connected, that is, the drain and the gate of the second transistor are short-circuited, and the drain (D pole) of the second transistor 3121 is used to output a second voltage signal.
  • the first current source and the second current source may be implemented by using a mirror current source, so that the second current source and the first current source are ensured to be a multiple relationship.
  • the second transistor 3121 Since the drain and the gate of the second transistor 3121 are connected, the second transistor 3121 operates in the saturation region, and the second voltage signal outputted from the drain of the second transistor 3121 is approximately a constant voltage, denoted as V 2 .
  • the first switching device 3114 is controlled by the first control signal, that is, the first control signal can be used to control the closing and opening of the first switching device 3114. Specifically, in the first period of time, the first control signal is used to control the closing of the first switching device 3114, and during the second period of time and the third period of time, the first control signal is used to control the opening of the first switching device 3114.
  • the current is approximately the current value of the first current source. Therefore, during the first time period, the first voltage signal is approximately a constant voltage.
  • the first switching device 3114 is turned off, the first current source 3112 starts charging the first capacitor 3113, and V 1 starts to increase.
  • V 1 V 2
  • the first driving signal output by the second driving circuit is inverted from a low level to a high level.
  • the duration T A of the second period between time t 2 and time t 3 is the time required for the voltage value of the first capacitor to increase from V T1 to V 2 , and therefore can be determined according to formula (5).
  • T A the duration of the second period between time t 2 and time t 3 is the time required for the voltage value of the first capacitor to increase from V T1 to V 2 , and therefore can be determined according to formula (5).
  • T A (V 2 -V T1 )*C 1 /I 1 Formula (5)
  • C 1 is the capacitance value of the first capacitor 3113.
  • the first transistor 3111 and the second transistor 3121 may adopt the same transistor parameter.
  • parameters such as ⁇ , C ox , W, and L may be the same, then the first transistor and the second transistor.
  • the V TH can be considered equal.
  • V GS1 is the voltage difference between the gate and the source of the first transistor 3111
  • V OV1 is the first transistor
  • V GS2 is the voltage difference between the gate and the source of the second transistor 3121
  • V OV2 is the overdrive voltage of the second transistor 3121.
  • the first transistor may also adopt the same transistor parameter as the transistor in the DA, and the current value of the first current source may also be in multiple relationship with the drain current of the transistor in the DA, for example, by mirroring current
  • the transconductance of the transistor in the transistor and the transconductance of the first transistor are also in a multiple relationship, ie Wherein, g m is the transconductance of the transistors in the DA, g m1 is the transconductance of the first transistor.
  • the amplification factor A v of the dynamic amplification circuit can be obtained as shown in the formula (9):
  • a V 2C 1 /C L
  • I 2 9I 1
  • a V 3C 1 /C L
  • ie A v is only related to the capacitance value, that is, as long as The overdrive voltage V OV1 of the first transistor and the overdrive voltage V OV2 of the second transistor have a multiple relationship to obtain a relatively stable gain.
  • the first transistor and the second transistor may be metal oxide semiconductor (MOS) transistors, for example, an N-channel depletion MOS transistor and an N-channel enhancement MOS.
  • MOS metal oxide semiconductor
  • a transistor, a P-channel depletion MOS transistor, or a P-channel enhancement MOS transistor, etc., the types of the transistors in the drawings of the embodiments of the present application are merely examples, and should not be construed as limiting the embodiments of the present application.
  • the equivalent circuits obtained according to the examples in the drawings all fall within the scope of protection of the embodiments of the present application.
  • FIG. 7 is a schematic structural diagram of an example of a second driving circuit according to an embodiment of the present application.
  • FIG. 7 shows a possible implementation manner of the second driving circuit, or a preferred implementation manner, but the embodiment of the present application does not. It is to be understood that the various modifications and variations of the present invention are within the scope of the embodiments of the present application.
  • the second driving circuit 700 includes a second capacitor 321, a first inverter 322, and a second inverter 323.
  • One end of the second capacitor 321 receives the first voltage signal through the second switching device 324, and Receiving a second voltage signal through the third switching device 325, and connecting the other end of the second capacitor 321 to the input end of the first inverter 322;
  • the input terminal and the output terminal of the first inverter 322 are connected by a fourth switching device 326, the output terminal of the first inverter 322 is connected to the input terminal of the second inverter 323, and the output terminal of the second inverter 323 is output. For outputting the first drive signal.
  • the first control signal is used to:
  • Controlling the second switching device to be turned off, the third switching device and the fourth switching device are closed during the first period of time, controlling the second switching device to be closed during the second period of time and the third period of time, the third switching device and the third The four-switch device is disconnected.
  • the operating state of the switching device controlled by the first control signal is as follows:
  • the first switching device is closed, a third switching device and fourth switching device, a second switching device turned off;
  • the first switching device, the third switching device, and the fourth switching device are turned off, and the second switching device is closed;
  • the second switching device 324 turns off at time t 1
  • the third switching device 325 is closed
  • the fourth switching device 326 is closed
  • the voltage at one end of the second capacitor 321 is V 2
  • the voltage at the other end is the threshold voltage V THINV of the first inverter 322
  • the voltage drop across the second capacitor 321 is V THINV - V 2 .
  • the third driving circuit The output second control signal is low.
  • the second switching device 324 is closed, the third switching device 325 is turned off, and the fourth switching device 326 is turned off, and the voltage at one end of the second capacitor 321 is V 1 , based on the principle of conservation of charge, the voltage drop across the second capacitor 321 is constant, then the voltage at the input of the first inverter is V 1 +V THINV ⁇ V 2 , since in the second period, V 1 ⁇ V 2 , then V 1 +V THINV -V 2 ⁇ V THINV , after passing through the first inverter, outputting a high level, and after passing through the second inverter, the first driving signal outputs a low level.
  • V 1 ⁇ V 2 is V 1 + V THINV -V 2 ⁇ V THINV, through the first inverter, the output low, then after the second inverter After the inverter is reversed, the first drive signal outputs a high level.
  • the embodiment of the present application may also use other equivalent circuits to implement the function of the second driving circuit, that is, if the first voltage signal is less than the second voltage signal, the low level is output, and the first voltage signal is greater than or equal to When the second voltage signal is output, a high level can be output.
  • the first bias circuit may further include an input end of the first control signal for input.
  • the first control signal controls the closing and opening of the first switching device by the first control signal.
  • the second driving circuit may further include an input end of the first control signal for inputting the first control signal, thereby controlling the closing of the second switching device, the third switching device, and the fourth switching device by the first control signal Disconnected, etc.
  • the first control signal is used to control the closing and opening of the first switching device, the second switching device, the third switching device, the fourth switching device, and the first control switch
  • the second The control signal is used to control the closing and opening of the second control switch, and only indicates that the control signal has the function of controlling the corresponding switching device, and does not indicate that the input ends of the control signals must have a direct connection relationship with the corresponding switching devices. As long as the input control signal can be controlled to control the closing and opening of the corresponding switching device.
  • the second driving circuit 320 is a continuous time comparator 327, and the first input terminal of the connection time comparator 327 is used for The first voltage signal V 1 is received, the second input of the connection time comparator is for receiving the second voltage signal V 2 , and the output of the continuous time comparator 327 is for outputting the first drive signal.
  • the continuous time comparator 327 outputs a low level
  • V 1 ⁇ V 2 the output voltage of the continuous time comparator 327 jumps from a low level to a high level.
  • both the continuous time comparator shown in FIG. 8 and the combined circuit shown in FIG. 7 can realize the function of the second driving circuit, that is, outputting a low level when the first voltage signal is smaller than the second voltage signal, at the first voltage When the signal is greater than or equal to the second voltage signal, the high level is output.
  • the combined circuit shown in FIG. 7 does not have to perform continuous comparison with respect to the continuous time comparator shown in FIG. 8, and thus the power consumption is relatively low.
  • FIG. 9 is a schematic structural diagram of an example of a third driving circuit according to an embodiment of the present application, as shown in FIG.
  • the third driving circuit 330 includes a third inverter 331, a fourth inverter 332, and a summing circuit 333.
  • the input end of the third inverter 331 is configured to receive the first control signal, and the output end of the third inverter 331 is connected to the first input end of the summing circuit 333;
  • the input end of the fourth inverter 332 is configured to receive the first driving signal, and the output end of the fourth inverter 332 is connected to the second input end of the summing circuit 333;
  • the output of the summing circuit 333 is for outputting a second control signal.
  • the second control signal outputs a high level only when both the first control signal and the first driving signal are at a low level, and when the first control signal and the first driving signal are in other working states, the second control The signal output is low.
  • the summing circuit 333 can be implemented with an AND gate, or other equivalent circuit.
  • the dynamic amplifying circuit of the embodiment of the present application controls the voltage value of the output of the first voltage signal and the second voltage signal by using the first control signal, and further controls the second time period according to the first voltage signal and the second voltage signal.
  • the duration is inversely proportional to the transconductance of the transistor in the DA in the saturation region, so that the dynamic amplification circuit can still provide a relatively stable gain when the PVT changes.
  • first, second, third, fourth, and various numerical numbers eg, the first driving circuit 310 and the second driving circuit 320, etc.
  • referred to herein are merely for convenience of description and are not intended to be limiting. The scope of protection of the embodiments of the present application.
  • the negative pole of the power source involved in the above embodiment may be set to the ground potential (ie, ground).
  • ground potential ie, ground
  • other potentials such as a negative potential, may be used.
  • the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application.
  • the implementation process constitutes any limitation.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present application which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

Abstract

本申请公开了一种动态放大电路，包括：第一驱动电路，用于接收该第一控制信号，产生第一电压信号和第二电压信号；第二驱动电路，用于接收第一电压信号和第二电压信号，产生该第一驱动信号；第三驱动电路，用于接收该第一控制信号和该第一驱动信号，产生第二控制信号；动态放大器DA，用于根据该第一控制信号和该第二控制信号分别控制该第一控制开关和第二控制开关的闭合和断开；在第一时间段，第一控制信号为高电平，第二驱动为低电平；在第二时间段内，第一控制信号为低电平，该第二控制信号为高电平；在第三时间段内，该第一控制信号为低电平，该第二控制信号为低电平；其中，该第二时间段的时长跟该晶体管在饱和区的跨导成反比。

Description

动态放大电路 技术领域
本申请实施例涉及电路领域，并且更具体地，涉及动态放大电路。
背景技术
动态放大器(Dynamic Amplifier，DA)相比于传统的基于带反馈的运算放大器实现而言，具有低功耗，无过冲的优点。
但是动态放大器的增益会随着例如，半导体工艺、供电电压和温度(Process、Voltage、Temperature，PVT)的变化而变化，在一定程度上限制了它的应用。
因此，需要一种动态放大电路，能够提供相对稳定的增益。
发明内容
本申请提供一种动态放大电路，能够提供相对稳定的增益。
第一方面，提供了一种动态放大电路，包括：
第一驱动电路，用于接收第一控制信号，产生第一电压信号和第二电压信号，所述第一电压信号随时间变化，所述第二电压信号为恒定电压；
第二驱动电路，用于接收所述第一电压信号和所述第二电压信号，产生第一驱动信号；
第三驱动电路，用于接收所述第一控制信号和所述第一驱动信号，产生第二控制信号；
动态放大器DA，包括第一控制开关、第二控制开关和晶体管；
所述DA，用于接收所述第一控制信号和所述第二控制信号，通过所述第一控制信号和所述第二控制信号分别控制所述第一控制开关和所述第二控制开关的闭合和断开；
在第一时间段，所述第一控制信号为高电平，所述第一电压信号输出的电压值为第一电压值，所述第二电压信号输出的电压值为第二电压值，所述第二控制信号为低电平；
在所述第一时间段之后的第二时间段内，所述第一控制信号为低电平，所述第一电压信号输出的电压值开始增大，但小于所述第二电压值，所述第 一驱动信号为低电平，所述第二控制信号为高电平；
在所述第二时间段之后的第三时间段内，所述第一控制信号为低电平，所述第一电压信号输出的电压值大于或等于所述第二电压值，所述第一驱动信号为高电平，所述第二控制信号为低电平；
其中，所述第二时间段的时长跟所述DA中的晶体管在饱和区的跨导成反比。
因此，本申请实施例的动态放大电路，通过第一控制信号控制第一电压信号和第二电压信号的输出的电压值，进而根据所述第一电压信号和所述第二电压信号，控制第二时间段的时长满足跟DA中的晶体管在饱和区的跨导成反比，从而使得在PVT变化时，该动态放大电路依然能够提供相对稳定的增益。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一驱动电路包括：
第一偏置电路，用于接收所述第一控制信号，产生所述第一电压信号；
第一偏置电路包括第一晶体管、第一电流源和第一电容器，所述第一晶体管的漏极连接所述第一电流源，所述第一电容器的一端连接所述第一晶体管的漏极，并且通过第一开关器件连接所述第一晶体管的栅极，所述第一晶体管的源级连接所述第一电容器的另一端，所述第一晶体管的漏极用于输出所述第一电压信号；
第二偏置电路，用于输出所述第二电压信号；
所述第二偏置电路包括第二晶体管和第二电流源，所述第二晶体管的漏极连接所述第二电流源，所述第二晶体管的漏极与所述第二晶体管的栅极连接，所述第二晶体管的漏极用于输出所述第二电压信号；
其中，所述第一晶体管和所述第二晶体管的晶体管参数相同，所述第二电流源的电流值大于所述第一电流源的电流值。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一控制信号还用于控制所述第一开关器件的闭合与断开；
其中，所述第一控制信号具体用于：
在所述第一时间段，控制所述第一开关器件闭合，在所述第二时间段和所述第三时间段，控制所述第一开关器件断开。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一晶体管 和所述第二晶体管的晶体管参数与所述DA的晶体管的晶体管参数相同。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一晶体管和所述第二晶体管为金属氧化物半导体MOS管。
结合第一方面，在第一方面的一种可能的实现方式中，通过镜像电流源给所述第一晶体管和所述DA的晶体管提供电流。
结合第一方面，在第一方面的一种可能的实现方式中，所述第二驱动电路包括第二电容器、第一反相器和第二反相器；
所述第二电容器的一端通过第二开关器件接收所述第一电压信号，以及通过第三开关器件接收所述第二电压信号，所述第二电容器的另一端与所述第一反相器的输入端连接；
所述第一反相器的输入端和输出端通过第四开关器件连接，所述第一反相器的输出端与所述第二反相器的输入端连接，所述第二反相器的输出端用于输出所述第一驱动信号。
结合第一方面，在第一方面的一种可能的实现方式中，所述第一控制信号还用于：
控制所述第二开关器件、第三开关器件和所述第四开关器件的闭合与断开；
其中，所述第一控制信号具体用于：
在所述第一时间段，控制所述第二开关器件断开，第三开关器件和所述第四开关器件闭合，在所述第二时间段和所述第三时间段，控制所述第二开关器件闭合，所述第三开关器件和所述第四开关器件断开。
结合第一方面，在第一方面的一种可能的实现方式中，所述第二驱动电路为连续时间比较器，所述连接时间比较器的第一输入端用于接收所述第一电压信号，所述连接时间比较器的第二输入端用于接收所述第二电压信号，所述连续时间比较器的输出端用于输出所述第一驱动信号。
结合第一方面，在第一方面的一种可能的实现方式中，所述第三驱动电路包括第三反相器、第四反相器和求与电路；
所述第三反相器的输入端用于接收所述第一控制信号，所述第三反相器的输出端与所述求与电路的第一输入端连接；
所述第四反相器的输入端用于接收所述第一驱动信号，所述第四反相器的输出端与所述求与电路的第二输入端连接；
所述求与电路的输出端用于输出所述第二控制信号。
结合第一方面，在第一方面的一种可能的实现方式中，所述DA还包括第三电容器，所述第三电容器的一端与电源的负极连接，所述第三电容器的另一端通过所述第一控制开关与电源的正级连接，所述电容器的另一端还连接所述第二控制开关的一端，所述第二控制开关的另一端与所述晶体管的漏极连接；
所述第一控制信号具体用于：
在所述第一时间段，控制所述第一控制开关闭合，在所述第二时间段和所述第三时间段，控制所述第一控制开关断开；
所述第二控制信号具体用于：
在所述第一时间段，控制所述第二控制开关断开，在所述第二时间段，控制所述第二控制开关闭合，在所述第三时间段控制所述第二控制开关断开。
结合第一方面，在第一方面的一种可能的实现方式中，所述第二电压值减去所述第二晶体管的阈值电压得到的电压值为所述第一电压值减去所述第一晶体管的阈值电压得到的电压值的倍数。
因此，本申请实施例的动态放大电路，通过第一控制信号控制第一电压信号和第二电压信号的输出的电压值，进而根据所述第一电压信号和所述第二电压信号，控制第二时间段的时长满足跟DA中的晶体管在饱和区的跨导成反比，从而使得在PVT变化时，该动态放大电路依然能够提供相对稳定的增益。
附图说明
图1是现有的动态放大电路的结构示意图。
图2是现有的动态放大电路的逻辑时序图。
图3是现有的动态放大电路的等效电路图。
图4是根据本申请实施例的动态放大电路的示意图。
图5是根据本申请实施例的动态放大电路的逻辑时序图。
图6是根据本申请实施例的第一驱动电路的一例结构示意图。
图7是根据本申请实施例的第二驱动电路的一例结构示意图。
图8是根据本申请实施例的第二驱动电路的另一例结构示意图。
图9是根据本申请实施例的第三驱动电路的一例结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
图1是现有的动态放大器的结构示意图，如图1所示，该动态放大器100为对称结构，右半边结构和左半边结构包括的器件，以及器件的参数相同，这里以左半边结构为例进行介绍，右半边结构中的器件的工作状态和左半结构中的对应器件的工作状态相同，这里不再赘述。
该动态放大器100包括晶体管110、电容器120、第一控制开关130以及第二控制开关140。
该动态放大器100的工作状态包括两个阶段：
第一阶段，第一控制开关130闭合，第二控制开关140断开，电容器120连接至电源的正极(VCC)，电容处于充电状态；
第二阶段，第一控制开关130断开，第二控制开关140闭合，电容器120通过第二控制开关140连接至晶体管110的漏极，电容处于放电状态。
图2是该动态放大器100的逻辑时序图，其中，
Figure PCTCN2017094529-appb-000001
为第一控制开关130的时序，
Figure PCTCN2017094529-appb-000002
为第二控制开关140的时序，Vout为输出电压的时序。
如图2所示，在第一阶段(记为TR)，第一控制开关130闭合，第二控制开关140断开，动态放大器处于复位(reset)状态；在第二阶段(记为TA)，第一控制开关130断开，第二控制开关140闭合，动态放大器处于放大状态，动态放大电路处于放大状态的时长为第二阶段的时长TA。
图3为该图1所示的动态放大器的等效电路图，其中，gm为晶体管110的跨导，CL为电容器120的电容值，由图3可得，该动态放大电路的放大系数(增益)Av如公式(1)所示：
Figure PCTCN2017094529-appb-000003
由于gm和CL会随PVT变化，因此，导致动态放大器的增益不稳定，而TA可以由设计者控制，因此，本申请实施例提供了一种动态放大电路，通过控制第二阶段的时长TA，能够提供相对稳定的增益。
图4是本申请实施例提供的动态放大电路300的示意性结构图，如图4所示，该动态放大电路300包括：
第一驱动电路310，用于接收第一控制信号，产生第一电压信号和第二电压信号，第一电压信号随时间变化，第二电压信号为恒定电压；
第二驱动电路320，用于接收第一电压信号和第二电压信号，产生第一驱动信号；
第三驱动电路330，用于接收第一控制信号和第一驱动信号，产生第二控制信号；
动态放大器DA340，包括第一控制开关、第二控制开关和晶体管；
DA用于接收第一控制信号和第二控制信号，通过第一控制信号和第二控制信号分别控制第一控制开关和第二控制开关的闭合和断开；
也就是说，第一控制信号和第二控制信号分别对应图2中的控制信号
Figure PCTCN2017094529-appb-000004
和
Figure PCTCN2017094529-appb-000005
，即，第一控制信号和第二控制信号可以用作图2中的控制信号
Figure PCTCN2017094529-appb-000006
和，分别用于控制DA100的第一控制开关130和第二控制开关140。
可选地，DA340可以为图1所示的DA100，或者，也可以为其他等效电路，DA340还可以包括第三电容器，第三电容器可以对应于图1所示的DA100中的电容器120，第三电容器的一端与电源的负极连接，第三电容器的另一端通过第一控制开关与电源的正级连接，电容器的另一端还连接第二控制开关的一端，第二控制开关的另一端与晶体管的漏极连接。
在本申请实施例中，第一控制信号具体用于：
在第一时间段，控制第一控制开关闭合，在第二时间段和第三时间段，控制第一控制开关断开；
第二控制信号具体用于：
在第一时间段，控制第二控制开关断开，在第二时间段，控制第二控制开关闭合，在第三时间段控制第二控制开关断开。
以下，结合图5，详细说明根据本申请实施例的动态放大电路的逻辑时序图。
在第一时间段内(对应于前文所述的第一阶段)，即t1至t2之间的时间段，第一控制信号为高电平，第一驱动电路输出的第一电压信号V1为第一电压值，第二电压信号V2为第二电压值，第一电压值小于第二电压值。第三驱动电路输出的第二控制信号为低电平。
需要说明的是，在本申请实施例中，在第一时间段内，第一驱动信号可以输出低电平，也可以输出高电平，图5仅以第一驱动信号为低电平作为示 例，只要在第一时间段内，第一控制信号为高电平，第二控制信号为低电平即可。
在第一时间段之后的第二时间段内(对应于前文所述的第二阶段)，即t2至t3之间的时间段，第一控制信号为低电平，在第二时间段内，第一驱动电路输出的第一电压信号开始增大，但仍小于所述第二电压值，第二电压信号仍为第二电压值，第二驱动电路根据第一电压信号和第二电压信号输出的第一驱动信号仍为低电平，第三驱动电路根据第一控制信号和第一驱动信号输出的第二控制信号从低电平转变为高电平。
在第二时间段之后的第三时间段，即t3之后的时间段，第一控制信号为低电平，第一驱动电路输出的第一电压信号大于或等于第二电压值，第二驱动电路输出的第一驱动信号由低电平转变为高电平，第三驱动电路输出的第二控制信号从高电平转变为低电平。
也就是说，本申请实施例的第一驱动电路可以根据第一控制信号输出第一电压信号V1和第二电压信号V2，其中，在第一时间段内，V1<V2，在第二时间段内，V1开始增大，但是依然小于V2，在第三时间段内，V1增大到大于或等于V2，即第二时间段和第三时间段的分界线为V1等于V2的时刻。
可选地，在第三时间段内，V1可以增大到等于V2之后不再增大，或者，也可以在等于V2之后继续增大到某个电压值后不再增大等，本申请实施例并不限定第一电压信号在第三时间段内的电压值的大小，只要第一驱动信号在V1等于V2的时刻发生翻转即可。
进一步地，第二驱动电路能够根据随时间变化的第一电压信号和第二电压信号输出第一驱动信号，即在第一电压信号的电压值小于第二电压信号的电压值时，输出低电平，在第一电压信号的电压值大于或等于第二电压信号的电压值时，输出高电平。
例如，第二驱动电路可以用比较器实现，具体地，该比较器可以为连续时间比较器。
更进一步地，第三驱动电路根据第一控制信号和第一驱动信号输出第二控制信号，其中，第三驱动电路只需控制在第一控制信号和第一驱动信号都为低电平时，第二控制信号输出高电平，在第一控制信号和第一驱动信号为其他状态时，第二控制信号都输出低电平即可。
例如，第三驱动电路可以用反相器和与门的组合电路实现，例如，可以 将第一控制信号和第一驱动信号都取反后，输入到与门的两个输入端，此时，可以控制在第一控制信号和第一驱动信号都为低电平时，与门的输出端输出高电平，其他状态下，与门的输出端都输出低电平。
本申请实施例的动态放大电路能够通过第一电压信号和第二电压信号控制第二时间段的时长TA与DA中的晶体管在饱和区的跨导成反比，即TA＝K/gm，从而公式(1)可以化简为公式(2)：
Figure PCTCN2017094529-appb-000008
此时，动态放大电路的增益只跟电容值有关，因此，动态放大电路的增益在PVT变化时，相对稳定。
因此，本申请实施例的动态放大电路，通过第一控制信号控制第一电压信号和第二电压信号的输出的电压值，进而根据第一电压信号和第二电压信号，控制第二时间段的时长TA满足跟DA中的晶体管在饱和区的跨导成反比，从而使得在PVT变化时，该动态放大电路依然能够提供相对稳定的增益。
以下，结合图6至图9所示的具体示例，详细介绍本申请实施例的动态放大电路的实现方式。
应理解，6至图9所示的例子是为了帮助本领域技术人员更好地理解本申请实施例，而非要限制本申请实施例的范围。本领域技术人员根据所给出的图6至图9，显然可以进行各种等价的修改或变化，这样的修改或变化也落入本申请实施例的范围内。
在介绍图6所示的第一驱动电路之前，首先介绍一下晶体管工作在饱和区时的电压电流特性。
工作在饱和区的晶体管的电压电流具有如下关系：
Figure PCTCN2017094529-appb-000009
其中，ID为晶体管的漏极电流，μ为载流子迁移率，Cox为单位面积的栅氧电容值，W为栅极的宽度，L为栅极的长度，VGS为栅极和源极的电压差，VTH为晶体管的阈值电压，或者说，栅极和源级的导通电压，Vov为晶体管的过驱动电压。
进一步地，可以根据公式(3)推到出晶体管的跨导gm的计算公式，如公式(4)所示：
Figure PCTCN2017094529-appb-000010
由公式(3)可知，漏极电流ID与(Vov)2成正比，或者说，在晶体管的参数确定后，晶体管的栅极和源级的压降只跟流过晶体管的电流有关。由公式(4)可知，gm与2ID/Vov成正比，或者说，在晶体管的参数确定后，晶体管的跨导gm只跟流过晶体管的电流有关。
需要说明的是，上述ID与(Vov)2成正比，以及gm与2ID/Vov成正比是一种近似的正比关系，由于晶体管的工艺或环境等因素的影响，会略有偏差，但偏差较小，在能够接受的范围内，可以认为近似成正比。
图6是根据本申请实施例的第一驱动电路的一例结构示意图，图6示出了第一驱动电路的一种可能的实现方式，或者说，优选的实现方式，但本申请实施例并不限于此实现方式，根据此实现方式的各种等价的修改或变化都落入本申请实施例的范围内。
如图6所示，该第一驱动电路310包括第一偏置电路311和第二偏置电路312。
具体地，第一偏置电路311包括第一晶体管3111、第一电流源3112、第一电容器3113和第一开关器件3114。第一晶体管3111的漏极(D极)连接第一电流源3112，第一电容器3113的一端连接第一晶体管3111的漏极(D极)，并且通过第一开关器件3114连接第一晶体管3111的栅极(S极)，第一晶体管3111的源级(S极)连接第一电容器3113的另一端，第一晶体管3111的漏极(D极)用于输出第一电压信号。
第二偏置电路312包括第二晶体管3121和第二电流源3122，第二晶体管3121的漏极(D极)与第二电流源3122连接，第二晶体管3121的漏极(D极)与第二晶体管3121的栅极(S极)连接，即第二晶体管的漏极和栅极短路，第二晶体管3121的漏极(D极)用于输出第二电压信号。
可选地，在本申请实施例中，第二电流源的电流值可以为第一电流源的电流值的倍数，例如，I2＝4I1，或I2＝9I1，或I2＝6I1等，其中，I1为第一电流源的电流值，I2为第二电流源的电流值。
可选地，在本申请实施例中，可以采用镜像电流源实现第一电流源和第二电流源，这样可以保证第二电流源和第一电流源为倍数关系。
由于第二晶体管3121的漏极和栅极连接，第二晶体管3121工作在饱和 区，第二晶体管3121的漏极输出的第二电压信号近似为恒定电压，记为V2。
在第一偏置电路311中，第一开关器件3114是由第一控制信号控制的，即第一控制信号可以用于控制第一开关器件3114的闭合和断开。具体地，在第一时间段，第一控制信号用于控制闭合第一开关器件3114，在第二时间段和第三时间段，第一控制信号用于控制断开第一开关器件3114。
以下，结合图5，详细说明第一驱动电路的工作状态。
在t1时刻内，第一开关器件3114闭合，第一晶体管3111的漏极和栅极短接，即VGS＝VDS，第一晶体管3111工作在饱和区，并且第一晶体管3111的漏极电流近似为第一电流源的电流值，因此，在第一时间段内，第一电压信号近似为恒定电压，为便于区分和描述，将第一电压信号在第一时间段的电压值，即第一电压值记为VT1＝VGS1＝VDS1，其中，VGS1为第一晶体管3111的栅极和源极的电压差，VDS1为第一晶体管3111的漏极和源极的电压差。
在t2时刻，第一开关器件3114断开，第一电流源3112开始对第一电容器3113充电，V1开始增加，在t2时刻之后的t3时刻，V1＝V2，此时，第二驱动电路输出的第一驱动信号由低电平翻转为高电平。
那么t2时刻至t3时刻之间的第二时间段的时长TA，即为第一电容器的电压值从VT1增大到V2所需的时间，因此，可以根据公式(5)确定TA：
TA＝(V2-VT1)*C1/I1             公式(5)
其中，C1为第一电容器3113的电容值。
可选地，在本申请实施例中，第一晶体管3111和第二晶体管3121可以采用相同的晶体管参数，例如，μ、Cox、W和L等参数可以相同，那么第一晶体管和第二晶体管的VTH可以认为相等。
由于VT1＝VGS1＝VOV1+VTH，V2＝VGS2＝VOV2+VTH，其中，VGS1为第一晶体管3111的栅极和源极的电压差，VOV1为第一晶体管3111的过驱动电压，VGS2为第二晶体管3121的栅极和源极的电压差，VOV2为第二晶体管3121的过驱动电压。
由公式(3)可知，
Figure PCTCN2017094529-appb-000011
那么VT1和V2的电压差为：
Figure PCTCN2017094529-appb-000012
那么将公式(6)代入公式(5)可得：
Figure PCTCN2017094529-appb-000013
可选地，第一晶体管也可以采用和DA中的晶体管相同的晶体管参数， 同时，第一电流源的电流值也可以和DA中的晶体管的漏极电流成倍数关系，例如，可以通过镜像电流源为第一晶体管和所述DA中的晶体管提供电流，这样流进DA中的晶体管的电流与流进第一晶体管的电流成倍数关系，即I＝KI1，由公式(4)可知，DA中的晶体管的跨导和第一晶体管的跨导也成倍数关系，即
Figure PCTCN2017094529-appb-000014
其中，gm为DA中的晶体管的跨导，gm1为第一晶体管的跨导。
由于gm1＝2I1/VOV1，则DA中的晶体管的跨导gm可以由公式(8)确定：
Figure PCTCN2017094529-appb-000015
将公式(8)和公式(7)代入公式(1)，可以得到动态放大电路的放大系数Av如公式(9)所示：
Figure PCTCN2017094529-appb-000016
当两个晶体管的晶体管参数和流进晶体管的电流都相等时，由公式(4)可知，晶体管的跨导也相等，即
Figure PCTCN2017094529-appb-000017
此时，公式(9)所示的动态放大电路的放大系数Av可以化简为公式(10)：
Figure PCTCN2017094529-appb-000018
例如，若I2＝4I1，则AV＝2C1/CL，若I2＝9I1，则AV＝3C1/CL，即Av只跟电容值有关，也就是说，只要第一晶体管的过驱动电压VOV1和第二晶体管的过驱动电压VOV2具有倍数关系即可得到相对稳定的增益。
可选地，在本申请实施例中，第一晶体管和第二晶体管可以为金属氧化物半导体(Metal Oxide Semiconductor，MOS)管，例如，N沟道耗尽型MOS管、N沟道增强型MOS管、P沟道耗尽型MOS管或P沟道增强型MOS管等，本申请实施例的附图中的晶体管的类型仅为示例，不应对本申请实施例构成任何限定，本领域技术人员根据附图中的示例得到的等效电路，都落入本申请实施例的保护范围。
图7是根据本申请实施例的第二驱动电路的一例结构示意图，图7示出了第二驱动电路的一种可能的实现方式，或者说，优选的实现方式，但本申请实施例并不限于此实现方式，根据此实现方式的各种等价的修改或变化都落入本申请实施例的范围内。
如图7所示，该第二驱动电路700包括第二电容器321、第一反相器322和第二反相器323。
第二电容器321的一端通过第二开关器件324接收第一电压信号，以及 通过第三开关器件325接收第二电压信号，第二电容器321的另一端与第一反相器322的输入端连接；
第一反相器322的输入端和输出端通过第四开关器件326连接，第一反相器322的输出端与第二反相器323的输入端连接，第二反相器323的输出端用于输出第一驱动信号。
其中，第一控制信号用于：
在第一时间段内，控制第二开关器件断开，第三开关器件和第四开关器件闭合，在第二时间段和第三时间段，控制第二开关器件闭合，第三开关器件和第四开关器件断开。
总的来说，第一控制信号控制的开关器件的工作状态如下：
在t1时刻，闭合第一开关器件、第三开关器件和第四开关器件，断开第二开关器件；
在t2时刻，断开第一开关器件、第三开关器件和第四开关器件，闭合第二开关器件；
在t3时刻，闭合第一开关器件、第三开关器件和第四开关器件，断开第二开关器件。
这样，在t1时刻至t2时刻之间的第一时间段，第二开关器件324断开，第三开关器件325闭合，第四开关器件326闭合，第二电容器321的一端的电压为V2，另一端的电压为第一反相器322的阈值电压VTHINV，则第二电容器321上的压降为VTHINV-V2。
如上文所述，在第一时间段内，我们并不关心第一驱动信号输出低电平还是高电平，只要在第一时间段内，第一控制信号为高电平，第三驱动电路输出的第二控制信号为低电平即可。
在t2时刻至t3时刻之间的第二时间段内，第二开关器件324闭合，第三开关器件325断开，第四开关器件326断开，则第二电容器321的一端的电压为V1，基于电荷守恒原理，第二电容器321上的压降不变，那么第一反相器的输入端的电压为V1+VTHINV-V2，由于在第二时间段内，V1<V2，则V1+VTHINV-V2<VTHINV，经过第一反相器后，输出高电平，再经过第二反相器后，第一驱动信号输出低电平。
在t3时刻之后的第三时间段内，V1≥V2，则V1+VTHINV-V2≥VTHINV，经过第一反相器后，输出低电平，再经过第二反相器反向后，第一驱动信号输 出高电平。
可选地，本申请实施例还可以采用其他等效电路来实现第二驱动电路的功能，即只要在第一电压信号小于第二电压信号时输出低电平，在第一电压信号大于或等于第二电压信号时输出高电平即可。
可选地，在本申请实施例中，由于第一控制信号可以用于控制第一开关器件的闭合和断开，那么第一偏置电路可以还包括第一控制信号的输入端，用于输入第一控制信号，从而通过第一控制信号控制第一开关器件的闭合和断开。
类似地，第二驱动电路也可以包括第一控制信号的输入端，用于输入第一控制信号，进而通过第一控制信号控制第二开关器件、第三开关器件、第四开关器件的闭合和断开等。
应理解，在本申请实施例中，第一控制信号用于控制第一开关器件、第二开关器件、第三开关器件、第四开关器件和第一控制开关的闭合和断开，以及第二控制信号用于控制第二控制开关的闭合和断开，仅表示控制信号具有控制各自对应的开关器件的功能，并非表示这些控制信号的输入端与各自对应的开关器件一定存在直接的连接关系。只要保证输入的控制信号可以控制对应的开关器件的闭合和断开即可。
图8是根据本申请实施例的第二驱动电路的另一例的结构示意图，如图8所示，第二驱动电路320为连续时间比较器327，连接时间比较器327的第一输入端用于接收第一电压信号V1，连接时间比较器的第二输入端用于接收第二电压信号V2，连续时间比较器327的输出端用于输出第一驱动信号。
具体地，在第一时间段和第二时间段内，V1<V2，连续时间比较器327输出低电平；
在第三时间段内，V1≥V2，连续时间比较器327的输出电压由低电平跳转为高电平。
因此，图8所示的连续时间比较器和图7所示的组合电路都可以实现第二驱动电路的功能，即在第一电压信号小于第二电压信号时输出低电平，在第一电压信号大于或等于第二电压信号时输出高电平，图7所示的组合电路相对于图8所示的连续时间比较器而言，不必进行连续的比较，因此功耗相对较低。
图9是根据本申请实施例的第三驱动电路的一例结构示意图，如图9所 示，第三驱动电路330包括第三反相器331、第四反相器332和求与电路333。
第三反相器331的输入端用于接收第一控制信号，第三反相器331的输出端与求与电路333的第一输入端连接；
第四反相器332的输入端用于接收第一驱动信号，第四反相器332的输出端与求与电路333的第二输入端连接；
求与电路333的输出端用于输出第二控制信号。
也就是说，第二控制信号只在第一控制信号和第一驱动信号都为低电平时，才输出高电平，当第一控制信号和第一驱动信号为其他工作状态时，第二控制信号输出低电平。
可选地，求与电路333可以用与门，或者其他等效电路来实现。
因此，本申请实施例的动态放大电路，通过第一控制信号控制第一电压信号和第二电压信号的输出的电压值，进而根据第一电压信号和第二电压信号，控制第二时间段的时长满足跟DA中的晶体管在饱和区的跨导成反比，从而使得在PVT变化时，该动态放大电路依然能够提供相对稳定的增益。
应理解，本文中涉及的第一、第二、第三、第四以及各种数字编号(例如第一驱动电路310和第二驱动电路320等)仅为描述方便进行的区分，并不用来限制本申请实施例的保护范围。
在上述实施例中涉及的电源的负极可以设置为地电位(即接地)，当然在具体实现中可以为其他电位如负电位，本申请实施例对此不作限制。
应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种动态放大电路，其特征在于，包括：
    第一驱动电路，用于接收第一控制信号，产生第一电压信号和第二电压信号，所述第一电压信号随时间变化，所述第二电压信号为恒定电压；
    第二驱动电路，用于接收所述第一电压信号和所述第二电压信号，产生第一驱动信号；
    第三驱动电路，用于接收所述第一控制信号和所述第一驱动信号，产生第二控制信号；
    动态放大器DA，包括第一控制开关、第二控制开关和晶体管；
    所述DA，用于接收所述第一控制信号和所述第二控制信号，通过所述第一控制信号和所述第二控制信号分别控制所述第一控制开关和所述第二控制开关的闭合和断开；
    在第一时间段，所述第一控制信号为高电平，所述第一电压信号输出的电压值为第一电压值，所述第二电压信号输出的电压值为第二电压值，所述第二控制信号为低电平；
    在所述第一时间段之后的第二时间段内，所述第一控制信号为低电平，所述第一电压信号输出的电压值开始增大，但小于所述第二电压值，所述第一驱动信号为低电平，所述第二控制信号为高电平；
    在所述第二时间段之后的第三时间段内，所述第一控制信号为低电平，所述第一电压信号输出的电压值大于或等于所述第二电压值，所述第一驱动信号为高电平，所述第二控制信号为低电平；
    其中，所述第二时间段的时长跟所述DA中的晶体管在饱和区的跨导成反比。
  2. 根据权利要求1所述的动态放大电路，其特征在于，所述第一驱动电路包括：
    第一偏置电路，用于接收所述第一控制信号，产生所述第一电压信号；
    第一偏置电路包括第一晶体管、第一电流源和第一电容器，所述第一晶体管的漏极连接所述第一电流源，所述第一电容器的一端连接所述第一晶体管的漏极，并且通过第一开关器件连接所述第一晶体管的栅极，所述第一晶体管的源级连接所述第一电容器的另一端，所述第一晶体管的漏极用于输出所述第一电压信号；
    第二偏置电路，用于输出所述第二电压信号；
    所述第二偏置电路包括第二晶体管和第二电流源，所述第二晶体管的漏极连接所述第二电流源，所述第二晶体管的漏极与所述第二晶体管的栅极连接，所述第二晶体管的漏极用于输出所述第二电压信号；
    其中，所述第一晶体管和所述第二晶体管的晶体管参数相同，所述第二电流源的电流值大于所述第一电流源的电流值。
  3. 根据权利要求2所述的动态放大电路，其特征在于，所述第二电流源的电流值为所述第一电流源的电流值的倍数。
  4. 根据权利要求2或3所述的动态放大电路，其特征在于，通过镜像电流源给所述第一晶体管和所述DA的晶体管提供电流。
  5. 根据权利要求2至4中任一项所述的动态放大电路，其特征在于，所述第一晶体管和所述第二晶体管与所述DA中的晶体管的晶体管参数相同。
  6. 根据权利要求2至5中任一项所述的动态放大电路，其特征在于，所述第一控制信号还用于控制所述第一开关器件的闭合与断开；
    其中，所述第一控制信号具体用于：
    在所述第一时间段，控制所述第一开关器件闭合，在所述第二时间段和所述第三时间段，控制所述第一开关器件断开。
  7. 根据权利要求2至6中任一项所述的动态放大电路，其特征在于，所述第一晶体管和所述第二晶体管为金属氧化物半导体MOS管。
  8. 根据权利要求2至7中任一项所述的动态放大电路，其特征在于，所述第二电压值减去所述第二晶体管的阈值电压得到的电压值为所述第一电压值减去所述第一晶体管的阈值电压得到的电压值的倍数。
  9. 根据权利要求1至8中任一项所述的动态放大电路，其特征在于，所述第二驱动电路包括第二电容器、第一反相器和第二反相器；
    所述第二电容器的一端通过第二开关器件接收所述第一电压信号，以及通过第三开关器件接收所述第二电压信号，所述第二电容器的另一端与所述第一反相器的输入端连接；
    所述第一反相器的输入端和输出端通过第四开关器件连接，所述第一反相器的输出端与所述第二反相器的输入端连接，所述第二反相器的输出端用于输出所述第一驱动信号。
  10. 根据权利要求9所述的动态放大电路，其特征在于，所述第一控制信号还用于：
    控制所述第二开关器件、第三开关器件和所述第四开关器件的闭合与断开；
    其中，所述第一控制信号具体用于：
    在所述第一时间段，控制所述第二开关器件断开，第三开关器件和所述第四开关器件闭合，在所述第二时间段和所述第三时间段，控制所述第二开关器件闭合，所述第三开关器件和所述第四开关器件断开。
  11. 根据权利要求1至8中任一项所述的动态放大电路，其特征在于，所述第二驱动电路为连续时间比较器，所述连接时间比较器的第一输入端用于接收所述第一电压信号，所述连接时间比较器的第二输入端用于接收所述第二电压信号，所述连续时间比较器的输出端用于输出所述第一驱动信号。
  12. 根据权利要求1至11中任一项所述的动态放大电路，其特征在于，所述第三驱动电路包括第三反相器、第四反相器和求与电路；
    所述第三反相器的输入端用于接收所述第一控制信号，所述第三反相器的输出端与所述求与电路的第一输入端连接；
    所述第四反相器的输入端用于接收所述第一驱动信号，所述第四反相器的输出端与所述求与电路的第二输入端连接；
    所述求与电路的输出端用于输出所述第二控制信号。
  13. 根据权利要求1至12中任一项所述的动态放大电路，其特征在于，所述DA还包括第三电容器，所述第三电容器的一端与电源的负极连接，所述第三电容器的另一端通过所述第一控制开关与电源的正级连接，所述电容器的另一端还连接所述第二控制开关的一端，所述第二控制开关的另一端与所述晶体管的漏极连接；
    所述第一控制信号具体用于：
    在所述第一时间段，控制所述第一控制开关闭合，在所述第二时间段和所述第三时间段，控制所述第一控制开关断开；
    所述第二控制信号具体用于：
    在所述第一时间段，控制所述第二控制开关断开，在所述第二时间段，控制所述第二控制开关闭合，在所述第三时间段控制所述第二控制开关断开。
PCT/CN2017/094529 2017-07-26 2017-07-26 动态放大电路 WO2019019058A1 (zh)

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