WO2019028595A1 - 振荡器、集成电路、计时芯片和电子设备 - Google Patents

振荡器、集成电路、计时芯片和电子设备 Download PDF

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Publication number
WO2019028595A1
WO2019028595A1 PCT/CN2017/096240 CN2017096240W WO2019028595A1 WO 2019028595 A1 WO2019028595 A1 WO 2019028595A1 CN 2017096240 W CN2017096240 W CN 2017096240W WO 2019028595 A1 WO2019028595 A1 WO 2019028595A1
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Prior art keywords
mos transistor
bias
branch
circuit
oscillator
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PCT/CN2017/096240
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English (en)
French (fr)
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王程左
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2017/096240 priority Critical patent/WO2019028595A1/zh
Priority to CN201780000882.3A priority patent/CN107690749B/zh
Publication of WO2019028595A1 publication Critical patent/WO2019028595A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse

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  • the present application relates to the field of electronic technology and, more particularly, to an oscillator, an integrated circuit, a timing chip, and an electronic device.
  • Low-power Bluetooth, wearable devices and other systems require an ultra-low-power oscillator as the standby clock for the device system during standby.
  • the frequency generally ranges from a few hertz to several tens of kilohertz.
  • the relaxation oscillator is commonly used to generate the clock.
  • the conventional bias current source circuit requires a large amount of resistance when generating a bias current of the order of nanoampere, which requires not only a very large chip area but also an oscillator power consumption. Too large, usually on the order of a few hundred nanoamperes, does not meet the demand for ultra-low power consumption.
  • the prior art proposes a relaxation oscillator that uses a substrate diode reverse saturation current to charge and discharge a capacitor and a threshold voltage as a comparison voltage.
  • the structure has extremely low power consumption, but its core elements ( The charge and discharge current and the comparison voltage have a strong correlation with the process, the cost is high, and the delay characteristics of the comparator are poor, resulting in very poor output frequency accuracy and low practicability.
  • An oscillator, an integrated circuit, a timing chip, and an electronic device are provided to effectively reduce power consumption and cost.
  • an oscillator comprising:
  • the bias circuit is coupled to the current mode comparator, the bias circuit for generating a bias current and a bias voltage, the bias current being used to power the current mode comparator;
  • the current mode comparator is configured to receive the bias voltage and compare the bias voltage as a reference voltage with an input voltage to generate a pulse signal.
  • the current mode comparator can share the bias voltage of the bias circuit and use the bias voltage as a reference voltage, thereby avoiding being provided by a dedicated reference voltage generating circuit.
  • the reference voltage (reducing the number of branches of the circuit) can effectively reduce Power consumption and cost.
  • the current mode comparator includes a second branch
  • the bias circuit includes: a first branch, the bias voltage generating circuit, and the second branch, wherein a second branch connected in parallel with the bias voltage generating circuit and the first branch, the bias voltage generating circuit for generating the bias voltage, and the second branch for receiving The bias voltage is used as the reference voltage, and the bias circuit generates the bias current by multiplexing the second branch.
  • the bias circuit and the current mode comparator share the second branch, that is, the second branch is not only used to generate the bias current, but also is a component of the current mode comparator. It is used to receive the bias voltage of the bias circuit and use the bias voltage as a reference voltage, which can effectively reduce the number of branches of the circuit, and reduce power consumption and cost.
  • the first branch includes: a first metal oxide semiconductor MOS transistor and a self-source common-collector MOS transistor
  • the self-co-source common-gate MOS transistor includes: a second MOS transistor and a a three MOS transistor, the first MOS transistor is connected to the third MOS transistor through the second MOS transistor, the third MOS transistor is connected to a device ground, and the bias voltage generating circuit is connected to the third a drain of the MOS transistor, the bias voltage generating circuit is configured to generate the bias voltage
  • the second branch is configured to receive the bias voltage, and compare the bias voltage as the current mode Reference voltage of the device.
  • the bias voltage generating circuit includes a first current mirror and a second current mirror, the first current mirror includes a fourth MOS transistor and a fifth MOS transistor, and the fourth MOS transistor and the The mirror ratio of the five MOS transistors is 1:k, the second current mirror includes a sixth MOS transistor and a seventh MOS transistor, and a mirror ratio of the sixth MOS transistor to the seventh MOS transistor is j:1, the fourth a MOS transistor is connected to a drain of the third MOS transistor through the seventh MOS transistor, and the fifth MOS transistor is connected to the device ground through the sixth MOS transistor, so that the bias voltage generating circuit generates The bias voltage, where k>1, j>1.
  • the fourth MOS transistor and the first MOS transistor form a third current mirror, and a mirror ratio of the fourth MOS transistor to the first MOS transistor is 1:m, wherein , m>1.
  • the second branch includes an eighth MOS transistor and a ninth MOS transistor, and the eighth MOS transistor is connected to a drain of the third MOS transistor through the ninth MOS transistor. So that the second branch receives the bias current and uses the bias voltage as the current mode ratio Comparator's reference voltage.
  • the fourth MOS transistor and the eighth MOS transistor form a fourth current mirror, and a mirror ratio of the fourth MOS transistor to the eighth MOS transistor is 1:p, wherein , p>1.
  • the current mode comparator further includes a third branch, the third branch includes an eleventh MOS transistor and a tenth MOS transistor, and the eleventh MOS transistor passes the A ten MOS transistor is connected to the input terminal of the input voltage, and a third branch is for receiving the input voltage.
  • the eighth MOS transistor and the eleventh MOS transistor form a fifth current mirror, and a mirror ratio of the eighth MOS transistor to the eleventh MOS transistor is 1:n
  • the ninth MOS transistor and the tenth MOS transistor form a sixth current mirror, and a mirror ratio of the ninth MOS transistor to the tenth MOS transistor is 1:n, where n>1.
  • designing different ratios n can effectively adjust the oscillator output frequency.
  • the third branch further includes a first MOS capacitor, and the eleventh MOS transistor is connected to the device ground through the tenth MOS transistor and the first MOS capacitor.
  • the oscillator further includes a charge and discharge branch, an output end of the current mode comparator is connected to the first MOS capacitor through the charge and discharge branch, and the charge and discharge branch is used to the first MOS capacitor Charging and discharging are performed, wherein a capacitance voltage of the first MOS capacitor is the input voltage.
  • the process parameter of the bias current is cancelled by using the MOS gate capacitance, so that the frequency of the pulse signal output by the oscillator is weakened with the process, and the frequency precision of the pulse signal output by the oscillator can be effectively improved.
  • the capacitor voltage of the first MOS capacitor is a sawtooth signal, and the magnitude of the capacitor voltage is equal to the voltage value of the bias voltage.
  • the oscillator further includes: at least one pair of inverters, an output end of the current mode comparator is connected to the at least one pair of inverters, and the at least one pair of inverters is used And amplifying the pulse signal output by the current mode comparator.
  • the oscillator further includes a flip-flop connected to the at least one pair of inverters for generating a clock signal according to the signals output by the at least one pair of inverters.
  • the oscillator further includes: a startup circuit coupled to the bias circuit, the startup circuit for activating the bias circuit.
  • CMOS integrated circuit comprising the oscillator of the first aspect.
  • a timing chip comprising: a memory, and the oscillator of the first aspect or the CMOS integrated circuit of the second aspect, the memory storing program, the oscillator or the A CMOS integrated circuit is used to execute a system clock of a program in the memory.
  • an electronic device comprising: any one of the first aspects, or the CMOS integrated circuit of the second aspect, or the timing chip of the third aspect.
  • 1 is a structural block diagram of an oscillator of an embodiment of the present invention.
  • FIG. 2 is a schematic circuit diagram of an oscillator for acquiring a bias voltage according to an embodiment of the present invention.
  • FIG. 3 is a schematic circuit diagram of an oscillator for acquiring an input voltage according to an embodiment of the present invention.
  • FIG. 4 is a schematic circuit schematic diagram of an oscillator in accordance with an embodiment of the present invention.
  • Figure 5 is a schematic circuit schematic diagram of a startup circuit in accordance with an embodiment of the present invention.
  • the present invention proposes an ultra-low power consumption oscillator, which can effectively reduce the number of branches of the oscillator by using current sharing technology. In turn, power consumption is reduced and costs are reduced.
  • FIG. 1 is a schematic block diagram of a circuit of an oscillator of an embodiment of the present invention.
  • an oscillator including:
  • bias circuit 100 and a current mode comparator 200;
  • the bias circuit 100 is coupled to the current mode comparator 200, the bias circuit 100 is configured to generate a bias current and a bias voltage, the bias current is used to supply the current
  • the analog comparator 200 is powered;
  • the current mode comparator 200 is configured to receive the bias voltage and compare the bias voltage as a reference voltage with an input voltage to generate a pulse signal.
  • the bias voltage of the bias circuit 100 is shared by the current mode comparator 200, thereby preventing the current mode comparator 200 from providing a reference voltage through a special reference voltage generating circuit (reducing the number of branches of the circuit). In turn, power consumption and cost can be effectively reduced.
  • the bias circuit 100 can include: a first branch, the bias voltage generating circuit, and a a second branch, the current mode comparator 200 includes the second branch; wherein the second branch is connected in parallel with the bias voltage generating circuit and the first branch, the second branch, the bias a voltage generating circuit and the first branch for generating the bias current, the bias voltage generating circuit for generating the bias voltage, the second branch for receiving the bias voltage, and the bias voltage As the reference voltage of the current mode comparator 200.
  • the current mode comparator 200 may further include a third branch for receiving an input voltage, so that the comparator can generate a pulse signal by comparing the input voltage and the reference voltage, it should be understood that The third branch in the embodiment of the present invention may be used in the prior art, and may be different from the prior art, and is not specifically limited in the embodiment of the present invention.
  • the bias circuit 100 and the current mode comparator 200 share the second branch, that is, the second branch is not only used to generate the bias current, but also is a current mode.
  • the component of the comparator 200 is configured to receive the bias voltage of the bias circuit 100 and use the bias voltage as a reference voltage.
  • the MOS transistor is also referred to as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • NMOSFET N-type MOS transistor
  • PMOSFET P-type MOS transistor
  • NMOSFET its source and drain Connected to the N-type semiconductor, the high voltage is the drain terminal, the low voltage is the source terminal, and the actual current direction is the inflow drain.
  • the source and the drain are connected to the P-type semiconductor, the high voltage is the source terminal, the low voltage is the drain terminal, and the actual current direction is the outflow drain.
  • the cascode MOS transistor in the embodiment of the present invention may include two PMOSFETs, and when one of the PMOSFETs operates in a linear region, the electrical characteristics may be equivalent to one resistor.
  • the self-sourced common-gate MOS transistor by using the self-sourced common-gate MOS transistor, it is possible to avoid using a large resistance, which can not only reduce the occupancy of the chip area, but also generate an ultra-low bias current, thereby effectively reducing Power consumption and cost.
  • circuit principle of the oscillator of the embodiment of the present invention will be exemplarily described below with reference to FIGS. 2 to 4. It should be understood that the circuit diagrams shown in FIG. 2 to FIG. 4 are merely exemplary descriptions of the embodiments of the present invention, and the embodiments of the present invention are not limited thereto.
  • the cascode MOS transistor in the embodiment of the present invention may include a second MOS. a transistor 102 and a third MOS transistor 103.
  • the source of the second MOS transistor 102 is connected to the drain of the third MOS transistor 103, and the gate of the second MOS transistor 102 is connected to the gate of the third MOS transistor 103.
  • the third MOS transistor 103 operates in the linear region, the third MOS transistor 103 is electrically equivalent to a resistor.
  • first the terms “first,” “second,” and “third,” and the like may be employed in the embodiments of the present invention. These terms are used only to distinguish the components from each other, and are not intended to limit the components.
  • the first MOS transistor and the second MOS transistor are merely for distinguishing the two MOS transistors, and the two MOS transistors are not limited to this term.
  • the first branch includes: a first metal oxide semiconductor MOS transistor 101 and the above-described self-source cascode MOS transistor, and the first MOS transistor 101 sequentially passes through the second MOS transistor 102 and
  • the third MOS transistor 103 is connected to the device ground GND
  • the bias voltage generating circuit is connected to the drain of the third MOS transistor 103
  • the bias voltage generating circuit is configured to generate the bias voltage
  • the second branch is used for the second branch
  • the bias voltage is received and used as a reference voltage of the current mode comparator 200.
  • the bias voltage generating circuit includes a first current mirror including a fourth MOS transistor 104 and a fifth MOS transistor 105, and a mirror ratio of the fourth MOS transistor 104 and the fifth MOS transistor 105.
  • the second current mirror includes a sixth MOS transistor 106 and a seventh MOS transistor 107, and a mirror ratio of the sixth MOS transistor 106 to the seventh MOS transistor 107 is j:1, and the fourth MOS transistor 104 passes The seventh MOS transistor 107 is connected to the drain of the third MOS transistor 103, and the fifth MOS transistor 105 is connected to the device ground through the sixth MOS transistor 106, so that the bias voltage generating circuit generates the bias voltage.
  • the second branch includes an eighth MOS transistor 108 and a ninth MOS transistor 109, and the eighth MOS transistor 108 is connected to the drain of the third MOS transistor 103 through the ninth MOS transistor 109 so that the second branch receives
  • the bias current is used as a reference voltage of the current mode comparator 200.
  • the second current mirror will operate in the sub-threshold region, and the mirror ratio is greater than 1 (J>1). Therefore, the gate-source voltage VGS of the sixth MOS transistor 106 and the seventh MOS transistor 107 will be different. , that is, VGS106>VGS107.
  • the source of the seventh MOS transistor 107 generates a voltage equal to VGS106-VGS107.
  • the third MOS transistor 103 operates in a linear region and is electrically equivalent to a resistor, and the drain of the third MOS transistor 103 is sourced through the seventh MOS transistor 107.
  • the pole voltage is biased, and therefore, the output current of the third MOS transistor 103 is equal to the bias voltage divided by the equivalent resistance of the third MOS transistor 103.
  • This structure not only generates a bias current, but also avoids the use of a large resistor, which can effectively reduce the chip area occupancy.
  • the fourth MOS transistor 104 and the first MOS transistor 101 may constitute a third current mirror, and the mirror ratio of the fourth MOS transistor 104 to the first MOS transistor 101 is 1:m. Where m>1.
  • the fourth MOS transistor 104 and the eighth MOS transistor 108 may constitute a fourth current mirror, and a mirror ratio of the fourth MOS transistor 104 to the eighth MOS transistor 108 is 1:p, where p>1.
  • device ground GND may also be referred to as "common ground” or “ground” or “device common ground” or the like.
  • the bias current I 0 generated by the bias power generating circuit is calculated below.
  • the sixth MOS transistor 106 and the seventh MOS transistor 107 operating in the subthreshold region generate a gate-source voltage difference (also referred to as a bias voltage) VX due to a difference in current density, and the VX can represent for:
  • n is the slope factor and V T is the thermal voltage.
  • the drain current I D of the third MOS transistor 103 can be expressed as:
  • I SQ is the process-dependent square current
  • ⁇ is the carrier mobility
  • C OX is the process parameter
  • i f is the forward current
  • i r is the reverse current.
  • V GB represents the gate-substrate voltage and V TH0 is the threshold voltage at which the transistor source-substrate voltage is zero.
  • the transistor second MOS transistor 102 and the third MOS transistor 103 are designed as self-source collinear MOS transistors, which not only ensures the bias current of the bias circuit 100 to generate nanoamperes, but also greatly saves Chip area, effectively reducing power consumption and cost.
  • the current mode comparator 200 in the embodiment of the present invention may include the second branch.
  • the second branch is configured to receive the bias voltage generated by the bias circuit 100 and use the bias voltage as a reference voltage.
  • the current mode comparator 200 may further include a third branch for receiving the input voltage.
  • the current mode comparator 200 generates a pulse signal by comparing the reference voltage with the input voltage.
  • the third branch may include an eleventh MOS transistor 111 and a tenth MOS transistor 110 through which the eleventh MOS transistor 111 passes.
  • the input of the input voltage is connected, and the third branch is used to receive the input voltage.
  • the eighth MOS transistor 108 and the eleventh MOS transistor 111 form a fifth current mirror, and a mirror ratio of the eighth MOS transistor 108 to the eleventh MOS transistor 111 is 1:n
  • the ninth The MOS transistor 109 and the tenth MOS transistor 110 form a sixth current mirror
  • the mirror ratio of the ninth MOS transistor 109 to the tenth MOS transistor 110 is 1:n, where n>1.
  • the oscillator can effectively reduce power consumption and cost by adding a self-source common-gate MOS transistor in the bias circuit 100 and a current sharing technology through the second branch.
  • the circuit of the embodiment of the present invention is composed only of MOS devices and can be compatible with a standard Complementary Metal Oxide Semiconductor (CMOS) process.
  • CMOS Complementary Metal Oxide Semiconductor
  • a method for obtaining the input voltage by the current mode comparator 200 is provided, and the process parameters of the oscillator can be effectively compensated by the MOS capacitor to reduce the cost.
  • 3 is an exemplary circuit schematic diagram of current mode comparator 200 for obtaining an input voltage in accordance with an embodiment of the present invention.
  • the third branch in the embodiment of the present invention may further include a first MOS capacitor 112 connected to the eleventh MOS transistor 110 and the first MOS capacitor 112 through the first MOS capacitor 112.
  • the oscillator further includes a charge and discharge branch, and an output end of the current mode comparator 200 is connected to the first MOS capacitor 112 through the charge and discharge branch, and the charge and discharge branch is used for the first MOS
  • the capacitor 112 is charged and discharged, wherein the capacitor voltage of the first MOS capacitor 112 is the input voltage.
  • the first MOS transistor 101 to the ninth MOS transistor 109 constitute a bias circuit 100, and output a bias current I0 and a bias voltage VX, wherein the second MOS transistor 102 and the third MOS transistor 103 form a self-coupling Source common gate MOS transistor.
  • the eighth MOS transistor 108 to the eleventh MOS transistor 111 constitute a current mode comparator 200, wherein the currents of the eighth MOS transistor 108 and the ninth MOS transistor 109 branch are shared with the bias circuit 100, and the tenth MOS transistor 110 is shared.
  • the current of the eleventh MOS transistor 111 branch is used for the charging current of the first MOS capacitor 112.
  • the source and the tenth of the ninth MOS tube 109 The source of the MOS transistor 110 is an input terminal of the comparator for receiving the bias voltage generated by the bias circuit 100 and the capacitor voltage of the first MOS capacitor 112, respectively.
  • the twelfth MOS transistor 113 is a reset transistor of the first MOS capacitor 112 for resetting the capacitor voltage to GND.
  • the current density of the sixth MOS transistor 106 and the seventh MOS transistor 107 operating in the subthreshold region is different, so that the gate-source voltage difference VX (also called the bias voltage) is generated and biased in the self-common source.
  • VX also called the bias voltage
  • a common gate MOS transistor forms a self-bias current source.
  • the current of the eighth MOS transistor 108 flows to the self-bias current source, and the current of the eleventh MOS transistor 111 is reused as the charging current of the first MOS capacitor 112, that is, the ninth MOS transistor 109 and the tenth MOS.
  • the source of tube 110 is the input of the comparator.
  • the reference voltage in the embodiment of the present invention is the bias voltage VX of the self-bias current source, and the input voltage is the capacitance voltage VC of the first MOS capacitor 112. Therefore, when VC is smaller than VX, the Vcmp signal outputted by the current mode comparator 200 is at a low level, the twelfth MOS transistor 113 is turned off, and the eleventh MOS transistor 111 continues to charge the first MOS capacitor 112, and the VC voltage is linear. When VC is greater than VX, Vcmp is high level, the twelfth MOS transistor 113 is turned on to discharge the charge of the first MOS capacitor 112, VC is reset to GND; after the VC is reset to GND, the above process is repeated. A continuous Vcmp signal (pulse signal) is obtained.
  • the capacitor voltage (VC) is a sawtooth signal
  • the magnitude of the capacitor voltage (VC) is equal to the voltage value of the bias voltage (VX).
  • the technical solution of the embodiment of the present invention can effectively isolate the influence of the coupling noise of the capacitor voltage (VC) on the bias voltage (VX), thereby improving The accuracy of the output frequency of the oscillator.
  • FIG. 4 is a schematic diagram of another exemplary circuit of an embodiment of the present invention.
  • the oscillator may further include: at least one pair of inverters, wherein an output end of the current mode comparator 200 is connected to the charge and discharge branch through at least one pair of inverters, wherein the at least one pair of inverters is used for
  • the Vcmp signal output from the output terminal of the current mode comparator 200 is amplified to an RS signal (pulse signal).
  • the oscillator may include a pair of inverters (first inverter 121 and second inverter 122)
  • the duty ratio of the RS signal may also be adjusted by a flip-flop, and then a CLK signal (clock signal) is formed.
  • the oscillator may further include: a flip-flop connected to the at least one pair of inverters for generating a clock signal according to the signals output by the at least one pair of inverters.
  • the oscillator can also include a flip flop 130.
  • the number of inverters in the embodiment of the present invention may be any even number.
  • the RS signal can also be used as a clock output without being divided by two, and the difference is that the duty ratio of the clock signal is different (the former frequency is multiplied by the latter frequency).
  • the RS signal is divided by two to obtain a CLK signal (clock signal) with a duty ratio of 50%.
  • the frequency of the CLK signal in the embodiment of the present invention is calculated below.
  • C M12 is the capacitance value of the first MOS capacitor 112, and the capacitance value can be expressed as:
  • K C is a conversion factor, which can be considered as a constant in the environment of the scheme.
  • the frequency of the CLK signal in the embodiment of the present invention can be expressed as:
  • t d represents the delay of the comparator, T S >> t d, t d is not negligible weight.
  • the output frequency of the oscillator of the embodiment of the present invention is only related to the circuit parameters m, j, k, p, n, the width to length ratio of the second MOS transistor 102 and the third MOS transistor 103, and the first MOS.
  • the gate area of the capacitor 112, the carrier mobility ⁇ , the thermal voltage VT are related, and the process parameter C OX is cancelled, that is, the correlation between the output frequency of the oscillator and the process is weakened, and the output frequency can be effectively increased. Accuracy and cost reduction.
  • the oscillator in the embodiment of the present invention may further include: a starting circuit connected to the bias circuit 100, wherein the starting circuit is used to activate the bias circuit 100.
  • the oscillator can include a startup circuit 140.
  • Figure 5 is an exemplary circuit schematic of a startup circuit in accordance with an embodiment of the present invention.
  • the startup circuit 140 may include a thirteenth MOS transistor 114 to a sixteenth MOS transistor 117, and a second MOS capacitor 118.
  • VDD is powered up, due to capacitor C second
  • the MOS capacitor 118 is much larger than the drain parasitic capacitance of the fifteenth MOS transistor 116, so the VY voltage will increase as VDD rises and the sixteenth MOS transistor 117 is turned on, and the startup current will sink into the VP node to cause the bias circuit 100 to be detached. There may be zero circuit stable operating points.
  • the bias circuit 100 When the bias circuit 100 has current, it is mirrored and outputted to the fourteenth MOS transistor 115 through the thirteenth MOS transistor 114, and the VY node is pulled down to GND by the fifteenth MOS transistor 116 so that the sixteenth MOS transistor 117 is turned off, and the circuit is activated. 140 stopped working.
  • the oscillator in the embodiments of the present invention may be configured in any circuit or electronic device. That is, in the embodiment of the present invention, a CMOS integrated circuit including the above oscillator may be provided.
  • a timing chip can also be provided, the timing chip comprising a memory, and the above oscillator or the CMOS integrated circuit, the memory storing program, the oscillator or the CMOS integrated circuit for executing a program in the memory clock.
  • An electronic device may also be provided, which may include the above oscillator, or the CMOS integrated circuit, or a timing chip. The embodiment of the invention is not specifically limited.

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Abstract

一种振荡器、集成电路、计时芯片和电子设备。该振荡器包括：偏置电路（100）和电流模比较器（200）；该偏置电路（100）与该电流模比较器（200）相连，该偏置电路（100）用于生成偏置电流和偏置电压，该偏置电流用于给该电流模比较器（200）供电；该电流模比较器（200），用于接收该偏置电压，并将该偏置电压作为参考电压与输入电压进行比较生成脉冲信号。电流模比较器（200）可以共享偏置电路（100）的偏置电压，并将该偏置电压作为参考电压，从而避免了通过专门的参考电压产生电路提供参考电压，减少电路的支路数量，进而可以有效降低功耗及成本。

Description

振荡器、集成电路、计时芯片和电子设备 技术领域
本申请涉及电子技术领域，并且更具体地，涉及一种振荡器、集成电路、计时芯片和电子设备。
背景技术
低功耗蓝牙、可穿戴设备等系统在待机时需要超低功耗的振荡器作为设备系统的待机时钟，频率一般从几赫兹至数十千赫兹不等，张弛振荡器是产生该时钟的常用结构之一。
现有的技术中，常规的偏置电流源电路在产生纳安培量级的偏置电流时所需的电阻是巨大无比的，不但需要占用非常大的芯片面积，而且会导致振荡器的功耗过大，通常在几百纳安培量级，不满足超低功耗的需求。为了解决上述问题，现有技术中提出了一种使用衬底二极管反向饱和电流给电容充放电及阈值电压作为比较电压的张弛振荡器，该结构具有极低的功耗，但是其核心要素(充放电电流和比较电压)与工艺有很强相关性，成本较高，且比较器的延时特性会很差而导致输出频率精度非常差，实用性较低。
因此，本领域急需一种能够有效降低功耗的振荡器。
发明内容
提供了一种振荡器、集成电路、计时芯片和电子设备，能够有效降低功耗及成本。
第一方面，提供了一种振荡器，包括：
偏置电路和电流模比较器；
所述偏置电路与所述电流模比较器相连，所述偏置电路用于生成偏置电流和偏置电压，所述偏置电流用于给所述电流模比较器供电；
所述电流模比较器，用于接收所述偏置电压，并将所述偏置电压作为参考电压与输入电压进行比较生成脉冲信号。
本发明实施例中，不仅振荡器不需要大电阻，而且，电流模比较器可以共享偏置电路的偏置电压，并将该偏置电压作为参考电压，避免了通过专门的参考电压产生电路提供参考电压(减少电路的支路数量)，能够有效降低 功耗及成本。
在一些可能的实现方式中，所述电流模比较器包括第二支路，所述偏置电路包括：第一支路、所述偏置电压产生电路和所述第二支路，其中，所述第二支路分别与所述偏置电压产生电路和所述第一支路并联连接，所述偏置电压产生电路用于产生所述偏置电压，所述第二支路用于接收所述偏置电压，并将所述偏置电压作为所述参考电压，所述偏置电路通过复用所述第二支路产生所述偏置电流。
本发明实施例中，该偏置电路和该电流模比较器共享该第二支路，也就是说，该第二支路不仅用于生成该偏置电流，同时也是电流模比较器的组成部分，用于接收该偏置电路的偏置电压，并将该偏置电压作为参考电压使用，能够有效减少电路的支路数量，降低功耗及成本。
在一些可能的实现方式中，所述第一支路包括：第一金属氧化物半导体MOS管和自共源共栅MOS管，所述自共源共栅MOS管包括：第二MOS管和第三MOS管，所述第一MOS管通过所述第二MOS管连接至所述第三MOS管，所述第三MOS管连接至设备地，所述偏置电压产生电路连接至所述第三MOS管的漏极，所述偏置电压产生电路用于生成所述偏置电压，所述第二支路用于接收所述偏置电压，并将所述偏置电压作为所述电流模比较器的参考电压。
在一些可能的实现方式中，所述偏置电压产生电路包括第一电流镜和第二电流镜，所述第一电流镜包括第四MOS管和第五MOS管，且第四MOS管与第五MOS管的镜像比率为1：k，所述第二电流镜包括第六MOS管和第七MOS管，且第六MOS管与第七MOS管的镜像比率为j：1，所述第四MOS管通过所述第七MOS管连接至所述第三MOS管的漏极，所述第五MOS管通过所述第六MOS管连接至所述设备地，以便所述偏置电压产生电路生成所述偏置电压，其中，k＞1，j＞1。
在一些可能的实现方式中，所述第四MOS管与所述第一MOS管组成第三电流镜，且所述第四MOS管与所述第一MOS管的镜像比率为1：m，其中，m＞1。
在一些可能的实现方式中，所述第二支路包括第八MOS管和第九MOS管，所述第八MOS管通过所述第九MOS管连接至所述第三MOS管的漏极，以便所述第二支路接收所述偏置电流，并将所述偏置电压作为所述电流模比 较器的参考电压。
在一些可能的实现方式中，所述第四MOS管与所述第八MOS管组成第四电流镜，且所述第四MOS管与所述第八MOS管的镜像比率为1：p，其中，p＞1。
在一些可能的实现方式中，所述电流模比较器还包括第三支路，所述第三支路包括第十一MOS管和第十MOS管，所述第十一MOS管通过所述第十MOS管与所述输入电压的输入端相连，第三支路用于接收所述输入电压。
在一些可能的实现方式中，所述第八MOS管与所述第十一MOS管组成第五电流镜，且所述第八MOS管与所述第十一MOS管的镜像比率为1：n，所述第九MOS管与所述第十MOS管组成第六电流镜，且所述第九MOS管与所述第十MOS管的镜像比率为1：n，其中，n＞1。
本发明实施例中，设计不同的比值n能够有效调节振荡器输出频率。
在一些可能的实现方式中，所述第三支路还包括第一MOS电容，所述第十一MOS管通过所述第十MOS管和所述第一MOS电容连接至所述设备地，所述振荡器还包括充放电支路，所述电流模比较器的输出端通过所述充放电支路连接至所述第一MOS电容，所述充放电支路用于对所述第一MOS电容进行充放电，其中，所述第一MOS电容的电容电压为所述输入电压。
本发明实施例中，通过使用MOS栅电容抵消了偏置电流的工艺参数，使得振荡器输出的脉冲信号的频率与工艺的相关性变弱，能够有效提高该振荡器输出的脉冲信号的频率精度。
在一些可能的实现方式中，所述第一MOS电容的电容电压为锯齿状信号，且所述电容电压的幅度等于所述偏置电压的电压值。
在一些可能的实现方式中，所述振荡器还包括：至少一对反相器，所述电流模比较器的输出端与所述至少一对反相器相连，所述至少一对反相器用于放大所述电流模比较器输出的所述脉冲信号。
在一些可能的实现方式中，所述振荡器还包括：触发器，与所述至少一对反相器相连，用于根据所述至少一对反相器输出的信号生成时钟信号。
在一些可能的实现方式中，所述振荡器还包括：启动电路，所述启动电路与所述偏置电路相连，所述启动电路用于启动所述偏置电路。
第二方面，提供了一种互补金属氧化物半导体CMOS集成电路，所述CMOS集成电路包括第一方面所述的振荡器。
第三方面，提供了一种提供了一种计时芯片，该计时芯片包括存储器，以及第一方面的振荡器或者第二方面的CMOS集成电路，所述存储器存储程序，所述振荡器或所述CMOS集成电路用于执行所述存储器中的程序的系统时钟。
第四方面，提供了一种电子设备，该电子设备包括：第一方面中的任一种振荡器，或者，第二方面的CMOS集成电路，或者，第三方面的计时芯片。
附图说明
图1是本发明实施例的振荡器的结构性框图。
图2是本发明实施例的振荡器获取偏置电压的示意性电路原理图。
图3是本发明实施例的振荡器获取输入电压的示意性电路原理图。
图4是本发明实施例的振荡器的示意性电路原理图。
图5是本发明实施例的启动电路的示意性电路原理图。
具体实施方式
下面将结合附图，对本发明实施例中的技术方案进行描述。应理解，本发明实施例的技术方案适用于任何配置有振荡器的装置以及设备。
为了解决现有技术中的振荡器功耗大、面积大和精度差的缺点，本发明提出了一种超低功耗的振荡器，通过使用电流共享技术，能够有效减少振荡器的支路数量，进而减小功耗，降低成本。
图1是本发明实施例的振荡器的电路的示意性框图。
如图1所示，第一方面，提供了一种振荡器，包括：
偏置电路100和电流模比较器200；该偏置电路100与该电流模比较器200相连，该偏置电路100用于生成偏置电流和偏置电压，该偏置电流用于给该电流模比较器200供电；该电流模比较器200，用于接收该偏置电压，并将该偏置电压作为参考电压与输入电压进行比较生成脉冲信号。
在本发明实施例中，通过电流模比较器200共享该偏置电路100的偏置电压，避免了电流模比较器200通过专门的参考电压产生电路提供参考电压(减少电路的支路数量)，进而能够有效降低功耗及成本。
例如，该偏置电路100可以包括：第一支路、该偏置电压产生电路和第 二支路，该电流模比较器200包括该第二支路；其中，该第二支路分别与该偏置电压产生电路和该第一支路并联连接，该第二支路、该偏置电压产生电路和该第一支路用于产生该偏置电流，该偏置电压产生电路用于产生该偏置电压，该第二支路用于接收该偏置电压，并将该偏置电压作为该电流模比较器200的参考电压。
此外，该电流模比较器200还可以包括第三支路，该第三支路用于接收输入电压，使得比较器能够通过对该输入电压和该参考电压的比较，生成脉冲信号，应理解，本发明实施例中的第三支路可以采用现有技术，也可以和现有技术不一样，本发明实施例不做具体限定。
可以理解，本发明实施例中，该偏置电路100和该电流模比较器200共享该第二支路，也就是说，该第二支路不仅用于生成该偏置电流，同时也是电流模比较器200的组成部分，用于接收该偏置电路100的偏置电压，并将该偏置电压作为参考电压使用。
为便于方案的理解，下面对自共源共栅MOS管(Self-Cascode MOSFET，SCM)进行介绍。
在本发明实施例中，MOS管也被称为金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)。其中，MOSFET根据“通道”(工作载流子)的极性不同，可以分为“N型”MOS管(NMOSFET)与“P型”MOS管(PMOSFET)，对于NMOSFET，其源极和漏极接在N型半导体上，接高压为漏端，接低压为源端，实际电流方向为流入漏极。对于PMOSFET，其源极和漏极则接在P型半导体上，接高压为源端，接低压为漏端，实际电流方向为流出漏极。例如，本发明实施例中的自共源共栅MOS管可以包括两个PMOSFET，当其中一个PMOSFET工作在线性区时，电气特性上可以等效成一个电阻。
本发明实施例的偏置电路100中，通过使用自共源共栅MOS管，能够避免使用较大的电阻，不仅可以减少芯片面积的占用率，还可以产生超低的偏置电流，有效降低功耗及成本。
下面结合图2至图4对本发明实施例的振荡器的电路原理进行示例性说明。应理解，图2至图4所示的电路图仅仅是本发明实施例的示例性描述，本发明实施例不限于此。
如图2所示，本发明实施例中的自共源共栅MOS管可以包括第二MOS 管102和第三MOS管103，该第二MOS管102源极与该第三MOS管103的漏极相连，且该第二MOS管102的栅极与该第三MOS管103的栅极相连，当该第三MOS管103工作在线性区时，该第三MOS管103在电气特性上等效成一个电阻。
应理解，在本发明实施例中可能采用术语“第一”、“第二”以及“第三”等等，这些术语仅用来将部件彼此区分开，而不是用来限定这些部件。例如，第一MOS管和第二MOS管，仅仅是为了区分开这两个MOS管，这两个MOS管不限于这种术语。
下面结合图2对本发明实施例的偏置电源产生电路进行说明。
例如，如图2所示，该第一支路包括：第一金属氧化物半导体MOS管101和上述的自共源共栅MOS管，该第一MOS管101依次通过该第二MOS管102和该第三MOS管103连接至设备地GND，该偏置电压产生电路连接至该第三MOS管103的漏极，该偏置电压产生电路用于生成该偏置电压，该第二支路用于接收该偏置电压，并将该偏置电压作为该电流模比较器200的参考电压。该偏置电压产生电路包括第一电流镜和第二电流镜，该第一电流镜包括第四MOS管104和第五MOS管105，且第四MOS管104与第五MOS管105的镜像比率为1：k，该第二电流镜包括第六MOS管106和第七MOS管107，且第六MOS管106与第七MOS管107的镜像比率为j：1，该第四MOS管104通过该第七MOS管107连接至该第三MOS管103的漏极，该第五MOS管105通过该第六MOS管106连接至该设备地，以便该偏置电压产生电路生成该偏置电压，其中，k＞1，j＞1。该第二支路包括第八MOS管108和第九MOS管109，该第八MOS管108通过该第九MOS管109连接至该第三MOS管103的漏极，以便该第二支路接收该偏置电流，并将该偏置电压作为该电流模比较器200的参考电压。
可以看出，该第二电流镜会工作在亚阈值区，且镜像比率大于1(J>1)，因此，该第六MOS管106与该第七MOS管107的栅-源电压VGS将不同，即VGS106>VGS107。该第七MOS管107的源极产生一个电压，该电压等于VGS106-VGS107。该自共源共栅MOS管中，该第三MOS管103工作在线性区，电气特性上等效成一个电阻，而该第三MOS管103的漏极由通过该第七MOS管107的源极电压偏置，因此，该第三MOS管103的输出电流等于该偏置电压除以第三MOS管103的等效电阻。本发明实施例中，通 过这种结构不仅能够产生偏置电流，还避免了采用大电阻，能够有效降低芯片面积的占用率。
作为示例而非限定性地，该第四MOS管104与该第一MOS管101可以组成第三电流镜，且该第四MOS管104与该第一MOS管101的镜像比率为1：m，其中，m＞1。该第四MOS管104与该第八MOS管108可以组成第四电流镜，且该第四MOS管104与该第八MOS管108的镜像比率为1：p，其中，p＞1。应理解，在一些实现中，设备地GND也可以称为“公共地”或“实地”或“设备公共地”等。
下面计算该偏置电源产生电路生成的偏置电流I0。
如图2所示，工作在亚阈值区的第六MOS管106、第七MOS管107由于电流密度的不同会产生栅-源电压差值(也称为偏置电压)VX，该VX可表示为：
VX＝VGS6-VGS7＝nVTln(j*k)    (1)
其中，n是斜率因子，VT是热电压。
根据ACM(Advance Compact Model)模型，第三MOS管103的漏极电流ID可表示为：
Figure PCTCN2017096240-appb-000001
式中ISQ是与工艺相关的方块电流，μ是载流子迁移率，COX是工艺参数，if表示正向电流，ir表示反向电流。其中，if(r)的表达式为：
Figure PCTCN2017096240-appb-000002
式中VGB表示栅-衬底电压，VTH0是晶体管源-衬底电压为零时的阈值电压。
因为第二MOS管102是栅-漏短接，因此ir2≈0。由图2可知VS2＝VD3＝VX，因此if2＝ir3且ID2＝mI0、ID3＝(1+m+k+p)I0。根据公式(1)至公式(3)可得：
Figure PCTCN2017096240-appb-000003
由式(4)可知，将晶体管第二MOS管102、第三MOS管103设计为自共源共栅MOS管，不仅可以保证偏置电路100生成纳安培的偏置电流，同时能够极大地节省芯片面积，有效降低功耗及成本。
可以理解，本发明实施例中的电流模比较器200可以包括该第二支路， 该第二支路用于接收偏置电路100生成的偏置电压，并将该偏置电压作为参考电压，同时，该电流模比较器200还可以包括第三支路，用于接收输入电压，由此，该电流模比较器200通过比较该参考电压和该输入电压生成脉冲信号。
作为示例而非限定性地，如图2所示，该第三支路可以包括第十一MOS管111和第十MOS管110，该第十一MOS管111通过该第十MOS管110与该输入电压的输入端相连，第三支路用于接收该输入电压。
可选地，该第八MOS管108与该第十一MOS管111组成第五电流镜，且该第八MOS管108与该第十一MOS管111的镜像比率为1：n，该第九MOS管109与该第十MOS管110组成第六电流镜，且该第九MOS管109与该第十MOS管110的镜像比率为1：n，其中，n＞1。本领域技术人员可以理解，设计不同的比值n能够有效调节振荡器输出频率。
本发明实施例中，该振荡器通过在偏置电路100中添加自共源共栅MOS管，以及通过第二支路的电流共享技术，能够有效降低功耗及成本。此外，本发明实施例的电路仅由MOS器件组成，能够兼容标准的互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)工艺。
本发明实施例中，还提供了一种该电流模比较器200获取该输入电压的方式，能够通过MOS电容有效补偿振荡器的工艺参数，降低成本。图3是本发明实施例电流模比较器200获取输入电压的示例性电路原理图。
例如，如图3所示，本发明实施例中的第三支路还可以包括第一MOS电容112，该第十一MOS管111通过该第十MOS管110和该第一MOS电容112连接至该设备地，该振荡器还包括充放电支路，该电流模比较器200的输出端通过该充放电支路连接至该第一MOS电容112，该充放电支路用于对该第一MOS电容112进行充放电，其中，该第一MOS电容112的电容电压为该输入电压。
具体而言，第一MOS管101～第九MOS管109组成了偏置电路100，输出偏置电流I0和偏置电压VX，其中，第二MOS管102与第三MOS管103组成了自共源共栅MOS管。第八MOS管108～第十一MOS管111组成了电流模比较器200，其中，第八MOS管108、第九MOS管109支路的电流与偏置电路100共享，而第十MOS管110、第十一MOS管111支路的电流复用于第一MOS电容112的充电电流。第九MOS管109的源极与第十 MOS管110的源极是比较器的输入端，分别用于接收偏置电路100生成的偏置电压和第一MOS电容112的电容电压。第十二MOS管113是第一MOS电容112的复位管，用于将电容电压复位至GND。
假设，电流镜第六MOS管106：第七MOS管107＝1：j、第四MOS管104：第五MOS管105＝1：k、第四MOS管104：第一MOS管101＝1：m、第四MOS管104：第八MOS管108＝1：p，第八MOS管108：第十一MOS管111＝第九MOS管109：第十MOS管110＝1：n。
由图3可知，工作在亚阈值区的第六MOS管106、第七MOS管107的电流密度不同因此产生的栅-源电压差值VX(也称偏置电压)并偏置在自共源共栅MOS管而形成自偏置电流源。其中，第八MOS管108的电流流向该自偏置电流源，而第十一MOS管111的电流则复用作第一MOS电容112的充电电流，即，第九MOS管109与第十MOS管110的源极是比较器的输入端。也就是说，本发明实施例中的参考电压是自偏置电流源的偏置电压VX，而输入电压是第一MOS电容112的电容电压VC。由此，当VC小于VX时，电流模比较器200输出的Vcmp信号为低电平，第十二MOS管113关断，第十一MOS管111继续给第一MOS电容112充电，VC电压线性增大；当VC大于VX时，Vcmp为高电平，第十二MOS管113开启将第一MOS电容112的电荷泄放，VC复位至GND；VC复位至GND后再重复上述过程，则可得到连续的Vcmp信号(脉冲信号)。
可以看出，本发明实施例中，该电容电压(VC)为锯齿状信号，且电容电压(VC)的幅度等于该偏置电压(VX)的电压值。与现有的技术方案(比较器采用单级共源放大器)相比，本发明实施例的技术方案可以有效隔离电容电压(VC)的耦合噪声对偏置电压(VX)的影响，从而能够提高振荡器的输出频率的精度。
图4是本发明实施例的另一示例性电路原理图。
为了进一步提高该振荡器的输出频率的精度。
可选地，该振荡器还可以包括：至少一对反相器，该电流模比较器200的输出端通过至少一对反相器连接至该充放电支路，上述至少一对反相器用于将该电流模比较器200的输出端输出的Vcmp信号放大至RS信号(脉冲信号)。例如，如图4所示，该振荡器可以包括一对反相器(第一反相器121和第二反相器122)
本发明实施例中，还可以通过触发器调整该RS信号的占空比，然后形成CLK信号(时钟信号)。具体而言，该振荡器还可以包括：触发器，与上述至少一对反相器相连，用于根据上述至少一对反相器输出的信号生成时钟信号。例如，如图4所示，该振荡器还可以包括触发器130。
需要指出的是，本发明实施例中的反相器的个数可以是任意的偶数。同时RS信号也可以作为时钟输出而不需要经过二分频后在输出，它们的区别是时钟信号的占空比不同(前者频率与后者频率的呈倍数关系)。例如，RS信号经二分频后得到占空比50％的CLK信号(时钟信号)。
下面计算本发明实施例中CLK信号的频率。
CM12是第一MOS电容112的电容值，其电容值可以表示为：
CM12＝KC*COX*(W*L)12    (5)
其中，KC是折算因数，在本方案的环境中可认为它是个常数。
此外，本发明实施例中的CLK信号的频率可表示为：
Figure PCTCN2017096240-appb-000004
其中，td表示比较器的延时，TS>>td，可忽略td不计。
将式(1)、(4)以及(5)代入式(6)可得振荡器的输出频率为：
Figure PCTCN2017096240-appb-000005
电路参数设计时需要满足
Figure PCTCN2017096240-appb-000006
由式(7)可知，本发明实施例的振荡器的输出频率仅与电路参数m、j、k、p、n及第二MOS管102、第三MOS管103的宽长比及第一MOS电容112的栅面积、载流子迁移率μ、热电压VT有关，并工艺参数COX被抵消，也就是说，该振荡器的输出频率与工艺的相关性被削弱，能够有效提高输出频率的精度，降低成本。
可选地，本发明实施例中的振荡器还可以包括：启动电路，与该偏置电路100相连，上述启动电路用于启动该偏置电路100。例如，如图4所示，振荡器可以包括启动电路140。
图5是本发明实施例的启动电路的示例性电路原理图。
如图5所示，上述启动电路140可以包括：第十三MOS管114～第十六MOS管117，以及第二MOS电容118。在VDD上电时，由于电容C第二 MOS电容118远大于第十五MOS管116漏极寄生电容，所以VY电压将跟随VDD上升而增大并将第十六MOS管117打开，启动电流将灌入VP节点从而使得偏置电路100脱离可能存在的零电路稳定工作点。当偏置电路100有电流之后通过第十三MOS管114镜像输出至第十四MOS管115，由第十五MOS管116将VY节点拉低至GND使得第十六MOS管117关闭，启动电路140停止工作。
应理解，本发明实施例中的振荡器可以配置在任何电路或者电子设备中。也就是说，本发明实施例中，可以提供了一种CMOS集成电路，该CMOS集成电路包括上文中的振荡器。也可以提供了一种计时芯片，该计时芯片包括存储器，以及上文中的振荡器或者该CMOS集成电路，该存储器存储程序，该振荡器或该CMOS集成电路用于执行该存储器中的程序的系统时钟。也可以提供了一种电子设备，该电子设备可以包括：上文中的振荡器，或者，该CMOS集成电路，或者，计时芯片。本发明实施例不做具体限定。
最后，需要注意的是，在本发明实施例和所附权利要求书中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明实施例。
例如，在本发明实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的部件，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明实施例的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的装置和部件，可以是或者也可以不是物理上分开的。可以根据实际的需要选择其中的部分或者全部部件来实现本发明实施例的目的。
以上内容，仅为本发明实施例的具体实施方式，但本发明实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明实施例的保护范围之内。因此，本发明实施例的保护范围应以权利要求的保护范围为准。

Claims (17)

  1. 一种振荡器，其特征在于，包括：
    偏置电路和电流模比较器；
    所述偏置电路与所述电流模比较器相连，所述偏置电路用于生成偏置电流和偏置电压，所述偏置电流用于给所述电流模比较器供电；
    所述电流模比较器，用于接收所述偏置电压，并将所述偏置电压作为参考电压与输入电压进行比较，生成脉冲信号。
  2. 根据权利要求1所述的振荡器，其特征在于，所述电流模比较器包括第二支路，所述偏置电路包括：第一支路、偏置电压产生电路和所述第二支路；其中，所述第二支路分别与所述偏置电压产生电路和所述第一支路并联连接，所述偏置电压产生电路用于产生所述偏置电压，所述第二支路用于接收所述偏置电压，并将所述偏置电压作为所述参考电压，所述偏置电路通过复用所述第二支路产生所述偏置电流。
  3. 根据权利要求2所述的振荡器，其特征在于，所述第一支路包括：第一金属氧化物半导体MOS管和自共源共栅MOS管，所述自共源共栅MOS管包括：第二MOS管和第三MOS管，所述第一MOS管通过所述第二MOS管连接至所述第三MOS管，所述第三MOS管连接至设备地，所述偏置电压产生电路连接至所述第三MOS管的漏极，所述偏置电压产生电路用于生成所述偏置电压，所述第二支路用于接收所述偏置电压，并将所述偏置电压作为所述电流模比较器的参考电压。
  4. 根据权利要求3所述的振荡器，其特征在于，所述偏置电压产生电路包括第一电流镜和第二电流镜，所述第一电流镜包括第四MOS管和第五MOS管，且第四MOS管与第五MOS管的镜像比率为1：k，所述第二电流镜包括第六MOS管和第七MOS管，且第六MOS管与第七MOS管的镜像比率为j：1，所述第四MOS管通过所述第七MOS管连接至所述第三MOS管的漏极，所述第五MOS管通过所述第六MOS管连接至所述设备地，以使所述偏置电压产生电路生成所述偏置电压，其中，k＞1，j＞1。
  5. 根据权利要求4所述的振荡器，其特征在于，所述第四MOS管与所述第一MOS管组成第三电流镜，且所述第四MOS管与所述第一MOS管的镜像比率为1：m，其中，m＞1。
  6. 根据权利要求3所述的振荡器，其特征在于，所述第二支路包括第八MOS管和第九MOS管，所述第八MOS管通过所述第九MOS管连接至所述第三MOS管的漏极，以使所述第二支路接收所述偏置电流，并将所述偏置电压作为所述电流模比较器的参考电压。
  7. 根据权利要求6所述的振荡器，其特征在于，所述第四MOS管与所述第八MOS管组成第四电流镜，且所述第四MOS管与所述第八MOS管的镜像比率为1：p，其中，p＞1。
  8. 根据权利要求1至7中任一项所述的振荡器，其特征在于，所述电流模比较器还包括第三支路，所述第三支路包括第十MOS管和第十一MOS管，所述第十一MOS管通过所述第十MOS管与所述输入电压的输入端相连，所述第三支路用于接收所述输入电压。
  9. 根据权利要求8所述的振荡器，其特征在于，所述第八MOS管与所述第十一MOS管组成第五电流镜，且所述第八MOS管与所述第十一MOS管的镜像比率为1：n，所述第九MOS管与所述第十MOS管组成第六电流镜，且所述第九MOS管与所述第十MOS管的镜像比率为1：n，其中，n＞1。
  10. 根据权利要求8或9所述的振荡器，其特征在于，所述第三支路还包括第一MOS电容，所述第十一MOS管通过所述第十MOS管和所述第一MOS电容连接至所述设备地，所述振荡器还包括充放电支路，所述电流模比较器的输出端通过所述充放电支路连接至所述第一MOS电容，所述充放电支路用于对所述第一MOS电容进行充放电，其中，所述第一MOS电容的电容电压为所述输入电压。
  11. 根据权利要求10所述的振荡器，其特征在于，所述第一MOS电容的电容电压为锯齿状信号，且所述电容电压的幅度等于所述偏置电压的电压值。
  12. 根据权利要求1至11中任一项所述的振荡器，其特征在于，所述振荡器还包括：至少一对反相器，所述电流模比较器的输出端与所述至少一对反相器相连，所述至少一对反相器用于放大所述电流模比较器输出的所述脉冲信号。
  13. 根据权利要求12所述的振荡器，其特征在于，所述振荡器还包括：触发器，与所述至少一对反相器相连，用于根据所述至少一对反相器输出的 信号生成时钟信号。
  14. 根据权利要求1至13中任一项所述的振荡器，其特征在于，所述振荡器还包括：启动电路，所述启动电路与所述偏置电路相连，所述启动电路用于启动所述偏置电路。
  15. 一种互补金属氧化物半导体CMOS集成电路，其特征在于，包括：
    权利要求1至14中任一项所述的振荡器。
  16. 一种计时芯片，其特征在于，包括：存储器，以及，
    权利要求1至14中任一项所述的振荡器，或者，权利要求15所述的CMOS集成电路，所述存储器用于存储程序，所述振荡器或所述CMOS集成电路用于执行所述存储器中的程序的系统时钟。
  17. 一种电子设备，其特征在于，包括：
    权利要求1至14中任一项所述的振荡器，或者，权利要求15所述的CMOS集成电路，或者，权利要求16所述的计时芯片。
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