WO2018074228A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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WO2018074228A1
WO2018074228A1 PCT/JP2017/036055 JP2017036055W WO2018074228A1 WO 2018074228 A1 WO2018074228 A1 WO 2018074228A1 JP 2017036055 W JP2017036055 W JP 2017036055W WO 2018074228 A1 WO2018074228 A1 WO 2018074228A1
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region
diffusion region
semiconductor substrate
semiconductor device
main surface
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PCT/JP2017/036055
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English (en)
Japanese (ja)
Inventor
振一郎 柳
野中　裕介
誠二 野間
晋也 櫻井
奨悟 池浦
淳志 笠原
伸 瀧澤
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株式会社デンソー
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Priority claimed from JP2017076087A external-priority patent/JP6642507B2/ja
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to CN201780063822.6A priority Critical patent/CN109863581B/zh
Publication of WO2018074228A1 publication Critical patent/WO2018074228A1/fr
Priority to US16/368,026 priority patent/US11114571B2/en

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66098—Breakdown diodes
    • H01L29/66106—Zener diodes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes

Definitions

  • the present disclosure relates to a semiconductor device including a Zener diode and a manufacturing method thereof.
  • a constant voltage power supply using a Zener diode is known.
  • a constant voltage power supply is also used for a battery monitoring IC mounted on a vehicle, but high-precision voltage control is required to supply power to the IC.
  • the Zener voltage is uniquely determined depending on the concentration of both.
  • the semiconductor device disclosed in Patent Document 1 the first diffusion region and the second diffusion region are provided in the semiconductor substrate, and the impurity concentration of the two diffusion regions related to the PN junction is arbitrarily controlled. Made possible.
  • the desired Zener characteristic can be obtained by controlling the impurity concentration of the diffusion region.
  • the breakdown voltage due to the overlap is reduced at the junction due to the overlap between the first diffusion region and the second diffusion region. And it is said that yielding occurs in the part corresponding to this overlap.
  • the portion corresponding to the overlap is an area existing three-dimensionally, and the yield phenomenon occurs somewhere in the three-dimensional area, but the position is indefinite. That is, the exact position at which yield occurs cannot be controlled.
  • the occurrence of hot carriers and the state of traps on the surface defects of the hot carriers differ depending on the position where breakdown occurs, so the occurrence position of breakdown is uncertain because it causes the amount of variation in Zener voltage over time to increase. Become. Then, a change in Zener voltage with time may hinder high-accuracy voltage control.
  • an object of the present disclosure is to provide a semiconductor device capable of suppressing a change in Zener voltage and a method for manufacturing the semiconductor device.
  • a semiconductor device includes a semiconductor substrate having a diode formation region, an upper diffusion region of a first conductivity type formed in a surface layer of a main surface of the semiconductor substrate in the diode formation region, and a depth of the semiconductor substrate.
  • a lower diffusion region of a second conductivity type formed at a position deeper than the upper diffusion region with respect to the main surface in the vertical direction, and the lower diffusion region is a PN junction with the upper diffusion region at a position deeper than the main surface And has a local maximum point indicating the local maximum in the impurity concentration profile of the lower diffusion region in the diode formation region.
  • the breakdown phenomenon can be easily generated at the maximum point.
  • the designer can arbitrarily determine the impurity concentration of the lower diffusion region and its peak position, and can control the position where the breakdown phenomenon occurs. That is, the variation factor of the Zener voltage can be suppressed to the minimum.
  • the PN junction surface between the upper diffusion region and the lower diffusion region is formed at a position deeper than the main surface of the semiconductor substrate, it is trapped by surface defects existing on the main surface when hot carriers are generated. Probability can be reduced. That is, the fluctuation amount of the Zener voltage can be reduced.
  • the method for manufacturing a semiconductor device according to the second aspect of the present disclosure is such that a semiconductor substrate is prepared, impurities are implanted into a surface layer of the main surface of the semiconductor substrate, and a rotationally symmetric shape is obtained when the main surface is viewed from the front.
  • An upper implantation region of the first conductivity type is formed at a position shallower to the main surface than the lower implantation region so as to have a rotationally symmetric shape concentric with the lower implantation region, After forming, the lower implantation region is diffused by annealing to form the lower diffusion region, and the upper implantation region is diffused to form the upper diffusion region.
  • the local maximum point where the impurity concentration becomes maximum can be formed on the rotational symmetry axis of the lower implantation region, the variation factor of the Zener voltage can be suppressed to the minimum.
  • a semiconductor device includes a second conductivity type semiconductor substrate having a diode formation region, and a first conductivity type upper diffusion formed in a surface layer of a main surface of the semiconductor substrate in the diode formation region.
  • a second conductivity type lower diffusion region formed at a position deeper than the upper diffusion region with respect to the main surface in the depth direction of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate; and a diode formation region
  • a second conductivity type counter electrode region formed on a surface layer of the main surface and having an impurity concentration higher than that of the semiconductor substrate, and further, a surface layer of the main surface between the upper diffusion region and the counter electrode region In the region, an inter-electrode region of the second conductivity type having an impurity concentration higher than that of the semiconductor substrate is formed.
  • the method for manufacturing a semiconductor device includes preparing a second conductivity type semiconductor substrate, implanting impurities into the surface layer of the main surface of the semiconductor substrate, and having an impurity concentration higher than that of the semiconductor substrate. Forming a raised second conductivity type lower implantation region; forming a lower implantation region; diffusing the lower implantation region by annealing; and diffusing by annealing of the lower implantation region; Impurities are implanted into the surface layer to form an upper implantation region of the first conductivity type at a position shallower than the main surface of the lower implantation region. After forming the upper implantation region, the lower implantation region is diffused by annealing.
  • FIG. 1 is a diagram illustrating a cross section and an upper surface of the semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view showing a process of preparing a semiconductor substrate
  • FIG. 3 is a cross-sectional view showing a process of forming the lower implantation region
  • FIG. 4 is a cross-sectional view showing the first annealing step
  • FIG. 5 is a cross-sectional view showing a process of forming the upper implantation region
  • FIG. 6 is a cross-sectional view showing the second annealing step
  • FIG. 7 is a diagram showing a three-dimensional profile of impurity concentration.
  • FIG. 8 is a diagram showing the change over time in the amount of fluctuation of the Zener voltage.
  • FIG. 9 is a cross-sectional view of the semiconductor device according to the second embodiment.
  • FIG. 10 is a cross-sectional view showing a process of forming the lower implantation region
  • FIG. 11 is a cross-sectional view showing the first annealing step
  • FIG. 12 is a cross-sectional view showing the process of forming the upper implantation region
  • FIG. 13 is a cross-sectional view of the semiconductor device according to the third embodiment.
  • FIG. 14 is a cross-sectional view showing a process of forming a lower injection region and a counter electrode injection region
  • FIG. 15 is a cross-sectional view showing the first annealing step
  • FIG. 16 is a cross-sectional view showing a process of forming the upper injection region and the interelectrode injection region
  • FIG. 17 is a cross-sectional view of the semiconductor device according to the fourth embodiment.
  • This semiconductor device includes a Zener diode as an element, and is introduced into a power supply circuit, for example, and functions as a constant voltage power supply.
  • the semiconductor device 100 includes a semiconductor substrate 10, an upper diffusion region 20, a lower diffusion region 30, and a silicide block layer 40.
  • the semiconductor substrate 10 is a part of an N conductivity type semiconductor wafer, and in particular, FIG. 1 shows a part of the main surface 10a side.
  • the semiconductor substrate 10 has a diode formation region Di.
  • a PN junction diode is formed as an element by forming an upper diffusion region 20 and a lower diffusion region 30 described later.
  • the P diffusion type upper diffusion region 20 functions as an anode
  • the N conductivity type semiconductor substrate 10 functions as a cathode.
  • the N conductivity type corresponds to the second conductivity type
  • the P conductivity type corresponds to the first conductivity type.
  • the upper diffusion region 20 is a P conductivity type semiconductor region.
  • the upper diffusion region 20 is formed in the surface layer on the main surface 10 a side of the semiconductor substrate 10 so as to be exposed on the main surface 10 a of the semiconductor substrate 10.
  • the upper diffusion region 20 is formed to be rotationally symmetric with respect to an axis A orthogonal to the main surface 10a.
  • the upper diffusion region 20 in the present embodiment is formed in a substantially perfect circle shape centered on a point passing through the axis A when the main surface 10a is viewed from the front.
  • region 20 has a structure which became depressed so that the axis
  • the upper diffusion region 20 in the present embodiment is a substantially perfect circle when the main surface 10a is viewed from the front, and has a shape like a so-called rotating body, but does not necessarily need to be a rotating body.
  • the shape may be n times symmetrical when the main surface 10a is viewed from the front.
  • an ellipse, a capsule shape (2-fold symmetry), an equilateral triangle (3-fold symmetry), a square (4-fold symmetry), or the like may be employed.
  • the lower diffusion region 30 is an N conductivity type semiconductor region.
  • the lower diffusion region 30 is formed so as to cover the upper diffusion region 20.
  • the lower diffusion region 30 is also rotationally symmetric with respect to the axis A.
  • the lower diffusion region 30 in the present embodiment has an axis when the main surface 10a is viewed from the front. It is formed in a substantially perfect circle shape centered on a point passing through A. Also for the lower diffusion region 30, the shape of the main surface 10 a when viewed from the front is not limited to a perfect circle, but may be formed to be n times symmetrical.
  • a PN junction surface S is formed between the lower diffusion region 30 of N conductivity type and the upper diffusion region of P conductivity type. Yes.
  • the PN junction surface S also has the same shape. That is, the PN junction surface S has a concave shape when the upper diffusion region 20 is mainly used.
  • the lower diffusion region 30 in the present embodiment completely covers the upper diffusion region 20, and a part thereof is exposed to the main surface 10a. That is, when the main surface 10a is viewed from the front, the lower diffusion region 30 is exposed to the main surface 10a in a region beyond the outer edge of the upper diffusion region 20 with respect to the formation center. In other words, when the main surface 10a is viewed from the front, the upper diffusion region 20, the lower diffusion region 30, and the N-conductivity type semiconductor region of the semiconductor substrate 10 are arranged in this order around the point where the axis A intersects the main surface 10a. It is formed in a concentric circle.
  • the P conductivity type semiconductor region of the upper diffusion region 20 and the lower diffusion region 30 and the N conductivity type semiconductor region of the semiconductor substrate 10 form a PN junction to form a diode.
  • the P diffusion type upper diffusion region 20 functions as an anode
  • the N conductivity type semiconductor substrate 10 functions as a cathode.
  • the silicide block layer 40 is an insulating film, and is formed of, for example, SiO 2 in this embodiment.
  • the silicide block layer 40 is formed in an annular shape around the point where the axis A and the main surface 10a intersect.
  • the upper diffusion region 20 and the lower diffusion region 30 are exposed on the main surface 10a, and the semiconductor region of the semiconductor substrate 10 is exposed outside thereof.
  • the silicide block layer 40 is formed so as to cover the surface from the outer edge of the upper diffusion region 20 through the lower diffusion region 30 to the semiconductor region of the semiconductor substrate 10.
  • the silicide block layer 40 functions as an electrode for the anode and the cathode. For example, when a silicide electrode containing cobalt is stacked on the main surface 10a, the silicide block layer 40 and the N diffusion type P diffusion region 20 are formed. It is formed for the purpose of maintaining electrical insulation between the lower diffusion region 30 and the semiconductor substrate 10.
  • a semiconductor substrate 10 having N conductivity type is prepared.
  • an N conductivity type lower implantation region 31 having a diameter R is formed. That is, a disk-shaped N conductivity type region having the axis A as the rotational symmetry axis is formed.
  • the lower implantation region 31 is a region before being diffused by annealing, and becomes the lower diffusion region 30 after two annealing steps described later.
  • the photoresist (not shown) is removed and a first annealing process is performed.
  • impurities forming the lower implantation region 31 diffuse in the semiconductor substrate 10 as shown in FIG.
  • the impurity region 32 in which the lower implantation region 31 is thermally diffused does not diffuse as much as the lower diffusion region 30 shown in FIG.
  • a photoresist (not shown) having the same center as that of the lower implantation region 31 and having a smaller diameter than the impurity region 32 shown in FIG. And boron is ion-implanted.
  • the ion implantation is performed with the same energy on the one surface 10a, and the implantation depth is made substantially constant.
  • a P conductivity type upper implantation region 21 surrounded by the impurity region 32 is formed. That is, a disk-shaped P conductivity type region having the axis A as a rotationally symmetric axis is formed.
  • the upper implantation region 21 is a region before being diffused by annealing, and becomes the upper diffusion region 20 after the second annealing step described later.
  • the photoresist (not shown) is removed and a second annealing step is performed.
  • the second annealing step the upper implantation region 21 is thermally diffused as shown in FIG. 6, and the impurity region 32 in which the lower implantation region 31 is diffused to some extent is further thermally diffused.
  • the upper implantation region 21 diffuses to a region corresponding to the upper diffusion region 20, and the lower implantation region 31 diffuses to a region corresponding to the lower diffusion region 30.
  • the formation depth of the lower diffusion region 30 after thermal diffusion is preferably designed to be substantially the same as the ion implantation diameter R of the lower implantation region 31.
  • Parameters for the annealing temperature, ion implantation energy, and impurity concentration may be determined by making the process common with other elements formed on the semiconductor substrate 10, and it may be difficult to change the values.
  • the formation depth of the lower diffusion region 30 is designed to be substantially the same as the ion implantation diameter R of the lower implantation region 31, the formation radius of the lower implantation region 31 is set to be the same as that of the assumed lower diffusion region 30. It means to match the formation depth.
  • the impurity concentration of the impurity region 32 caused by the lower implantation region 31 has a peak at a position on the axis A and deeper than the upper implantation region 21.
  • the conductivity type is unlikely to be reversed in the vicinity of the center of the disk-shaped upper implantation region 21.
  • the cross-sectional shape passing through the axis A of the upper diffusion region 20 becomes a structure that is recessed toward the vicinity of the axis A as shown in FIG. 1. Yes. That is, the upper diffusion region 20 is formed in a disk shape with a recessed center. That is, the PN junction surface S between the upper diffusion region 20 and the lower diffusion region 30 has a concave shape when the upper diffusion region 20 is mainly used.
  • contour lines shown in the lower diffusion region 30 in FIG. 6 indicate the contour lines of the impurity concentration, and that the peak of the impurity concentration in the lower diffusion region 30 is located below the dent in the upper diffusion region 20. Show.
  • the silicide block layer 40 is formed so as to straddle the boundary line L2 with the substrate 10.
  • the semiconductor device 100 can be manufactured by a manufacturing method including the above steps.
  • the respective impurity profiles are also substantially rotationally symmetric with respect to the axis A. It becomes.
  • the inventor simulated a specific impurity profile using a computer. The simulation results are shown in FIG.
  • the lower diffusion region 30 formed in the diode formation region Di has a maximum point P at which the impurity concentration is maximum.
  • the maximum point P in the present embodiment is on the axis A and is located below the PN junction surface S.
  • the high impurity concentration portion of the lower diffusion region 30 exhibiting N conductivity is not three-dimensionally distributed as in the prior art, but is defined as zero dimension (point). Therefore, it is possible to identify the portion where the yield phenomenon occurs as a point. That is, the yielding phenomenon in the semiconductor device 100 can be fixed at a substantially predetermined position (maximum point P).
  • the cause of increasing the amount of fluctuation of the Zener voltage over time is presumed to be that the generation of the breakdown phenomenon is indefinite because the generation source of the breakdown phenomenon is distributed three-dimensionally.
  • the occurrence position of the breakdown phenomenon can be determined as a point. According to this, as compared with the conventional configuration in which the breakdown phenomenon occurs three-dimensionally, the generation position of the breakdown phenomenon can be limited. As shown in FIG. It can be suppressed compared to.
  • the output voltage can be controlled with high accuracy regardless of the passage of time.
  • the semiconductor device 100 has a concave structure in which the PN junction surface S is recessed when the upper diffusion region 20 is mainly used.
  • the structure is recessed near the axis A. According to this, as shown in FIG. 7, it is possible to easily form an impurity distribution having a peak in the lower diffusion region 30 at the lower portion of the recessed portion of the upper diffusion region 20. In other words, the maximum impurity concentration can be easily formed in a dot shape.
  • the upper diffusion region 20 and the lower diffusion region 30 have a rotationally symmetric shape, particularly a perfect circle shape, when the one surface 10a is viewed from the front.
  • the maximum of the impurity concentration in the lower diffusion region 30 can be on the rotational symmetry axis (axis A in the present embodiment), and the maximum of the impurity concentration can be easily formed in a dot shape.
  • the formation diameter R of the lower implantation region 31 that is a precursor region of the lower diffusion region 30 is substantially the same as the assumed formation depth of the lower diffusion region 30.
  • the maximum of the impurity concentration in the lower diffusion region 30 can be easily formed in a dot shape.
  • the maximum impurity concentration is distributed one-dimensionally or two-dimensionally extending in the direction along the main surface 10a. Cheap.
  • the maximum impurity concentration in the lower diffusion region 30 can be easily formed in a dot shape.
  • the semiconductor device 100 ion-implants impurities with a uniform depth in the manufacturing process, particularly in the formation of the upper implantation region 21.
  • the conductivity type is easily reversed at the portion where the impurity concentration in the impurity region 32 which is the precursor region of the lower diffusion region 30 is low, and the concave structure of the PN junction surface S can be easily formed. it can. That is, as described above, the maximum impurity concentration of the lower diffusion region 30 can be easily formed in a dot shape.
  • the lower diffusion region 30 is formed so as to cover the upper diffusion region 20, and is exposed to the main surface 10a.
  • the depletion layer formed between the P conductivity type upper diffusion region 20 and the N conductivity type region extends in the direction along the main surface 10a. 30 can be suppressed as compared with a configuration in which the main surface is not exposed. Thereby, it is possible to suppress trapping of hot carriers at a level caused by surface defects existing in the vicinity of the main surface 10a, and it is possible to suppress an amount of fluctuation of the Zener voltage with time.
  • the semiconductor device 100 includes the silicide block layer 40 on the main surface 10a.
  • the silicide block layer 40 is formed so as to straddle the PN junction line L1 between the upper diffusion region 20 and the lower diffusion region 30 when the lower diffusion region 30 is exposed to the main surface 10a.
  • it should be formed so as to straddle the boundary line L ⁇ b> 2 between the lower diffusion region 30 and the semiconductor region in the semiconductor substrate 10.
  • the lower diffusion region 30 is not exposed to the main surface 10 a, it should be formed so as to straddle the boundary line between the upper diffusion region 20 and the semiconductor region in the semiconductor substrate 10.
  • the PN junction surface S between the upper diffusion region 20 and the lower diffusion region 30 is a concave surface, but a convex surface may be used.
  • the semiconductor device 110 in this embodiment includes an upper diffusion region 50 and a lower diffusion region 60 having shapes different from those in the first embodiment, as shown in FIG.
  • the semiconductor device 110 has a convex surface portion C that becomes a convex surface in the cross section of the PN junction surface S.
  • the shape of the upper diffusion region 50 and the lower diffusion region 60 when viewed from the main surface 10a is a perfect circle, and an axis B passing through the center of the perfect circle and orthogonal to the main surface 10a is an axis of symmetry.
  • a rotating body is formed.
  • the concave portion C has a convex vertex on the axis B.
  • the impurity concentration of the lower diffusion region 60 has a peak in the vicinity of the lower portion of the concave surface portion formed outside the convex surface portion C of the PN junction surface S. That is, the cross section shown in FIG. 9 has the maximum point of impurity concentration at the points indicated by points P1 and P2.
  • the maximum points P1 and P2 are also part of a circle having the axis B as the symmetry axis. That is, as for the maximum points of the impurity concentration of the lower diffusion region 60 in the present embodiment, a plurality of maximum points are distributed around the axis B in a one-dimensional manner (specifically, in a circular shape).
  • the maximum points of the impurity concentration of the lower diffusion region 60 can be distributed one-dimensionally. Similar to the first embodiment, since the maximum point of the impurity concentration is effective as the occurrence position of the breakdown phenomenon, the occurrence position of the breakdown phenomenon can be defined as a line in the semiconductor device 110. According to this, as compared with the conventional configuration in which the breakdown phenomenon occurs three-dimensionally, the generation position of the breakdown phenomenon can be limited, and the variation of the Zener voltage with time can be suppressed. For example, when a Zener diode included in the semiconductor device 110 is employed as a constant voltage power source, the output voltage can be controlled with high accuracy regardless of the passage of time.
  • a semiconductor substrate 10 is prepared as shown in FIG.
  • the lower injection region 61 is formed in a rotationally symmetric shape with the axis B as the axis of symmetry. In particular, in the present embodiment, it is formed in an annular shape.
  • the lower injection region 31 in the first embodiment is a perfect circle when viewed from the main surface 10a, but the lower injection region 61 in the present embodiment is an annular shape in which the vicinity of the center is hollowed out. Since FIG. 10 is a cross-sectional view, the two lower injection regions 61 are illustrated as being separated from each other, but are actually continuous in the front-rear direction of the paper.
  • the lower implantation region 61 is a region that becomes the lower diffusion region 60 by two thermal diffusions in a later process.
  • the first annealing step is performed.
  • the lower implantation region 61 is thermally diffused to form an N conductivity type impurity region 62. Since the lower implantation region 61 before the annealing step is annular, the impurity concentration structure in the impurity region 62 after the thermal diffusion is a substantially torus structure in which the higher concentration portion is distributed in a circle having the axis B as the symmetry axis. ing.
  • the upper implantation region 51 is formed so as to be included in the impurity region 62. Specifically, the upper implantation region 51 is formed on the upper portion of the impurity region 61 that is the precursor region of the lower diffusion region 60 where the concentration reaches a peak. That is, the upper injection region 51 is formed in a rotationally symmetric shape with the axis B as the axis of symmetry. In particular, in the present embodiment, the upper injection region 51 is formed in an annular shape.
  • the upper injection region 21 in the first embodiment is a perfect circle when viewed from the main surface 10a, but the upper injection region 51 in the present embodiment has an annular shape in which the vicinity of the center is hollowed out. Since FIG. 12 is a cross-sectional view, the two upper injection regions 51 are illustrated so as to be separated from each other, but are actually continuous in the front-rear direction of the drawing.
  • the upper implantation region 51 is a region that becomes the upper diffusion region 50 by two thermal diffusions in a later step.
  • a second annealing step is performed.
  • the upper implantation region 51 is thermally diffused, and the impurity region 62 in which the lower implantation region 61 is diffused to some extent is further thermally diffused.
  • the upper implantation region 51 after the second annealing step is diffused to a region corresponding to the upper diffusion region 50, and the lower implantation region 61 is diffused to a region corresponding to the lower diffusion region 60.
  • the torus shape of the impurity concentration distribution of the impurity region 62 which is a precursor region of the lower diffusion region 60 is substantially maintained, and the maximum impurity concentration of the lower diffusion region 60 is configured in the circular shape as described above.
  • the silicide block layer 40 is formed so as to straddle the PN junction line between the P conductivity type upper diffusion region 50 exposed on the main surface 10a and the N conductivity type semiconductor region, and the boundary line between the lower diffusion region 60 and the semiconductor substrate 10. To do.
  • the semiconductor device 110 in which the PN junction surface S is a convex surface can be manufactured.
  • the depletion layer when the breakdown occurs is the lower diffusion regions 30 and 60 in the surface layer of the semiconductor substrate 10. May extend to a wide area outside. This is presumed to be caused by surface traps in the surface layer of the semiconductor device 10, and an increase in the electrical resistance of the current path between the upper diffusion regions 20 and 50 as the anode and the cathode occurs. This increase in electrical resistance may cause a change in Zener voltage with time.
  • the semiconductor device 120 has a cathode whose impurity concentration is higher than that of the semiconductor substrate 10 in the diode formation region Di in addition to the upper diffusion region 70 and the lower diffusion region 80.
  • a region 90 and an inter-electrode region 91 formed between the upper diffusion region 70 functioning as an anode and the cathode region 90 are provided.
  • the cathode region 90 corresponds to a counter electrode region.
  • the upper diffusion region 70 and the lower diffusion region 80 in the present embodiment are formed in the same manner as the upper diffusion region 20 and the lower diffusion region 30 in the first embodiment, respectively. That is, the upper diffusion region 70 is a P conductivity type semiconductor region formed so as to be exposed on the main surface 10 a, and the lower diffusion region 80 is formed so as to cover the upper diffusion region 70 in the semiconductor substrate 10. This is an N conductivity type semiconductor region. Although a detailed structure has been described in the first embodiment, it will be omitted. However, in this embodiment as well, the PN junction surface S between the upper diffusion region 70 and the lower diffusion region 80 has a concave shape, and the breakpoint is almost the same. It is structurally controlled to be formed as a point (0 dimension).
  • the cathode region 90 which is a counter electrode region is an N conductivity type semiconductor region having a concentration higher than that of the semiconductor substrate 10 and is an annular region concentric with the upper diffusion region 70 when the main surface 10a is viewed from the front. .
  • Cathode region 90 is exposed at main surface 10a, and the cathode electrode is in ohmic contact with the exposed surface.
  • the cathode region 90 and the lower diffusion region 80 are formed by the same process, and the average impurity concentration is substantially the same.
  • the interelectrode region 91 is an N conductivity type semiconductor region formed between the upper diffusion region 70 and the cathode region 90.
  • the interelectrode region 91 has an impurity concentration higher than that of the semiconductor substrate 10.
  • the inter-electrode region 91 is formed so as to be exposed on the main surface 10a, whereby the region surrounded by the cathode region 90 is exposed on the main surface 10a of the N conductivity type region constituting the semiconductor substrate 10. Not done.
  • the distribution of the radial impurities seen from the center of the upper diffusion region 70 is the P conductivity type of the upper diffusion region 70 and the N conductivity type of the lower diffusion region 80 exposed on the main surface 10a.
  • the N conductivity type of the inter-electrode region 91 and the N conductivity type of the cathode region 90 are spread concentrically.
  • the interelectrode region 91 is formed as a separate process from the process of forming the lower diffusion region 80 and the cathode region 90. Therefore, the impurity concentration in the inter-electrode region 91 can be controlled independently of the lower diffusion region 80 and the cathode region 90, and is determined based on the intention of the designer.
  • the impurity concentration of the interelectrode region 91 needs to be lower than that of the cathode region 90 to which the cathode electrode is connected, is higher than that of the semiconductor substrate 10, and is impurity concentration of the lower diffusion region 80. Preferably, the concentration is lower than the maximum value.
  • the place where the impurity concentration of the lower diffusion region 80 in the present embodiment is the maximum is the maximum point of the impurity concentration, which is formed as a point (zero dimension) and becomes a breakpoint.
  • the impurity concentration in the inter-electrode region 91 is set lower than this breakpoint. Thereby, breakdown in the vicinity of the inter-electrode region 91 is prevented. In other words, breakdown is intentionally generated in the lower diffusion region 80.
  • the method for manufacturing the semiconductor device 120 will be described with reference to FIGS. 14 to 16 with reference to the description regarding the method for manufacturing the semiconductor device 100 in the first embodiment.
  • a semiconductor substrate 10 having N conductivity type is prepared.
  • the lower implantation region 81 is formed by ion implantation, as in the first embodiment.
  • the counter electrode injection region 92 is formed by the same or different process as the lower injection region 81. Both lower injection region 81 and counter electrode injection region 92 are formed in the surface layer of main surface 10a. These regions are regions that become the lower diffusion region 80 and the cathode region 90 by an annealing process described later.
  • an annealing process is performed to thermally diffuse impurities.
  • impurities are diffused in the semiconductor substrate 10 to form a semiconductor region having a higher concentration than the semiconductor substrate 10 by the annealing process.
  • ions are implanted into the region where the lower implantation region 81 is thermally diffused by the annealing process, thereby forming a P conductivity type upper implantation region 71. Further, ions are implanted into the surface layer of the main surface 10 a surrounded by the lower implantation region 81 and the counter electrode implantation region 92 to form an N conductivity type interelectrode implantation region 93.
  • the silicide block layer 40 is formed in an annular shape, and the semiconductor device 120 is manufactured.
  • the silicide block layer 40 has an annular inner edge that covers the upper diffusion region 70 and an annular outer edge that covers the cathode region 90. That is, the exposed portion of the lower diffusion region 80 and the inter-electrode region 91 in the main surface 10 a are completely hidden by the silicide block layer 40.
  • the depletion layer when breakdown occurs may extend to a wide region outside the lower diffusion regions 30 and 60 in the surface layer of the semiconductor substrate 10, which is a surface trap in the surface layer of the semiconductor device 10. It is presumed to be caused.
  • the semiconductor device 120 includes the cathode region 90 and the inter-electrode region 91 having a higher concentration than that of the semiconductor substrate 10 so that the N-conductivity type impurity layer constituting the semiconductor substrate 10 is not exposed in the semiconductor substrate 10a. Yes.
  • an interelectrode region 91 is formed as a portion where a lower diffusion region 80 and a cathode region 90 as a counter electrode region overlap.
  • the inter-electrode region 91 is of N conductivity type, and is higher in concentration than the impurity concentration constituting the semiconductor substrate 10 as in the third embodiment.
  • the upper diffusion regions 20, 50, and 70 and the upper implantation regions 21, 51, and 71 are formed in a perfect circle shape with the axis A or the axis B as the symmetry axis.
  • the shapes of the upper diffusion regions 20, 50, 70 and the upper injection regions 21, 51, 71 viewed from the front from the surface 10a are not limited to a perfect circle, and may be n-fold symmetrical shapes. Specifically, an ellipse, capsule shape (2 times symmetry), equilateral triangle (3 times symmetry), square (4 times symmetry), regular pentagon (5 times symmetry), regular hexagon (6 times symmetry), etc. are adopted. Also good.
  • the lower diffusion regions 30, 60, 80 and the lower injection regions 31, 61, 81 are formed in a perfect circle shape with the axis A or the axis B as a symmetry axis is shown.
  • the shapes of the lower diffusion regions 30, 60, 80 and the lower implantation regions 31, 61, 81 are not limited to a perfect circle, but may be any n-fold symmetrical shape. In the two-fold symmetrical shape, the maximum impurity concentration is not a point but a linear shape (one-dimensional) along the long side.
  • the lower diffusion regions 30, 60, 80 corresponding to the upper diffusion regions 20, 50, 70 are preferably similar in shape to each other when viewed from the main surface 10a. Since the upper diffusion regions 20, 50, 70 and the corresponding lower diffusion regions 30, 60, 80 have symmetry, the lower diffusion regions 30, 60, 80 break in one or zero dimensions lower than three dimensions. It is easy to form points.
  • the silicide block layer 40 is formed in the same center as the upper diffusion regions 20, 50, 70 and the lower diffusion regions 30, 60, 80 has been described. However, the formation center may be shifted. It should be noted that the silicide block layer 40 may be unnecessary if the electrode is not formed by silicide, and is not an essential element in such a form.
  • the P conductivity type is adopted for the upper diffusion regions 20 and 50 and the N conductivity type is adopted for the lower diffusion regions 30 and 60.
  • these conductivity types are configured to be reversed to each other. May be.
  • substrate was described as a semiconductor substrate, about the semiconductor substrate, N conductivity type and P conductivity were used irrespective of the conductivity type of the upper diffusion regions 20 and 50 and the lower diffusion regions 30 and 60. Any type of mold may be employed.
  • the inter-electrode region 91 is provided, the counter electrode region corresponding to the cathode region 90, the lower diffusion regions 30, 60, and 80, and the semiconductor substrate 10 need to be of the same conductivity type.
  • the lower diffusion regions 30, 60, 80 are illustrated as being exposed to the main surface 10 a by completely covering the corresponding upper diffusion regions 20, 50, 70 inside the semiconductor substrate 10.
  • the lower diffusion region may be positioned only below the upper diffusion region and not exposed to the main surface 10a.
  • the P conductivity type upper diffusion regions 20, 50, 70 and N The spread of the depletion layer formed between the conductive type region in the direction along the main surface 10a can be suppressed as compared with the configuration in which the lower diffusion regions 30, 60, and 80 are not exposed on the main surface.
  • the diode formation region Di in which a Zener diode is formed in the semiconductor substrate 10 has been described.
  • another element is formed in the semiconductor substrate 10 in a region other than the diode formation region. I will not prevent it.
  • a MOSFET or IGBT may be separately formed on the same semiconductor substrate 10.
  • the joint surface between the upper diffusion regions 20, 50, 70 and the lower diffusion regions 30, 60, 80 has a concave shape, so that the lower diffusion regions 30, 60, 80 are formed.
  • the configuration in which the maximum point indicating the maximum concentration is formed has been described.
  • the bonding surface between the upper diffusion regions 20, 50, 70 and the lower diffusion regions 30, 60, 80 is flat.
  • the formation of the inter-electrode region 91 can provide an effect of suppressing the variation with time of the Zener voltage.
  • the effect of providing the inter-electrode region 91 can be realized independently of the technical idea of forming a maximum point indicating the maximum concentration in the impurity concentration profile of the lower diffusion regions 30, 60, 80. .

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Abstract

La présente invention concerne un dispositif à semi-conducteur qui est pourvu : d'un substrat semi-conducteur (10) pourvu d'une région de formation de diode (Di); d'une région de diffusion supérieure d'un premier type de conductivité (20, 50, 70) formée dans la couche de surface d'une surface principale (10a) du substrat semi-conducteur, ainsi que dans la région de formation de diode; d'une région de diffusion inférieure d'un second type de conductivité (30, 60, 80) formée à un endroit plus profond que la région de diffusion supérieure par rapport à la surface principale dans le sens de la profondeur du substrat semi-conducteur, et qui possède une concentration d'impuretés plus élevée que le substrat semi-conducteur. En outre, la région de diffusion inférieure forme une surface de jonction PN (S) avec la région de diffusion supérieure à un endroit plus profond que la surface principale, et comprend un point maximal (P, P1, P2) qui indique la concentration maximale dans un profil de concentration d'impuretés de la région de diffusion inférieure dans la région de formation de diode.
PCT/JP2017/036055 2016-10-18 2017-10-04 Dispositif à semi-conducteur et son procédé de fabrication WO2018074228A1 (fr)

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JPS5662374A (en) * 1979-10-18 1981-05-28 Philips Nv Zener diode
JPH08507178A (ja) * 1993-12-18 1996-07-30 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング ドリフトフリーアバランシ降伏ダイオード
JP2002057349A (ja) * 2000-08-10 2002-02-22 Fuji Electric Co Ltd 半導体装置
JP2006319072A (ja) * 2005-05-11 2006-11-24 Denso Corp 半導体装置およびその設計方法

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EP0283788A1 (fr) * 1987-03-09 1988-09-28 Siemens Aktiengesellschaft Dispositif semi-conducteur de puissance à extinction
TW335557B (en) * 1996-04-29 1998-07-01 Philips Electronics Nv Semiconductor device
JP5191132B2 (ja) * 2007-01-29 2013-04-24 三菱電機株式会社 半導体装置
WO2011141981A1 (fr) * 2010-05-10 2011-11-17 株式会社日立製作所 Dispositif à semi-conducteur
CN103460392B (zh) * 2011-04-04 2016-02-10 三菱电机株式会社 半导体装置及其制造方法
JP5898473B2 (ja) * 2011-11-28 2016-04-06 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662374A (en) * 1979-10-18 1981-05-28 Philips Nv Zener diode
JPH08507178A (ja) * 1993-12-18 1996-07-30 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング ドリフトフリーアバランシ降伏ダイオード
JP2002057349A (ja) * 2000-08-10 2002-02-22 Fuji Electric Co Ltd 半導体装置
JP2006319072A (ja) * 2005-05-11 2006-11-24 Denso Corp 半導体装置およびその設計方法

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