WO2018058915A1 - Dispositif de détection de perte de signal d'horloge - Google Patents

Dispositif de détection de perte de signal d'horloge Download PDF

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Publication number
WO2018058915A1
WO2018058915A1 PCT/CN2017/077152 CN2017077152W WO2018058915A1 WO 2018058915 A1 WO2018058915 A1 WO 2018058915A1 CN 2017077152 W CN2017077152 W CN 2017077152W WO 2018058915 A1 WO2018058915 A1 WO 2018058915A1
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signal
delay unit
gate
output
input
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PCT/CN2017/077152
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English (en)
Chinese (zh)
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司晓明
赵春河
李超林
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深圳市中兴微电子技术有限公司
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Publication of WO2018058915A1 publication Critical patent/WO2018058915A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/19—Monitoring patterns of pulse trains

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  • the present invention relates to the field of signal detection technologies, and in particular, to a device for detecting clock loss.
  • the conventional clock loss detecting device simultaneously counts the number of cycles of the input clock signal and the reference clock signal, and determines whether the input clock signal is lost by comparing the number of cycles of the input clock signal and the reference clock signal in a fixed period of time.
  • 1 is a schematic diagram of clock loss detection in the prior art. As shown in FIG. 1, the period of the input clock signal and the reference clock signal are simultaneously counted. When the count value of the reference clock signal reaches the set count threshold M, it is determined. At this time, the magnitude relationship between the count value N of the input clock signal and the count value M of the reference clock signal is determined. When M is greater than N, it is judged that the input clock signal is lost, and when M is less than or equal to N, it is judged that the input clock signal is not lost.
  • the traditional clock loss detection device has the advantage that the implementation principle is simple and intuitive, and can be directly realized by digital circuits.
  • the disadvantage is that additional reference signals are needed, and additional circuit design work is added.
  • the detection accuracy of the conventional clock signal loss detection method is related to the count value M of the reference clock signal. The larger the M value is, the more accurate the detection result is, but the detection speed is also lowered, and the detection of the input clock signal loss cannot be realized quickly and accurately. happening.
  • a fast clock loss detecting device is derived on the basis of the traditional clock loss detecting device.
  • the basic working principle of the device is: judging within one cycle of the clock signal to be detected Whether the number of periods P of the reference clock signal satisfies the set count threshold Q.
  • the period of the clock signal to be detected is greater than 10 times the reference clock period of 0.1 us, that is, the frequency of the clock signal to be detected is less than 1 M, and the clock signal is determined to be lost; On the contrary, if the number of periods P of the reference clock signal is less than or equal to the count threshold Q, it is judged that the clock signal is not lost.
  • the improved clock loss detection apparatus only needs to detect whether the clock signal is lost during one input clock signal period, and greatly improves the detection speed.
  • the improved device cannot detect a fixed level of input signal and also requires a fixed reference clock signal for clock detection, adding additional circuit design work.
  • the embodiment of the present invention is intended to provide a device and method for detecting clock loss, which can improve the detection speed and simplify the hardware circuit design when the clock signal is lost, and can also detect the fixed level and expand the clock. Loss of application range of the detection device.
  • An embodiment of the present invention provides a clock signal loss detection apparatus, including: a first delay unit, a second delay unit, a D flip-flop, a first NOT gate, a second NOT gate, and an AND gate; wherein
  • the input end of the first delay unit, the clock end of the D flip-flop, and the input end of the second non-gate respectively access a clock signal
  • the output end of the first delay unit is connected in series with the first non- a reset end of the D flip-flop is connected to the gate
  • a D terminal of the D flip-flop is connected to a power source
  • an output end of the second NOT gate is connected to a first input end of the AND gate
  • the D of the D flip-flop The end is connected to the second input end of the AND gate, and the output end of the AND gate is connected to the input end of the second delay unit;
  • the D flip-flop is configured to output a low level signal at its Q terminal when a high level signal is connected to its reset terminal;
  • Each delay unit is configured to output a pulse signal after a falling edge delay when its own input signal is a pulse signal and the frequency of its own input signal is less than a frequency threshold; the input signal is a pulse signal, and itself Output when the frequency of the input signal is greater than or equal to the frequency threshold a high level signal; wherein the pulse signal after the falling edge delay of the output of the second delay unit is used to indicate that the clock signal is lost, and the high level signal output by the second delay unit is used to indicate The clock signal is not lost.
  • each delay unit is further configured to output a fixed level signal on the input signal of the self, and the fixed level signal output by the second delay unit is used to indicate The clock signal is lost.
  • the first delay unit and the second delay unit have the same internal structure.
  • each delay unit is further provided with a control end, and each delay unit is configured to determine a frequency threshold based on the control signal when the control terminal accesses the control signal.
  • control signal of each delay unit determines the frequency threshold by controlling an access state of at least one controlled device inside each delay unit, and the access status of each controlled device is used to indicate corresponding receiving Control whether the device is connected.
  • the controlled device is a positive channel metal oxide semiconductor PMOS; when the number of controlled devices inside each delay unit is greater than 2, each controlled device inside each delay unit The width to length ratio is different.
  • control signal accessed by each delay unit is a voltage signal or a current signal.
  • the device further includes: a third non-gate
  • the output end of the second delay unit is connected to the input end of the third NOT gate.
  • the device further includes: a logic control circuit; the logic control circuit is connected to an output end of the second delay unit or an output end of the third NOT gate,
  • the logic control circuit is configured to wait for n preset delay amounts after starting to receive the output signal of the second delay unit or the third NOT gate, and then receive the current received from the The signal output of the second delay unit or the third NOT gate, n is an integer greater than 0, and the preset delay amount is a falling edge delay time of each delay unit.
  • the device further includes: a frequency divider; the clock signal is respectively connected to the input end of the first delay unit, the clock end of the D flip-flop, and the second non-gate through the frequency divider Input.
  • An apparatus for detecting loss of a clock signal includes: a first delay unit, a second delay unit, a D flip-flop, a first NOT gate, a second NOT gate, and an AND gate; wherein The input end of the first delay unit, the clock end of the D flip-flop, and the input end of the second non-gate respectively access a clock signal, and the output end of the first delay unit is connected in series with the first NOT gate Connecting the reset end of the D flip-flop, the D end of the D flip-flop is connected to the power source, the output end of the second NOT gate is connected to the first input end of the AND gate, and the Q end of the D flip-flop is connected a second input end of the AND gate, an output end of the AND gate is connected to an input end of the second delay unit; and a pulse signal after a falling edge delay output by the second delay unit is used to indicate The clock signal is lost, and the high level signal output by the second delay unit is used to indicate that the clock signal is not lost.
  • 1 is a schematic diagram of clock loss detection in the prior art
  • FIG. 2 is a schematic diagram of a first component structure of an apparatus for clock signal loss detection according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a D-flip-flop of a modified TSPC structure according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a programmable falling edge delay unit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a second component of an apparatus for detecting clock loss in an embodiment of the present invention.
  • FIG. 6 is a timing diagram of an input signal at a fixed level 0 in an embodiment of the present invention.
  • FIG. 7 is a timing diagram of an input signal at a fixed level 1 according to an embodiment of the present invention.
  • FIG. 8 is a timing diagram of an input signal frequency below a threshold frequency in an embodiment of the present invention.
  • FIG. 9 is a timing diagram of an input signal frequency higher than a threshold frequency according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram showing a third component structure of an apparatus for detecting clock loss in an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a logic control circuit according to an embodiment of the present invention.
  • FIG. 2 is a first schematic structural diagram of a device for detecting clock loss of the present invention. As shown in FIG. 2, the device includes: a first delay unit 1, a first NOT gate 2, a D flip-flop 3, and a second NOT gate. 4. an AND gate 5 and a second delay unit 6; wherein
  • the input end of the first delay unit 1, the clock end of the D flip-flop 3, and the input end of the second NOT gate 4 respectively access the clock signal CLK_IN, and the output end of the first delay unit 1 is connected in series
  • the first non-gate 2 is connected to the reset end of the D flip-flop 3, the D end of the D flip-flop 3 is connected to a power source, and the output end of the second NOT gate 4 is connected to the first end of the AND gate 5.
  • the input end, the Q end of the D flip-flop 3 is connected to the second input end of the AND gate 5, and the output end of the AND gate 5 is connected to the input end of the second delay unit 6;
  • the D flip-flop 3 is configured to output a low level signal at its Q terminal when a high level signal is connected to its reset terminal;
  • Each delay unit is configured to output a pulse signal after a falling edge delay when its own input signal is a pulse signal and the frequency of its own input signal is less than a frequency threshold; the input signal is a pulse signal, and itself a high level signal is output when the frequency of the input signal is greater than or equal to the frequency threshold; wherein the pulse signal after the falling edge delay output by the second delay unit 6 is used to indicate that the clock signal is lost, the second The high level signal output by the delay unit 6 is used to indicate that the clock signal is not lost.
  • the D flip-flop 3 may be a D flip-flop with reset having an asynchronous reset function.
  • an asynchronous reset function can be implemented by using a D-flip-flop of an improved TSPC structure, which has the characteristics of logic simplicity, low hardware overhead, and the like.
  • the improved TSPC structure D flip-flop includes: four positive channel metal oxide semiconductor (PMOS) cells (MP5, MP6, MP7, MP8) and four negative channel metal oxide semiconductors. (NMOS, Negative channel Metal Oxide Semiconductor)
  • PMOS positive channel metal oxide semiconductor
  • NMOS Negative channel Metal Oxide Semiconductor
  • a three-stage inverter consisting of a MN5, MN6, MN7, and MN8, a power input terminal, a clock input terminal, a reset signal input terminal, and an output terminal.
  • the X node When the rising edge of CLK arrives and the input signal Reset of the reset signal input terminal is a low level signal, the X node is high level, the QN node is also high level, the output Q is high level; when the input signal of the reset signal input end is Reset When it is a high level signal, the signal of the X node is a low level signal, the signal of the QN node is a high level signal, and the Q node outputs a low level signal.
  • the first delay unit 1 and the second delay unit 6 have the same internal structure.
  • Each delay unit is further provided with a control end, each delay unit is configured to determine a frequency threshold based on the control signal when the control terminal accesses the control signal, and the control signal accessed by each delay unit is a voltage signal or Current signal.
  • the control signal of each delay unit determines the frequency threshold by controlling an access state of at least one controlled device inside each delay unit, and the access status of each controlled device is used to indicate whether the corresponding controlled device is connected In.
  • the controlled device may be a positive channel metal oxide semiconductor PMOS; when the number of controlled devices inside each delay unit is greater than 2, the width and length ratio of each controlled device inside each delay unit is different.
  • the first delay unit and the second delay unit may be programmable falling edge delay units
  • FIG. 4 is a schematic structural diagram of a programmable falling edge delay unit according to an embodiment of the present invention, as shown in FIG. 4 .
  • the falling edge delay unit can include:
  • a frequency threshold adjustment module composed of four PMOS transistors MP0-MP3, one NMOS transistor MN0, one capacitor C0, one PMOS (MP4) and one NMOS (MN1) inverter.
  • the aspect ratio (W/L, Width/length) of POMS is much smaller than that of NMOS W/L, therefore, when the PMOS is turned on, the power supply VDD charges the capacitor C0 much faster than the discharge speed of C0 when the NMOS is turned on.
  • the rising edge of the clock signal arrives, at least one PMOS transistor (MP0, MP1, MP2, MP3) in the frequency threshold adjustment module is turned on, and when the rising edge of the clock signal comes, the NMOS transistor (MN0) is turned on, so that the pair can be realized.
  • the falling edge of the input signal is delayed and the rising edge remains essentially unchanged.
  • the access of each PMOS transistor in the frequency threshold adjustment module can be controlled by the voltage control signal VCTRL, thereby setting different delay edge delay amounts, that is, setting different frequency thresholds.
  • VCTRL can control access to MP0, MP1, MP2 or MP3 separately, and can also control MP0, MP1, MP2 and MP3 combined access.
  • the W/L of MP0, MP1, MP2, and MP3 are 1, 2, 3, and 4, respectively. If the voltage control signal VCTRL controls the parallel combination of MP0 and MP1, the PMOS of the PMOS in the access circuit is combined. /L is 3; if the voltage control signal VCTRL controls MP0 to MP4 in parallel combination access, the W/L of the PMOS in the combined access circuit is 10.
  • each delay unit can be used to determine the relationship between the half period of the input clock signal and the delay amount.
  • the output signal is output. It is a fixed high level signal; when the input clock signal half period is greater than the delay amount, the output signal is a wide pulse signal after the falling edge delay.
  • the delay amount set by each delay unit can also be converted into a frequency threshold for comparison.
  • the output signal is a pulse signal after the falling edge delay; when the frequency of the input clock signal is input
  • the frequency threshold is greater than or equal to, the output signal is a fixed high level signal.
  • the low level signal output by the second delay unit 6 is used to indicate that the input clock signal is lost, and the high level signal output by the second delay unit 6 is used to indicate that the input clock signal is not lost.
  • control of the frequency threshold is controlled by the control signal, and the frequency threshold is programmable, so that the clock signal loss detecting apparatus of the embodiment of the present invention can be applied to different applications, and the applicability is strong.
  • each delay unit is further configured to output a fixed level signal to the input signal of the self, and the fixed level signal output by the second delay unit 6 Used to indicate that the clock signal is lost.
  • the clock signal loss detecting apparatus can detect the clock signal regardless of the input signal when the detected clock signal is lost, and can also detect any fixed level, and has high practicability.
  • FIG. 5 is a second schematic structural diagram of a device for detecting clock loss of the present invention.
  • the device for detecting loss of a clock signal may further include: a third NOT gate 7, and an output terminal of the second delay unit 6 is connected. The input of the third NOT gate 7.
  • FIG. 7, FIG. 8 and FIG. 9 are timing diagrams of respective nodes of the apparatus for detecting clock loss in the embodiment of the present invention in FIG. 5.
  • CLK_IN represents an input signal
  • A represents an input signal.
  • B represents the signal after the A node signal passes the first NOT gate 2
  • C represents the Q terminal output signal of the D flip-flop 3
  • D represents the input signal after passing through the second NOT gate 4.
  • E denotes the C node signal and D node signal as the output signal of the AND gate 5 when the two inputs of the AND gate 5
  • F denotes the output signal of the E node signal after passing through the second delay unit 6
  • LOS_OUT denotes the F node signal
  • the clock lost signal after the third NOT gate 7 is output.
  • FIG. 6 is a timing diagram of the input signal at a fixed level 0 according to an embodiment of the present invention.
  • the principle according to the embodiment of the present invention shown in FIG. 6 is as follows:
  • the input signal CLK_IN is a fixed low level signal
  • the low level signal is fixed as the input signal of the first delay unit 1
  • the output signal is consistent with the input signal, and the first delay
  • the output of unit 1 is still a fixed low level signal (A); the A node signal passes through the first NOT gate 2 and is output as a fixed high level signal (B), and the Node B signal acts as a D touch.
  • the reset signal of the transmitter 3 causes the D flip-flop 3 to output a fixed low level signal (C), and the clock signal CLK_IN passes through the second NOT gate 4 to output a fixed high level signal (D); the C node signal and the D node signal are used as When the two input signals of the gate 5 are, the AND gate 5 outputs a fixed low level signal (E); when the low level signal is fixed as the input signal of the second delay unit 6, the output is a fixed low level signal (F), Finally, the F-node signal passes through the NOT gate 7 and outputs a fixed high-level signal; the output signal of the NOT gate 7 is used as a clock loss signal, and when the clock loss signal is a high-level signal, it indicates that the input clock signal is lost.
  • FIG. 7 is a timing diagram of the input signal at a fixed level 1 according to an embodiment of the present invention.
  • the principle according to the embodiment of the present invention shown in FIG. 7 is as follows:
  • the input signal CLK_IN is a fixed high level signal
  • the high level signal is fixed as the input signal of the first delay unit 1
  • the output signal is consistent with the input signal, and the first delay
  • the output of unit 1 is still a fixed high level signal (A);
  • the A node signal is output as a fixed low level signal (B) after passing through the first NOT gate 2, and the B node signal is used as the reset signal of the D flip-flop 3
  • the output Q of the D flip-flop 3 is consistent with the fixed high level of the D terminal input, that is, the output is a fixed high level signal (C), and the clock signal CLK_IN passes through the second NOT gate 4 and outputs a fixed low level signal (D).
  • the AND gate 5 When the C node signal and the D node signal are used as the two input signals of the AND gate 5, the AND gate 5 outputs a fixed low level signal (E); when the low level signal is fixed as the input signal of the second delay unit 6, The output of the second delay unit is still a fixed low level signal (F). Finally, the F node signal passes through the non-gate 7 and outputs a high level signal; the output signal of the NOT gate 7 is used as a clock loss signal, and when the clock loss signal is high. When the signal is flat, it indicates that the input clock signal is lost.
  • FIG. 8 is a timing diagram of an input signal frequency lower than a threshold frequency according to an embodiment of the present invention.
  • the principle according to the embodiment of the present invention shown in FIG. 8 is as follows:
  • the output of the first delay unit 1 is The wide pulse signal (A) after the falling edge of the clock signal is delayed.
  • the A node signal passes through the first NOT gate 2 and outputs a narrow pulse signal (B), and the Node B signal acts as D
  • the output of the D flip-flop 3 is a fixed low-level signal (C); it can be understood that the output of the first delay unit 1 is output due to the delay of the first delay unit 1.
  • the rising edge and the falling edge of the wide pulse signal have a delay phenomenon compared with the input signal of the own, so when the B node signal is used as the reset signal of the D flip-flop 3, when the rising edge of the clock signal input to the clock terminal of the D flip-flop 3 comes At the time, the reset terminal signal of the D flip-flop 3 is still 1, so that the D flip-flop outputs a low level signal.
  • the clock signal CLK_IN passes through the non-gate 4 and outputs the same frequency as the clock signal CLK_IN, the logic wave 0 and the logic 1 are completely opposite to the square wave signal (D), the C node signal and the D node signal serve as the two input signals of the AND gate 5, the AND gate 5 output fixed low level signal (E), after the second delay unit 6, the output is a fixed low level signal (F), and finally the F node signal passes through the non-gate 7 and outputs a high level signal; when the clock loss signal is A high level signal indicates that the input clock signal is lost.
  • FIG. 9 is a timing diagram of an input signal frequency higher than a threshold frequency according to an embodiment of the present invention.
  • the principle according to the embodiment of the present invention shown in FIG. 9 is as follows:
  • the first delay unit When the input signal is a clock signal, and the frequency of the clock signal is greater than or equal to the threshold frequency, that is, the half period of the clock signal is less than or equal to the delay amount of the falling edge delay unit, when the falling edge of the input clock signal arrives, the first delay unit
  • the output of 1 is a fixed high level signal (A); the A node signal outputs a fixed low level signal (B) after passing through the first NOT gate 2, and the D node 3 is used as a reset signal of the D flip-flop 3
  • the fixed high level signal (C) is output.
  • the clock signal CLK_IN passes through the non-gate 4 and outputs the same frequency as the clock signal CLK_IN.
  • the logic 0 and the logic 1 are completely opposite to the square wave signal (D), and the C node signal and the D node signal are used as The two input signals of the gate 5, the gate 5 outputs a square wave signal (E) identical to the D node signal, and the square wave signal outputs a fixed high level signal (F) after the second delay unit, and finally F
  • the node signal passes through the third NOT gate 7 and outputs a fixed low level signal; when the clock loss signal is a low level signal, it indicates that the input clock signal is not lost.
  • the apparatus for detecting clock loss may further include: a logic control circuit 8; and the logic control circuit 8 is connected to the second delay unit 6. The output or the output 7 of the third NOT gate.
  • a logic control circuit configured to wait for n preset delay amounts after starting to receive the output signal of the second delay unit 6 or the third NOT gate 7, and then to receive the current received second
  • the signal output of the delay unit or the third NOT gate n is an integer greater than 0, and the preset delay amount is a falling edge delay time of each delay unit.
  • the detection result is output after starting to detect the loss of the clock signal by three delay amounts. Since the detection of the clock signal is lost, at most two delay amounts are needed, in order to prevent the clock signal from being collected before and after the clock signal. Error, so choose to output the detection result after 3 delay clocks, thus ensuring the accuracy of the test results.
  • the detection result is output after 3 delays, that is, 1.2us, when the detection of the clock signal is lost.
  • the logic control circuit may be composed of an AND gate 81, and the output end of the third NOT gate 7 is connected to the first input of the AND gate 81.
  • the voltage control signal VCTRL1 is connected to the second input terminal of the AND gate 81, and the AND gate 81 outputs the final detection result, that is, the clock signal loss detection result is output after starting the detection of the clock signal loss for n delay amounts.
  • the second input of the AND gate 81 may also be a current control signal.
  • the clock signal loss detecting apparatus of the embodiment of the present invention when the detected clock signal is lost, the clock signal loss state can be detected by requiring at most two delay amounts, and the detection speed is fast.
  • the device for detecting the loss of the clock signal may further include: a frequency divider 9; the clock signal is respectively connected to the input end of the first delay unit 1, the clock end of the D flip-flop 3, and the input of the second NOT gate 4 through the frequency divider end.
  • the frequency divider 9 is a two-divider.
  • the input clock signal is implemented based on a duty ratio of 50%, if the input is The duty ratio of the incoming clock signal is not 50%.
  • the delay of the falling edge will be deviated, and the inaccurate detection of the lost clock signal occurs.
  • the input clock signal has a frequency of 1 MHz and a duty ratio of 70%.
  • the clock signal has a period of 1 us and a pulse width of 0.7 us.
  • the delay value of the falling edge of each delay unit is 0.4us, that is, the frequency threshold is 1.25MHz; at this time, the half period of the clock signal is greater than the falling edge delay amount, that is, the frequency of the clock signal is less than the frequency threshold, due to the input clock
  • the duty ratio of the signal is not 50%, so the first delay unit 1 delays the falling edge of the input clock signal by 0.4us and outputs a fixed high level signal, and cannot output a wide pulse signal, resulting in the output of the second delay unit 6. A high level signal indicating that the clock signal has not been lost.
  • the clock signal is respectively connected to the input end of the first delay unit 1, the clock end of the D flip-flop 3, and the input end of the second NOT gate 4 through the frequency divider. .
  • the divided signal duty cycle is 50%, which is consistent with the duty cycle requirements of the input clock signal in accordance with an embodiment of the present invention.
  • the circuit structure when the clock signal loss detection is performed, the circuit structure is simple, the hardware overhead is small, and only a simple delay device and a logic gate can be realized, and a complicated reference clock circuit is not required; the detection speed is fast, In any environment, only two delay amounts are needed to detect whether the input clock signal is lost.
  • the application range of the clock loss detecting device is expanded.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the present invention is directed to a method, apparatus (system), and computer program in accordance with an embodiment of the present invention
  • the flow chart and/or block diagram of the product is described. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG.
  • These computer program instructions can be provided to a processor of a general purpose computer, a special purpose computer, an embedded processor, or other programmable clock loss detection device to produce a machine that is executed by a processor of a computer or other programmable clock signal loss detection device
  • the instructions produce means for implementing the functions specified in one or more flows of the flowchart or in a block or blocks of the flowchart.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable clock loss detection device to operate in a particular manner, such that instructions stored in the computer readable memory produce an article of manufacture including the instruction device.
  • the instruction means implements the functions specified in one or more blocks of the flow or in a flow or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable clock loss detection device to perform a series of operational steps on a computer or other programmable device to produce computer-implemented processing on a computer or other programmable device.
  • the instructions that are executed provide steps for implementing the functions specified in one or more blocks of the flowchart or in a block or blocks of the flowchart.
  • the clock signal is respectively input through the input end of the first delay unit, the clock end of the D flip-flop, and the input end of the second non-gate, and the output end of the first delay unit is connected in series
  • the first non-gate is connected to the reset end of the D flip-flop
  • the D end of the D flip-flop is connected to a power source
  • the output end of the second NOT gate is connected to the first input end of the AND gate
  • the Q end of the D flip-flop is connected to the second input end of the AND gate
  • the output end of the AND gate is connected to the input end of the second delay unit; after the falling edge of the output of the second delay unit is delayed
  • Pulse signal is used to indicate the location

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Abstract

L'invention concerne un dispositif de détection de perte de signal d'horloge, comprenant : une première unité de retard, une seconde unité de retard, une bascule D, une première grille NON, une seconde grille NON, et une grille ET. Une extrémité d'entrée de la première unité de retard, une extrémité d'horloge de la bascule D, et une extrémité d'entrée de la seconde grille NON accèdent séparément à un signal d'horloge; une extrémité de sortie de la première unité de retard est connectée à la première grille NON en série et est ensuite connectée à une extrémité de réinitialisation de la bascule D; une extrémité D de la bascule D est connectée à une alimentation électrique; une extrémité de sortie de la seconde grille NON est connectée à une première extrémité d'entrée de la grille ET; une extrémité Q de la bascule D est connectée à une seconde extrémité d'entrée de la grille ET; une extrémité de sortie de la grille ET est connectée à une extrémité d'entrée de la seconde unité de retard; un signal d'impulsion avec un front descendant retardé émis par la seconde unité de retard est utilisé pour indiquer que le signal d'horloge est perdu; un signal de haut niveau émis par la seconde unité de retard est utilisé pour indiquer que le signal d'horloge n'est pas perdu.
PCT/CN2017/077152 2016-09-28 2017-03-17 Dispositif de détection de perte de signal d'horloge WO2018058915A1 (fr)

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Application Number Priority Date Filing Date Title
CN201610864963.5 2016-09-28
CN201610864963.5A CN107872208B (zh) 2016-09-28 2016-09-28 一种时钟信号丢失检测的装置

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