WO2018054149A1 - 有机发光二极管(oled)阵列基板及其制备方法、显示装置 - Google Patents

有机发光二极管(oled)阵列基板及其制备方法、显示装置 Download PDF

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WO2018054149A1
WO2018054149A1 PCT/CN2017/093162 CN2017093162W WO2018054149A1 WO 2018054149 A1 WO2018054149 A1 WO 2018054149A1 CN 2017093162 W CN2017093162 W CN 2017093162W WO 2018054149 A1 WO2018054149 A1 WO 2018054149A1
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Prior art keywords
trace
power supply
oled
pixel
array substrate
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PCT/CN2017/093162
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English (en)
French (fr)
Inventor
李全虎
王玲
李永谦
孟松
吴月
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京东方科技集团股份有限公司
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Priority to EP17825720.0A priority Critical patent/EP3518281B1/en
Priority to US15/744,993 priority patent/US10332919B2/en
Publication of WO2018054149A1 publication Critical patent/WO2018054149A1/zh

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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
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    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements

Definitions

  • Embodiments of the present disclosure relate to an organic light emitting diode (OLED) array substrate, a method of fabricating the same, and a display device.
  • OLED organic light emitting diode
  • OLED Organic Light-Emitting Diode
  • PDAs personal digital assistants
  • a mainstream display mode of an OLED is an oxide thin film transistor (Oxide Thin Film Transistor), a white light OLED display (WOLED), and a color filter film formed on a color filter on array (COA).
  • the driving pixel of the above display mode adopts the external compensation technology of 3T1C, wherein “3T1C” refers to three pixel circuits.
  • the pixel opening area of the organic electroluminescent device is small, resulting in a decrease in the pixel aperture ratio. Therefore, the OLED illumination intensity must be increased to compensate for the adverse effect of the pixel aperture ratio on the OLED, thereby affecting the OLED device. The service life.
  • At least one embodiment of the present disclosure provides an organic light emitting diode (OLED) array substrate
  • the OLED array substrate includes: a substrate substrate; a power supply trace and a pixel structure disposed on the base substrate; wherein the power source is a line is disposed under the pixel structure and at least partially overlaps with the pixel structure; an insulating layer is disposed between the power supply line and the pixel structure, and a first via structure is disposed in the insulating layer; The power trace is connected to the drive transistor in the pixel structure through the first via structure.
  • the driving crystal The body tube is a top gate type thin film transistor, and the power supply trace overlaps with an active layer of the top gate type thin film transistor to shield the active layer from light.
  • the power supply trace is a planar structure formed by a metal mesh.
  • each column of the pixel structure corresponds to the power trace provided with a planar structure.
  • a gate line and a data line disposed on the base substrate are further included, wherein the pixel structure is disposed on the gate line and the data line In the cross-defined area, a hollow structure is disposed in a region corresponding to the pixel structure, the gate line, and the data line.
  • the hollow structure includes a plurality of discontinuous sub-hollow structures.
  • the driving transistor is a bottom gate type thin film transistor
  • the power supply trace is disposed on a gate metal layer of the bottom gate thin film transistor and the lining Between the base plates.
  • At least one embodiment of the present disclosure further provides a display device including any of the above organic light emitting diode (OLED) array substrates.
  • OLED organic light emitting diode
  • At least one embodiment of the present disclosure further provides a method for fabricating an organic light emitting diode (OLED) array substrate, comprising: providing a substrate; forming a power trace and a pixel structure on the substrate; Forming an insulating layer between the pixel structure, forming a first via structure in the insulating layer; wherein the power trace is disposed under the pixel structure and at least partially overlapping the pixel structure; The power trace is connected to the drive transistor in the pixel structure through the first via structure.
  • OLED organic light emitting diode
  • the driving transistor is a top gate thin film transistor
  • the power supply trace overlaps with an active layer of the top gate thin film transistor to be active.
  • the layer is shaded.
  • the power supply trace is a planar structure formed of a metal mesh.
  • each column of the pixel structure corresponds to the power trace provided with a planar structure.
  • the preparation method provided by at least one embodiment of the present disclosure further includes the substrate And forming a gate line and a data line, wherein the pixel structure is formed in a region defined by the intersection of the gate line and the data line, the power supply trace and the pixel structure, the gate line, and the The area corresponding to the data line is provided with a hollow structure.
  • the hollow structure includes a plurality of discontinuous sub-hollow structures.
  • the driving transistor is a bottom gate type thin film transistor
  • the power supply trace is disposed on a gate metal layer of the bottom gate type thin film transistor and the substrate Between the substrates.
  • OLED organic light emitting diode
  • FIG. 2 is a schematic diagram of a planar structure of a power supply line disposed in a hollow structure according to an embodiment of the present disclosure
  • OLED organic light emitting diode
  • OLED organic light emitting diode
  • 5a is a schematic diagram of a 2T1C pixel circuit according to an embodiment of the present disclosure.
  • FIG. 5b is a schematic diagram of still another 2T1C pixel circuit according to an embodiment of the present disclosure.
  • FIG. 5c is a schematic diagram of still another 2T1C pixel circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a method for fabricating an organic light emitting diode (OLED) array substrate according to an embodiment of the present disclosure
  • FIG. 7 is a flowchart of a method for fabricating another organic light emitting diode (OLED) array substrate according to an embodiment of the present disclosure.
  • the dimensions of the respective patterns in the OLED array substrate according to the embodiments of the present disclosure are generally on the order of micrometers or less in actual products, and the dimensions of the structures in the drawings of the embodiments of the present disclosure are exaggerated for clarity, unless otherwise It is not explicitly stated that the dimensions of the structures in the drawings of the embodiments of the present disclosure do not represent actual dimensions and ratios.
  • the power supply trace occupies a part of the pixel's open area and the capacitor area.
  • the OVDD trace itself has a resistance.
  • the voltage drop on the OVDD trace affects the luminescence current, which causes a certain difference in the amplitude of the OVDD signal.
  • the characteristics of the thin film transistor (TFT) are not ideal (the saturation current is not only related to V gs but also related to V ds )
  • the voltage drop on the OVDD trace affects V ds , so the current output from the OLED sub-pixels at different positions It will change due to the change in OVDD voltage. Therefore, it is necessary to reduce the resistance of the OVDD trace as much as possible, thereby reducing the voltage drop on the OVDD trace.
  • At least one embodiment of the present disclosure provides an organic light emitting diode (OLED) array substrate including a substrate substrate, a power supply trace and a pixel structure disposed on the base substrate, wherein the power source The trace is disposed under the pixel structure and at least partially overlaps the pixel structure, and an insulating layer is disposed between the power trace and the pixel structure, and the first via structure is disposed in the insulating layer, and the power trace passes through the first via structure and The drive transistors in the pixel structure are connected.
  • OLED organic light emitting diode
  • the power trace is disposed under the pixel structure and at least partially overlaps the pixel structure, and the power trace is disposed in an insulating layer disposed between the power trace and the pixel structure
  • the first via structure is connected to the driving transistor, thereby avoiding the OVDD trace occupying the opening area and the capacitance area of the pixel, thereby increasing the aperture ratio of the pixel area and reducing the impedance of the display area pixel to OVDD.
  • FIG. 1 is a schematic plan view of an organic light emitting diode (OLED) array substrate according to an embodiment of the present disclosure.
  • the organic light emitting diode (OLED) array substrate includes a base substrate 101 , a power supply line 102 disposed on the base substrate 101 , and a pixel structure 105 , and the power supply trace 102 is disposed under the pixel structure 105 .
  • an insulating layer (not shown in FIG. 1) is disposed between the power trace 102 and the pixel structure 105, and the first via structure 110 is disposed in the insulating layer, and the power trace 102 passes through
  • the first via structure 110 is connected to the driving transistor 107 in the pixel structure 105.
  • a gate line 103 and a data line 104 are further disposed on the base substrate 101.
  • the pixel structure 105 is disposed in a region defined by the intersection of the gate line 103 and the data line 104.
  • the pixel structure 105 includes a switching transistor 106.
  • the transistor 107 and the OLED device 108 are driven, and the switching transistor 106 is connected to the gate line 103 and the data line 104.
  • the driving transistor 107 is connected to the switching transistor 106, the power supply line 102, and the OLED device 108, and the positions of the switching transistor 106 and the driving transistor 107. See the corresponding dashed box.
  • FIG. 1 Although only four pixel structures juxtaposed to each other are shown in FIG. 1, and are used to emit white light (W), red light (R), green light (G), and blue light (B), respectively, those of ordinary skill in the art should It is understood that the pixel structure included in the array substrate in the embodiment of the present disclosure is not limited to four shown in FIG. 1, and may include more.
  • Each of the pixel structures further includes a storage capacitor including a first electrode 113 and a second electrode 123 disposed opposite to each other.
  • the first electrode 113 and the second electrode 123 are both in a block shape and both A dielectric layer formed of an insulating material is disposed therebetween.
  • the first electrode 113 is connected to the drain of the driving transistor 107
  • the second electrode 123 is connected to the drain of the switching transistor 106.
  • the OLED array substrate includes a display area and a peripheral area other than the display area, wherein the display area is also referred to as an AA (Active Area) area, and is generally used to implement display, and the peripheral area can be used to set a driving circuit for packaging of the display panel, etc. .
  • AA Active Area
  • the above pixel structure, gate line and data line Both are located in the display area.
  • the OLED array substrate may further include a detection compensation line connecting the pixel unit and the detection integrated circuit, and the detection compensation line may also be located in the display area.
  • the power supply trace is set to a wider area, and the area where the driving transistor is located and the area where the storage capacitor is located are perpendicular to the OLED array substrate.
  • the power trace of the planar structure can reduce the voltage drop of the power trace (IR drop), thereby reducing the energy consumption of the OLED array substrate. It should be noted that the power supply trace of the planar structure means that the power trace has a certain size and extension range in the width and length directions of the pixel structure.
  • a planar power trace can be provided for each column of pixel structures, so that multiple planar power traces can be continuously connected to form an integrated structure, which can make the area of the power trace more Larger, which further reduces the voltage drop of the power supply trace (IR drop), thereby further reducing the energy consumption of the OLED array substrate.
  • IR drop voltage drop of the power supply trace
  • a region of the power trace of the planar structure corresponding to the pixel structure, the gate line, and the data line may be provided with a hollow structure.
  • the size of the hollow structure corresponds to the size of the pixel structure, the gate line and the data line, and the size of the hollow structure is larger than the size of the mesh in the metal mesh.
  • FIG. 2 is a schematic diagram of a planar structure of a power supply line disposed in a hollow structure according to an embodiment of the present disclosure. As shown in FIG.
  • the area corresponding to the power supply line 102 and the pixel structure is configured as a hollow structure 20 mainly for Prevent the metal trace from blocking, affecting the transmittance of light, that is, providing a hollow structure in the corresponding area of the pixel structure can increase the transmittance of the light, and fully utilize the incident light; the power trace 102 and the gate line and the data line
  • the corresponding area is set to a hollow structure, mainly to prevent capacitance between the power supply trace and the gate line and the data line. For example, as shown in FIG.
  • the hollow structure 20 may include a plurality of non-contiguous sub-hollow structures 201 (ie, a plurality of sub-hollow structures are spaced apart from each other), which is equivalent to dividing the power supply lines of the planar structure into a plurality of Parallel areas, which can reduce the resistance of the planar power supply traces, thus greatly reducing the voltage drop of the power supply traces.
  • the driving transistor may be a bottom gate thin film transistor or a top gate thin film transistor.
  • the driving transistor is a top gate type thin film transistor, such as a power supply trace and a top gate type thin film transistor
  • the active layer overlaps to shield the active layer;
  • the driving transistor is a bottom gate type thin film transistor, for example, the power supply trace is disposed between the gate metal layer of the bottom gate type thin film transistor and the substrate, and The source layers overlap.
  • a driving transistor as a top gate type thin film transistor and a bottom gate type thin film transistor as an example.
  • the driving transistor is a top gate type thin film transistor
  • the power supply wiring overlaps with the active layer of the top gate type thin film transistor to shield the active layer from light.
  • FIG. 3 is a partial cross-sectional structural diagram of an organic light emitting diode (OLED) array substrate according to an embodiment of the present disclosure.
  • the driving transistor is a top gate type thin film transistor.
  • the driving transistor is a top gate type thin film transistor.
  • a power supply trace 102 and a switching transistor are disposed on the base substrate 101 (not shown in FIG. 3). ), drive transistors and OLED devices.
  • the distance between the power supply line 102 and the gate line 103 and the data line 104 is relatively long, which can reduce the mutual interference between the gate line 103 and the power supply line 102, the data line 104 and the power supply line 102, and reduce the occurrence of electrostatic discharge ( The risk of electro-static discharge (ESD).
  • ESD electro-static discharge
  • a first insulating layer 109 is further disposed on the base substrate 101, and an active layer 116 of a driving transistor is disposed on the first insulating layer 109, and a gate is sequentially formed on the active layer 116.
  • the insulating layer 111, the gate metal layer 115, and the second insulating layer 112 form a source electrode 1071 and a drain electrode 1072 on the second insulating layer 112.
  • a first via structure 110 is formed in the first insulating layer 109 and the second insulating layer 112, and the power trace 102 is electrically connected to the source 1071 of the driving transistor through the first via structure 110.
  • a passivation layer 117 is formed over the source 1071 and the drain 1072, and a second via structure 118 is formed on the passivation layer 117.
  • the dielectric layer between the first electrode 113 and the second electrode 123 in the storage capacitor shown in FIG. 1 may be the second insulating layer 112.
  • the driving transistor 107 is provided with an OLED device 108.
  • the anode 1081 of the OLED device is electrically connected to the drain 1072 through the second via structure 118, so that the power supply line 102 supplies current to the driving transistor 107.
  • an illuminating current is provided for the OLED device.
  • a pixel defining layer 1082 is formed on the anode 1081 of the OLED device, a light emitting layer 1083 is formed on the pixel defining layer 1082, a cathode 1084 is formed on the light emitting layer 1083, and a cathode 1084 of the OLED device is grounded.
  • an etch stop layer may be formed on the active layer.
  • the disclosed embodiments do not limit this.
  • the power supply trace 102 overlaps with the active layer 116, so that the power supply trace 102 can be used as a light shielding layer at the same time, thereby saving one patterning process and saving production cost.
  • each pixel defining area of the pixel defining layer corresponds to one pixel electrode
  • each column sub-pixel defining area in the pixel defining structure is a sub-pixel defining area of the same color.
  • the sub-pixel defining area includes The white sub-pixel defining area W, the red sub-pixel defining area R, the green sub-pixel defining area G, and the blue sub-pixel defining area B.
  • a sub-pixel defining region 101 is connected to adjacent sub-pixel defining regions 101 of the same color, and each sub-pixel defining region 101 is connected at most to adjacent two sub-pixel defining regions 101 of the same color.
  • the driving transistor and the switching transistor can be the same as the top gate type thin film transistor.
  • the source of the switching transistor is connected to the data line
  • the drain of the switching transistor is electrically connected to the gate of the driving transistor
  • the gate of the switching transistor is electrically connected to the gate line.
  • the driving transistor is a bottom gate type thin film transistor
  • the power supply trace is disposed between the gate metal layer and the base substrate, and the power supply trace overlaps with the active layer of the bottom gate type thin film transistor.
  • FIG. 4 is a partial cross-sectional structural diagram of an organic light emitting diode (OLED) array substrate according to an embodiment of the present disclosure.
  • a power supply trace 102 is disposed on the base substrate 101.
  • the first insulating layer 109 is disposed between the power trace 102 and the pixel structure 105, and the power trace 102 at least partially overlaps the pixel structure 105.
  • a first via structure 110 is formed in the gate insulating layer 111 and the first insulating layer 109, and the power supply trace 102 is connected to the source 1071 of the driving transistor 107 through the first via structure 110.
  • the dielectric layer between the first electrode 113 and the second electrode 123 of the storage capacitor may be the gate insulating layer 111.
  • the driving transistor 107 is provided with an OLED device 108 including an anode, a light emitting layer, and a cathode.
  • the anode 1081 of the OLED device is electrically coupled to the drain 1072 of the drive transistor 107 through a second via structure 118 that extends through the second insulating layer 112.
  • a pixel defining layer 1082 is formed on the anode 1081 of the OLED device, a light emitting layer 1083 is formed in the opening portion of the pixel defining layer 1082, and a cathode 1084 is formed on the light emitting layer 1083, and the cathode 1084 of the OLED device is grounded.
  • each pixel defining area of the pixel defining layer corresponds to one pixel electrode
  • each column sub-pixel defining area in the pixel defining structure is a sub-pixel defining area of the same color
  • the sub-pixel defining area includes white as shown in FIG.
  • a sub-pixel defining region 101 is connected to adjacent sub-pixel defining regions 101 of the same color, and each sub-pixel defining region 101 is connected at most to adjacent two sub-pixel defining regions 101 of the same color.
  • the driving transistor and the switching transistor can be the same as the bottom gate type thin film transistor.
  • the source of the switching transistor is connected to the data line
  • the drain of the switching transistor is electrically connected to the gate of the driving transistor
  • the gate of the switching transistor is electrically connected to the gate line.
  • the power supply line 102 is a planar structure formed of a metal mesh.
  • the planar structure formed by the mutually intersecting metal wires (strips) can further reduce the electrical resistance.
  • the base substrate 101 may be a transparent glass substrate or a transparent plastic substrate.
  • the material of the power supply trace 102, the gate metal layer 115, the gate line 103, the source 1071, the drain 1072, and the data line 104 may be a copper-based metal, for example, copper (Cu), copper-molybdenum alloy (Cu/Mo ), Cu-Ti alloy, Cu/Mo/Ti, Cu/Mo/W, Cu/Mo/Nb, etc.
  • chromium-based metal for example, a chromium-molybdenum alloy (Cr/Mo), a chromium-titanium alloy (Cr/Ti), a chromium-molybdenum-titanium alloy (Cr/Mo/Ti), or the like, or other suitable materials.
  • Cr/Mo chromium-molybdenum alloy
  • Cr/Ti chromium-titanium alloy
  • Cr/Mo/Ti chromium-molybdenum-titanium alloy
  • the active layer is formed of a semiconductor material such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, an oxide semiconductor, or the like, and the oxide semiconductor material may be, for example, IGZO (indium gallium zinc oxide) or ZnO (zinc oxide). )Wait.
  • IGZO indium gallium zinc oxide
  • ZnO zinc oxide
  • a region of the active layer 116 that is in contact with the source electrode 1071 and the drain electrode 1072 can be conductorized by a process of plasma treatment and high temperature processing, so that transmission of an electrical signal can be better achieved.
  • the first insulating layer 109, the second insulating layer 112, and the pixel defining layer 1082 are generally formed using an organic insulating material (for example, an acrylic resin) or an inorganic insulating material (for example, silicon nitride SiN x or silicon oxide SiO x ).
  • the first insulating layer 109 and the second insulating layer 112 may be a single layer structure composed of silicon nitride or silicon oxide, or a two-layer structure composed of silicon nitride and silicon oxide.
  • the first insulating layer 109 generally has more than two layers, which can reduce the parasitic capacitance between the power trace 102 and other layer metal traces.
  • materials used as the gate insulating layer 111 include silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), or other suitable materials.
  • a material used as the passivation layer 117 includes silicon nitride SiN x , silicon oxide SiO x , silicon oxynitride SiN x O y or an acrylic resin.
  • the cathode can be a low work function metal, and the anode is a high work function transparent material.
  • the material forming the anode 1081 of the OLED device includes indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO) zinc oxide (ZnO), indium oxide (In 2 O 3 ), aluminum oxide zinc (AZO) and carbon nanotubes.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IGO indium gallium oxide
  • GZO gallium zinc oxide
  • ZnO zinc oxide
  • In 2 O 3 aluminum oxide zinc
  • AZO aluminum oxide zinc
  • the material forming the cathode 1084 of the OLED device includes magnesium aluminum alloy (MgAl), lithium aluminum alloy (LiAl), or magnesium, aluminum, lithium single metal.
  • a reflective layer can also be formed separately in the OLED device.
  • the material forming the luminescent layer 1083 of the OLED device can be selected according to the color of its emitted light.
  • the material of the light-emitting layer 1083 includes a fluorescent light-emitting material or a phosphorescent light-emitting material.
  • a doping system is generally employed, that is, a doping material is mixed in a host luminescent material to obtain a usable luminescent material.
  • the host light-emitting material may be a metal compound material, a ruthenium derivative, an aromatic diamine compound, a triphenylamine compound, an aromatic triamine compound, a biphenyldiamine derivative, or a triarylamine polymer.
  • each column of pixel structures 105 corresponds to a planar power trace.
  • the power traces disposed in each column of pixel structures are spaced apart from each other, and the impedance of the display area pixels to the power traces can be further reduced.
  • a color film layer may be further disposed in the sub-pixel defining region.
  • the white light OLED device and the corresponding red color film layer may be combined. Blue color film layer and green color film layer are obtained.
  • the color film layer may be a filter or a light conversion layer (for example, a fluorescent layer).
  • a flat layer may be provided on the color film layer.
  • Figures 5a-5c are schematic illustrations of a 2T1C pixel circuit provided by an embodiment of the present disclosure.
  • the pixel structure 105 in addition to the switching transistor T1 and the driving transistor T2, the pixel structure 105 further includes a storage capacitor Cs, one end of which is connected to the drain of the switching transistor T1 and the driving transistor T2. The gate is connected to the driving transistor T2 at the other end The drain and the positive terminal of the OLED.
  • another 2T1C pixel circuit includes a switching transistor T1, a driving transistor T2, and a storage capacitor Cs.
  • the gate of the switching transistor T1 is connected to a gate line (scanning line) to receive a scan signal (Scan1), for example, the source is connected to the data line to receive the data signal (Vdata), and the drain is connected to the gate of the driving transistor T2;
  • the source of the driving transistor T2 is connected to the first power terminal (Vdd, high voltage terminal), and the drain is connected to the positive terminal of the OLED;
  • one end of the storage capacitor Cs is connected to the drain of the switching transistor T1 and the gate of the driving transistor T2, and One end is connected to the source of the driving transistor T2 and the first power terminal; the cathode of the OLED is connected to the second power terminal (Vss, low voltage terminal), for example, grounded.
  • the 2T1C pixel circuit is driven by controlling the brightness and darkness (gray scale) of the pixel via the two TFTs and the storage capacitor Cs.
  • the scan signal Scan1 is applied through the gate line to turn on the switching transistor T1
  • the data voltage (Vdata) fed by the data driving circuit through the data line charges the storage capacitor Cs via the switching transistor T1, thereby storing the data voltage in the storage capacitor Cs.
  • the stored data voltage controls the degree of conduction of the driving transistor T2, thereby controlling the magnitude of the current flowing through the driving transistor to drive the OLED to emit light, that is, the current determines the gray level of the pixel illumination.
  • the switching transistor T1 is an N-type transistor and the driving transistor is a P-type transistor.
  • another 2T1C pixel circuit also includes a switching transistor T1, a driving transistor T2, and a storage capacitor Cs, but the connection mode thereof is slightly changed, and the driving transistor T2 is an N-type transistor.
  • the variation of the pixel circuit of FIG. 5c with respect to FIG. 5b includes that the positive terminal of the OLED is connected to the first power terminal (Vdd, high voltage terminal) and the negative terminal is connected to the drain of the driving transistor T2, the driving transistor The source of T2 is connected to the second power supply terminal (Vss, low voltage terminal), such as ground.
  • the operation mode of the 2T1C pixel circuit is basically the same as that of the pixel circuit shown in FIG. 1A, and details are not described herein again.
  • the switching transistor T1 is not limited to the N-type transistor, and may be a P-type transistor, thereby controlling the polarity of the scan signal (Scan1) which is turned on or off accordingly. Change it.
  • the pixel circuit may also be 3T1C, 4T2C, etc., and may include a compensation transistor, a reset transistor, and the like in addition to the above-described switching transistor and the driving transistor, which are not limited herein.
  • An embodiment of the present disclosure further provides a display device including any of the above-described organic light emitting diode (OLED) array substrates, and further includes a gate driving circuit, a data driving circuit, a power source, and the like, and the gate lines are connected to the gate driving circuit.
  • the data line is connected to the data driving circuit, and the power wiring is connected to the power source.
  • the display device can be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the organic light emitting diode (OLED) array substrate included in the display device of the embodiment of the present disclosure has the same structure as the organic light emitting diode (OLED) array substrate shown in FIG. 3 or FIG. 4, and the technical effect is the same as the implementation principle. I will not repeat them here.
  • the display device may adopt a bottom emission or a top emission mode, and may also adopt a two-sided emission mode.
  • a bottom emission mode may be employed.
  • FIG. 6 is a flowchart of a method for preparing an OLED array substrate according to an embodiment of the present disclosure. As shown in FIG. 6 , the preparation method includes the following steps:
  • Step 101 Providing a substrate.
  • Step 102 Form a power supply trace, a gate line, and a data line on the base substrate.
  • Step 103 Form a pixel structure in a region defined by intersection of the gate line and the data line, the pixel structure including a switching transistor, a driving transistor, and an OLED device.
  • Step 104 Form an insulating layer between the power supply trace and the pixel structure, and form a first via structure in the insulating layer.
  • the insulating layer when the driving transistor is a top gate type thin film transistor, the insulating layer includes a first insulating layer 109 and a second insulating layer 112; as shown in FIG. 4, when the driving transistor is a bottom gate type thin film transistor
  • the insulating layer includes a gate insulating layer 111 and a first insulating layer 109.
  • the switching transistor is connected to the gate line and the data line
  • the driving transistor is connected to the switching transistor, the power supply line, and the OLED device
  • the power supply line is disposed under the pixel structure and at least partially overlaps with the pixel structure
  • the power supply line passes through the first
  • the hole structure is connected to the driving transistor.
  • the power supply trace is disposed under the pixel structure and at least partially overlaps with the pixel structure; the power supply trace is connected to the driving transistor through the first via structure, thereby avoiding The power trace occupies the open area and the capacitive area of the pixel, increases the aperture ratio, and reduces the impedance of the display area pixel to OVDD.
  • FIG. 7 is a flowchart of a method for fabricating the OLED array substrate shown in FIG. Includes the following steps:
  • Step 201 Providing a base substrate.
  • the base substrate may be a glass substrate, a quartz substrate, or the like.
  • Step 202 Form a power supply trace, a gate line, and a data line on the base substrate.
  • Step 203 forming a pixel structure in a region defined by intersection of the gate line and the data line, and forming a switching transistor, a driving transistor, and an OLED device in the pixel structure.
  • Step 204 Form an insulating layer between the power supply trace and the pixel structure, and form a first via structure in the insulating layer.
  • a switching transistor is coupled to the gate line and the data line
  • a drive transistor is coupled to the switching transistor, the power supply trace, and the OLED device
  • the power supply trace is disposed below the pixel structure and at least partially overlaps the pixel structure.
  • the insulating layer includes a first insulating layer 109 and a second insulating layer 112.
  • the driving transistor includes an active layer, a gate insulating layer, a gate metal layer, a second insulating layer, and a source/drain electrode layer (including a source and a drain) which are sequentially disposed on the first insulating layer, in the first insulating layer A first via structure is formed in the second insulating layer, and the power supply trace is connected to the driving transistor through the first via structure.
  • Step 205 forming a passivation layer on the driving transistor, and a second via structure on the passivation layer.
  • the anode of the OLED device is electrically connected to the drain through the second via structure to implement a power supply trace to supply current to the driving transistor.
  • an illuminating current is provided for the OLED device.
  • Step 206 forming a pixel defining layer on the anode of the OLED device.
  • Step 207 forming a light-emitting layer on the pixel defining layer.
  • Step 208 forming a cathode on the light-emitting layer, the cathode being grounded.
  • the power trace is a planar structure formed by a metal mesh. This can reduce the voltage drop of the power supply trace (IR drop), thereby reducing the energy consumption of the OLED array substrate.
  • each column of pixel structure corresponds to a power line with a planar structure, so that the power lines of the plurality of planar structures are connected to form an integrated structure, which can make the area of the power supply line larger, thereby making the power supply line.
  • the voltage drop (IR drop) is further reduced, thereby further reducing the energy consumption of the OLED array substrate.
  • the area of the power trace corresponding to the pixel structure, the gate line, and the data line is set to be hollowed out. structure.
  • the area corresponding to the power supply line and the pixel structure is set to be hollowed out.
  • the main purpose is to prevent the metal trace from being shielded from light, which affects the transmittance of light.
  • the area corresponding to the power supply line and the gate line and the data line is set to a hollow structure, mainly to prevent A capacitor is formed between the power supply line and the gate line and the data line.
  • the hollow structure includes a plurality of non-continuous sub-hollow structures, which is equivalent to dividing the power supply trace of the planar structure into a plurality of parallel regions, thereby reducing the resistance of the planar power supply traces, thereby greatly increasing Reduce the voltage drop of the power trace.
  • the driving transistor is a top gate type thin film transistor
  • the power supply wiring overlaps with the active layer of the top gate type thin film transistor to shield the active layer from light.
  • the driving transistor is a bottom gate type thin film transistor
  • the power supply trace is disposed between the gate metal layer and the base substrate, and the power supply trace overlaps with the active layer of the bottom gate type thin film transistor.
  • Embodiments of the present disclosure provide an organic light emitting diode (OLED) array substrate, a method for fabricating the same, and a display device, which have at least one of the following beneficial effects:
  • the organic light emitting diode (OLED) array substrate is connected to a switching transistor by connecting a switching transistor to a gate line and a data line,
  • the power supply trace and the OLED device, the power supply trace is disposed under the pixel structure and at least partially overlaps with the pixel structure, and the power supply trace is connected to the driving transistor through the first via structure disposed in the insulating layer, thereby avoiding the OVDD trace Occupying the open area and the capacitive area of the pixel, the aperture ratio is increased, and the impedance of the display area pixel to OVDD is lowered.
  • the driving transistor is a top gate type thin film transistor
  • the OVDD trace can use a light shielding layer without occupying extra space, and is also increased. Large aperture ratio without adding additional steps.
  • the first insulating layer generally has two or more layers, which can reduce the parasitic capacitance between the power supply trace and the other metal traces.

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Abstract

一种有机发光二极管(OLED)阵列基板及其制备方法、显示装置，该OLED阵列基板包括：衬底基板(101)；设置在衬底基板(101)上的电源走线(102)和像素结构(105)，其中，电源走线(102)设置在像素结构(105)的下方且与像素结构(105)至少部分重叠；在电源走线(102)与像素结构(105)之间设置有绝缘层，绝缘层中设置有第一过孔结构(110)；电源走线(102)通过第一过孔结构(110)与像素结构(105)中的驱动晶体管(107)连接。该OLED阵列基板增大了开口率，并降低了显示区域像素到OVDD走线的阻抗。

Description

有机发光二极管(OLED)阵列基板及其制备方法、显示装置 技术领域
本公开的实施例涉及一种有机发光二极管(OLED)阵列基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)是一种采用电激发荧光体或磷光体有机化合物实现发光的器件。有机发光二极管(OLED)因其具有自发光、全固态、宽视角、响应快等诸多优点而被认为在显示领域中有着巨大的应用前景。有机发光二极管已被广泛地应用于手机、数码摄像机、个人数字助理(PDA)以及笔记本电脑中。
目前，OLED的一种主流显示方式为氧化物薄膜晶体管(Oxide Thin Film Transistor)、白光OLED显示(WOLED)和彩色滤色膜制作在阵列基板上(color filter on array，COA)的结构。为了解决氧化物薄膜晶体管的阈值电压(Vth)偏移及发光亮度不均一的问题，上述显示方式的驱动像素采用了3T1C的外部补偿技术，其中“3T1C”是指一个像素电路中包括三个薄膜晶体管(T)以及一个存储电容(C)。但是，该有机电致发光器件的像素开口区域较小，从而导致像素开口率减小，因此OLED的发光强度必须增大才能弥补像素开口率减小对OLED带来的不利影响，从而影响OLED器件的使用寿命。
发明内容
本公开至少一实施例提供一种有机发光二极管(OLED)阵列基板，该OLED阵列基板包括：衬底基板；设置在所述衬底基板上的电源走线和像素结构；其中，所述电源走线设置在所述像素结构的下方且与所述像素结构至少部分重叠；所述电源走线与所述像素结构之间设置有绝缘层，所述绝缘层中设置有第一过孔结构；所述电源走线通过所述第一过孔结构与所述像素结构中的驱动晶体管连接。
例如，在本公开至少一实施例提供的OLED阵列基板中，所述驱动晶 体管为顶栅型薄膜晶体管，所述电源走线与所述顶栅型薄膜晶体管的有源层重叠以对所述有源层进行遮光。
例如，在本公开至少一实施例提供的OLED阵列基板中，所述电源走线为由金属网格形成的面状结构。
例如，在本公开至少一实施例提供的OLED阵列基板中，每一列所述像素结构对应设置一条面状结构的所述电源走线。
例如，在本公开至少一实施例提供的OLED阵列基板中，还包括设置在所述衬底基板上的栅线和数据线，其中，所述像素结构设置在所述栅线和所述数据线交叉限定的区域内，所述电源走线与所述像素结构、所述栅线和所述数据线对应的区域内设置有镂空结构。
例如，在本公开至少一实施例提供的OLED阵列基板中，所述镂空结构包括多个非连续的子镂空结构。
例如，在本公开至少一实施例提供的OLED阵列基板中，所述驱动晶体管为底栅型薄膜晶体管，所述电源走线设置在所述底栅型薄膜晶体管的栅极金属层和所述衬底基板之间。
本公开至少一实施例还提供一种显示装置，包括上述任一有机发光二极管(OLED)阵列基板。
本公开至少一实施例还提供一种有机发光二极管(OLED)阵列基板的制备方法，包括：提供衬底基板；在所述衬底基板上形成电源走线和像素结构；在所述电源走线与所述像素结构之间形成绝缘层，在所述绝缘层中形成第一过孔结构；其中，所述电源走线设置在所述像素结构的下方且与所述像素结构至少部分重叠；所述电源走线通过所述第一过孔结构与所述像素结构中的驱动晶体管连接。
例如，在本公开至少一实施例提供的制备方法中，所述驱动晶体管为顶栅型薄膜晶体管，所述电源走线与所述顶栅型薄膜晶体管的有源层重叠以对所述有源层进行遮光。
例如，在本公开至少一实施例提供的制备方法中，所述电源走线为由金属网格形成的面状结构。
例如，在本公开至少一实施例提供的制备方法中，每一列所述像素结构对应设置一条面状结构的所述电源走线。
例如，本公开至少一实施例提供的制备方法，还包括在所述衬底基板 上形成栅线和数据线，其中，所述像素结构形成在所述栅线和所述数据线交叉限定的区域内，所述电源走线的与所述像素结构、所述栅线和所述数据线对应的区域设置有镂空结构。
例如，在本公开至少一实施例提供的制备方法中，所述镂空结构包括多个非连续的子镂空结构。
例如，在本公开至少一实施例提供的制备方法中，所述驱动晶体管为底栅型薄膜晶体管，所述电源走线设置在所述底栅型薄膜晶体管的栅极金属层和所述衬底基板之间。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种有机发光二极管(OLED)阵列基板的平面结构示意图；
图2为本公开一实施例提供的一种电源走线设置成镂空结构的平面结构示意图；
图3为本公开一实施例提供的一种有机发光二极管(OLED)阵列基板的部分截面结构示意图；
图4为本公开一实施例提供的再一种有机发光二极管(OLED)阵列基板的部分截面结构示意图；
图5a为本公开实施例提供的一种2T1C像素电路的示意图；
图5b为本公开实施例提供的再一种2T1C像素电路的示意图；
图5c为本公开实施例提供的又一种2T1C像素电路的示意图；
图6为本公开一实施例提供的一种有机发光二极管(OLED)阵列基板的制备方法的流程图；以及
图7为本公开一实施例提供的另一种有机发光二极管(OLED)阵列基板的制备方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本 公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开实施例所涉及的OLED阵列基板中各图案的尺寸在实际产品中通常为微米或更小量级，为了清楚起见，本公开实施例的附图中各结构的尺寸均被放大，除非另有没明确说明，本公开实施例的附图中各结构的尺寸不代表实际尺寸与比例。
研究发现，在目前的OLED阵列基板的结构中，电源走线(OVDD)会占用一部分像素的开口区域和电容区域。除此之外，OVDD走线自身具有电阻，当有电流通过OVDD走线时，OVDD走线上的电压降会对发光电流产生影响，这样会导致OVDD信号的幅值有一定的差异。考虑到薄膜晶体管(TFT)的特性并非理想(饱和区电流不仅和Vgs有关，还和Vds有关)，OVDD走线上的电压降会影响Vds，因此不同位置的OLED子像素输出的电流会因为OVDD电压的变化而变化。所以要尽量地减小OVDD走线的电阻，进而减小OVDD走线上的电压降。
本公开至少一实施例提供了一种有机发光二极管(OLED)阵列基板，该有机发光二极管(OLED)阵列基板包括衬底基板，设置在衬底基板上的电源走线和像素结构，其中，电源走线设置在像素结构的下方且与像素结构至少部分重叠，电源走线与像素结构之间设置有绝缘层，绝缘层中设置有第一过孔结构，电源走线通过第一过孔结构与像素结构中的驱动晶体管连接。
在该有机发光二极管(OLED)阵列基板中，通过将电源走线设置在像素结构的下方且与像素结构至少部分重叠，且电源走线通过设置在电源走线与像素结构之间的绝缘层中的第一过孔结构与驱动晶体管连接，从而避免了OVDD走线占用像素的开口区域和电容区域，进而增大了像素区域的开口率，并降低了显示区域像素到OVDD的阻抗。
本公开的实施例提供一种有机发光二极管(OLED)阵列基板，图1为本公开的实施例提供的一种有机发光二极管(OLED)阵列基板的平面结构示意图。如图1所示，该有机发光二极管(OLED)阵列基板包括衬底基板101、设置在衬底基板101上的电源走线102和像素结构105，电源走线102设置在像素结构105的下方且与像素结构105至少部分重叠；在电源走线102与像素结构105之间设置有绝缘层(图1中未示出)，该绝缘层中设置有第一过孔结构110，电源走线102通过第一过孔结构110与像素结构105中的驱动晶体管107连接。
例如，如图1所示，衬底基板101上还设置有栅线103和数据线104，像素结构105设置在栅线103和数据线104交叉限定的区域内，该像素结构105包括开关晶体管106、驱动晶体管107和OLED器件108，且开关晶体管106连接到栅线103和数据线104，驱动晶体管107连接到开关晶体管106、电源走线102和OLED器件108，开关晶体管106和驱动晶体管107的位置参见相应的虚线框。
图1中虽然仅示出了四个彼此并列的像素结构，且分别用于发出白光(W)、红光(R)、绿光(G)和蓝光(B)，但是本领的普通技术人员应该理解，本公开的实施例中的阵列基板所包括的像素结构不限于图1中示出的四个，可以包括更多个。
每个像素结构中还包括存储电容，该存储电容包括彼此相对设置的第一电极113和第二电极123，如图1所示，第一电极113和第二电极123均呈块状且二者之间设置有由绝缘材料形成的介电层。例如，第一电极113与驱动晶体管107的漏极连接，第二电极123与开关晶体管106的漏极连接。
例如，该OLED阵列基板包括显示区域和显示区域之外的外围区域，其中显示区域又称为AA(Active Area)区，一般用于实现显示，外围区域可用于设置驱动电路进行显示面板的封装等。上述像素结构、栅线和数据线 均位于显示区域。例如，在该OLED阵列基板中除了栅线、数据线等导线外，还可以包括连接像素单元与检测集成电路的检测补偿线，该检测补偿线也可以位于显示区域。
例如，考虑到栅线所在区域和驱动晶体管、存储电容的区域相距很近，将电源走线设置成更宽的区域，可以使之与驱动晶体管所在区域、存储电容所在区域在垂直于OLED阵列基板的方向上相交叠，可以在包括栅线、驱动晶体管以及存储电容的区域形成横向大面积的电源走线区域，例如，该电源走线为由金属网格形成的面状电极结构(而非单个条状或线状)，该金属网格形成的面状电极结构包括多个网孔。该面状结构的电源走线可以降低电源走线的电压降(IR drop)，从而可以降低OLED阵列基板的能耗。需要说明的是，面状结构的电源走线是指电源走线在像素结构的宽度和长度方向上均有一定的尺寸和延伸范围。
例如，在一个示例中，可以为每一列像素结构对应设置一条面状的电源走线，这样可以继续将多条面状的电源走线相连，形成一体的结构，可以使得电源走线的面积更大，进而使得电源走线的电压降(IR drop)进一步降低，从而可以进一步减少OLED阵列基板的能耗。
例如，在一个示例中，面状结构的电源走线的与像素结构、栅线和数据线对应的区域可以设置有镂空结构。需要说明的是，该镂空结构的尺寸与像素结构、栅线和数据线的尺寸相对应，该镂空结构的尺寸大于上述金属网格中网孔的尺寸。例如，图2为本公开一实施例提供的一种电源走线设置成镂空结构的平面结构示意图，如图2所示，电源走线102与像素结构对应的区域设置成镂空结构20主要是为了防止金属走线遮光，影响光线的透过率，即在像素结构对应的区域设置镂空结构可以增大光线的透过率，对入射光线进行充分的利用；电源走线102与栅线、数据线对应的区域设置成镂空结构，主要是为了防止电源走线与栅线、数据线之间形成电容。例如，如图2所示，该镂空结构20可以包括多个非连续的子镂空结构201(即多个子镂空结构彼此间间隔开)，这样相当于把面状结构的电源走线分割成多个并联的区域，这样可以减小面状电源走线的电阻，从而可以大幅度的减小电源走线的电压降。
例如，驱动晶体管可以为底栅型薄膜晶体管或者顶栅型薄膜晶体管。当驱动晶体管为顶栅型薄膜晶体管时，例如电源走线与顶栅型薄膜晶体管 的有源层重叠以对有源层进行遮光；当驱动晶体管为底栅型薄膜晶体管时，例如电源走线设置在底栅型薄膜晶体管的栅极金属层和衬底基板之间，且与有源层重叠。
下面分别以驱动晶体管为顶栅型薄膜晶体管和底栅型薄膜晶体管为例加以说明。
示例一，驱动晶体管为顶栅型薄膜晶体管，电源走线与顶栅型薄膜晶体管的有源层重叠以对有源层进行遮光。
例如，图3为本公开的实施例提供的一种有机发光二极管(OLED)阵列基板的部分截面结构示意图。如图3所示，驱动晶体管为顶栅型薄膜晶体管。例如，如图3所示，该驱动晶体管为顶栅型薄膜晶体管，结合图1和图3可以看出，在衬底基板101上设置有电源走线102、开关晶体管(图3中未示出)、驱动晶体管和OLED器件。该电源走线102与栅线103、数据线104之间的距离较远，能够减少栅线103与电源走线102、数据线104与电源走线102之间的相互干扰、降低发生静电放电(electro-static discharge,简称ESD)的风险。
例如，如图3所示，在衬底基板101上还设置有第一绝缘层109，在第一绝缘层109上设置有驱动晶体管的有源层116，在有源层116上依次形成有栅绝缘层111、栅极金属层115和第二绝缘层112，在第二绝缘层112上形成源极1071和漏极1072。在第一绝缘层109和第二绝缘层112中形成第一过孔结构110，电源走线102通过该第一过孔结构110与驱动晶体管的源极1071电连接。在源极1071和漏极1072上形成钝化层117，在钝化层117上形成第二过孔结构118。在该示例中，图1中所示的存储电容中第一电极113和第二电极123之间的介电层可以为第二绝缘层112。
如图3所示，该驱动晶体管107上设置有OLED器件108，OLED器件的阳极1081通过该第二过孔结构118与漏极1072电连接，以实现电源走线102为驱动晶体管107提供电流，进而为OLED器件提供发光电流。在OLED器件的阳极1081上形成像素界定层1082，在像素界定层1082上形成发光层1083，在发光层1083上形成阴极1084，OLED器件的阴极1084接地。
例如，在通过构图工艺形成源极和漏极的过程中，根据有源层材料的不同，如果有源层容易受到影响，还可以在有源层上形成刻蚀阻挡层，本 公开的实施例对此不作限制。
例如，电源走线102与有源层116重叠，这样该电源走线102可以同时被用作遮光层，从而可以节省一次构图工艺，节省生产成本。
需要说明的是，像素界定层的每个像素限定区对应一个像素电极，像素限定结构中每一列亚像素限定区为同种颜色的亚像素限定区，如图1所示，亚像素限定区包括白色亚像素限定区W，红色亚像素限定区R，绿色亚像素限定区G，蓝色亚像素限定区B。一个亚像素限定区101与相邻的同种颜色的亚像素限定区101连接，每个亚像素限定区101至多与相邻的两个同种颜色的亚像素限定区101连接。
驱动晶体管和开关晶体管可以同为顶栅型薄膜晶体管。例如，像素结构中开关晶体管的源极与数据线连接，开关晶体管的漏极与驱动晶体管的栅极电连接，开关晶体管的栅极与栅线电连接。
示例二，驱动晶体管为底栅型薄膜晶体管，该电源走线设置在栅极金属层和衬底基板之间，电源走线与底栅型薄膜晶体管的有源层重叠。
例如，图4为本公开的实施例提供的一种有机发光二极管(OLED)阵列基板的部分截面结构示意图，结合图1和图4可以看出，在衬底基板101上设置有电源走线102、第一绝缘层109、开关晶体管、驱动晶体管和OLED器件。该第一绝缘层109设置在电源走线102与像素结构105之间，电源走线102与像素结构105至少部分重叠。该电源走线102与栅线103、数据线104之间的距离较远，能够减少栅线103与电源走线102、数据线104与电源走线102之间相互干扰、降低发生静电放电(electro-static discharge,简称ESD)的风险。如图4所示，在栅绝缘层111和第一绝缘层109中形成第一过孔结构110，电源走线102通过第一过孔结构110与驱动晶体管107的源极1071连接。在该示例中，存储电容的第一电极113和第二电极123之间的介电层可以为栅绝缘层111。
例如，如图4所示，该驱动晶体管107上设置有OLED器件108，该OLED器件108包括阳极、发光层和阴极。OLED器件的阳极1081与驱动晶体管107的漏极1072通过第二过孔结构118电连接，该第二过孔结构118贯穿第二绝缘层112。在OLED器件的阳极1081上形成像素界定层1082，在像素界定层1082的开口部分形成发光层1083，在发光层1083上形成阴极1084，OLED器件的阴极1084接地。
需要说明的是，像素界定层的每个像素限定区对应一个像素电极，像素限定结构中每一列亚像素限定区为同种颜色的亚像素限定区，如图1所示亚像素限定区包括白色亚像素限定区W，红色亚像素限定区R，绿色亚像素限定区G，蓝色亚像素限定区B。一个亚像素限定区101与相邻的同种颜色的亚像素限定区101连接，每个亚像素限定区101至多与相邻的两个同种颜色的亚像素限定区101连接。
驱动晶体管和开关晶体管可以同为底栅型薄膜晶体管。例如，像素结构中开关晶体管的源极与数据线连接，开关晶体管的漏极与驱动晶体管的栅极电连接，开关晶体管的栅极与栅线电连接。
在示例一和示例二中，电源走线102为由金属网格形成的面状结构。由相互交叉的金属线(条)形成的面状结构可以进一步减少电阻。
例如，衬底基板101可以为透明的玻璃基板或透明的塑料基板。
例如，电源走线102、栅极金属层115、栅线103、源极1071、漏极1072以及数据线104的材料可以为铜基金属，例如，铜(Cu)、铜钼合金(Cu/Mo)、铜钛合金(Cu/Ti)、铜钼钛合金(Cu/Mo/Ti)、铜钼钨合金(Cu/Mo/W)、铜钼铌合金(Cu/Mo/Nb)等；也可以为铬基金属，例如，铬钼合金(Cr/Mo)、铬钛合金(Cr/Ti)、铬钼钛合金(Cr/Mo/Ti)等或者其他适合的材料。
例如，有源层采用半导体材料形成，该半导体材料例如为非晶硅、微晶硅、多晶硅、氧化物半导体等，氧化物半导体材料例如可以为IGZO(铟镓锌氧化物)、ZnO(氧化锌)等。
例如，有源层116的与源极1071、漏极1072接触的区域可以通过等离子体处理和高温处理的工序被导体化，从而能够更好地实现电信号的传输。
例如，第一绝缘层109、第二绝缘层112、像素界定层1082通常采用有机绝缘材料(例如，丙烯酸类树脂)或者无机绝缘材料(例如，氮化硅SiNx或者氧化硅SiOx)形成。例如，该第一绝缘层109和第二绝缘层112可以为由氮化硅或者氧化硅构成的单层结构，或者由氮化硅和氧化硅构成的双层结构。例如，第一绝缘层109一般有两层以上，可以减少电源走线102和其它层金属走线之间的寄生电容。
例如，被用作栅绝缘层111的材料包括氮化硅(SiNx)、氧化硅(SiOx)、 氧化铝(Al2O3)、氮化铝(AlN)或其他适合的材料。
例如，被用作钝化层117的材料包括氮化硅SiNx、氧化硅SiOx、氧氮化硅SiNxOy或者丙烯酸类树脂。
例如，在OLED器件中，为了将电子或空穴有效地注入发光层，需要降低注入的能垒，大部分用于OLED的有机材料的LUMO能级在2.5Ev～3.5Ev,HOMO能级在5Ev～6Ev,因此，阴极可以低功函的金属，阳极为高功函的透明材料。
例如，形成OLED器件的阳极1081的材料包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等。
例如，形成OLED器件的阴极1084的材料包括镁铝合金(MgAl)、锂铝合金(LiAl)或者镁、铝、锂单金属。为了得到顶发射或底发射模式，还可以在OLED器件中单独形成反射层。
例如，形成OLED器件的发光层1083的材料可以根据其发射光颜色的不同进行选择。发光层1083的材料包括荧光发光材料或磷光发光材料。目前，通常采用掺杂体系，即在主体发光材料中混入掺杂材料来得到可用的发光材料。例如，主体发光材料可以采用金属化合物材料、蒽的衍生物、芳香族二胺类化合物、三苯胺化合物、芳香族三胺类化合物、联苯二胺衍生物、或三芳胺聚合物等。
例如，每一列像素结构105对应设置一条面状的电源走线。这样，每一列像素结构中设置的电源走线之间相互间隔开，可以进一步地减少显示区域像素到电源走线的阻抗。
例如，在OLED阵列基板中，亚像素限定区内还可以设置彩膜层，例如，对于红色亚像素、蓝色亚像素以及绿色亚像素，可以通过组合白光OLED器件以及相应的红色彩膜层、蓝色彩膜层以及绿色彩膜层得到。该彩膜层可以为滤光片或者光转换层(例如荧光层)。又例如，在彩膜层上还可以设置平坦层。
例如，图5a-5c为本公开的实施例提供的2T1C像素电路的示意图。结合图1和图5a可以看出，除了开关晶体管T1和驱动晶体管T2之外，该像素结构105还包括存储电容Cs，该存储电容Cs的一端连接到开关晶体管T1的漏极以及驱动晶体管T2的栅极，另一端连接到驱动晶体管T2的 漏极和OLED的正极端。
如图5b所示，另一种2T1C像素电路包括开关晶体管T1、驱动晶体管T2以及存储电容Cs。例如，该开关晶体管T1的栅极连接栅线(扫描线)以接收扫描信号(Scan1)，例如源极连接到数据线以接收数据信号(Vdata)，漏极连接到驱动晶体管T2的栅极；驱动晶体管T2的源极连接到第一电源端(Vdd，高压端)，漏极连接到OLED的正极端；存储电容Cs的一端连接到开关晶体管T1的漏极以及驱动晶体管T2的栅极，另一端连接到驱动晶体管T2的源极以及第一电源端；OLED的负极连接到第二电源端(Vss，低压端)，例如接地。该2T1C像素电路的驱动方式是将像素的明暗(灰阶)经由两个TFT和存储电容Cs来控制。当通过栅线施加扫描信号Scan1以开启开关晶体管T1时，数据驱动电路通过数据线送入的数据电压(Vdata)将经由开关晶体管T1对存储电容Cs充电，由此将数据电压存储在存储电容Cs中，且此存储的数据电压控制驱动晶体管T2的导通程度，由此控制流过驱动晶体管以驱动OLED发光的电流大小，即此电流决定该像素发光的灰阶。在图5b所示的2T1C像素电路中，开关晶体管T1为N型晶体管而驱动晶体管为P型晶体管。
如图5c所示，又一种2T1C像素电路也包括开关晶体管T1、驱动晶体管T2以及存储电容Cs，但是其连接方式略有改变，且驱动晶体管T2为N型晶体管。更具体而言，图5c的像素电路相对于图5b的变化之处包括：OLED的正极端连接到第一电源端(Vdd，高压端)而负极端连接到驱动晶体管T2的漏极，驱动晶体管T2的源极连接到第二电源端(Vss，低压端)，例如接地。存储电容Cs的一端连接到开关晶体管T1的漏极以及驱动晶体管T2的栅极，另一端连接到驱动晶体管T2的源极以及第二电源端。该2T1C像素电路的工作方式基本上与图1A所示的像素电路基本相同，这里不再赘述。
此外，对于图5b和图5c所示的像素电路，开关晶体管T1不限于N型晶体管，也可以为P型晶体管，由此控制其导通或截止的扫描信号(Scan1)的极性进行相应地改变即可。
例如，在本公开的实施例中，像素电路还可以为3T1C、4T2C等，除上述开关晶体管和驱动晶体管之外，还可以包括补偿晶体管、复位晶体管等，在此不做限制。
本公开的实施例还提供一种显示装置，包括上述任一有机发光二极管(OLED)阵列基板，并且还可以包括栅极驱动电路、数据驱动电路以及电源等，栅线与栅极驱动电路连接，数据线与数据驱动电路连接，电源布线与电源连接。该显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例中的显示装置所包括的有机发光二极管(OLED)阵列基板与上述图3或图4所示的有机发光二极管(OLED)阵列基板的结构相同，其技术效果与实现原理相同，在此不再赘述。
另外，该显示装置可以采用底发射或者顶发射模式，还可以采用两面发射模式。例如，显示装置包括图3或图4所示的OLED阵列基板时，可以采用底发射模式。
本公开的实施例还提供一种OLED阵列基板的制备方法，图6为本公开的实施例提供的OLED阵列基板的制备方法的流程图，如图6所示，该制备方法包括如下步骤：
步骤101、提供衬底基板。
步骤102、在衬底基板上形成电源走线、栅线和数据线。
步骤103、在栅线和数据线交叉限定的区域内形成像素结构，该像素结构包括开关晶体管、驱动晶体管和OLED器件。
步骤104、在电源走线与像素结构之间形成绝缘层，在绝缘层中形成第一过孔结构。
例如，如图3所示，当驱动晶体管为顶栅型薄膜晶体管时，该绝缘层包括第一绝缘层109和第二绝缘层112；如图4所示，当驱动晶体管为底栅型薄膜晶体管时，该绝缘层包括栅绝缘层111和第一绝缘层109。
例如，开关晶体管连接到栅线和数据线，驱动晶体管连接到开关晶体管、电源走线和OLED器件；电源走线设置在像素结构的下方且与像素结构至少部分重叠；电源走线通过第一过孔结构与驱动晶体管连接。
在本公开的实施例提供的OLED阵列基板的制备方法中，电源走线设置在像素结构的下方且与像素结构至少部分重叠；电源走线通过第一过孔结构与驱动晶体管连接，从而避免了电源走线占用像素的开口区域和电容区域，增大了开口率，并降低了显示区域像素到OVDD的阻抗。
本公开的实施例提供的OLED阵列基板的制备方法，以驱动晶体管为顶栅型薄膜晶体管为例加以说明，例如，图7为形成图3所示OLED阵列基板的制备方法的流程图，该方法包括以下步骤：
步骤201、提供衬底基板，例如，该衬底基板可以为玻璃基板、石英基板等。
步骤202、在衬底基板上形成电源走线、栅线和数据线。
步骤203、在栅线和数据线交叉限定的区域内形成像素结构，在像素结构内形成开关晶体管、驱动晶体管和OLED器件。
步骤204、在电源走线与像素结构之间形成绝缘层，在绝缘层中形成第一过孔结构。
例如，开关晶体管连接到栅线和数据线，驱动晶体管连接到开关晶体管、电源走线和OLED器件，电源走线设置在像素结构的下方且与像素结构至少部分重叠。
例如，如图3所示，该绝缘层包括第一绝缘层109和第二绝缘层112。
例如，驱动晶体管包括依次设置在第一绝缘层上的有源层、栅绝缘层、栅极金属层、第二绝缘层和源漏电极层(包括源极和漏极)，在第一绝缘层和第二绝缘层中形成第一过孔结构，电源走线通过第一过孔结构与驱动晶体管连接。
步骤205、在驱动晶体管上形成钝化层，在钝化层上第二过孔结构，OLED器件的阳极通过该第二过孔结构与漏极电连接，以实现电源走线为驱动晶体管提供电流，进而为OLED器件提供发光电流。
步骤206、在OLED器件的阳极上形成像素界定层。
步骤207、在像素界定层上形成发光层。
步骤208、在发光层上形成阴极，该阴极接地。
例如，电源走线为由金属网格形成的面状结构。这样可以降低电源走线的电压降(IR drop)，从而可以降低OLED阵列基板的能耗。
例如，每一列像素结构对应设置一条面状结构的电源走线，这样将多条面状结构的电源走线相连，形成一体的结构，可以使得电源走线的面积更大，进而使得电源走线的电压降(IR drop)进一步降低，从而可以进一步减少OLED阵列基板的能耗。
例如，电源走线的与像素结构、栅线和数据线对应的区域设置有镂空 结构。电源走线与像素结构对应的区域设置成镂空结构主要是为了防止金属走线遮光，影响光线的透过率，电源走线与栅线、数据线对应的区域设置成镂空结构，主要是为了防止电源走线与栅线、数据线之间形成电容。例如，该镂空结构包括多个非连续的子镂空结构，这样相当于把面状结构的电源走线分割成多个并联的区域，这样可以减小面状电源走线的电阻，从而可以大幅度的减小电源走线的电压降。
例如，驱动晶体管为顶栅型薄膜晶体管，电源走线与顶栅型薄膜晶体管的有源层重叠以对有源层进行遮光。
例如，驱动晶体管为底栅型薄膜晶体管，该电源走线设置在栅极金属层和衬底基板之间，电源走线与底栅型薄膜晶体管的有源层重叠。
其他结构的有机发光二极管(OLED)阵列基板的制备方法类似，在此不再赘述。
本公开的实施例提供一种有机发光二极管(OLED)阵列基板及其制备方法、显示装置，具有以下至少一项有益效果：
(1)在本公开至少一实施例提供的有机发光二极管(OLED)阵列基板中，该有机发光二极管(OLED)阵列基板通过将开关晶体管连接到栅线和数据线，驱动晶体管连接到开关晶体管、电源走线和OLED器件，电源走线设置在像素结构的下方且与像素结构至少部分重叠，电源走线通过设置在绝缘层中的第一过孔结构与驱动晶体管连接，从而避免了OVDD走线占用像素的开口区域和电容区域，增大了开口率，并降低了显示区域像素到OVDD的阻抗。
(2)在本公开至少一实施例提供的有机发光二极管(OLED)阵列基板中，当驱动晶体管为顶栅型薄膜晶体管时，该OVDD走线可以使用遮光层，不必占用额外的空间，同样增大开口率，且不用增加额外的工序。
(3)在本公开至少一实施例提供的有机发光二极管(OLED)阵列基板中，第一绝缘层一般有两层以上，可以减少电源走线和其它层金属走线之间的寄生电容。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区 域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年9月23日递交的中国专利申请第201610848552.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种有机发光二极管(OLED)阵列基板，包括：
    衬底基板；
    设置在所述衬底基板上的电源走线和像素结构；
    其中，所述电源走线设置在所述像素结构的下方且与所述像素结构至少部分重叠；所述电源走线与所述像素结构之间设置有绝缘层，所述绝缘层中设置有第一过孔结构；所述电源走线通过所述第一过孔结构与所述像素结构中的驱动晶体管连接。
  2. 根据权利要求1所述的OLED阵列基板，其中，所述驱动晶体管为顶栅型薄膜晶体管，所述电源走线与所述顶栅型薄膜晶体管的有源层重叠以对所述有源层进行遮光。
  3. 根据权利要求1或2所述的OLED阵列基板，其中，所述电源走线为由金属网格形成的面状结构。
  4. 根据权利要求3所述的OLED阵列基板，其中，每一列所述像素结构对应设置一条面状结构的所述电源走线。
  5. 根据权利要求1-4中任一项所述的OLED阵列基板，还包括设置在所述衬底基板上的栅线和数据线，其中，所述像素结构设置在所述栅线和所述数据线交叉限定的区域内，所述电源走线与所述像素结构、所述栅线和所述数据线对应的区域内设置有镂空结构。
  6. 根据权利要求5所述的OLED阵列基板，其中，所述镂空结构包括多个非连续的子镂空结构。
  7. 根据权利要求1所述的OLED阵列基板，其中，所述驱动晶体管为底栅型薄膜晶体管，所述电源走线设置在所述底栅型薄膜晶体管的栅极金属层和所述衬底基板之间。
  8. 一种显示装置，包括权利要求1-7中任一项所述的有机发光二极管(OLED)阵列基板。
  9. 一种机发光二极管(OLED)阵列基板的制备方法，包括：
    提供衬底基板；
    在所述衬底基板上形成电源走线和像素结构；
    在所述电源走线与所述像素结构之间形成绝缘层，在所述绝缘层中形 成第一过孔结构；
    其中，所述电源走线设置在所述像素结构的下方且与所述像素结构至少部分重叠；所述电源走线通过所述第一过孔结构与所述像素结构中的驱动晶体管连接。
  10. 根据权利要求9所述的制备方法，其中，所述驱动晶体管为顶栅型薄膜晶体管，所述电源走线与所述顶栅型薄膜晶体管的有源层重叠以对所述有源层进行遮光。
  11. 根据权利要求9或10所述的制备方法，其中，所述电源走线为由金属网格形成的面状结构。
  12. 根据权利要求11所述的OLED阵列基板，其中，每一列所述像素结构对应设置一条面状结构的所述电源走线。
  13. 根据权利要求9-12中任一项所述的制备方法，还包括在所述衬底基板上形成栅线和数据线，其中，所述像素结构形成在所述栅线和所述数据线交叉限定的区域内，所述电源走线的与所述像素结构、所述栅线和所述数据线对应的区域设置有镂空结构。
  14. 根据权利要求13所述的制备方法，其中，所述镂空结构包括多个非连续的子镂空结构。
  15. 根据权利要求9所述的制备方法，其中，所述驱动晶体管为底栅型薄膜晶体管，所述电源走线设置在所述底栅型薄膜晶体管的栅极金属层和所述衬底基板之间。
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