Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0191—Manufacturing their doped wells
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/0237—Materials
  • H01L21/02373—Group 14 semiconducting materials
  • H01L21/02381—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02532—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02612—Formation types
  • H01L21/02617—Deposition types
  • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/351—Substrate regions of field-effect devices
  • H10D62/357—Substrate regions of field-effect devices of FETs
  • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
  • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/85—Complementary IGFETs, e.g. CMOS
  • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]

Definitions

• Radiation hardened and other high reliability electronic circuits are desired for a variety of applications in which systems and circuits are exposed to radiation, electromagnetic interference (EMI) or other adverse electrical noise conditions.
• Example applications include satellites and other spacecraft, aircraft, medical devices such as x-ray equipment, circuits used in nuclear power plants, processor cores and other sensitive digital circuits.
• radiation can cause latchup in metal oxide semiconductor (MOS) circuits due to wells and doped regions that operate as bipolar transistors.
• MOS metal oxide semiconductor
• these parasitic bipolar transistors can be turned on by current flow beneath the MOS circuit components, leading to potentially large currents that interfere with operation of logic circuits in an integrated circuit (IC), and can sometimes cause the IC to become permanently damaged.
• MOS metal oxide semiconductor
• latchup involves inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic PNPN (silicon controlled rectifier or SCR) structure operating as a PNP and an NPN transistor stacked next to each other.
• parasitic PNPN silicon controlled rectifier or SCR
• SCR parasitic rectifier
• a single event latchup (SEL) is a latchup caused by a single event upset, typically from heavy ions or protons from cosmic rays or solar flares.
• a method includes forming a first epitaxial semiconductor layer of a first conductivity type on a first side of a semiconductor substrate of the first conductivity type, and forming a second epitaxial semiconductor layer of the first conductivity type on the second side of the semiconductor substrate.
• Described semiconductor device examples include a semiconductor substrate of a first conductivity type, a first epitaxial semiconductor layer of the first conductivity type formed on the first side of the semiconductor substrate, and a second epitaxial semiconductor layer of the first conductivity type formed on the second side of the semiconductor substrate.
• the device can be used to fabricate an integrated circuit by forming transistors at least partially on the first epitaxial semiconductor layer.
• a nitride or oxide protection layer is formed on a top side of the first epitaxial semiconductor layer before forming the second epitaxial layer, and the protection layer is removed after the second epitaxial layer is formed.
• the first and second epitaxial semiconductor layers are more lightly doped than the semiconductor substrate.
• FIG. 1 is a perspective view of a semiconductor wafer device with first and second lightly doped p-type epitaxial layers on opposite top and bottom sides of a more heavily doped p-type substrate.
• FIG. 2 is a partial sectional side elevation view of an integrated circuit fabricated using the semiconductor wafer of FIG. 1.
• FIG. 3 is a flow diagram of a method to fabricate a semiconductor wafer and to fabricate an integrated circuit.
• FIG. 8 is a perspective view of a semiconductor wafer with first and second lightly doped n-type epitaxial layers on opposite top and bottom sides of a more heavily doped n-type substrate.
• the device 100 in one example is generally cylindrical having a diameter suitable for semiconductor fabrication processes, such as 150 mm, 200 mm, 300 mm, 450 mm diameter, etc.
• the first epitaxial layer 104a includes an exposed top side 111 and has a thickness Tl .
• the thickness Tl is 3.0 ⁇ or more.
• the thickness Tl is from 3.0 to 20 ⁇ .
• thicknesses Tl of greater than 20 ⁇ can be used.
• the thickness Tl in certain examples is set by CMOS processing requirements of a given circuit application for transistors and other circuitry to be formed on or in the first epitaxial layer 104a.
• CMOS latchup mechanisms can be mitigated to a certain extent by formation of a relatively high resistivity epitaxial layer over a lower resistivity starting substrate.
• the transistors and other components are formed in the more lightly doped, higher sheet resistivity P- epitaxial layer, and thus parasitic bipolar and SCR devices have much lower gain and are less likely to cause latchup.
• P+/P- epitaxial substrates are used to fabricate integrated circuits to mitigate sensitivity to latchup caused by cosmic rays (e.g., terrestrial neutron and proton reactions) in avionic applications and/or sensitivity to heavy ions in space applications.
• the second epitaxial layer 104b operates as a barrier to outward migration of boron or other dopants from the heavily doped substrate 102 during thermal processing, thereby mitigating auto doping during integrated circuit fabrication. Moreover, the second epitaxial layer 104b counteracts in-process warping by providing a second interface to the substrate 102 on the opposite side of the first epitaxial layer 104a.
• an integrated circuit (IC) 200 is shown, which is built using the device 100 of FIG. 1.
• the IC 200 includes a semiconductor substrate 102 of a first conductivity type (e.g., p-type) which has a planar first (e.g., upper) side 102a and a planar opposite second (e.g., bottom) side 102b.
• the first epitaxial semiconductor layer 104a also p-type in this example, is formed on the first side 102a of the substrate 102
• the p-type second epitaxial semiconductor layer 104b is formed on the second side 102b of the substrate 102.
• the IC 200 also includes one or more transistors 202 and 206 formed at least partially on the first epitaxial semiconductor layer 104a. Many such transistors and other electronic components (not shown) can be formed at least partially on the epitaxial layer 104a using standard fabrication techniques.
• a PMOS transistor 202 is formed in a lightly doped (e.g., N-) n-well 204. Relatively heavily doped P+ source/drain regions are formed in the n-well 204 on opposite sides of a channel region, with a gate structure formed at least partially over the PMOS channel region.
• an N+ well contact is included, and the PMOS transistor 202 is isolated from other peripheral components by one or more isolation structures 208 (shallow trench isolation or STI structures in this example).
• the second transistor 206 in FIG. 2 is an MOS transistor including N+ source/drains formed in the lightly doped P- epitaxial layer material 104a and a gate structure formed over the P- channel region between the N+ source/drains.
• a P+ substrate contact is also formed adjacent the NMOS transistor 206 in this example to provide electrical conductivity to the P+ substrate 102.
• the transistor source/drain regions are formed in the top side 111 of the first epitaxial layer 104a, with the gate structures and source/drain contacts formed above the top side 111, the transistors 202, 206 are at least partially formed on the first epitaxial semiconductor layer 104a.
• the IC 200 in FIG. 2 also includes a pre-metal dielectric (PMD) structure layer formed over the top side 111.
• the PMD layer includes one or more conductive contact structures forming electrical contacts to the source/drain regions, the gates and the well/substrate contacts.
• the IC 200 further includes one or more metallization layers Ml and M2 and an upper passivation layer 210.
• Each of the metallization layers Ml, M2 includes interlayer dielectric (ILD) material and conductive contact structures to interconnect various components and component terminals of an electrical circuit formed by the transistors 202, 206 and other electrical components of the IC 200.
• ILD interlayer dielectric
• the use of the lightly doped P- epitaxial layer 104a advantageously mitigates radiation-induced latchup of the transistors 202, 206 and other problems related to exposure to radiation.
• the second or lower epitaxial layer 104b advantageously provides a barrier to mitigate or prevent auto doping during fabrication, and also counteracts any warping effects associated with the presence of the upper first epitaxial layer 104a.
• the second epitaxial layer 104b does not suffer from charge accumulation during plasma or implantation processing steps, and thus is not subject to arcing problems previously associated with auto doping prevention (e.g. nitride) layers.
• FIG. 3 shows a method 300 to fabricate a semiconductor device, including process steps 303 to form a starting wafer or device 100 as shown in FIG. 1, and further processing steps to form an integrated circuit such as the IC 200 of FIG. 2.
• FIGS. 4-7 show the semiconductor wafer device 100 of FIG. 1 at various stages of fabrication according to the methods 300 and 303 of FIG. 3.
• the methods 300, 303 can be used in association with P-/P+/P- devices 100 is shown in FIGS. 1 and 2, and with N-/N+/N- devices as illustrated and described hereinbelow in connection with FIGS. 8 and 9.
• the method 300 begins at 302 with a starting wafer or substrate 102.
• the method 300 includes fabrication of a device (e.g., device 100 described hereinabove) at 303, including forming a first epitaxial silicon layer 104a at 304 of the first conductivity type on a first side of the substrate (e.g., first side 102a in FIG. 2 described hereinabove).
• FIG. 4 shows an example of the processing at 304, in which an epitaxial growth process step 400 is used to form the p-type first epitaxial layer 104a to a first thickness Tl on the first side 102a of the P+ substrate 102.
• Any suitable epitaxial growth process 400 can be used at 304 to provide lightly doped p-type silicon material having a crystalline structure that generally mimics the crystalline orientation of the first side 102a of the substrate 102.
• an optional protection layer is formed at 306 on the exposed top side 111 of the first epitaxial layer 104a.
• an oxidation process 500 is used in FIG. 5 to form an oxide and/or nitride protection layer 106 to a thickness of approximately 400 A or more, such as 400-2000 A on the top side 111 of the first epitaxial semiconductor layer 104a.
• the substrate is flipped or inverted at 308, leaving the exposed second side 102a of the substrate 102 on top of the structure.
• the protection layer 106 provides protection for the top side 111 of the first epitaxial layer 104a during subsequent fabrication processing, with the first epitaxial layer 104a being designed for subsequent formation of transistors and other electronic components in the finished IC device 200 of FIG. 2.
• a nitride material is formed at 306 on the top side 111 of the first epitaxial silicon layer 104a before forming 310 the second epitaxial silicon layer 104b.
• an oxide material is formed at 306 on the top side 111 of the first epitaxial silicon layer 104a before forming 310 the second epitaxial silicon layer 104b.
• the method 303 further includes forming a second lightly doped p-type epitaxial silicon layer 104b at 310 on the second side 102b of the silicon substrate 102.
• a second epitaxial growth process 600 is performed to form the second epitaxial layer 104b to a thickness T2 on the second side 102b of the substrate 102.
• the second epitaxial layer thickness T2 can be the same or similar as the thickness Tl of the first epitaxial layer 104a, although not a strict requirement of all implementations of the methods 300, 303.
• any suitable second epitaxial growth process 600 can be used at 310 to form the second lightly doped epitaxial layer 104b.
• FIG. 7 illustrates an example etch or material removal process 700 used to remove the protection layer 106, leaving the top side 111 of the first epitaxial layer 104a exposed.
• the processing at 303 in FIG. 3 yields a device 100 is shown in FIG. 1 where p-type semiconductor materials 102, 104 are used.
• the processing steps 303 in FIG. 3 can be used to fabricate a device 802 as shown in FIG. 8, including an N+ substrate 802 and first and second lightly doped N- epitaxial layers 804a and 804b.
• the IC fabrication method 300 in one example further includes forming a plurality of transistors 202, 206 at least partially on the first epitaxial silicon layer 104a at 316 after removing the protection layer 106 from the first epitaxial silicon layer 104a.
• One or more metallization layers and other back-and processing is performed at 318 in FIG. 3 to provide an integrated circuit device, such as the IC 200 of FIG. 2 described hereinabove.
• FIGS. 8 and 9 show an N-/N+/N- wafer or device 800, including an N+ substrate 802, a first lightly doped N-epitaxial layer 804a formed on a first side of the substrate 802, and a second lightly doped N- epitaxial layer 804b formed on an opposite second side of the substrate 802.
• the device 800 and the IC 900 in FIGS. 8 and 9 can be fabricated using the processes 300 and 303 of FIG. 3 with p-type dopants and materials being replaced with n-type dopants and materials, and vice versa. As described hereinabove in connection with the P-/P+/P- device 100 of FIG.
• the device 800 can be used as a starting wafer for fabricating a high reliability and/or radiation hardened IC, in which the first and second epitaxial layers 804 provide counterbalancing with respect to warping during processing, and mitigating auto doping during processing.
• the first epitaxial layer 804a can be used for fabricating transistors and other electronic components in a relatively lightly doped semiconductor material to mitigate latchup and other radiation-based effects on the resulting IC.
• the processing steps 303 in FIG. 3 can be used to fabricate the device 800 of FIG. 8, where the materials used in the substrate 802 and the epitaxial layers 804 are n-type doped (e.g., using phosphorus or other suitable n-dopants).
• FIG. 9 shows an example IC 900 fabricated using the device 800 of FIG. 8, including the substrate 802, the first epitaxial layer 804a formed on a first side 802a of the substrate 802, and the second epitaxial layer 804b on the opposite second side 802b of the substrate 802.
• a PMOS transistor 902 is formed on the top side 811 of the first epitaxial semiconductor layer 804a, including P+ source/drains formed in the lightly doped N- epitaxial layer 804a.
• This example also includes an N+ substrate contact formed with the PMOS transistor 902 between a pair of STI structures 908.
• the IC 900 also includes a lightly doped P- p-well 904 in which an NMOS transistor 906 and a P+ well contact are formed in the first epitaxial layer 804a.
• the transistors 902 and 906 also include gate structures overlying the corresponding channel regions, and a PMD structure layer, and one or more metallization layers Ml and M2, and an upper passivation layer 910.
• the doped second epitaxial layer blocks boron out-diffusion in P-/P+/P- examples to mitigate auto-doping.
• the second epitaxial layer 104b 804b also provides a backside conductivity of the substrate to chucking equipment during fabrication, and can thus be used in regular fabrication equipment without additional modification or additional blocking layers.

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• Engineering & Computer Science (AREA)
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