KR102469160B1 - 기판 상에 양면형 에피택셜을 사용한 공정 개선 - Google Patents

기판 상에 양면형 에피택셜을 사용한 공정 개선 Download PDF

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KR102469160B1
KR102469160B1 KR1020197004299A KR20197004299A KR102469160B1 KR 102469160 B1 KR102469160 B1 KR 102469160B1 KR 1020197004299 A KR1020197004299 A KR 1020197004299A KR 20197004299 A KR20197004299 A KR 20197004299A KR 102469160 B1 KR102469160 B1 KR 102469160B1
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epitaxial
layer
type
conductivity type
semiconductor
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KR20190039138A (ko
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제임스 프레드 살즈만
브래들리 데이빗 서처
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텍사스 인스트루먼츠 인코포레이티드
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H01L21/823892—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L27/0248—
    • H01L27/0921—
    • H01L29/1083—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020197004299A 2016-08-16 2017-08-16 기판 상에 양면형 에피택셜을 사용한 공정 개선 Active KR102469160B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/238,445 2016-08-16
US15/238,445 US10002870B2 (en) 2016-08-16 2016-08-16 Process enhancement using double sided epitaxial on substrate
PCT/US2017/047148 WO2018035226A1 (en) 2016-08-16 2017-08-16 Process enhancement using double sided epitaxial on substrate

Publications (2)

Publication Number Publication Date
KR20190039138A KR20190039138A (ko) 2019-04-10
KR102469160B1 true KR102469160B1 (ko) 2022-11-22

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KR1020197004299A Active KR102469160B1 (ko) 2016-08-16 2017-08-16 기판 상에 양면형 에피택셜을 사용한 공정 개선

Country Status (6)

Country Link
US (3) US10002870B2 (enExample)
EP (1) EP3501035A4 (enExample)
JP (2) JP7070970B2 (enExample)
KR (1) KR102469160B1 (enExample)
CN (1) CN109564854A (enExample)
WO (1) WO2018035226A1 (enExample)

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CN109727852B (zh) * 2018-12-29 2020-12-01 长江存储科技有限责任公司 一种改善晶圆翘曲的方法、装置和设备
US10879155B2 (en) * 2019-05-09 2020-12-29 Texas Instruments Incorporated Electronic device with double-sided cooling
JP2021034584A (ja) * 2019-08-26 2021-03-01 キオクシア株式会社 半導体装置及び半導体装置の製造方法
WO2021205695A1 (ja) * 2020-04-10 2021-10-14 株式会社村田製作所 可変容量素子及びそれを備えた発振器
JP7334698B2 (ja) * 2020-09-11 2023-08-29 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
JP7380517B2 (ja) * 2020-10-21 2023-11-15 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
US12027582B2 (en) * 2021-10-05 2024-07-02 Globalfoundries U.S. Inc. IC structure including porous semiconductor layer under trench isolation
US12119352B2 (en) 2022-01-06 2024-10-15 Globalfoundries U.S. Inc. IC structure including porous semiconductor layer in bulk substrate adjacent trench isolation
WO2025106550A1 (en) * 2023-11-14 2025-05-22 Cornell University Increasing density of semiconductor devices on a substrate

Citations (5)

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US20080296675A1 (en) 2007-05-29 2008-12-04 Sanyo Electric Co., Ltd. Semiconductor device
WO2009001833A1 (ja) 2007-06-26 2008-12-31 Sumco Corporation エピタキシャルウェーハおよびその製造方法
US20100075175A1 (en) * 2008-09-11 2010-03-25 Soraa, Inc. Large-area seed for ammonothermal growth of bulk gallium nitride and method of manufacture
US20110095358A1 (en) 2009-10-28 2011-04-28 Stmicrolectronics S.R.L. Double-sided semiconductor structure and method for manufacturing same
US20130264467A1 (en) * 2012-04-09 2013-10-10 Omnivision Technologies, Inc. Double-sided image sensor

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JPH10229162A (ja) 1997-02-14 1998-08-25 Tokai Rika Co Ltd 両面回路基板及びその製造方法
JPH10303207A (ja) * 1997-04-23 1998-11-13 Hitachi Ltd 半導体ウエハおよびその製造方法、ならびに半導体集積回路装置
JP2000124144A (ja) * 1998-10-21 2000-04-28 Hitachi Ltd 半導体集積回路装置の製造方法、ならびに半導体ウエハおよびその製造方法
JP2002231634A (ja) * 2001-01-30 2002-08-16 Shin Etsu Handotai Co Ltd シリコンエピタキシャルウェーハ及びシリコンエピタキシャルウェーハの製造方法
JP2002305304A (ja) 2001-04-05 2002-10-18 Toshiba Corp 電力用半導体装置
WO2007131343A1 (en) * 2006-05-15 2007-11-22 Arise Technologies Corporation Low-temperature doping processes for silicon wafer devices
US20080023824A1 (en) 2006-07-28 2008-01-31 Texas Instruments Double-sided die
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US8455290B2 (en) * 2010-09-04 2013-06-04 Masimo Semiconductor, Inc. Method of fabricating epitaxial structures
US8530298B2 (en) 2011-11-01 2013-09-10 Texas Instruments Incorporated Radiation hardened integrated circuit
US20130126508A1 (en) 2011-11-17 2013-05-23 Texas Instruments Incorporated Extending Radiation Tolerance By Localized Temperature Annealing Of Semiconductor Devices
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US20080296675A1 (en) 2007-05-29 2008-12-04 Sanyo Electric Co., Ltd. Semiconductor device
WO2009001833A1 (ja) 2007-06-26 2008-12-31 Sumco Corporation エピタキシャルウェーハおよびその製造方法
US20100075175A1 (en) * 2008-09-11 2010-03-25 Soraa, Inc. Large-area seed for ammonothermal growth of bulk gallium nitride and method of manufacture
US20110095358A1 (en) 2009-10-28 2011-04-28 Stmicrolectronics S.R.L. Double-sided semiconductor structure and method for manufacturing same
US20130264467A1 (en) * 2012-04-09 2013-10-10 Omnivision Technologies, Inc. Double-sided image sensor

Also Published As

Publication number Publication date
KR20190039138A (ko) 2019-04-10
JP7070970B2 (ja) 2022-05-18
US11056490B2 (en) 2021-07-06
EP3501035A1 (en) 2019-06-26
US10002870B2 (en) 2018-06-19
CN109564854A (zh) 2019-04-02
US20180254272A1 (en) 2018-09-06
US20190296013A1 (en) 2019-09-26
JP2022101678A (ja) 2022-07-06
EP3501035A4 (en) 2019-09-04
JP2019528573A (ja) 2019-10-10
US10304827B2 (en) 2019-05-28
WO2018035226A1 (en) 2018-02-22
US20180053764A1 (en) 2018-02-22

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