WO2018028198A1 - 补偿像素电路、显示面板、显示设备、补偿及驱动方法 - Google Patents

补偿像素电路、显示面板、显示设备、补偿及驱动方法 Download PDF

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Publication number
WO2018028198A1
WO2018028198A1 PCT/CN2017/076917 CN2017076917W WO2018028198A1 WO 2018028198 A1 WO2018028198 A1 WO 2018028198A1 CN 2017076917 W CN2017076917 W CN 2017076917W WO 2018028198 A1 WO2018028198 A1 WO 2018028198A1
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Prior art keywords
transistor
compensation
voltage
pixel circuit
circuit
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PCT/CN2017/076917
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English (en)
French (fr)
Inventor
杨盛际
董学
吕敬
陈小川
刘冬妮
王磊
肖丽
岳晗
卢鹏程
付杰
刘英明
张粲
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2017550869A priority Critical patent/JP6879928B2/ja
Priority to KR1020177029231A priority patent/KR101998174B1/ko
Priority to EP17771325.2A priority patent/EP3499492B1/en
Priority to US15/562,513 priority patent/US10643539B2/en
Publication of WO2018028198A1 publication Critical patent/WO2018028198A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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Definitions

  • Embodiments of the present disclosure relate to a compensation pixel circuit, a display panel, a display device, a region compensation method, and a driving method.
  • organic light-emitting diode (OLED) display panels have the characteristics of self-luminous, high contrast, low power consumption, wide viewing angle, fast response, flexible panel, wide temperature range, and simple manufacturing. Prospects.
  • the organic light emitting diode (OLED) display panel can be applied to a device having a display function such as a mobile phone, a display, a notebook computer, a digital camera, an instrument meter, and the like.
  • Embodiments of the present disclosure provide a compensation pixel circuit including: a compensation driving circuit including a driving transistor and an organic light emitting diode, wherein the compensation driving circuit is configured to receive a light emitting data signal, compensate a threshold voltage of the driving transistor, and Driving the organic light emitting diode to emit light according to the light emitting data signal; a signal collecting circuit connected to the compensation driving circuit is configured to collect a gate voltage of the driving transistor.
  • the signal acquisition circuit is electrically connected to the gate of the drive transistor.
  • the compensation driving circuit further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a storage capacitor.
  • the first pole of the first transistor is electrically connected to the first power line to receive the first voltage, the gate of the first transistor, the fifth transistor
  • the gate is electrically connected to the second scan signal line to receive the second scan signal
  • the second pole of the first transistor is electrically connected to the first node
  • the first pole of the second transistor is electrically connected to the light-emitting data signal line Receiving a light-emitting data signal, a gate of the second transistor, a gate of the fourth transistor
  • the pole is electrically connected to the first scan signal line to receive the first scan signal, the second pole of the second transistor is electrically connected to the first node
  • the first pole of the third transistor is electrically connected to the second power line
  • Receiving a second voltage, a gate of the third transistor is electrically connected to a control signal line to receive a control signal, a second pole of the third transistor is electrically connected to a second node; and a first pole of the fourth transistor Electrically connected to the second node
  • the second power line is grounded.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all P-type transistors.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all thin film transistors.
  • the compensation pixel circuit provided by the embodiment of the present disclosure further includes a compensation controller, wherein the compensation controller is configured to receive a gate voltage of the driving transistor collected by the signal acquisition circuit.
  • the compensation controller is further configured to: receive the illuminating data signal received by the compensation driving circuit, and subtract the compensation driving circuit by using a gate voltage of the driving transistor A illuminating voltage in the received illuminating data signal to obtain a threshold voltage of the driving transistor.
  • Embodiments of the present disclosure also provide a display panel including the compensation pixel circuit provided by any of the embodiments of the present disclosure.
  • a display panel provided by an embodiment of the present disclosure includes a plurality of compensation regions, wherein each of the compensation regions includes at least one of the compensation pixel circuits.
  • each of the compensation regions further includes a non- Compensating the pixel circuit, the sub-pixel region occupied by the pair of non-compensating pixel circuits and the sub-pixel region occupied by the compensation pixel circuit are adjacent to each other.
  • the display panel provided by the embodiment of the present disclosure further includes a compensation controller, wherein the compensation controller is configured to receive a gate voltage of the driving transistor collected by the signal acquisition circuit, and according to the driving transistor The gate voltage compensates for the uncompensated pixel circuit.
  • the compensation controller is further configured to: receive the illuminating data signal received by the compensation driving circuit, and subtract the compensation driving by using a gate voltage of the driving transistor a illuminating voltage in the illuminating data signal received by the circuit to obtain a threshold voltage of the driving transistor, receiving an illuminating data signal of the uncompensated pixel circuit, and adding a illuminating voltage of the illuminating data signal of the uncompensated pixel circuit And a threshold voltage to obtain an emission voltage of the updated illumination data signal of the non-compensated pixel circuit, and to transmit the illumination voltage of the updated illumination data signal to the non-compensated pixel circuit.
  • each of the compensation regions includes one compensation pixel circuit and eight non-compensation pixel circuits, and the non-compensation pixel circuit is disposed around the compensation pixel circuit.
  • An embodiment of the present disclosure further provides a display device including the display panel provided by any embodiment of the present disclosure.
  • An embodiment of the present disclosure further provides a region compensation method, comprising: receiving a gate voltage of a driving transistor collected by a signal acquisition circuit in a compensation pixel circuit; and compensating for a non-compensating pixel circuit according to a gate voltage of the driving transistor.
  • the compensating the non-compensated pixel circuit according to the gate voltage of the driving transistor includes: receiving the illuminating data signal received by the compensation driving circuit; using the gate of the driving transistor Substituting a voltage of the illuminating data signal received by the compensation driving circuit to obtain a threshold voltage of the compensation driving transistor; receiving an illuminating data signal of the non-compensating pixel circuit; and illuminating with the non-compensating pixel circuit An illuminating voltage of the data signal is added to the threshold voltage to obtain an illuminating voltage of the updated illuminating data signal of the uncompensated pixel circuit; and a illuminating voltage of the updated illuminating data signal is transmitted to the uncompensated pixel circuit.
  • An embodiment of the present disclosure further provides a method for driving a compensation pixel circuit provided by any one of the embodiments of the present disclosure, including: a reset period, a compensation period, and an illumination period, where
  • control signal is set to a turn-off voltage
  • first scan signal is set to a turn-off voltage
  • second scan signal is set to an turn-on voltage
  • a preparation period is further included, in which the setting control signal is a shutdown voltage, the first scan signal is set as a shutdown voltage, and the second scan is set.
  • the signal is the off voltage.
  • FIG. 1(a) is a schematic diagram of a compensation pixel circuit according to an embodiment of the present disclosure
  • FIG. 1(b) is a schematic diagram of still another compensation pixel circuit according to an embodiment of the present disclosure
  • FIG. 2(a) is a schematic diagram of still another compensation pixel circuit according to an embodiment of the present disclosure
  • FIG. 2(b) is a schematic diagram of a signal acquisition circuit in a compensation pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a driving timing diagram of the compensation pixel circuit shown in FIG. 2( a ) according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of an example of a compensation area in a display panel according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a non-compensated pixel circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a region compensation method according to an embodiment of the present disclosure.
  • FIG. 9 is a flowchart of an example of step S20 in the area compensation method shown in FIG. 8 according to an embodiment of the present disclosure.
  • Figure 10 (a) and Figure 10 (b) show a 4T2C compensation drive circuit and 4T1C compensation, respectively. Pay drive circuit.
  • OLED display panels typically employ an active drive approach that includes a plurality of sub-pixels arranged in an array.
  • the most basic pixel circuit of each sub-pixel is 2T1C (ie, including two transistors (scanning transistor and driving transistor) and one storage capacitor) mode, for example, see the 2T1C pixel circuit shown in FIG.
  • the pixel circuit of each sub-pixel can be obtained on the basis of the above 2T1C mode to obtain a pixel circuit with a compensation function.
  • Such a pixel circuit can be referred to as a compensation pixel circuit, based on the compensation principle.
  • the compensation pixel circuit can include three types of voltage compensation, current compensation, and hybrid compensation.
  • the OLED display panel using the compensation pixel circuit can obtain better brightness uniformity, but the panel area occupied by the driving circuit portion of each sub-pixel is increased, which is disadvantageous for obtaining a high-resolution OLED display. panel.
  • Embodiments of the present disclosure provide a compensation pixel circuit, a display panel, a display device, a region compensation method, and a driving method, by compensating a gate voltage of a driving transistor in a pixel circuit, and compensating a peripheral non-compensating pixel circuit according to the voltage, Thereby threshold voltage compensation is achieved.
  • This arrangement reduces the number of compensation drive circuits and compresses the area of the panel occupied by the drive circuit, thereby helping to increase the physical resolution of the display panel.
  • FIG. 1(a) is a schematic diagram of a compensation pixel circuit provided by an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a compensation pixel circuit 100.
  • the compensation pixel circuit 100 includes a compensation driving circuit 110 and a signal acquisition circuit 120 connected to the compensation driving circuit 110.
  • the compensation driving circuit 110 includes a driving transistor DT and an organic light emitting diode OLED; the compensation driving circuit 110 is configured to receive the light emitting data signal Data, compensate the threshold voltage of the driving transistor DT, and drive the organic light emitting diode OLED to emit light according to the light emitting data signal Data.
  • the signal acquisition circuit 120 is configured to collect the gate voltage of the drive transistor DT.
  • FIG. 1(b) is a schematic diagram of still another compensation pixel circuit provided by an embodiment of the present disclosure.
  • the compensation pixel circuit 100 may further include a compensation controller 130 configured to receive the gate voltage of the driving transistor DT collected by the signal acquisition circuit 120 in the compensation pixel circuit 100, and compensate the non-gate voltage according to the gate voltage of the driving transistor DT Compensate the pixel circuit. See below for a description of the uncompensated pixel circuit.
  • the compensation controller 130 is further configured to: receive the illuminating data signal Data received by the compensation driving circuit 110; subtract the gate voltage (Vdata+Vth) of the driving transistor DT Compensating the illuminating voltage Vdata in the illuminating data signal Data received by the driving circuit 110 to acquire the threshold voltage Vth of the driving transistor DT; receiving the illuminating data signal Data1 of the uncompensated pixel circuit; illuminating the voltage Vdata1 of the illuminating data signal Data1 using the non-compensating pixel circuit The previously acquired threshold voltage Vth is added to obtain the illuminating voltage Vdata1+Vth of the updated illuminating data signal of the uncompensated pixel circuit; and the illuminating voltage Vdata1+Vth of the updated illuminating data signal is transmitted to the non-compensating pixel circuit.
  • the threshold voltage of the driving transistor in the peripheral uncompensated pixel circuit is compensated by the threshold voltage of the driving transistor in the peripheral uncompensated pixel circuit.
  • FIG. 2(a) is a schematic diagram of still another compensation pixel circuit provided by an embodiment of the present disclosure.
  • the signal acquisition circuit 120 is electrically connected to the gate of the driving transistor DT, so that the gate of the driving transistor DT can be collected. Extreme voltage.
  • the compensation driving circuit 110 further includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.
  • the first electrode of the first transistor T1 is electrically connected to the first power line to receive the first voltage Vdd; the first transistor T1 The gate of the fifth transistor T5 is electrically connected to the second scan signal line to receive the second scan signal Scan2; the second electrode of the first transistor T1 is electrically connected to the first node N1.
  • the first pole of the second transistor T2 is electrically connected to the light-emitting data signal line to receive the light-emitting data signal Data; the gate of the second transistor T2, the gate of the fourth transistor T4 is electrically connected to the first scan signal line to receive the first scan The signal Scan1; the second pole of the second transistor T2 is electrically connected to the first node N1.
  • the first pole of the third transistor T3 is electrically connected to the second power line to receive the second voltage Vint; the gate of the third transistor T3 is electrically connected to the control signal line to receive the control signal Em; the second pole of the third transistor T3
  • the second node N2 is electrically connected.
  • the first pole of the fourth transistor T4 is electrically connected to the second node N2; the second pole of the fourth transistor T4 is electrically connected to the third node N3.
  • the first pole of the fifth transistor T5 is electrically connected to the third node N3; the second pole of the fifth transistor T5 is electrically connected to the first pole (eg, the anode) of the organic light emitting diode OLED.
  • the second pole (eg, cathode) of the organic light emitting diode OLED is grounded.
  • the first electrode of the driving transistor DT is electrically connected to the first node N1; the gate of the driving transistor DT is electrically connected to the second node N2; and the second electrode of the driving transistor DT is electrically connected to the third node N3.
  • the first end of the storage capacitor C is electrically connected to the second power line; the second end of the storage capacitor C is electrically connected to the second node N2.
  • the compensation driving circuit in the pixel circuit 100 shown in FIG. 2( a ) is simple in structure, convenient in fabrication, stable in operation, and better in achieving threshold voltage compensation of the driving transistor.
  • the compensation driving circuit in the compensation pixel circuit 100 shown in FIG. 2(a) is only an example.
  • the compensation driving circuit in the pixel circuit 100 may also be other compensation driving circuits having a function of compensating for the threshold voltage of the driving transistor DT and driving the function of the organic light emitting diode OLED according to the lighting data signal Data.
  • the compensation drive circuit may also be a circuit as shown in Figure 10(a) or as shown in Figure 10(b).
  • the basic principle is the first driving transistor M 2 is turned off, and diode-connected, the latter is in the ON state, charging the storage capacitor C st, until the drive transistor The gate voltage reaches a threshold voltage and is turned off, thereby storing the threshold voltage on the storage capacitor C st .
  • the first transistor M 1 is turned on, the charge storage capacitor C st, the transistor M 2 is turned on, the diode-connected structure M 3, to complete the driver circuit I
  • the second power line is grounded. That is, the second voltage Vint is a ground voltage (for example, 0 V).
  • embodiments of the present disclosure include, but are not limited to, the case where the second voltage is a ground voltage, and the second voltage may also be a stable low voltage, such as 1V.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all P-type transistors.
  • the process flow can be unified to facilitate product production.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all thin film transistors.
  • the transistor may be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the first pole of the transistor of the embodiment of the present disclosure may be a source, and the second pole may be a drain; or the first extreme drain of the transistor and the second source of the second.
  • the transistor can be divided into N-type and P-type transistors according to the characteristics of the transistor.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all P-type transistors. The example is explained. Based on the description and teachings of the implementation of the present disclosure, those skilled in the art can easily realize the implementation of the N-type transistor or the combination of the N-type and P-type transistors in the embodiments of the present disclosure without making creative efforts. These implementations are also within the scope of the present disclosure.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all P-type transistors, and the compensation driving circuit can be conveniently implemented, which is convenient for fabrication, and the signal setting is simple. single.
  • the signal acquisition circuit can be implemented by an analog to digital converter (A/D), and the function of the analog to digital converter is to continuously measure the time and the amplitude. Converted to digital signals with discrete time and discrete amplitudes.
  • A/D analog to digital converter
  • the signal acquisition circuit is disposed on the display panel and can be implemented by an integrated circuit chip.
  • FIG. 2(b) is a schematic diagram of a signal acquisition circuit in a compensation pixel circuit according to an embodiment of the present disclosure.
  • the signal acquisition circuit shown in Figure 2(b) is implemented using a successive approximation analog-to-digital converter.
  • the signal acquisition circuit in the compensation pixel circuit is not limited to the case shown in FIG. 2(b), and may be implemented by other circuits having a voltage acquisition function.
  • the compensation driving circuit 110 is connected to the "-" terminal of the comparator in the signal acquisition circuit, and the compensation controller 130 is connected to the buffer register in the signal acquisition circuit to realize the signal acquisition function. .
  • the turn-on voltage in the embodiment of the present disclosure refers to a voltage that enables the first and second stages of the respective transistors to be turned on
  • the turn-off voltage refers to a voltage that can turn off the first and second stages of the respective transistors.
  • the turn-on voltage is a low voltage (for example, 0V)
  • the turn-off voltage is a high voltage (for example, 5V)
  • the turn-on voltage is a high voltage (for example, 5V)
  • the voltage is a low voltage (eg, 0V).
  • the driving waveforms shown in FIG. 3 are all described by taking a P-type transistor as an example, that is, the turn-on voltage is a low voltage (for example, 0 V), and the turn-off voltage is a high voltage (for example, 5 V).
  • FIG. 3 is a driving timing diagram of the compensation pixel circuit shown in FIG. 2(a) according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure also provide a method of driving a compensation pixel circuit provided by any of the embodiments of the present disclosure. The driving process and the working process of the compensation pixel circuit will be described below with reference to FIG. 2(a) and FIG.
  • the control signal Em is the off voltage
  • the first scan signal Scan1 is the off voltage
  • the second scan signal Scan2 is the off voltage. Therefore, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all in a closed state.
  • the preparation period can provide a stable process for the compensation pixel circuit to prevent the circuit from being abnormal due to incomplete discharge of parasitic capacitance.
  • the control signal Em is an on voltage
  • the first scan signal Scan1 is a turn-off voltage
  • the second scan signal Scan2 is a turn-off voltage. Therefore, the third transistor T3 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are all in a closed state.
  • the voltage across the storage capacitor C is initialized to a second voltage Vint (eg, the second voltage Vint can be a stable low voltage or ground voltage), enabling initialization of the compensation pixel circuit.
  • the control signal Em is a turn-off voltage
  • the first scan signal Scan1 is an on voltage
  • the second scan signal Scan2 is a turn-off voltage. Therefore, the second transistor T2 and the fourth transistor T4 are turned on, and the first transistor T1, the third transistor T3, and the fifth transistor T5 are both in a closed state.
  • the illuminating data signal Data charges the second node N2 through the second transistor T2, the driving transistor DT and the fourth transistor T4 until the voltage of the second node N2 is Vdata+Vth, where Vdata is the illuminating voltage of the illuminating data signal Data, Vth is the threshold voltage of the driving transistor DT because the voltage difference between the gate and the source of the driving transistor DT is satisfied at this time as Vth. After the charging is completed, the voltage difference across the storage capacitor C is Vdata+Vth.
  • the fifth transistor T5 since the fifth transistor T5 is in a closed state, the current does not pass through the OLED, and the OLED is prevented from emitting light during this period, thereby improving the display effect and reducing the loss of the OLED.
  • the signal collecting circuit 120 collects the gate voltage (Vdata+Vth) of the driving transistor DT at this time, and is used to compensate the non-compensating pixel circuit around the compensation pixel circuit.
  • the control signal Em is a turn-off voltage
  • the first scan signal Scan1 is a turn-off voltage
  • the second scan signal Scan2 is an turn-on voltage. Therefore, the first transistor T1 and the fifth transistor T5 are turned on, and the second transistor T2, the third transistor T3, and the fourth transistor T4 are both turned off.
  • the voltage of the third node N3 is maintained at Vdata+Vth, and the illuminating current IOLED flows through the first transistor T1, the driving transistor DT, the fifth transistor T5, and the organic light emitting diode OLED, and organic light is emitted.
  • the diode OLED emits light.
  • the illuminating current IOLED satisfies the following saturation current formula:
  • ⁇ n is the channel mobility of the driving transistor
  • Cox is the channel capacitance per unit area of the driving transistor
  • W and L are the channel width and channel length of the driving transistor, respectively
  • VGS is the gate-source voltage of the driving transistor (driving transistor The difference between the gate voltage and the source voltage).
  • the illuminating current IOLED has not been affected by the threshold voltage Vth of the driving transistor, and is only related to the voltage Vdata of the illuminating data signal and the first voltage Vdd.
  • the problem of threshold voltage drift of the driving transistor is solved, and the normal operation of the OLED display panel is ensured.
  • the driving method provided by the embodiment of the present disclosure may include only the reset period t2, the compensation period t3, and the lighting period t4, and does not include the preparation period t1. There is no limit here.
  • FIG. 4 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a display panel 10, as shown in FIG. 4, which includes the compensation pixel circuit 100 provided by any embodiment of the present disclosure.
  • the display panel 10 provided by the embodiment of the present disclosure includes a plurality of compensation regions 11 each including at least one compensation pixel circuit 100.
  • each of the compensation regions 11 further includes a non-compensating pixel circuit 200, and the sub-pixel region occupied by the non-compensating pixel circuit 200 and the compensation pixel circuit 100 The occupied sub-pixel regions are adjacent to each other.
  • the compensation controller 130 may also be disposed in the display panel 10, and the compensation controller 130 is configured to receive the gate voltage of the driving transistor DT collected by the signal acquisition circuit 120 in the compensation pixel circuit 100, and The uncompensated pixel circuit 200 is compensated according to the gate voltage of the driving transistor DT (eg, compensates for the non-compensating pixel circuit 200 in the same compensation region).
  • the display panel 10 provided by the embodiment of the present disclosure further includes a scan driver 13, a data driver 14, a timing controller 15, an illumination data signal line, a first scan signal line, and a second scan signal line.
  • control signal lines light-emitting data signal lines, first scanning signal lines, second scanning signal lines, and control signal lines are not shown in FIG. 4).
  • the data driver 14 is configured to provide an illumination data signal to the compensation pixel circuit 100 and the non-compensation pixel circuit 200 through the illumination data signal line;
  • the scan driver 13 is configured to pass the first scan signal line, the second scan signal line, and the control signal line, respectively The first scan signal Scan1, the second scan signal Scan2, and the control signal Em are supplied to the compensation pixel circuit 100;
  • the timing controller 15 is configured to provide a clock signal to coordinate the operation of the system.
  • the compensation controller 130 is further configured to: receive the illuminating data signal Data received by the compensation driving circuit 110; subtract the gate voltage (Vdata+Vth) of the driving transistor DT Compensating the illuminating data signal Data received by the driving circuit 110
  • the illuminating voltage Vdata is obtained to obtain the threshold voltage Vth of the driving transistor DT; the illuminating data signal Data1 of the uncompensated pixel circuit 200 is received; the illuminating voltage Vdata1 of the illuminating data signal Data1 of the non-compensating pixel circuit 200 is added to the previously acquired threshold voltage Vth Acquiring the illuminating voltage Vdata1+Vth of the updated illuminating data signal of the uncompensated pixel circuit; and transmitting the illuminating voltage Vdata1+Vth of the updated illuminating data signal to the non-compensating pixel circuit.
  • the threshold voltage of the driving transistor in the peripheral uncompensated pixel circuit can be compensated by the threshold voltage of the driving transistor obtained from the compensation pixel circuit.
  • the threshold voltage is superimposed on the illuminating data signal of the non-compensating pixel circuit by the compensation controller to implement threshold voltage compensation.
  • the use of the compensation pixel circuit and the non-compensation pixel circuit can reduce the area occupied by the driver circuit portion in the pixel circuit, thereby improving the resolution of the display panel.
  • each compensation region 11 includes one compensation pixel circuit 100 and eight non-compensation pixel circuits 200, and the non-compensation pixel circuit 200 surrounds the compensation pixel circuit 100.
  • Settings for example, as shown in FIG. 4, in the display panel 10 provided by the embodiment of the present disclosure, each compensation region 11 includes one compensation pixel circuit 100 and eight non-compensation pixel circuits 200, and the non-compensation pixel circuit 200 surrounds the compensation pixel circuit 100.
  • the setting of the compensation area 11 includes, but is not limited to, the situation shown in FIG. 4, and may also include other settings.
  • FIG. 5 is a schematic diagram of an example of a compensation area in a display panel according to an embodiment of the present disclosure.
  • the compensation region 11 includes a compensation pixel circuit 100 and twenty-four non-compensated pixel circuits 200. That is, the threshold voltage obtained from a compensated pixel circuit is used to compensate for the twenty-four uncompensated pixel circuits.
  • the setting of the compensation region 11 can be comprehensively selected according to factors such as the consistency of the threshold voltage of the driving transistor, the area occupied by the pixel circuit, and the like.
  • the compensation region can be set larger, that is, a threshold voltage obtained in the compensation pixel circuit can be used to compensate for a larger number of non-compensating pixel circuits in the periphery.
  • FIG. 6 is a schematic diagram of a non-compensated pixel circuit provided by an embodiment of the present disclosure.
  • the uncompensated pixel circuit 200 is 2T1C (i.e., includes two transistors (scanning transistor ST and driving transistor DT') and a storage capacitor C') circuit.
  • the uncompensated pixel circuit 200 does not have a threshold compensation function Can, but occupy a small area, used in conjunction with the compensation pixel circuit to improve the resolution of the display panel.
  • the uncompensated pixel circuit shown in FIG. 7 is only an example, and embodiments of the present disclosure include but are not limited thereto.
  • FIG. 7 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a display device 1.
  • the display device 1 includes the display panel 10 provided by any embodiment of the present disclosure.
  • the display device may include any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • FIG. 8 is a flowchart of a region compensation method according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure also provide a region compensation method, as shown in FIG. 8, the method includes the following steps.
  • Step S10 receiving a gate voltage of a driving transistor collected by the signal collecting circuit in the compensation pixel circuit
  • Step S20 Compensating the uncompensated pixel circuit according to the gate voltage of the driving transistor.
  • FIG. 9 is a flowchart of an example of step S20 in the area compensation method shown in FIG. 8 according to an embodiment of the present disclosure.
  • the compensation of the uncompensated pixel circuit according to the gate voltage of the driving transistor ie, the above step S20 further includes the following steps.
  • Step S21 receiving the illuminating data signal received by the compensation driving circuit
  • Step S22 subtracting the illuminating voltage in the illuminating data signal received by the driving circuit by using the gate voltage of the driving transistor to obtain a threshold voltage for compensating the driving transistor;
  • Step S23 receiving an illumination data signal of the uncompensated pixel circuit
  • Step S24 adding a threshold voltage by using a light-emitting voltage of the light-emitting data signal of the non-compensating pixel circuit to obtain a light-emitting voltage of the updated light-emitting data signal of the non-compensating pixel circuit;
  • Step S25 transmitting a lighting voltage for updating the illuminating data signal to the non-compensating pixel circuit.
  • step S22 and step S23 can be exchanged with each other.
  • Embodiments of the present disclosure provide a compensation pixel circuit, a display panel, a display device, a region compensation method, and a driving method, by compensating a gate voltage of a driving transistor in a pixel circuit, and compensating a peripheral non-compensating pixel circuit according to the voltage, Thereby threshold voltage compensation is achieved.
  • This setting is reduced
  • the number of compensation drive circuits is reduced, and the panel area occupied by the drive circuit is compressed, thereby contributing to the improvement of the physical resolution of the display panel.

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Abstract

一种补偿像素电路、显示面板、显示设备、区域补偿方法及驱动方法，该补偿像素电路(100)包括补偿驱动电路(110)和与所述补偿驱动电路(110)连接的信号采集电路(120)。补偿驱动电路(110)包括驱动晶体管和有机发光二极管，其中，所述补偿驱动电路(110)被配置为接收发光数据信号、补偿所述驱动晶体管的阈值电压以及根据所述发光数据信号驱动所述有机发光二极管发光；信号采集电路(120)被配置为采集所述驱动晶体管的栅极电压。通过采集补偿像素电路中驱动晶体管的栅极电压，并根据该电压补偿周边的非补偿像素电路，从而实现阈值电压补偿。这种设置减少了补偿驱动电路的数量，压缩了驱动电路占用的面板区域，从而有助于提高显示面板的物理分辨率。

Description

补偿像素电路、显示面板、显示设备、补偿及驱动方法 技术领域
本公开的实施例涉及一种补偿像素电路、显示面板、显示设备、区域补偿方法及驱动方法。
背景技术
在显示领域，有机发光二极管(OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。
由于上述特点，有机发光二极管(OLED)显示面板可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
发明内容
本公开的实施例提供一种补偿像素电路，包括：补偿驱动电路，包括驱动晶体管和有机发光二极管，其中，所述补偿驱动电路被配置为接收发光数据信号、补偿所述驱动晶体管的阈值电压以及根据所述发光数据信号驱动所述有机发光二极管发光；与所述补偿驱动电路连接的信号采集电路，被配置为采集所述驱动晶体管的栅极电压。
例如，在本公开实施例提供的补偿像素电路中，所述信号采集电路与所述驱动晶体管的栅极电连接。
例如，在本公开实施例提供的补偿像素电路中，所述补偿驱动电路还包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和存储电容。
例如，在本公开实施例提供的补偿像素电路中，所述第一晶体管的第一极与第一电源线电连接以接收第一电压，所述第一晶体管的栅极、所述第五晶体管的栅极与第二扫描信号线电连接以接收第二扫描信号，所述第一晶体管的第二极与第一节点电连接；所述第二晶体管的第一极与发光数据信号线电连接以接收发光数据信号，所述第二晶体管的栅极、所述第四晶体管的栅 极与第一扫描信号线电连接以接收第一扫描信号，所述第二晶体管的第二极与所述第一节点电连接；所述第三晶体管的第一极与第二电源线电连接以接收第二电压，所述第三晶体管的栅极与控制信号线电连接以接收控制信号，所述第三晶体管的第二极与第二节点电连接；所述第四晶体管的第一极与所述第二节点电连接，所述第四晶体管的第二极与第三节点电连接；所述第五晶体管的第一极与所述第三节点电连接，所述第五晶体管的第二极与所述有机发光二极管的第一极电连接；所述有机发光二极管的第二极接地；所述驱动晶体管的第一极与所述第一节点电连接，所述驱动晶体管的栅极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接；所述存储电容的第一端与所述第二电源线电连接，所述存储电容的第二端与所述第二节点电连接。
例如，在本公开实施例提供的补偿像素电路中，所述第二电源线接地。
例如，在本公开实施例提供的补偿像素电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管均为P型晶体管。
例如，在本公开实施例提供的补偿像素电路中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管均为薄膜晶体管。
例如，本公开实施例提供的补偿像素电路，还包括补偿控制器，其中，所述补偿控制器被配置为接收所述信号采集电路采集的所述驱动晶体管的栅极电压。
例如，本公开实施例提供的补偿像素电路，所述补偿控制器还被配置为：接收所述补偿驱动电路接收的发光数据信号，用所述驱动晶体管的栅极电压减去所述补偿驱动电路接收的发光数据信号中的发光电压以获取所述驱动晶体管的阈值电压。
本公开的实施例还提供一种显示面板，包括本公开任一实施例提供的补偿像素电路。
例如，本公开实施例提供的显示面板，包括多个补偿区域，其中，每个所述补偿区域包括至少一个所述补偿像素电路。
例如，在本公开实施例提供的显示面板中，每个所述补偿区域还包括非 补偿像素电路，所述非补偿像素电路所对占据的亚像素区域与所述补偿像素电路所占据的亚像素区域彼此相邻。
例如，本公开实施例提供的显示面板，还包括补偿控制器，其中，所述补偿控制器被配置为接收所述信号采集电路采集的所述驱动晶体管的栅极电压，并根据所述驱动晶体管的栅极电压补偿所述非补偿像素电路。
例如，在本公开实施例提供的显示面板中，所述补偿控制器还被配置为：接收所述补偿驱动电路接收的发光数据信号，用所述驱动晶体管的栅极电压减去所述补偿驱动电路接收的发光数据信号中的发光电压以获取所述驱动晶体管的阈值电压，接收所述非补偿像素电路的发光数据信号，用所述非补偿像素电路的发光数据信号的发光电压加上所述阈值电压以获取所述非补偿像素电路的更新发光数据信号的发光电压，以及向所述非补偿像素电路发送所述更新发光数据信号的发光电压。
例如，在本公开实施例提供的显示面板中，每个所述补偿区域包括一个补偿像素电路和八个非补偿像素电路，所述非补偿像素电路围绕所述补偿像素电路设置。
本公开的实施例还提供一种显示设备，包括本公开任一实施例提供的显示面板。
本公开的实施例还提供一种区域补偿方法，包括：接收补偿像素电路中信号采集电路采集的驱动晶体管的栅极电压；根据所述驱动晶体管的栅极电压补偿非补偿像素电路。
例如，在本公开实施例提供的区域补偿方法中，根据所述驱动晶体管的栅极电压补偿所述非补偿像素电路包括：接收补偿驱动电路接收的发光数据信号；用所述驱动晶体管的栅极电压减去所述补偿驱动电路接收的发光数据信号中的发光电压，以获取所述补偿驱动晶体管的阈值电压；接收所述非补偿像素电路的发光数据信号；用所述非补偿像素电路的发光数据信号的发光电压加上所述阈值电压，以获取所述非补偿像素电路的更新发光数据信号的发光电压；以及向所述非补偿像素电路发送所述更新发光数据信号的发光电压。
本公开的实施例还提供一种驱动本公开任一实施例提供的补偿像素电路的方法，包括：复位时段、补偿时段及发光时段，其中，
在所述复位时段，设置控制信号为开启电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压；
在所述补偿时段，设置控制信号为关闭电压，设置第一扫描信号为开启电压，设置第二扫描信号为关闭电压；
在所述发光时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为开启电压。
例如，在本公开实施例提供的驱动方法中，在所述复位时段之前还包括准备时段，在所述准备时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1(a)是本公开实施例提供的一种补偿像素电路的示意图；
图1(b)是本公开实施例提供的又一种补偿像素电路的示意图；
图2(a)是本公开实施例提供的又一种补偿像素电路的示意图；
图2(b)是本公开实施例提供的一种补偿像素电路中信号采集电路的示意图；
图3是本公开实施例提供的如图2(a)所示的补偿像素电路的驱动时序图；
图4是本公开实施例提供的一种显示面板的示意图；
图5是本公开实施例提供的一种显示面板中补偿区域一个示例的示意图；
图6是本公开实施例提供的一种非补偿像素电路的示意图；
图7是本公开实施例提供的一种显示设备的示意图；
图8是本公开实施例提供的一种区域补偿方法的流程图；
图9是本公开实施例提供的如图8所示的区域补偿方法中步骤S20的一个示例的流程图；以及
图10(a)和图10(b)分别示出了一种4T2C补偿驱动电路和4T1C补 偿驱动电路。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
近年来，随着增强现实、虚拟现实等消费电子产品的崛起，为提高用户观看体验，人们对高分辨率显示面板的需求越来越迫切。
在OLED显示面板中，分辨率主要受制于光刻工艺水平和高精度金属掩模板(Fine Metal Mask，FFM)的尺寸。在光刻工艺水平和高精度金属掩模板的制造水平达到一定程度的情况下，OLED显示面板的分辨率很难提高。因此，需要另辟蹊径以应对高分辨率的问题。
OLED显示面板通常采用有源驱动方式，包括多个排列为阵列的子像素。每个子像素最基本的像素电路为2T1C(即包括两个晶体管(扫描晶体管与驱动晶体管)以及一个存储电容)模式，例如参见图6示出的2T1C像素电路。为了改善整个面板的显示均一性，则可以使得每个子像素的像素电路在上述2T1C的模式的基础上来得到具有补偿功能的像素电路，这种像素电路可以被称为补偿像素电路，基于补偿原理，补偿像素电路可以包括电压补偿、电流补偿和混合补偿三种。然而，相比于基本的2T1C像素电路，采用补偿像素电路的OLED显示面板能够获得更好的亮度均一性，但是每个子像素的驱动电路部分占据的面板区域增加，不利于获得高分辨率OLED显示面板。
本公开的实施例提供一种补偿像素电路、显示面板、显示设备、区域补偿方法及驱动方法，通过采集补偿像素电路中驱动晶体管的栅极电压，并根据该电压补偿周边的非补偿像素电路，从而实现阈值电压补偿。这种设置减少了补偿驱动电路的数量，压缩了驱动电路占用的面板区域，从而有助于提高显示面板的物理分辨率。
例如，图1(a)是本公开实施例提供的一种补偿像素电路的示意图。本公开的实施例提供一种补偿像素电路100，如图1(a)所示，补偿像素电路100包括补偿驱动电路110以及与补偿驱动电路110连接的信号采集电路120。补偿驱动电路110包括驱动晶体管DT和有机发光二极管OLED；补偿驱动电路110被配置为接收发光数据信号Data、补偿驱动晶体管DT的阈值电压以及根据发光数据信号Data驱动有机发光二极管OLED发光。信号采集电路120被配置为采集驱动晶体管DT的栅极电压。
例如，图1(b)是本公开实施例提供的又一种补偿像素电路的示意图。补偿像素电路100还可以包括补偿控制器130，补偿控制器130被配置为接收补偿像素电路100中信号采集电路120采集的驱动晶体管DT的栅极电压，并根据驱动晶体管DT的栅极电压补偿非补偿像素电路。关于非补偿像素电路的描述请参见下文。
例如，在本公开实施例提供的显示面板10中，补偿控制器130还被配置为：接收补偿驱动电路110接收的发光数据信号Data；用驱动晶体管DT的栅极电压(Vdata+Vth)减去补偿驱动电路110接收的发光数据信号Data中的发光电压Vdata以获取驱动晶体管DT的阈值电压Vth；接收非补偿像素电路的发光数据信号Data1；用非补偿像素电路的发光数据信号Data1的发光电压Vdata1加上之前获取的阈值电压Vth以获取非补偿像素电路的更新发光数据信号的发光电压Vdata1+Vth；以及向非补偿像素电路发送更新发光数据信号的发光电压Vdata1+Vth。这样，就实现了利用从补偿像素电路中获取的驱动晶体管的阈值电压来补偿周边非补偿像素电路中驱动晶体管的阈值电压。
例如，图2(a)是本公开实施例提供的又一种补偿像素电路的示意图。如图2(a)所示，在本公开实施例提供的补偿像素电路100中，信号采集电路120与驱动晶体管DT的栅极电连接，从而可以采集驱动晶体管DT的栅 极电压。
例如，如图2(a)所示，在本公开实施例提供的补偿像素电路100中，补偿驱动电路110还包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和存储电容C。
例如，如图2(a)所示，在本公开实施例提供的补偿像素电路100中，第一晶体管T1的第一极与第一电源线电连接以接收第一电压Vdd；第一晶体管T1的栅极、第五晶体管T5的栅极与第二扫描信号线电连接以接收第二扫描信号Scan2；第一晶体管T1的第二极与第一节点N1电连接。第二晶体管T2的第一极与发光数据信号线电连接以接收发光数据信号Data；第二晶体管T2的栅极、第四晶体管T4的栅极与第一扫描信号线电连接以接收第一扫描信号Scan1；第二晶体管T2的第二极与第一节点N1电连接。第三晶体管T3的第一极与第二电源线电连接以接收第二电压Vint；第三晶体管T3的栅极与控制信号线电连接以接收控制信号Em；第三晶体管T3的第二极与第二节点N2电连接。第四晶体管T4的第一极与第二节点N2电连接；第四晶体管T4的第二极与第三节点N3电连接。第五晶体管T5的第一极与第三节点N3电连接；第五晶体管T5的第二极与有机发光二极管OLED的第一极(例如，阳极)电连接。有机发光二极管OLED的第二极(例如，阴极)接地。驱动晶体管DT的第一极与第一节点N1电连接；驱动晶体管DT的栅极与第二节点N2电连接；驱动晶体管DT的第二极与第三节点N3电连接。存储电容C的第一端与第二电源线电连接；存储电容C的第二端与第二节点N2电连接。
例如，图2(a)所示的像素电路100中的补偿驱动电路结构简单、制作方便、工作稳定、较好地实现了驱动晶体管的阈值电压补偿。
例如，如上所述，图2(a)所示的补偿像素电路100中的补偿驱动电路仅为一个示例。在本公开的一个实施例中，像素电路100中的补偿驱动电路也可以是其它具有补偿驱动晶体管DT阈值电压功能以及根据发光数据信号Data驱动有机发光二极管OLED发光功能的其它补偿驱动电路。例如，参见图10(a)和图10(b)，补偿驱动电路也可以为如图10(a)所示的或如图10(b)所示的电路。例如，对于如图10(a)所示的4T2C电路，其基本原理是先将驱动晶体管M2截止，然后接成二极管，后者处于导通状态，对存 储电容Cst充电，直至驱动晶体管的栅极电压达到阈值电压而截止，从而将该阈值电压存储在存储电容Cst上。例如，如图10(b)所示的4T1C电路，先将晶体管M1导通，对存储电容Cst充电，使晶体管M2导通，将M3连接成二极管结构，以完成将驱动电路IDATA转换成存储在存储电容Cst上的电压的过程。
例如，在本公开实施例提供的补偿像素电路100中，第二电源线接地。也就是说，第二电压Vint为接地电压(例如，0V)。
需要说明的是，本公开的实施例包括但不局限于第二电压为接地电压的情形，第二电压也可以为一个稳定的低电压，例如1V。
例如，在本公开实施例提供的补偿像素电路100中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5均为P型晶体管。例如，采用相同类型的晶体管可以统一制作工艺流程，便于产品生产。
例如，在本公开实施例提供的补偿像素电路100中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5均为薄膜晶体管。
需要说明的是，在本公开的一个实施例中，晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管，本公开的实施例以第一晶体管、第二晶体管、第三晶体管、第四晶体管和第五晶体管均为P型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到本公开实施例采用N型晶体管或N型和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
例如，第一晶体管、第二晶体管、第三晶体管、第四晶体管和第五晶体管均为P型晶体管可以方便地实现补偿驱动电路，便于制作，且信号设置简 单。
例如，在本公开的一个实施例中，信号采集电路可以通过模数转换器(analog to digital converter，A/D)实现，模数转换器的作用是将时间连续、幅值也连续的模拟量转换为时间离散、幅值也离散的数字信号。
例如，信号采集电路设置在显示面板上，可以通过集成电路芯片实现。
例如，图2(b)是本公开实施例提供的一种补偿像素电路中信号采集电路的示意图。图2(b)中所示的信号采集电路采用逐次逼近式的模数转换器实现。
需要说明的是，在本公开的一个实施例中，补偿像素电路中的信号采集电路不局限于图2(b)中所示的情形，还可以采用其它具有电压采集功能的电路实现。
例如，如图2(b)所示，补偿驱动电路110与信号采集电路中的比较器的“-”端连接，补偿控制器130与信号采集电路中的缓冲寄存器连接，即可实现信号采集功能。
例如，本公开实施例中的开启电压是指能使相应晶体管第一极和第二级导通的电压，关闭电压是指能使相应晶体管的第一极和第二级断开的电压。当晶体管为P型晶体管时，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)；当晶体管为N型晶体管时，开启电压为高电压(例如，5V)，关闭电压为低电压(例如，0V)。图3所示的驱动波形均以P型晶体管为例进行说明，即开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)。
例如，图3是本公开实施例提供的如图2(a)所示的补偿像素电路的驱动时序图。本公开的实施例还提供一种驱动本公开任一实施例提供的补偿像素电路的方法。以下结合图2(a)和图3对该驱动方法及补偿像素电路的工作过程进行介绍。
在准备时段t1，控制信号Em为关闭电压，第一扫描信号Scan1为关闭电压，第二扫描信号Scan2为关闭电压。因此，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5均处于关闭状态。准备时段可以为补偿像素电路提供一个稳定的过程，防止电路因寄生电容放电不完全等影响导致的电路异常。
在复位时段t2，控制信号Em为开启电压，第一扫描信号Scan1为关闭电压，第二扫描信号Scan2为关闭电压。因此，第三晶体管T3导通，第一晶体管T1、第二晶体管T2、第四晶体管T4和第五晶体管T5均处于关闭状态。存储电容C两端的电压被初始化为第二电压Vint(例如，第二电压Vint可以为一个稳定的低电压或接地电压)，实现了补偿像素电路的初始化。
在补偿时段t3，控制信号Em为关闭电压，第一扫描信号Scan1为开启电压，第二扫描信号Scan2为关闭电压。因此，第二晶体管T2和第四晶体管T4导通，第一晶体管T1、第三晶体管T3和第五晶体管T5均处于关闭状态。发光数据信号Data通过第二晶体管T2、驱动晶体管DT和第四晶体管T4对第二节点N2充电，直到第二节点N2的电压为Vdata+Vth为止，其中，Vdata为发光数据信号Data的发光电压，Vth为驱动晶体管DT的阈值电压，因为此时满足驱动晶体管DT栅极和源极之间的电压差为Vth。充电完成后，存储电容C两端的电压差为Vdata+Vth。另外，由于第五晶体管T5处于关闭状态，使得电流不会通过OLED，避免OLED在此时段发光，提升了显示效果，降低了OLED的损耗。例如，在充电完成后、发光时段t4之前，信号采集电路120采集此时驱动晶体管DT的栅极电压(Vdata+Vth)，并用于补偿该补偿像素电路周边的非补偿像素电路。
在发光时段t4，控制信号Em为关闭电压，第一扫描信号Scan1为关闭电压，第二扫描信号Scan2为开启电压。因此，第一晶体管T1和第五晶体管T5导通，第二晶体管T2、第三晶体管T3和第四晶体管T4均处于关闭状态。在发光时段中，由于存储电容C的作用，第三节点N3的电压保持在Vdata+Vth，发光电流IOLED流经第一晶体管T1、驱动晶体管DT、第五晶体管T5和有机发光二极管OLED，有机发光二极管OLED发光。发光电流IOLED满足如下饱和电流公式：
IOLED＝K(VGS-Vth)2
＝K(Vdata+Vth-Vdd-Vth)2
＝K(Vdata-Vdd)2
其中，
Figure PCTCN2017076917-appb-000001
μn为驱动晶体管的沟道迁移率，Cox为驱动晶体管单位面积的沟道电容，W和L分别为驱动晶体管的沟道宽度和沟道长度， VGS为驱动晶体管的栅源电压(驱动晶体管的栅极电压与源极电压之差)。
由上式中可以看到发光电流IOLED已经不受驱动晶体管的阈值电压Vth的影响，只与发光数据信号的电压Vdata以及第一电压Vdd有关。解决了驱动晶体管阈值电压漂移的问题，保证了OLED显示面板的正常工作。
需要说明的是，本公开实施例提供的驱动方法可以仅包括复位时段t2、补偿时段t3及发光时段t4，而不包括准备时段t1。在此不做限定。
例如，图4是本公开实施例提供的一种显示面板的示意图。本公开的实施例还提供一种显示面板10，如图4所示，显示面板10包括本公开任一实施例提供的补偿像素电路100。
例如，本公开实施例提供的显示面板10，包括多个补偿区域11，每个补偿区域11包括至少一个补偿像素电路100。
例如，如图4所示，在本公开实施例提供的显示面板10中，每个补偿区域11还包括非补偿像素电路200，非补偿像素电路200所对占据的亚像素区域与补偿像素电路100所占据的亚像素区域彼此相邻。
例如，如图4所示，补偿控制器130也可以被设置在显示面板10中，补偿控制器130被配置为接收补偿像素电路100中信号采集电路120采集的驱动晶体管DT的栅极电压，并根据驱动晶体管DT的栅极电压补偿非补偿像素电路200(例如，补偿同一补偿区域中的非补偿像素电路200)。
例如，如图4所示，本公开的实施例提供的显示面板10，还包括扫描驱动器13、数据驱动器14、时序控制器15、发光数据信号线、第一扫描信号线、第二扫描信号线和控制信号线(发光数据信号线、第一扫描信号线、第二扫描信号线和控制信号线在图4中未示出)。数据驱动器14被配置为通过发光数据信号线向补偿像素电路100以及非补偿像素电路200提供发光数据信号；扫描驱动器13被配置为分别通过第一扫描信号线、第二扫描信号线和控制信号线向补偿像素电路100提供第一扫描信号Scan1、第二扫描信号Scan2和控制信号Em；时序控制器15配置为提供时钟信号，从而协调系统的工作。
例如，在本公开实施例提供的显示面板10中，补偿控制器130还被配置为：接收补偿驱动电路110接收的发光数据信号Data；用驱动晶体管DT的栅极电压(Vdata+Vth)减去补偿驱动电路110接收的发光数据信号Data中 的发光电压Vdata以获取驱动晶体管DT的阈值电压Vth；接收非补偿像素电路200的发光数据信号Data1；用非补偿像素电路200的发光数据信号Data1的发光电压Vdata1加上之前获取的阈值电压Vth以获取非补偿像素电路的更新发光数据信号的发光电压Vdata1+Vth；以及向非补偿像素电路发送更新发光数据信号的发光电压Vdata1+Vth。这样，就实现了利用从补偿像素电路中获取的驱动晶体管的阈值电压来补偿周边非补偿像素电路中驱动晶体管的阈值电压。
需要说明的是，由于显示面板中相近区域的工艺特性比较接近，相近区域的驱动晶体管的阈值电压及漂移特性也较为接近。因此，可以利用从补偿像素电路中获取的驱动晶体管的阈值电压来补偿周边非补偿像素电路中驱动晶体管的阈值电压。例如，通过补偿控制器把阈值电压叠加在非补偿像素电路的发光数据信号中，实现阈值电压补偿。同时，补偿像素电路和非补偿像素电路的配合使用可减小像素电路中驱动电路部分占用的面积，进而提高显示面板的分辨率。
例如，如图4所示，在本公开实施例提供的显示面板10中，每个补偿区域11包括一个补偿像素电路100和八个非补偿像素电路200，非补偿像素电路200围绕补偿像素电路100设置。
需要说明的是，补偿区域11的设置包括但不局限于图4所示的情形，也可以包括其他设置的情形。
例如，图5是本公开实施例提供的一种显示面板中补偿区域一个示例的示意图。如图5所示，补偿区域11中包括一个补偿像素电路100和二十四个非补偿像素电路200。也就是说，从一个补偿像素电路中获取的阈值电压用于补偿周边二十四个非补偿像素电路。
例如，补偿区域11的设置可以根据驱动晶体管阈值电压的一致性、像素电路需要占用的面积等因素综合选择。例如，当驱动晶体管阈值电压一致性较高时，补偿区域可以设置的更大，也就是说可以用一个补偿像素电路中获取的阈值电压用于补偿周边更多数量的非补偿像素电路。
例如，图6是本公开实施例提供的一种非补偿像素电路的示意图。非补偿像素电路200为2T1C(即包括两个晶体管(扫描晶体管ST与驱动晶体管DT’)以及一个存储电容C’)电路。非补偿像素电路200不具有阈值补偿功 能，但占用面积较小，与补偿像素电路配合使用以提高显示面板的分辨率。需要说明的是，图7所示的非补偿像素电路仅为一个示例，本公开的实施例包括但不仅限于此。
例如，图7是本公开实施例提供的一种显示设备的示意图。本公开的实施例还提供一种显示设备1，如图7所示，显示设备1包括本公开任一实施例提供的显示面板10。
例如，本公开实施例提供的显示设备可以包括手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
例如，图8是本公开实施例提供的一种区域补偿方法的流程图。本公开的实施例还提供一种区域补偿方法，如图8所示，该方法包括如下步骤。
步骤S10：接收补偿像素电路中信号采集电路采集的驱动晶体管的栅极电压；
步骤S20：根据驱动晶体管的栅极电压补偿非补偿像素电路。
例如，图9是本公开实施例提供的如图8所示的区域补偿方法中步骤S20的一个示例的流程图。如图9所示，在本公开实施例提供的区域补偿方法中，根据驱动晶体管的栅极电压补偿非补偿像素电路(即上述步骤S20)进一步包括如下步骤。
步骤S21：接收补偿驱动电路接收的发光数据信号；
步骤S22：用驱动晶体管的栅极电压减去补偿驱动电路接收的发光数据信号中的发光电压，以获取补偿驱动晶体管的阈值电压；
步骤S23：接收非补偿像素电路的发光数据信号；
步骤S24：用非补偿像素电路的发光数据信号的发光电压加上阈值电压，以获取非补偿像素电路的更新发光数据信号的发光电压；以及
步骤S25：向非补偿像素电路发送更新发光数据信号的发光电压。
例如，上述步骤的顺序仅为本公开实施例的一个示例，而非对本公开的限制，在不影响本公开提供的区域补偿方法实现的情况下，某些步骤的顺序可以调换。例如，步骤S22和步骤S23的顺序可以相互交换。
本公开的实施例提供一种补偿像素电路、显示面板、显示设备、区域补偿方法及驱动方法，通过采集补偿像素电路中驱动晶体管的栅极电压，并根据该电压补偿周边的非补偿像素电路，从而实现阈值电压补偿。这种设置减 少了补偿驱动电路的数量，压缩了驱动电路占用的面板区域，从而有助于提高显示面板的物理分辨率。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
本专利申请要求于2016年8月12日递交的中国专利申请第201610664473.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种补偿像素电路，包括：
    补偿驱动电路，包括驱动晶体管和有机发光二极管，其中，所述补偿驱动电路被配置为接收发光数据信号、补偿所述驱动晶体管的阈值电压以及根据所述发光数据信号驱动所述有机发光二极管发光；
    与所述补偿驱动电路连接的信号采集电路，被配置为采集所述驱动晶体管的栅极电压。
  2. 根据权利要求1所述的补偿像素电路，其中，所述信号采集电路与所述驱动晶体管的栅极电连接。
  3. 根据权利要求1所述的补偿像素电路，其中，所述补偿驱动电路还包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和存储电容。
  4. 根据权利要求3所述的补偿像素电路，其中，
    所述第一晶体管的第一极与第一电源线电连接以接收第一电压，所述第一晶体管的栅极、所述第五晶体管的栅极与第二扫描信号线电连接以接收第二扫描信号，所述第一晶体管的第二极与第一节点电连接；
    所述第二晶体管的第一极与发光数据信号线电连接以接收发光数据信号，所述第二晶体管的栅极、所述第四晶体管的栅极与第一扫描信号线电连接以接收第一扫描信号，所述第二晶体管的第二极与所述第一节点电连接；
    所述第三晶体管的第一极与第二电源线电连接以接收第二电压，所述第三晶体管的栅极与控制信号线电连接以接收控制信号，所述第三晶体管的第二极与第二节点电连接；
    所述第四晶体管的第一极与所述第二节点电连接，所述第四晶体管的第二极与第三节点电连接；
    所述第五晶体管的第一极与所述第三节点电连接，所述第五晶体管的第二极与所述有机发光二极管的第一极电连接；
    所述有机发光二极管的第二极接地；
    所述驱动晶体管的第一极与所述第一节点电连接，所述驱动晶体管的栅极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接；
    所述存储电容的第一端与所述第二电源线电连接，所述存储电容的第二端与所述第二节点电连接。
  5. 根据权利要求4所述的补偿像素电路，其中，所述第二电源线接地。
  6. 根据权利要求3-5任一项所述的补偿像素电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管均为P型晶体管。
  7. 根据权利要求3-5任一项所述的补偿像素电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管均为薄膜晶体管。
  8. 根据权利要求3-5任一项所述的补偿像素电路，还包括补偿控制器，其中，所述补偿控制器被配置为接收所述信号采集电路采集的所述驱动晶体管的栅极电压。
  9. 根据权利要求8所述的补偿像素电路，其中，所述补偿控制器还被配置为：
    接收所述补偿驱动电路接收的发光数据信号，
    用所述驱动晶体管的栅极电压减去所述补偿驱动电路接收的发光数据信号中的发光电压以获取所述驱动晶体管的阈值电压。
  10. 一种显示面板，包括如权利要求1-9任一项所述的补偿像素电路。
  11. 根据权利要求10所述的显示面板，包括多个补偿区域，其中，每个所述补偿区域包括至少一个所述补偿像素电路。
  12. 根据权利要求11所述的显示面板，其中，每个所述补偿区域还包括非补偿像素电路，所述非补偿像素电路所对占据的亚像素区域与所述补偿像素电路所占据的亚像素区域彼此相邻。
  13. 根据权利要求12所述的显示面板，还包括补偿控制器，其中，所述补偿控制器被配置为接收所述信号采集电路采集的所述驱动晶体管的栅极电压，并根据所述驱动晶体管的栅极电压补偿所述非补偿像素电路。
  14. 根据权利要求13所述的显示面板，其中，所述补偿控制器还被配置为：
    接收所述补偿驱动电路接收的发光数据信号，
    用所述驱动晶体管的栅极电压减去所述补偿驱动电路接收的发光数据信 号中的发光电压以获取所述驱动晶体管的阈值电压，
    接收所述非补偿像素电路的发光数据信号，
    用所述非补偿像素电路的发光数据信号的发光电压加上所述阈值电压以获取所述非补偿像素电路的更新发光数据信号的发光电压，以及
    向所述非补偿像素电路发送所述更新发光数据信号的发光电压。
  15. 根据权利要求12所述的显示面板，其中，每个所述补偿区域包括一个补偿像素电路和八个非补偿像素电路，所述非补偿像素电路围绕所述补偿像素电路设置。
  16. 一种显示设备，包括如权利要求10-15任一项所述的显示面板。
  17. 一种区域补偿方法，包括：
    接收补偿像素电路中信号采集电路采集的驱动晶体管的栅极电压；
    根据所述驱动晶体管的栅极电压补偿非补偿像素电路。
  18. 根据权利要求17所述的区域补偿方法，其中，根据所述驱动晶体管的栅极电压补偿所述非补偿像素电路包括：
    接收补偿驱动电路接收的发光数据信号；
    用所述驱动晶体管的栅极电压减去所述补偿驱动电路接收的发光数据信号中的发光电压，以获取所述补偿驱动晶体管的阈值电压；
    接收所述非补偿像素电路的发光数据信号；
    用所述非补偿像素电路的发光数据信号的发光电压加上所述阈值电压，以获取所述非补偿像素电路的更新发光数据信号的发光电压；以及
    向所述非补偿像素电路发送所述更新发光数据信号的发光电压。
  19. 一种驱动如权利要求1-9任一项所述补偿像素电路的方法，包括：复位时段、补偿时段及发光时段，其中，
    在所述复位时段，设置控制信号为开启电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压；
    在所述补偿时段，设置控制信号为关闭电压，设置第一扫描信号为开启电压，设置第二扫描信号为关闭电压；
    在所述发光时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为开启电压。
  20. 根据权利要求19所述的方法，在所述复位时段之前还包括准备时段， 在所述准备时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压。
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