WO2018028209A1 - 像素电路、显示面板、显示设备及驱动方法 - Google Patents

像素电路、显示面板、显示设备及驱动方法 Download PDF

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Publication number
WO2018028209A1
WO2018028209A1 PCT/CN2017/077982 CN2017077982W WO2018028209A1 WO 2018028209 A1 WO2018028209 A1 WO 2018028209A1 CN 2017077982 W CN2017077982 W CN 2017077982W WO 2018028209 A1 WO2018028209 A1 WO 2018028209A1
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Prior art keywords
voltage
setting
turn
transistor
signal
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PCT/CN2017/077982
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English (en)
French (fr)
Inventor
杨盛际
董学
吕敬
陈小川
赵文卿
杨亚锋
王磊
刘冬妮
肖丽
卢鹏程
岳晗
付杰
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2017552040A priority Critical patent/JP6981877B2/ja
Priority to US15/562,673 priority patent/US10535306B2/en
Priority to EP17771324.5A priority patent/EP3499491B1/en
Publication of WO2018028209A1 publication Critical patent/WO2018028209A1/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a display panel, a display device, and a driving method.
  • organic light-emitting diode (OLED) display panels have the characteristics of self-luminous, high contrast, low power consumption, wide viewing angle, fast response, flexible panel, wide temperature range, and simple manufacturing. Prospects.
  • the organic light emitting diode (OLED) display panel can be applied to a device having a display function such as a mobile phone, a display, a notebook computer, a digital camera, an instrument meter, and the like.
  • Embodiments of the present disclosure provide a pixel circuit including: a light emitting circuit including a plurality of light emitting sub-circuits; a compensation driving circuit including an output end and a driving transistor, wherein the plurality of light emitting sub-circuits are electrically connected to the output end Connected, the compensation drive circuit is configured to receive the illumination data signal, compensate the threshold voltage of the drive transistor, and drive any one of the illumination sub-circuits to emit light according to an output signal output by the output.
  • the pixel circuit provided by the embodiment of the present disclosure further includes a selection circuit, wherein the selection circuit is electrically connected to the output end, and the plurality of illumination sub-circuits are respectively electrically connected to the selection circuit, and the compensation drive The circuit is configured to drive any one of the plurality of illuminating sub-circuits to emit light through the selection circuit.
  • each of the light-emitting sub-circuits includes a switching element and a light-emitting element connected in series.
  • the switching element includes a transistor
  • the light emitting element includes an organic light emitting diode
  • the light emitting circuit includes a first illuminating sub-circuit, a second illuminating sub-circuit, and a third illuminating sub-circuit
  • the first illuminating sub-circuit includes a first switching transistor connected in series And a first organic light emitting diode
  • the second light emitting subcircuit comprises a series connection a second switching transistor and a second organic light emitting diode
  • the third lighting sub-circuit comprising a third switching transistor and a third organic light emitting diode connected in series.
  • the first pole of the first switching transistor, the first pole of the second switching transistor, and the first pole of the third switching transistor are electrically connected to the first node Connected
  • the gate of the first switching transistor is configured to receive a first strobe signal
  • the gate of the second switching transistor is configured to receive a second strobe signal
  • a gate of the third switching transistor is Configuring to receive a third strobe signal
  • the second pole of the first switching transistor is electrically connected to the first pole of the first organic light emitting diode
  • the second pole of the second switching transistor is opposite to the second organic
  • the first pole of the light emitting diode is electrically connected
  • the second pole of the third switching transistor is electrically connected to the first pole of the third organic light emitting diode
  • the second pole of the first organic light emitting diode, the second The second pole of the organic light emitting diode and the second pole of the third organic light emitting diode are both grounded.
  • the compensation driving circuit further includes a first compensation transistor configured to provide a first power voltage to the driving transistor in response to the second scan signal; and a second compensation transistor, Configuring to provide the illumination data signal to the drive transistor in response to a first scan signal; the third compensation transistor configured to provide a second supply voltage to the drive transistor in response to the control signal; a fourth compensation transistor, Configuring to connect a gate and a second pole of the driving transistor in response to the first scan signal; a fifth compensation transistor configured to connect the second pole and the gate of the driving transistor in response to the second scan signal
  • the illuminating circuit, and the storage capacitor are configured to store a voltage difference between the first pole and the second pole of the third compensating transistor.
  • the first pole of the first compensation transistor is configured to receive a first power voltage, a gate of the first compensation transistor, and a gate of the fifth compensation transistor
  • the pole is configured to receive the second scan signal, the second pole of the first compensation transistor is electrically coupled to the second node;
  • the first pole of the second compensation transistor is configured to receive the illumination data signal, the a gate of the second compensation transistor, a gate of the fourth compensation transistor configured to receive a first scan signal, a second pole of the second compensation transistor being electrically coupled to the second node;
  • the third compensation transistor a first pole is configured to receive a second supply voltage, a gate of the third compensation transistor is configured to receive a control signal, and a second pole of the third compensation transistor is electrically coupled to a third node;
  • a first pole of the compensation transistor is electrically connected to the third node, a second pole of the fourth compensation transistor is electrically connected to the fourth node;
  • a first pole of the fifth compensation transistor is The fourth node is electrically
  • the first switching transistor, the second switching transistor, the third switching transistor, the first compensation transistor, the second compensation transistor, the The third compensation transistor, the fourth compensation transistor, and the fifth compensation transistor are all P-type transistors.
  • the first switching transistor, the second switching transistor, the third switching transistor, the first compensation transistor, the second compensation transistor, the The third compensation transistor, the fourth compensation transistor, and the fifth compensation transistor are all thin film transistors.
  • An embodiment of the present disclosure further provides a display panel including the pixel circuit provided by any of the embodiments of the present disclosure.
  • the display panel provided by the embodiment of the present disclosure further includes a scan driver, a data driver, an illumination data signal line, a first strobe signal line, a second strobe signal line, and a third strobe signal line, wherein the data a driver configured to provide a light emitting data signal to the pixel circuit through the light emitting data signal line; the scan driver configured to pass the first gate signal line, the second gate signal line, and the third selected communication, respectively
  • the number line provides a first strobe signal, a second strobe signal, and a third strobe signal to the pixel circuit.
  • An embodiment of the present disclosure further provides a display device including the display panel provided by any embodiment of the present disclosure.
  • An embodiment of the present disclosure further provides a method of driving a pixel circuit provided by any one of the embodiments of the present disclosure, comprising: including a plurality of time periods in a frame display time, driving one of the light emitting sub-circuits in each of the time periods .
  • An embodiment of the present disclosure further provides a method for driving a pixel circuit provided by any one of the embodiments of the present disclosure, including: including a first time period, a second time period, and a third time period in a frame display time, wherein the first The period includes a first reset period, a first compensation period, and a first lighting period; the second period includes a second reset period, a second compensation period, and a second lighting period; the third period includes a third reset period, a third compensation period, and a third lighting period; driving, in the first lighting period, the first organic light emitting diode to emit light; and in the second lighting period, driving the second organic light emitting diode to emit light Driving the third organic light emitting diode to emit light during the third light emitting period.
  • the first time period before the first reset period, further includes a first preparation period; before the second reset period, the second period A second preparation period is further included; the third period further includes a third preparation period before the third reset period.
  • the control signal in the first preparation period, is set to a shutdown voltage, the first scan signal is set to a shutdown voltage, and the second scan signal is set to a shutdown voltage.
  • a strobe signal is a turn-off voltage, a second strobe signal is set to a turn-off voltage, and a third strobe signal is set to a turn-off voltage; during the first reset period, a control signal is set to an on voltage, and the first scan signal is set to be off.
  • the control signal is a turn-off voltage
  • the first scan signal is set to an on voltage
  • the second scan signal is set to a turn-off voltage
  • the first strobe signal is set to a turn-off voltage
  • the second strobe signal is set to a turn-off voltage
  • a third strobe signal is set.
  • the second reset period setting a control signal to an on voltage, setting a first scan signal to a shutdown voltage, setting a second scan signal to a shutdown voltage, setting a first strobe signal to a shutdown voltage, and setting a second selection communication
  • the number is the off voltage
  • the third strobe signal is set to be the off voltage
  • the control signal is set to the off voltage
  • the first scan signal is set to the turn-on voltage
  • the second scan signal is set to the turn-off voltage.
  • a strobe signal is a turn-off voltage
  • a second strobe signal is set to a turn-off voltage
  • a third strobe signal is set to a turn-off voltage
  • the control signal is set to a shutdown voltage
  • the first scanning signal is set to a shutdown voltage
  • the second scanning signal is set to an on voltage
  • the first gate signal is set to a shutdown voltage
  • the second gate signal is set to an on voltage
  • Setting the third strobe signal to turn off the voltage In the third preparation period, setting the control signal to the off voltage, setting the first scan signal to the off voltage, setting the second scan signal to the off voltage, setting the first strobe signal to the off voltage, and setting the second strobe signal to Turning off the voltage, setting the third strobe signal to be the off voltage; setting the control signal to the turn-on voltage during the third reset period, setting the first scan signal to the off voltage, setting the second scan signal to the off voltage, setting the first selection
  • the pass signal is a turn-off voltage
  • the second strobe signal is set to a turn-off voltage
  • the third strobe signal is set to a turn-off voltage; in the third compensation period, the control signal is set to a turn-off voltage, and the first scan signal is set to an turn-on voltage, Setting a second scan signal to be a turn-off voltage, setting a first strobe signal to a turn-off voltage, setting a second strobe signal to a turn-off voltage,
  • FIG. 1(a) and 1(b) are schematic diagrams of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 6 is a driving waveform diagram of a driving method according to an embodiment of the present disclosure.
  • 8(a) and 8(b) show a 4T2C pixel circuit and a 4T1C pixel circuit, respectively.
  • OLED display panels typically employ an active drive approach that includes a plurality of sub-pixels arranged in an array.
  • the most basic pixel circuit of each sub-pixel is 2T1C (ie, including two transistors (scanning transistor and driving transistor) and one storage capacitor) mode, for example, see two types of 2T1C shown in FIG. 7(a) and FIG. 7(b) respectively.
  • Pixel circuit. In order to improve the display uniformity of the entire panel, the pixel circuit of each sub-pixel can be obtained on the basis of the above 2T1C mode to obtain a pixel circuit with a compensation function. Such a pixel circuit can be referred to as a compensation pixel circuit, based on the compensation principle.
  • the compensation pixel circuit may include three types of voltage compensation, current compensation, and hybrid compensation, whereby various compensation pixel circuits such as 4T2C or 4T1C can be obtained, for example, see FIGS. 8(a) and 8(b).
  • various compensation pixel circuits such as 4T2C or 4T1C can be obtained, for example, see FIGS. 8(a) and 8(b).
  • the OLED display panel using the compensation pixel circuit can obtain better brightness uniformity, but the panel area occupied by the driving circuit portion of each sub-pixel is increased, which is disadvantageous for obtaining a high-resolution OLED display. panel.
  • Embodiments of the present disclosure provide a pixel circuit, a display panel, a display device, and a driving method, using a plurality of sub-pixels (eg, sub-pixels of three colors of red, green, and blue) to share at least partially compensated pixel circuits, and By field sequential driving, these sub-pixels are displayed in a time-division manner within the display time of one frame of image, that is, a plurality of transmissions are time-divisionally driven by a compensation driving circuit.
  • the photonic circuit emits light. This arrangement saves the number of compensation drive circuits and compresses the panel area occupied by the compensation drive circuit, thereby contributing to an increase in the physical resolution of the display panel.
  • FIG. 1(a) is a schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a pixel circuit 100.
  • the pixel circuit 100 includes a light emitting circuit 110 and a compensation driving circuit 120.
  • the light emitting circuit 110 includes a plurality of light emitting sub-circuits 111.
  • the compensation driving circuit 120 includes The output terminal 121 and the driving transistor DT.
  • the plurality of illuminating sub-circuits 111 are electrically connected to the output terminal 121.
  • the compensating driving circuit 120 is configured to receive the illuminating data signal Data, compensate the threshold voltage of the driving transistor DT, and drive any one of the illuminating sub-circuits according to the output signal output from the output terminal 121. 111 light.
  • Each of the illuminating sub-circuits may correspond to one sub-pixel, and any one of the plurality of illuminating sub-circuits 111' may be electrically connected to the compensating driving circuit 120 according to a predetermined signal.
  • FIG. 1(b) is a schematic diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a pixel circuit 100.
  • the pixel circuit 100 includes a light emitting circuit 110, a compensation driving circuit 120, and a selection circuit 130.
  • the light emitting circuit 110 includes a plurality of light emitting sub-circuits 111.
  • the compensation drive circuit 120 includes an output terminal 121 and a drive transistor DT.
  • the selection circuit 130 is connected to the output terminal 121.
  • the plurality of illuminating sub-circuits 111' are electrically connected to the selection circuit 130, respectively, and the compensation driving circuit 120 is configured to receive the illuminating data signal Data, compensate the threshold voltage of the driving transistor DT, and can be driven by the selection circuit 130 according to the output signal output from the output terminal 121. Any one of the illuminating sub-circuits 111 emits light. Each of the illuminating sub-circuits may correspond to one sub-pixel.
  • the selection circuit 130 can electrically connect any one of the plurality of light-emitting sub-circuits 111' to the compensation drive circuit 120 in accordance with a predetermined signal.
  • a plurality of illuminating sub-circuits 111 are connected together and electrically connected to the output terminal 121.
  • FIG. 2 is a schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • each of the light-emitting sub-circuits 111 in the light-emitting circuit 110 includes a switching element and a light-emitting element connected in series.
  • the switching element can electrically connect the illuminating sub-circuit 111 in which it is located to the compensating driving circuit 120 according to a predetermined signal.
  • three switching elements may be arranged together to form a selection circuit 130 as shown in FIG.
  • the light-emitting sub-circuit 111' may not include a switch.
  • the components are electrically connected to drive the light-emitting elements separately.
  • the switching element includes a transistor.
  • the light emitting element includes an organic light emitting diode.
  • the light emitting circuit 110 includes a first illuminating sub-circuit, a second illuminating sub-circuit, and a third illuminating sub-circuit, for example, a first illuminating sub-circuit,
  • the second illuminating subcircuit is connected in parallel with the third illuminating subcircuit.
  • the first illuminating sub-circuit includes a first switching transistor M1 and a first organic light emitting diode OLED1 connected in series
  • the second illuminating sub-circuit includes a second switching transistor M2 and a second organic light emitting diode OLED2 connected in series
  • the third illuminating sub-circuit comprises a series connection The third switching transistor M3 and the third organic light emitting diode OLED3.
  • the light-emitting circuit 110 shown in FIG. 2 is only one example, and the light-emitting circuit 110 may include two, four or other number of light-emitting sub-circuits.
  • the structure of the illuminating sub-circuit is not limited to the case shown in FIG.
  • the first organic light emitting diode OLED1 is a red organic light emitting diode
  • the second organic light emitting diode OLED2 is a green organic light emitting diode
  • the third organic light emitting diode OLED3 is a blue organic light emitting diode.
  • the three illuminating sub-circuits respectively correspond to the RGB sub-pixels, that is, the RGB sub-pixels constitute one pixel.
  • one pixel may include, in addition to RGB sub-pixels, a sub-pixel (ie, W) that emits white light or a sub-pixel that emits yellow light (ie, Y), thereby obtaining RGBW or RGBY. layout.
  • the first pole of the first switching transistor M1, the first pole of the second switching transistor M2, and the first pole of the third switching transistor M3 are The first node N1 is electrically connected.
  • the gate of the first switching transistor M1 is electrically connected to the first strobe signal line to receive the first strobe signal G1;
  • the gate of the second switching transistor M2 is electrically connected to the second strobe signal line to receive the second strobe signal G2;
  • the gate of the third switching transistor M3 is electrically connected to the third strobe signal line to receive the third strobe signal G3.
  • the second pole of the first switching transistor M1 is electrically connected to the first pole (eg, the anode) of the first organic light emitting diode OLED1; the second pole of the second switching transistor M2 and the first pole of the second organic light emitting diode OLED2 (eg The anode is electrically connected; the second pole of the third switching transistor M3 is electrically connected to the first pole (eg, the anode) of the third organic light emitting diode OLED3.
  • a second pole (eg, a cathode) of the first organic light emitting diode OLED1, a second pole (eg, a cathode) of the second organic light emitting diode OLED2, and a second pole (eg, a cathode) of the third organic light emitting diode OLED3 are both grounded.
  • FIG. 3 is a schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • the compensation driving circuit 120 further includes a first compensation.
  • the pixel circuit has a compensation function and is a 6T1C mode. It will be apparent that embodiments of the invention are not limited to the particular compensation pixel circuit as shown, and for example, may be equally applicable to other types of compensation pixel circuits.
  • the following is an exemplary illustration in the 6T1C mode as shown in FIG.
  • the first compensation transistor T1 is configured to provide a first power supply voltage Vdd to the driving transistor DT in response to the second scan signal Scan2;
  • the second compensation transistor T2 is configured to provide illumination data to the driving transistor DT in response to the first scan signal Scan1 a signal Data;
  • a third compensation transistor T3 configured to provide a second power supply voltage Vint to the driving transistor DT in response to the control signal Em;
  • the fourth compensation transistor T4 is configured to connect the gate of the driving transistor DT in response to the first scanning signal Scan1 and a second pole;
  • the fifth compensation transistor T5 is configured to connect the second pole of the driving transistor DT and the lighting circuit 110 in response to the second scanning signal Scan2;
  • the storage capacitor C is configured to store the first pole and the second of the third compensation transistor T3 The voltage difference between the poles.
  • the first pole of the first compensation transistor T1 is electrically connected to the first power line to receive the first power voltage Vdd; the gate of the first compensation transistor T1, the fifth compensation The gate of the transistor T5 is electrically connected to the second scan signal line to receive the second scan signal Scan2; the second pole of the first compensation transistor T1 is electrically connected to the second node N2.
  • the first pole of the second compensation transistor T2 is electrically connected to the light-emitting data signal line to receive the light-emitting data signal Data; the gate of the second compensation transistor T2 and the gate of the fourth compensation transistor T4 are electrically connected to the first scan signal line to receive The first scan signal Scan1; the second pole of the second compensation transistor T2 is electrically connected to the second node N2.
  • the first pole of the third compensation transistor T3 is electrically connected to the second power line to receive the second power voltage Vint; the gate of the third compensation transistor T3 is electrically connected to the control signal line to receive the control signal Em; the third compensation transistor T3 The second pole is electrically connected to the third node N3.
  • the first pole of the fourth compensation transistor T4 is electrically connected to the third node N3; the second pole of the fourth compensation transistor T4 is electrically connected to the fourth node N4.
  • the first pole of the fifth compensation transistor T5 is electrically connected to the fourth node N4; the second pole of the fifth compensation transistor T5 is electrically connected to the first node N1, that is, the second pole of the fifth compensation transistor T5 is used as a compensation drive.
  • the output of circuit 120 is electrically coupled to a plurality of illuminating subcircuits.
  • the first electrode of the driving transistor DT is electrically connected to the second node N2; the gate of the driving transistor DT is electrically connected to the third node N3; and the second electrode of the driving transistor DT is electrically connected to the fourth node N4.
  • the first end of the storage capacitor C is electrically connected to the second power line to receive the second power voltage Vint, and the second of the storage capacitor C The terminal is electrically connected to the third node N3.
  • the compensation driving circuit 120 shown in FIG. 3 is only an example, and the embodiments of the present disclosure include but are not limited to the compensation driving circuit shown in FIG. 3, and may also have other functions of compensating the threshold voltage of the driving transistor DT and The other compensation driving circuit for driving the light emitting function of the light emitting sub-circuit according to the output signal outputted from the output terminal.
  • the second power line is grounded. That is, the second power supply voltage Vint is a ground voltage (for example, 0 V).
  • embodiments of the present disclosure include, but are not limited to, the case where the second power supply voltage is a ground voltage, and the second power supply voltage may also be a stable low voltage, such as 1V.
  • the fourth compensation transistor T4 and the fifth compensation transistor T5 are all P-type transistors. For example, using the same type of transistor, the process flow can be unified to facilitate product production.
  • the fourth compensation transistor T4 and the fifth compensation transistor T5 are all thin film transistors.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the first pole of the transistor of the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described, so the first pole of all or part of the transistors in the embodiment of the present disclosure
  • the second pole is interchangeable as needed.
  • the first pole of the transistor of the embodiment of the present disclosure may be a source
  • the second pole may be a drain; or the first extreme drain of the transistor and the second source of the second.
  • the transistor can be divided into N-type and P-type transistors according to the characteristics of the transistor.
  • the embodiment of the present disclosure uses the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, and the first compensation transistor T1.
  • the two compensation transistors T2, the third compensation transistor T3, the fourth compensation transistor T4, and the fifth compensation transistor T5 are all P-type transistors as an example. Based on the description and teaching of this implementation of the present disclosure, those of ordinary skill in the art are not making The implementation of the embodiment of the present disclosure using N-type transistors or N-type and P-type transistor combinations can be easily conceived under the premise of inventive labor, and therefore, these implementations are also within the scope of the present disclosure.
  • FIG. 4 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a display panel 10, as shown in FIG. 4, which includes the pixel circuit 100 provided by any embodiment of the present disclosure.
  • the display panel 10 includes a plurality of pixel circuits 100.
  • the display panel 10 includes a plurality of pixel regions, each of which includes a plurality of sub-pixel regions.
  • the light-emitting circuits in the pixel circuit 100 are in one-to-one correspondence with the pixel regions, and the light-emitting sub-circuits in the light-emitting circuits are in one-to-one correspondence with the sub-pixel regions.
  • the display panel 10 provided by the embodiment of the present disclosure further includes a scan driver 11, a data driver 12, a timing controller 13, an illumination data signal line, a first strobe signal line, a second strobe signal line, and a third strobe signal.
  • the lines (the illuminating data signal line, the first strobe signal line, the second strobe signal line, and the third strobe signal line are not shown in FIG. 4).
  • the data driver 12 is configured to provide a light-emitting data signal to the pixel circuit 100 through the light-emitting data signal line; the scan driver 11 is configured to pass the first gate signal line, the second gate signal line, and the third gate signal line to the pixel, respectively.
  • the circuit 100 provides a first strobe signal G1, a second strobe signal G2, and a third strobe signal G3.
  • the timing controller 13 is configured to provide a clock signal to the system to coordinate the operation of the system.
  • the display panel 10 further includes a first scan signal line, a second scan signal line, and a control signal line.
  • the scan driver is further configured to supply the first scan signal Scan1, the second scan signal Scan2, and the control signal Em to the pixel circuit 100 through the first scan signal line, the second scan signal line, and the control signal line, respectively.
  • FIG. 5 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a display device 1.
  • the display device 1 includes the display panel 10 provided by any embodiment of the present disclosure.
  • the display device may include any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Embodiments of the present disclosure also provide a method of driving a pixel circuit 100 provided by any of the embodiments of the present disclosure, the method comprising: including a plurality of time periods within a frame display time, driving one of the light emitting sub-circuits in each time period. That is to say, the plurality of illuminating sub-circuits are time-divisionally driven to emit light within one frame display time.
  • FIG. 6 is a driving waveform diagram of a driving method provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure further provides a method of driving the pixel circuit 100 provided by any of the embodiments of the present disclosure, the method comprising: including a first time period, a second time period, and a third time period in a frame display time.
  • the first period includes a first reset period t12, a first compensation period t13, and a first lighting period t14;
  • the second period includes a second reset period t22, a second compensation period t23, and a second lighting period t24;
  • the third period includes the third a reset period t32, a third compensation period t33, and a third lighting period t34; driving the first organic light emitting diode OLED1 to emit light during the first lighting period t14; driving the second organic light emitting diode OLED2 to emit light during the second lighting period t24;
  • the three-emission period t34 drives the third organic light-emitting diode OLED3 to emit light.
  • the first period before the first reset period t12, the first period further includes a first preparation period t11; before the second reset period t22, the second period further includes a second preparation The period t21; before the third reset period t32, the third period further includes a third preparation period t31.
  • the driving signals are set as follows.
  • the turn-on voltage in the embodiment of the present disclosure refers to a voltage that enables the first and second stages of the respective transistors to be turned on
  • the turn-off voltage refers to a voltage that can turn off the first and second stages of the respective transistors.
  • the turn-on voltage is a low voltage (for example, 0V)
  • the turn-off voltage is a high voltage (for example, 5V)
  • the turn-on voltage is a high voltage (for example, 5V)
  • the voltage is a low voltage (eg, 0V).
  • the driving waveforms shown in FIG. 6 are all described by taking a P-type transistor as an example, that is, the turn-on voltage is a low voltage (for example, 0 V), and the turn-off voltage is a high voltage (for example, 5 V).
  • the control signal Em is set to be the off voltage
  • the first scan signal Scan1 is set to the off voltage
  • the second scan signal Scan2 is set to the off voltage
  • the first gate signal G1 is set.
  • the pass signal G3 is a turn-off voltage.
  • the control signal Em is set to be the off voltage
  • the first scan signal Scan1 is set to be the off voltage
  • the second scan signal Scan2 is set to the off voltage
  • the first gate signal G1 is set.
  • set the second strobe signal G2 to the off voltage
  • set the third strobe signal G3 to the off voltage
  • set the control signal Em to the turn-on voltage
  • the control signal Em is set to be the off voltage
  • the first scan signal Scan1 is set to be the off voltage
  • the second scan signal Scan2 is set to the off voltage
  • the first gate signal G1 is set.
  • the control signal Em is set to be the turn-on voltage
  • the first scan signal Scan1 is set to the turn-off voltage.
  • the control signal Em is a turn-off voltage
  • the first scan signal Scan1 is a turn-off voltage
  • the second scan signal Scan2 is a turn-off voltage
  • the first strobe signal G1 is a turn-off voltage
  • the second strobe signal G2 is a turn-off voltage
  • the third strobe signal G3 is a turn-off voltage. Therefore, the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, the first compensation transistor T1, the second compensation transistor T2, the third compensation transistor T3, the fourth compensation transistor T4, and the fifth compensation transistor T5 are both Is off.
  • the first preparation period can provide a stable process for the pixel circuit to prevent the circuit from being abnormal due to incomplete discharge of the parasitic capacitance.
  • the control signal Em is an on voltage
  • the first scan signal Scan1 is a turn-off voltage
  • the second scan signal Scan2 is a turn-off voltage
  • the first strobe signal G1 is a turn-off voltage
  • the second strobe signal G2 is off.
  • the voltage, the third strobe signal G3 is a turn-off voltage. Therefore, the third compensation transistor T3 is turned on, the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, the first compensation transistor T1, the second compensation transistor T2, the fourth compensation transistor T4, and the fifth compensation transistor.
  • T5 is off.
  • the voltage across the storage capacitor C is initialized to a second supply voltage Vint (eg, the second supply voltage Vint can be a stable low voltage or ground voltage), enabling initialization of the pixel circuit.
  • the control signal Em is a turn-off voltage
  • the first scan signal Scan1 is an on voltage
  • the second scan signal Scan2 is a turn-off voltage
  • the first strobe signal G1 is a turn-off voltage
  • the second strobe signal G2 is off.
  • the voltage, the third strobe signal G3 is a turn-off voltage. Therefore, the second compensation transistor T2 and the fourth compensation transistor T4 are turned on, the first switching transistor M1, the second switching transistor M2, the third switching transistor M3, the first compensation transistor T1, the third compensation transistor T3, and the fifth compensation transistor T5 is off.
  • the illuminating data signal Data charges the third node N3 through the second compensating transistor T2, the driving transistor DT and the fourth compensating transistor T4 until the voltage of the third node N3 is Vdata+Vth, where Vdata is the voltage of the illuminating data signal Data.
  • Vth is the threshold voltage of the driving transistor DT because the voltage difference between the gate and the source of the driving transistor DT is satisfied at this time as Vth.
  • the voltage difference across the storage capacitor C is Vdata+Vth.
  • the fifth compensation transistor T5 since the fifth compensation transistor T5 is in the off state, the current does not pass through the OLED, and the OLED is prevented from emitting light during this period, thereby improving the display effect and reducing the loss of the OLED.
  • the control signal Em is the off voltage
  • the first scan signal Scan1 is the off voltage
  • the second scan signal Scan2 is the on voltage
  • the first gate signal G1 is the on voltage
  • the second gate signal G2 is off.
  • the voltage, the third strobe signal G3 is a turn-off voltage. Therefore, the first switching transistor M1, the first compensation transistor T1 and the fifth compensation transistor T5 are turned on, the second switching transistor M2, the third switching transistor M3, the second compensation transistor T2, the third compensation transistor T3, and the fourth compensation transistor T4 is off.
  • the voltage of the third node N3 is maintained at Vdata+Vth, and the lighting current IOLED flows through the first compensation transistor T1, the driving transistor DT, the fifth compensation transistor T5, and the first switch.
  • the transistor M1 and the first organic light emitting diode OLED1 emit light.
  • the illuminating current IOLED satisfies the following saturation current formula:
  • ⁇ n is the channel mobility of the driving transistor
  • Cox is the channel capacitance per unit area of the driving transistor
  • W and L are the channel width and channel length of the driving transistor, respectively
  • VGS is the gate-source voltage of the driving transistor (driving transistor The difference between the gate voltage and the source voltage).
  • the illuminating current IOLED has not been affected by the threshold voltage Vth of the driving transistor, and is only related to the voltage Vdata of the illuminating data signal and the first power supply voltage Vdd.
  • the problem of threshold voltage drift of the driving transistor is solved, and the normal operation of the OLED display panel is ensured.
  • the working process of the second organic light emitting diode OLED2 in the second time period and the working process of the third organic light emitting diode OLED3 in the third time period are similar to the first time period, and details are not described herein again.
  • a method for driving a pixel circuit includes, but is not limited to, the above situation.
  • the illuminating circuit further includes a fourth illuminating sub-circuit, and the fourth illuminating sub-circuit includes a fourth organic illuminating diode; further includes a fourth period of time during a frame display period, and driving the fourth OLED OLED 3 to emit light during the fourth illuminating period .
  • Embodiments of the present disclosure provide a pixel circuit, a display panel, a display device, and a driving method, wherein a plurality of sub-pixels share a manner of at least partially compensating a pixel circuit, and the field sequential driving mode is used to make a pixel display time of one frame of an image.
  • multiple subpixels for example, red, green, and blue
  • the sub-pixels of the three colors are displayed in a time-sharing manner, that is, a plurality of illuminating sub-circuits are driven to be time-divisionally driven by a compensation driving circuit.
  • This arrangement saves the number of compensation drive circuits and compresses the backplane space occupied by the compensation drive circuit, thereby increasing the resolution of the display panel.

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Abstract

一种像素电路、显示面板、显示设备及驱动方法，该像素电路(100)包括：发光电路(110)，包括多个发光子电路(111)；补偿驱动电路(120)，包括输出端(121)和驱动晶体管，其中，所述多个发光子电路(111)均与所述输出端(121)电连接，所述补偿驱动电路(120)被配置为接收发光数据信号、补偿所述驱动晶体管的阈值电压以及根据所述输出端输出的输出信号驱动任意一个所述发光子电路(111)发光。这种设置节省了补偿驱动电路的数量，压缩了补偿驱动电路占用的背板空间，从而提高了显示面板的分辨率。

Description

像素电路、显示面板、显示设备及驱动方法 技术领域
本公开的实施例涉及一种像素电路、显示面板、显示设备及驱动方法。
背景技术
在显示领域，有机发光二极管(OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。
由于上述特点，有机发光二极管(OLED)显示面板可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
发明内容
本公开的实施例提供一种像素电路，包括：发光电路，包括多个发光子电路；补偿驱动电路，包括输出端和驱动晶体管，其中，所述多个发光子电路均与所述输出端电连接，所述补偿驱动电路被配置为接收发光数据信号、补偿所述驱动晶体管的阈值电压以及根据所述输出端输出的输出信号驱动任意一个所述发光子电路发光。
例如，本公开实施例提供的像素电路，还包括选择电路，其中，所述选择电路与所述输出端电连接，所述多个发光子电路分别与所述选择电路电连接，所述补偿驱动电路被配置为通过所述选择电路驱动任意一个所述多个发光子电路发光。
例如，在本公开实施例提供的像素电路中，所述发光电路中的每个发光子电路均包括串联的开关元件和发光元件。
例如，在本公开实施例提供的像素电路中，所述开关元件包括晶体管，所述发光元件包括有机发光二极管。
例如，在本公开实施例提供的像素电路中，所述发光电路包括第一发光子电路、第二发光子电路和第三发光子电路，所述第一发光子电路包括串联的第一开关晶体管和第一有机发光二极管，所述第二发光子电路包括串联的 第二开关晶体管和第二有机发光二极管，所述第三发光子电路包括串联的第三开关晶体管和第三有机发光二极管。
例如，在本公开实施例提供的像素电路中，所述第一开关晶体管的第一极、所述第二开关晶体管的第一极、所述第三开关晶体管的第一极与第一节点电连接，所述第一开关晶体管的栅极被配置为接收第一选通信号，所述第二开关晶体管的栅极被配置为接收第二选通信号，所述第三开关晶体管的栅极被配置为接收第三选通信号，所述第一开关晶体管的第二极与所述第一有机发光二极管的第一极电连接，所述第二开关晶体管的第二极与所述第二有机发光二极管的第一极电连接，所述第三开关晶体管的第二极与所述第三有机发光二极管的第一极电连接，所述第一有机发光二极管的第二极、所述第二有机发光二极管的第二极和所述第三有机发光二极管的第二极均接地。
例如，在本公开实施例提供的像素电路中，所述补偿驱动电路还包括第一补偿晶体管，被配置为响应于第二扫描信号向所述驱动晶体管提供第一电源电压；第二补偿晶体管，被配置为响应于第一扫描信号向所述驱动晶体管提供所述发光数据信号；第三补偿晶体管，被配置为响应于控制信号向所述驱动晶体管提供第二电源电压；第四补偿晶体管，被配置为响应于所述第一扫描信号连接所述驱动晶体管的栅极和第二极；第五补偿晶体管，被配置为响应于所述第二扫描信号连接所述驱动晶体管的第二极和所述发光电路，以及存储电容，被配置为存储所述第三补偿晶体管第一极和第二极之间的电压差。
例如，在本公开实施例提供的像素电路中，所述第一补偿晶体管的第一极被配置为接收第一电源电压，所述第一补偿晶体管的栅极、所述第五补偿晶体管的栅极被配置为接收第二扫描信号，所述第一补偿晶体管的第二极与第二节点电连接；所述第二补偿晶体管的第一极被配置为接收所述发光数据信号，所述第二补偿晶体管的栅极、所述第四补偿晶体管的栅极被配置为接收第一扫描信号，所述第二补偿晶体管的第二极与所述第二节点电连接；所述第三补偿晶体管的第一极被配置为接收第二电源电压，所述第三补偿晶体管的栅极被配置为接收控制信号，所述第三补偿晶体管的第二极与第三节点电连接；所述第四补偿晶体管的第一极与所述第三节点电连接，所述第四补偿晶体管的第二极与第四节点电连接；所述第五补偿晶体管的第一极与所述 第四节点电连接，所述第五补偿晶体管的第二极与所述第一节点电连接；所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的栅极与所述第三节点电连接，所述驱动晶体管的第二极与所述第四节点电连接；所述存储电容的第一端被配置为接收所述第二电源电压，所述存储电容的第二端与所述第三节点电连接。
例如，在本公开实施例提供的像素电路中，所述第一开关晶体管、所述第二开关晶体管、所述第三开关晶体管、所述第一补偿晶体管、所述第二补偿晶体管、所述第三补偿晶体管、所述第四补偿晶体管、所述第五补偿晶体管均为P型晶体管。
例如，在本公开实施例提供的像素电路中，所述第一开关晶体管、所述第二开关晶体管、所述第三开关晶体管、所述第一补偿晶体管、所述第二补偿晶体管、所述第三补偿晶体管、所述第四补偿晶体管、所述第五补偿晶体管均为薄膜晶体管。
本公开的实施例还提供一种显示面板，包括本公开任一实施例提供的像素电路。
例如，本公开实施例提供的显示面板，还包括扫描驱动器、数据驱动器、发光数据信号线、第一选通信号线、第二选通信号线以及第三选通信号线，其中，所述数据驱动器被配置为通过所述发光数据信号线向所述像素电路提供发光数据信号；所述扫描驱动器被配置为分别通过所述第一选通信号线、第二选通信号线以及第三选通信号线向所述像素电路提供第一选通信号、第二选通信号以及第三选通信号。
本公开的实施例还提供一种显示设备，包括本公开任一实施例提供的显示面板。
本公开的实施例还提供一种驱动本公开任一实施例提供的像素电路的方法，包括：在一帧显示时间内包括多个时段，在每个所述时段内驱动一个所述发光子电路。
本公开的实施例还提供一种驱动本公开任一实施例提供的像素电路的方法，包括：在一帧显示时间内包括第一时段、第二时段和第三时段，其中，所述第一时段包括第一复位时段、第一补偿时段和第一发光时段；所述第二时段包括第二复位时段、第二补偿时段和第二发光时段；所述第三时段包括 第三复位时段、第三补偿时段和第三发光时段；在所述第一发光时段，驱动所述第一有机发光二极管发光；在所述第二发光时段，驱动所述第二有机发光二极管发光；在所述第三发光时段，驱动所述第三有机发光二极管发光。
例如，在本公开任一实施例提供的驱动方法中，在所述第一复位时段之前，所述第一时段还包括第一准备时段；在所述第二复位时段之前，所述第二时段还包括第二准备时段；在所述第三复位时段之前，所述第三时段还包括第三准备时段。
例如，在本公开任一实施例提供的驱动方法中，在所述第一准备时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；在所述第一复位时段，设置控制信号为开启电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；在所述第一补偿时段，设置控制信号为关闭电压，设置第一扫描信号为开启电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；在所述第一发光时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为开启电压，设置第一选通信号为开启电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；在所述第二准备时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；在所述第二复位时段，设置控制信号为开启电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；在所述第二补偿时段，设置控制信号为关闭电压，设置第一扫描信号为开启电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；在所述第二发光时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为开启电压，设置第一选通信号为关闭电压，设置第二选通信号为开启电压，设置第三选通信号为关闭电压； 在所述第三准备时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；在所述第三复位时段，设置控制信号为开启电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；在所述第三补偿时段，设置控制信号为关闭电压，设置第一扫描信号为开启电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；在所述第三发光时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为开启电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为开启电压。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1(a)和图1(b)是本公开实施例提供的一种像素电路的示意图；
图2是本公开实施例提供的一种像素电路的示意图；
图3是本公开实施例提供的一种像素电路的示意图；
图4是本公开实施例提供的一种显示面板的示意图；
图5是本公开实施例提供的一种显示设备的示意图；
图6是本公开实施例提供的驱动方法的驱动波形图；
图7(a)和图7(b)分别示出了一种2T1C像素电路；以及
图8(a)和图8(b)分别示出了一种4T2C像素电路和4T1C像素电路。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中 示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
近年来，随着增强现实、虚拟现实等消费电子产品的崛起，为提高用户观看体验，人们对高分辨率显示面板的需求越来越迫切。
在OLED显示面板中，分辨率主要受制于光刻工艺水平和高精度金属掩模板(Fine Metal Mask，FFM)的尺寸。在光刻工艺水平和高精度金属掩模板的制造水平达到一定程度的情况下，OLED显示面板的分辨率很难提高。因此，需要另辟蹊径以应对高分辨率的问题。
OLED显示面板通常采用有源驱动方式，包括多个排列为阵列的子像素。每个子像素最基本的像素电路为2T1C(即包括两个晶体管(扫描晶体管与驱动晶体管)以及一个存储电容)模式，例如参见图7(a)和图7(b)分别示出的两种2T1C像素电路。为了改善整个面板的显示均一性，则可以使得每个子像素的像素电路在上述2T1C的模式的基础上来得到具有补偿功能的像素电路，这种像素电路可以被称为补偿像素电路，基于补偿原理，补偿像素电路可以包括电压补偿、电流补偿和混合补偿三种，由此可以得到例如4T2C或4T1C等多种补偿像素电路，例如参见图8(a)和图8(b)。然而，相比于基本的2T1C像素电路，采用补偿像素电路的OLED显示面板能够获得更好的亮度均一性，但是每个子像素的驱动电路部分占据的面板区域增加，不利于获得高分辨率OLED显示面板。
本公开的实施例提供一种像素电路、显示面板、显示设备及驱动方法，采用多个子像素(例如，红色、绿色和蓝色三种颜色的子像素)共享至少部分补偿像素电路的方式，并且通过场序驱动方式，使得这些子像素在一帧图像的显示时间内分时显示，也就是说，用一个补偿驱动电路分时驱动多个发 光子电路发光。这种设置节省了补偿驱动电路的数量，压缩了补偿驱动电路占用的面板区域，从而有助于提高显示面板的物理分辨率。
例如，图1(a)是本公开实施例提供的一种像素电路的示意图。本公开的实施例提供一种像素电路100，如图1所示，该像素电路100包括发光电路110和补偿驱动电路120，该发光电路110包括多个发光子电路111；该补偿驱动电路120包括输出端121和驱动晶体管DT。多个发光子电路111均与输出端121电连接，补偿驱动电路120被配置为接收发光数据信号Data、补偿驱动晶体管DT的阈值电压以及可以根据输出端121输出的输出信号驱动任意一个发光子电路111发光。每个发光子电路可以对应于一个子像素，可以根据预定信号使得多个发光子电路111’中任意一个与补偿驱动电路120电连接。
例如，图1(b)是本公开实施例提供的另一种像素电路的示意图。本公开的实施例提供一种像素电路100，如图1(b)所示，该像素电路100包括发光电路110、补偿驱动电路120和选择电路130，该发光电路110包括多个发光子电路111’；该补偿驱动电路120包括输出端121和驱动晶体管DT。选择电路130连接在输出端121。多个发光子电路111’分别与选择电路130电连接，补偿驱动电路120被配置为接收发光数据信号Data、补偿驱动晶体管DT的阈值电压以及可以根据输出端121输出的输出信号通过选择电路130驱动任意一个发光子电路111发光。每个发光子电路可以对应于一个子像素。选择电路130可以根据预定信号，将多个发光子电路111’中任意一个与补偿驱动电路120电连接。
例如，多个发光子电路111连接在一起并与输出端121电连接。
例如，图2是本公开实施例提供的一种像素电路的示意图。例如，如图2所示，在本公开实施例提供的像素电路100中，发光电路110中的每个发光子电路111均包括串联的开关元件和发光元件。该开关元件可以根据预定信号使得其所在的发光子电路111与补偿驱动电路120电连接。或者，可以将三个开关元件布置在一起构成如图1(b)所示的选择电路130，分别与相应的发光子电路111’的发光元件(此时，发光子电路111’可以不包括开关元件)电连接以分别驱动这些发光元件。
例如，在本公开实施例提供的像素电路100中，开关元件包括晶体管， 发光元件包括有机发光二极管。
例如，如图2所示，在本公开实施例提供的像素电路100中，发光电路110包括第一发光子电路、第二发光子电路和第三发光子电路，例如，第一发光子电路、第二发光子电路和第三发光子电路并联。第一发光子电路包括串联的第一开关晶体管M1和第一有机发光二极管OLED1，第二发光子电路包括串联的第二开关晶体管M2和第二有机发光二极管OLED2，第三发光子电路包括串联的第三开关晶体管M3和第三有机发光二极管OLED3。
需要说明的是，图2中所示的发光电路110仅为一个示例，发光电路110可以包括2个、4个或其它数量的发光子电路。发光子电路的结构也不局限于图3所示的情形。
例如，第一有机发光二极管OLED1为红色有机发光二极管，第二有机发光二极管OLED2为绿色有机发光二极管，第三有机发光二极管OLED3为蓝色有机发光二极管。此时，三个发光子电路分别对应于RGB子像素，即RGB子像素构成一个像素。显然，本发明的实施例不限于此，例如，一个像素除了RGB子像素，还可以包括发白光的子像素(即W)或发黄光的子像素(即Y)，由此得到RGBW或RGBY布局。
例如，如图2所示，在本公开实施例提供的像素电路100中，第一开关晶体管M1的第一极、第二开关晶体管M2的第一极、第三开关晶体管M3的第一极与第一节点N1电连接。第一开关晶体管M1的栅极与第一选通信号线电连接以接收第一选通信号G1；第二开关晶体管M2的栅极与第二选通信号线电连接以接收第二选通信号G2；第三开关晶体管M3的栅极与第三选通信号线电连接以接收第三选通信号G3。第一开关晶体管M1的第二极与第一有机发光二极管OLED1的第一极(例如，阳极)电连接；第二开关晶体管M2的第二极与第二有机发光二极管OLED2的第一极(例如，阳极)电连接；第三开关晶体管M3的第二极与第三有机发光二极管OLED3的第一极(例如，阳极)电连接。第一有机发光二极管OLED1的第二极(例如，阴极)、第二有机发光二极管OLED2的第二极(例如，阴极)和第三有机发光二极管OLED3的第二极(例如，阴极)均接地。
例如，图3是本公开实施例提供的一种像素电路的示意图。如图3所示，在本公开实施例提供的像素电路100中，补偿驱动电路120还包括第一补偿 晶体管T1、第二补偿晶体管T2、第三补偿晶体管T3、第四补偿晶体管T4、第五补偿晶体管T5和存储电容C。该像素电路具有补偿功能，为6T1C模式。显然，本发明的实施例并不局限于如图所示的具体补偿像素电路，例如同样可以适用于其他类型的补偿像素电路。下面以如图3所示的6T1C模式进行示范性说明。
例如，第一补偿晶体管T1被配置为响应于第二扫描信号Scan2向驱动晶体管DT提供第一电源电压Vdd；第二补偿晶体管T2被配置为响应于第一扫描信号Scan1向驱动晶体管DT提供发光数据信号Data；第三补偿晶体管T3被配置为响应于控制信号Em向驱动晶体管DT提供第二电源电压Vint；第四补偿晶体管T4被配置为响应于第一扫描信号Scan1连接驱动晶体管DT的栅极和第二极；第五补偿晶体管T5被配置为响应于第二扫描信号Scan2连接驱动晶体管DT的第二极和发光电路110；存储电容C被配置为存储第三补偿晶体管T3第一极和第二极之间的电压差。
例如，在本公开实施例提供的像素电路100中，第一补偿晶体管T1的第一极与第一电源线电连接以接收第一电源电压Vdd；第一补偿晶体管T1的栅极、第五补偿晶体管T5的栅极与第二扫描信号线电连接以接收第二扫描信号Scan2；第一补偿晶体管T1的第二极与第二节点N2电连接。第二补偿晶体管T2的第一极与发光数据信号线电连接以接收发光数据信号Data；第二补偿晶体管T2的栅极、第四补偿晶体管T4的栅极与第一扫描信号线电连接以接收第一扫描信号Scan1；第二补偿晶体管T2的第二极与第二节点N2电连接。第三补偿晶体管T3的第一极与第二电源线电连接以接收第二电源电压Vint；第三补偿晶体管T3的栅极与控制信号线电连接以接收控制信号Em；第三补偿晶体管T3的第二极与第三节点N3电连接。第四补偿晶体管T4的第一极与第三节点N3电连接；第四补偿晶体管T4的第二极与第四节点N4电连接。第五补偿晶体管T5的第一极与第四节点N4电连接；第五补偿晶体管T5的第二极与第一节点N1电连接，也就是说，第五补偿晶体管T5的第二极作为补偿驱动电路120的输出端与多个发光子电路电连接。驱动晶体管DT的第一极与第二节点N2电连接；驱动晶体管DT的栅极与第三节点N3电连接；驱动晶体管DT的第二极与第四节点N4电连接。存储电容C的第一端与第二电源线电连接以接收第二电源电压Vint，存储电容C的第二 端与第三节点N3电连接。
如上所述，图3所示的补偿驱动电路120仅为一个示例，本公开的实施例包括但不局限于图3所示的补偿驱动电路，也可以是其它具有补偿驱动晶体管DT阈值电压功能以及根据输出端输出的输出信号驱动发光子电路发光功能的其它补偿驱动电路。
例如，在本公开实施例提供的像素电路100中，第二电源线接地。也就是说，第二电源电压Vint为接地电压(例如，0V)。
需要说明的是，本公开的实施例包括但不局限于第二电源电压为接地电压的情形，第二电源电压也可以为一个稳定的低电压，例如1V。
例如，在本公开实施例提供的像素电路100中，第一开关晶体管M1、第二开关晶体管M2、第三开关晶体管M3、第一补偿晶体管T1、第二补偿晶体管T2、第三补偿晶体管T3、第四补偿晶体管T4、第五补偿晶体管T5均为P型晶体管。例如，采用相同类型的晶体管可以统一制作工艺流程，便于产品生产。
例如，在本公开实施例提供的像素电路100中，第一开关晶体管M1、第二开关晶体管M2、第三开关晶体管M3、第一补偿晶体管T1、第二补偿晶体管T2、第三补偿晶体管T3、第四补偿晶体管T4、第五补偿晶体管T5均为薄膜晶体管。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管.本公开的实施例以第一开关晶体管M1、第二开关晶体管M2、第三开关晶体管M3、第一补偿晶体管T1、第二补偿晶体管T2、第三补偿晶体管T3、第四补偿晶体管T4、第五补偿晶体管T5均为P型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创 造性劳动前提下能够容易想到本公开实施例采用N型晶体管或N型和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
例如，图4是本公开实施例提供的一种显示面板的示意图。本公开的实施例还提供一种显示面板10，如图4所示，该显示面板10包括本公开任一实施例提供的像素电路100。
例如，如图4所示，显示面板10包括多个像素电路100。
例如，显示面板10包括多个像素区域，每个像素区域包括多个子像素区域，像素电路100中的发光电路与像素区域一一对应，发光电路中的发光子电路与子像素区域一一对应。
本公开的实施例提供的显示面板10，还包括扫描驱动器11、数据驱动器12、时序控制器13、发光数据信号线、第一选通信号线、第二选通信号线以及第三选通信号线(发光数据信号线、第一选通信号线、第二选通信号线以及第三选通信号线在图4中未示出)。数据驱动器12被配置为通过发光数据信号线向像素电路100提供发光数据信号；扫描驱动器11被配置为分别通过第一选通信号线、第二选通信号线以及第三选通信号线向像素电路100提供第一选通信号G1、第二选通信号G2以及第三选通信号G3。时序控制器13配置为为系统提供时钟信号，从而协调系统的工作。
例如，显示面板10还包括第一扫描信号线、第二扫描信号线和控制信号线。扫描驱动器还被配置为分别通过第一扫描信号线、第二扫描信号线和控制信号线向像素电路100提供第一扫描信号Scan1、第二扫描信号Scan2和控制信号Em。
例如，图5是本公开实施例提供的一种显示设备的示意图。本公开的实施例还提供一种显示设备1，如图5所示，显示设备1包括本公开任一实施例提供的显示面板10。
例如，本公开实施例提供的显示设备可以包括手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例还提供一种驱动本公开任一实施例提供的像素电路100的方法，该方法包括：在一帧显示时间内包括多个时段，在每个时段内驱动一个发光子电路。也就是说，多个发光子电路在一帧显示时间内被分时驱动发光。
例如，图6是本公开实施例提供的驱动方法的驱动波形图。本公开的实施例还提供一种驱动本公开任一实施例提供的像素电路100的方法，该方法包括：在一帧显示时间内包括第一时段、第二时段和第三时段。第一时段包括第一复位时段t12、第一补偿时段t13和第一发光时段t14；第二时段包括第二复位时段t22、第二补偿时段t23和第二发光时段t24；第三时段包括第三复位时段t32、第三补偿时段t33和第三发光时段t34；在第一发光时段t14，驱动第一有机发光二极管OLED1发光；在第二发光时段t24，驱动第二有机发光二极管OLED2发光；在第三发光时段t34，驱动第三有机发光二极管OLED3发光。
例如，在本公开任一实施例提供的驱动方法中，在第一复位时段t12之前，第一时段还包括第一准备时段t11；在第二复位时段t22之前，第二时段还包括第二准备时段t21；在第三复位时段t32之前，第三时段还包括第三准备时段t31。
例如，如图6所示，在本公开任一实施例提供的驱动方法中，驱动信号设置如下。
例如，本公开实施例中的开启电压是指能使相应晶体管第一极和第二级导通的电压，关闭电压是指能使相应晶体管的第一极和第二级断开的电压。当晶体管为P型晶体管时，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)；当晶体管为N型晶体管时，开启电压为高电压(例如，5V)，关闭电压为低电压(例如，0V)。图6中所示的驱动波形均以P型晶体管为例进行说明，即开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)。
例如，在第一时段中，在第一准备时段t11，设置控制信号Em为关闭电压，设置第一扫描信号Scan1为关闭电压，设置第二扫描信号Scan2为关闭电压，设置第一选通信号G1为关闭电压，设置第二选通信号G2为关闭电压，设置第三选通信号G3为关闭电压；在第一复位时段t12，设置控制信号Em为开启电压，设置第一扫描信号Scan1为关闭电压，设置第二扫描信号Scan2为关闭电压，设置第一选通信号G1为关闭电压，设置第二选通信号G2为关闭电压，设置第三选通信号G3为关闭电压；在第一补偿时段t13，设置控制信号Em为关闭电压，设置第一扫描信号Scan1为开启电压，设置第二扫描 信号Scan2为关闭电压，设置第一选通信号G1为关闭电压，设置第二选通信号G2为关闭电压，设置第三选通信号G3为关闭电压；在第一发光时段t14，设置控制信号Em为关闭电压，设置第一扫描信号Scan1为关闭电压，设置第二扫描信号Scan2为开启电压，设置第一选通信号G1为开启电压，设置第二选通信号G2为关闭电压，设置第三选通信号G3为关闭电压。
例如，在第二时段中，在第二准备时段t21，设置控制信号Em为关闭电压，设置第一扫描信号Scan1为关闭电压，设置第二扫描信号Scan2为关闭电压，设置第一选通信号G1为关闭电压，设置第二选通信号G2为关闭电压，设置第三选通信号G3为关闭电压；在第二复位时段t22，设置控制信号Em为开启电压，设置第一扫描信号Scan1为关闭电压，设置第二扫描信号Scan2为关闭电压，设置第一选通信号G1为关闭电压，设置第二选通信号G2为关闭电压，设置第三选通信号G3为关闭电压；在第二补偿时段t23，设置控制信号Em为关闭电压，设置第一扫描信号Scan1为开启电压，设置第二扫描信号Scan2为关闭电压，设置第一选通信号G1为关闭电压，设置第二选通信号G2为关闭电压，设置第三选通信号G3为关闭电压；在第二发光时段t24，设置控制信号Em为关闭电压，设置第一扫描信号Scan1为关闭电压，设置第二扫描信号Scan2为开启电压，设置第一选通信号G1为关闭电压，设置第二选通信号G2为开启电压，设置第三选通信号G3为关闭电压。
例如，在第三时段中，在第三准备时段t31，设置控制信号Em为关闭电压，设置第一扫描信号Scan1为关闭电压，设置第二扫描信号Scan2为关闭电压，设置第一选通信号G1为关闭电压，设置第二选通信号G2为关闭电压，设置第三选通信号G3为关闭电压；在第三复位时段t32，设置控制信号Em为开启电压，设置第一扫描信号Scan1为关闭电压，设置第二扫描信号Scan2为关闭电压，设置第一选通信号G1为关闭电压，设置第二选通信号G2为关闭电压，设置第三选通信号G3为关闭电压；在第三补偿时段t33，设置控制信号Em为关闭电压，设置第一扫描信号Scan1为开启电压，设置第二扫描信号Scan2为关闭电压，设置第一选通信号G1为关闭电压，设置第二选通信号G2为关闭电压，设置第三选通信号G3为关闭电压；在第三发光时段t34，设置控制信号Em为关闭电压，设置第一扫描信号Scan1为关闭电压，设置第二扫描信号Scan2为开启电压，设置第一选通信号G1为关闭电压，设置 第二选通信号G2为关闭电压，设置第三选通信号G3为开启电压。
例如，以下结合图3和图6对像素电路的工作过程进行介绍。以第一时段为例，在第一准备时段t11，控制信号Em为关闭电压，第一扫描信号Scan1为关闭电压，第二扫描信号Scan2为关闭电压，第一选通信号G1为关闭电压，第二选通信号G2为关闭电压，第三选通信号G3为关闭电压。因此，第一开关晶体管M1、第二开关晶体管M2、第三开关晶体管M3、第一补偿晶体管T1、第二补偿晶体管T2、第三补偿晶体管T3、第四补偿晶体管T4和第五补偿晶体管T5均处于关闭状态。第一准备时段可以为像素电路提供一个稳定的过程，防止电路因寄生电容放电不完全等影响导致的电路异常。
在第一复位时段t12，控制信号Em为开启电压，第一扫描信号Scan1为关闭电压，第二扫描信号Scan2为关闭电压，第一选通信号G1为关闭电压，第二选通信号G2为关闭电压，第三选通信号G3为关闭电压。因此，第三补偿晶体管T3导通，第一开关晶体管M1、第二开关晶体管M2、第三开关晶体管M3、第一补偿晶体管T1、第二补偿晶体管T2、第四补偿晶体管T4和第五补偿晶体管T5均处于关闭状态。存储电容C两端的电压被初始化为第二电源电压Vint(例如，第二电源电压Vint可以为一个稳定的低电压或接地电压)，实现了像素电路的初始化。
在第一补偿时段t13，控制信号Em为关闭电压，第一扫描信号Scan1为开启电压，第二扫描信号Scan2为关闭电压，第一选通信号G1为关闭电压，第二选通信号G2为关闭电压，第三选通信号G3为关闭电压。因此，第二补偿晶体管T2和第四补偿晶体管T4导通，第一开关晶体管M1、第二开关晶体管M2、第三开关晶体管M3、第一补偿晶体管T1、第三补偿晶体管T3和第五补偿晶体管T5均处于关闭状态。发光数据信号Data通过第二补偿晶体管T2、驱动晶体管DT和第四补偿晶体管T4对第三节点N3充电，直到第三节点N3的电压为Vdata+Vth为止，其中，Vdata为发光数据信号Data的电压，Vth为驱动晶体管DT的阈值电压，因为此时满足驱动晶体管DT栅极和源极之间的电压差为Vth。充电完成后，存储电容C两端的电压差为Vdata+Vth。另外，由于第五补偿晶体管T5处于关闭状态，使得电流不会通过OLED，避免OLED在此时段发光，提升了显示效果，降低了OLED的损耗。
在第一发光时段t14，控制信号Em为关闭电压，第一扫描信号Scan1为关闭电压，第二扫描信号Scan2为开启电压，第一选通信号G1为开启电压，第二选通信号G2为关闭电压，第三选通信号G3为关闭电压。因此，第一开关晶体管M1、第一补偿晶体管T1和第五补偿晶体管T5导通，第二开关晶体管M2、第三开关晶体管M3、第二补偿晶体管T2、第三补偿晶体管T3和第四补偿晶体管T4均处于关闭状态。在第一发光时段中，由于存储电容C的作用，第三节点N3的电压保持在Vdata+Vth，发光电流IOLED流经第一补偿晶体管T1、驱动晶体管DT、第五补偿晶体管T5和第一开关晶体管M1和第一有机发光二极管OLED1，第一有机发光二极管OLED1发光。发光电流IOLED满足如下饱和电流公式：
IOLED＝K(VGS-Vth)2
＝K(Vdata+Vth-Vdd-Vth)2
＝K(Vdata-Vdd)2
其中，
Figure PCTCN2017077982-appb-000001
μn为驱动晶体管的沟道迁移率，Cox为驱动晶体管单位面积的沟道电容，W和L分别为驱动晶体管的沟道宽度和沟道长度，VGS为驱动晶体管的栅源电压(驱动晶体管的栅极电压与源极电压之差)。
由上式中可以看到发光电流IOLED已经不受驱动晶体管的阈值电压Vth的影响，只与发光数据信号的电压Vdata以及第一电源电压Vdd有关。解决了驱动晶体管阈值电压漂移的问题，保证了OLED显示面板的正常工作。
例如，第二时段中第二有机发光二极管OLED2的工作过程以及第三时段中第三有机发光二极管OLED3的工作过程与第一时段类似，在此不再赘述。
需要说明的是，在本公开的实施例还提供一种驱动本公开任一实施例提供的像素电路的方法包括但不局限于上述情形。例如，发光电路还包括第四发光子电路，第四发光子电路包括第四有机发光二极管；在一帧显示时间内还包括第四时段，在第四发光时段，驱动第四有机发光二极管OLED3发光。
本公开的实施例提供一种像素电路、显示面板、显示设备及驱动方法，采用多个子像素共享至少部分补偿像素电路的方式，并且通过场序驱动方式，使得像素在一帧图像的显示时间内，多个子像素(例如，红色、绿色和蓝色 三种颜色的子像素)分时显示，也就是说，用一个补偿驱动电路分时驱动多个发光子电路发光。这种设置节省了补偿驱动电路的数量，压缩了补偿驱动电路占用的背板空间，从而提高了显示面板的分辨率。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
本专利申请要求于2016年8月12日递交的中国专利申请第201610663613.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种像素电路，包括：
    发光电路，所述发光电路包括多个发光子电路；
    补偿驱动电路，包括输出端和驱动晶体管，其中，所述多个发光子电路均与所述输出端电连接，所述补偿驱动电路被配置为接收发光数据信号、补偿所述驱动晶体管的阈值电压以及根据所述输出端输出的输出信号驱动任意一个所述发光子电路发光。
  2. 根据权利要求1所述的像素电路，还包括选择电路，其中，所述选择电路与所述输出端电连接，所述多个发光子电路分别与所述选择电路电连接，所述补偿驱动电路被配置为通过所述选择电路驱动任意一个所述多个发光子电路发光。
  3. 根据权利要求1所述的像素电路，其中，所述发光电路中的每个发光子电路均包括串联的开关元件和发光元件。
  4. 根据权利要求3所述的像素电路，其中，所述开关元件包括晶体管，所述发光元件包括有机发光二极管。
  5. 根据权利要求1所述的像素电路，其中，所述发光电路包括第一发光子电路、第二发光子电路和第三发光子电路，所述第一发光子电路包括串联的第一开关晶体管和第一有机发光二极管，所述第二发光子电路包括串联的第二开关晶体管和第二有机发光二极管，所述第三发光子电路包括串联的第三开关晶体管和第三有机发光二极管。
  6. 根据权利要求5所述的像素电路，其中，所述第一开关晶体管的第一极、所述第二开关晶体管的第一极、所述第三开关晶体管的第一极与第一节点电连接，所述第一开关晶体管的栅极被配置为接收第一选通信号，所述第二开关晶体管的栅极被配置为接收第二选通信号，所述第三开关晶体管的栅极被配置为接收第三选通信号，所述第一开关晶体管的第二极与所述第一有机发光二极管的第一极电连接，所述第二开关晶体管的第二极与所述第二有机发光二极管的第一极电连接，所述第三开关晶体管的第二极与所述第三有机发光二极管的第一极电连接，所述第一有机发光二极管的第二极、所述第二有机发光二极管的第二极和所述第三有机发光二极管的第二极均接地。
  7. 根据权利要求6所述的像素电路，其中，所述补偿驱动电路还包括：
    第一补偿晶体管，被配置为响应于第二扫描信号向所述驱动晶体管提供第一电源电压；
    第二补偿晶体管，被配置为响应于第一扫描信号向所述驱动晶体管提供所述发光数据信号；
    第三补偿晶体管，被配置为响应于控制信号向所述驱动晶体管提供第二电源电压；
    第四补偿晶体管，被配置为响应于所述第一扫描信号连接所述驱动晶体管的栅极和第二极；
    第五补偿晶体管，被配置为响应于所述第二扫描信号连接所述驱动晶体管的第二极和所述发光电路，以及
    存储电容，被配置为存储所述第三补偿晶体管第一极和第二极之间的电压差。
  8. 根据权利要求7所述的像素电路，其中，
    所述第一补偿晶体管的第一极被配置为接收所述第一电源电压，所述第一补偿晶体管的栅极、所述第五补偿晶体管的栅极被配置为接收所述第二扫描信号，所述第一补偿晶体管的第二极与第二节点电连接；
    所述第二补偿晶体管的第一极被配置为接收所述发光数据信号，所述第二补偿晶体管的栅极、所述第四补偿晶体管的栅极被配置为接收所述第一扫描信号，所述第二补偿晶体管的第二极与所述第二节点电连接；
    所述第三补偿晶体管的第一极被配置为接收所述第二电源电压，所述第三补偿晶体管的栅极被配置为接收所述控制信号，所述第三补偿晶体管的第二极与第三节点电连接；
    所述第四补偿晶体管的第一极与所述第三节点电连接，所述第四补偿晶体管的第二极与第四节点电连接；
    所述第五补偿晶体管的第一极与所述第四节点电连接，所述第五补偿晶体管的第二极与所述第一节点电连接；
    所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的栅极与所述第三节点电连接，所述驱动晶体管的第二极与所述第四节点电连接；
    所述存储电容的第一端被配置为接收所述第二电源电压，所述存储电容 的第二端与所述第三节点电连接。
  9. 根据权利要求7或8所述的像素电路，其中，所述第一开关晶体管、所述第二开关晶体管、所述第三开关晶体管、所述第一补偿晶体管、所述第二补偿晶体管、所述第三补偿晶体管、所述第四补偿晶体管、所述第五补偿晶体管均为P型晶体管。
  10. 根据权利要求7或8所述的像素电路，其中，所述第一开关晶体管、所述第二开关晶体管、所述第三开关晶体管、所述第一补偿晶体管、所述第二补偿晶体管、所述第三补偿晶体管、所述第四补偿晶体管、所述第五补偿晶体管均为薄膜晶体管。
  11. 一种显示面板，包括如权利要求1-10任一项所述的像素电路。
  12. 根据权利要求11所述的显示面板，还包括扫描驱动器、数据驱动器、发光数据信号线、第一选通信号线、第二选通信号线以及第三选通信号线，其中，
    所述数据驱动器被配置为通过所述发光数据信号线向所述像素电路提供发光数据信号；
    所述扫描驱动器被配置为分别通过所述第一选通信号线、第二选通信号线以及第三选通信号线向所述像素电路提供第一选通信号、第二选通信号以及第三选通信号。
  13. 一种显示设备，包括如权利要求11或12所述的显示面板。
  14. 一种驱动如权利要求1-10任一项所述像素电路的方法，包括：在一帧显示时间内包括多个时段，在每个所述时段内驱动一个所述发光子电路。
  15. 一种驱动如权利要求7-10任一项所述像素电路的方法，包括：在一帧显示时间内包括第一时段、第二时段和第三时段，其中，
    所述第一时段包括第一复位时段、第一补偿时段和第一发光时段；
    所述第二时段包括第二复位时段、第二补偿时段和第二发光时段；
    所述第三时段包括第三复位时段、第三补偿时段和第三发光时段；
    在所述第一发光时段，驱动所述第一有机发光二极管发光；
    在所述第二发光时段，驱动所述第二有机发光二极管发光；
    在所述第三发光时段，驱动所述第三有机发光二极管发光。
  16. 根据权利要求15所述的驱动方法，其中，
    在所述第一复位时段之前，所述第一时段还包括第一准备时段；
    在所述第二复位时段之前，所述第二时段还包括第二准备时段；
    在所述第三复位时段之前，所述第三时段还包括第三准备时段。
  17. 根据权利要求16所述的驱动方法，其中，
    在所述第一准备时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；
    在所述第一复位时段，设置控制信号为开启电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；
    在所述第一补偿时段，设置控制信号为关闭电压，设置第一扫描信号为开启电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；
    在所述第一发光时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为开启电压，设置第一选通信号为开启电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；
    在所述第二准备时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；
    在所述第二复位时段，设置控制信号为开启电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；
    在所述第二补偿时段，设置控制信号为关闭电压，设置第一扫描信号为开启电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；
    在所述第二发光时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为开启电压，设置第一选通信号为关闭电压，设置第二选通信号为开启电压，设置第三选通信号为关闭电压；
    在所述第三准备时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压， 设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；
    在所述第三复位时段，设置控制信号为开启电压，设置第一扫描信号为关闭电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；
    在所述第三补偿时段，设置控制信号为关闭电压，设置第一扫描信号为开启电压，设置第二扫描信号为关闭电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为关闭电压；
    在所述第三发光时段，设置控制信号为关闭电压，设置第一扫描信号为关闭电压，设置第二扫描信号为开启电压，设置第一选通信号为关闭电压，设置第二选通信号为关闭电压，设置第三选通信号为开启电压。
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