WO2018233599A1 - 像素电路及其驱动方法、阵列基板和显示装置 - Google Patents

像素电路及其驱动方法、阵列基板和显示装置 Download PDF

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Publication number
WO2018233599A1
WO2018233599A1 PCT/CN2018/091814 CN2018091814W WO2018233599A1 WO 2018233599 A1 WO2018233599 A1 WO 2018233599A1 CN 2018091814 W CN2018091814 W CN 2018091814W WO 2018233599 A1 WO2018233599 A1 WO 2018233599A1
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Prior art keywords
transistor
node
coupled
signal input
control
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PCT/CN2018/091814
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English (en)
French (fr)
Inventor
李俊杰
蔡鹏�
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京东方科技集团股份有限公司
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Priority to US16/336,346 priority Critical patent/US11004388B2/en
Publication of WO2018233599A1 publication Critical patent/WO2018233599A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes

Definitions

  • Embodiments of the present disclosure relate to the field of pixel circuits, and in particular, to a pixel circuit, an array substrate, a display device, and a driving method.
  • OLED Organic Light Emitting Diode
  • LCD liquid crystal display
  • Embodiments of the present disclosure provide a pixel circuit, an array substrate, a display device, and a driving method.
  • a pixel circuit may include a reset circuit, a drive transistor, a data signal write circuit, a compensation circuit, a voltage supply circuit, a control circuit, and a light emitting device.
  • the reset circuit can provide an initialization signal from the initialization signal input terminal to the first node and one end of the light emitting device under the control of the reset signal from the reset signal input terminal.
  • the control electrode of the driving transistor is coupled to the first node, the first pole of the driving transistor is coupled to the second node, the second pole of the driving transistor is coupled to the third node, and the driving transistor is controlled by the voltage of the first node , providing drive current.
  • the data signal writing circuit can provide the data signal from the data signal input terminal to the third node under the control of the strobe signal from the strobe signal input terminal.
  • the second node is coupled to the first node under control of the compensation circuit.
  • the voltage supply circuit can provide a first voltage signal from the first voltage signal input to the second node under control of a control signal from the control signal input.
  • the control circuit can provide a driving current supplied from the driving transistor to the light emitting device under the control of the control signal.
  • the light emitting device can emit light according to the driving current.
  • the reset circuit may include a first transistor and a second transistor.
  • the control electrode of the first transistor is coupled to the reset signal input terminal, the first pole of the first transistor is coupled to the initialization signal input terminal, and the second pole of the first transistor is coupled to the first node.
  • the control electrode of the second transistor is coupled to the reset signal input terminal, the first electrode of the second transistor is coupled to the initialization signal input terminal, and the second electrode of the second transistor is coupled to the light emitting device.
  • the data signal writing circuit may include a third transistor.
  • the control electrode of the third transistor is coupled to the strobe signal input terminal, the first electrode of the third transistor is coupled to the data signal input terminal, and the second electrode of the third transistor is coupled to the third node.
  • the compensation circuit may include a fourth transistor.
  • the control electrode of the fourth transistor is coupled to the strobe signal input terminal, the first electrode of the fourth transistor is coupled to the second node, and the second electrode of the fourth transistor is coupled to the first node.
  • the voltage supply circuit may include a fifth transistor.
  • the control electrode of the fifth transistor is coupled to the control signal input terminal, the first electrode of the fifth transistor is coupled to the first voltage signal input terminal, and the second electrode of the fifth transistor is coupled to the second node.
  • control circuit may include a sixth transistor.
  • the control electrode of the sixth transistor is coupled to the control signal input terminal, the first electrode of the sixth transistor is coupled to the third node, and the second electrode of the sixth transistor is coupled to the light emitting device.
  • the pixel circuit may further include a voltage stabilizing circuit.
  • the voltage stabilizing circuit is configured to stabilize the voltage of the first node.
  • the voltage stabilizing circuit may include a capacitor. One end of the capacitor is coupled to the first voltage signal input end, and the other end of the capacitor is coupled to the first node.
  • a pixel circuit includes a first transistor, a driving transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a light emitting device.
  • the control electrode of the first transistor is coupled to the reset signal input terminal, the first pole of the first transistor is coupled to the initialization signal input terminal, and the second pole of the first transistor is coupled to the first node.
  • the control electrode of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the second node, and the second electrode of the driving transistor is coupled to the third node.
  • the control electrode of the second transistor is coupled to the reset signal input terminal, the first electrode of the second transistor is coupled to the initialization signal input terminal, and the second electrode of the second transistor is coupled to the light emitting device.
  • the control electrode of the third transistor is coupled to the strobe signal input terminal, the first electrode of the second transistor is coupled to the data signal input terminal, and the second electrode of the second transistor is coupled to the third node.
  • the control electrode of the fourth transistor is coupled to the strobe signal input terminal, the first electrode of the fourth transistor is coupled to the second node, and the second electrode of the fourth transistor is coupled to the first node.
  • the control electrode of the fifth transistor is coupled to the control signal input terminal, the first electrode of the fifth transistor is coupled to the first voltage signal input terminal, and the second electrode of the fifth transistor is coupled to the second node.
  • the control electrode of the sixth transistor is coupled to the control signal input terminal, the first electrode of the sixth transistor is coupled to the third node, and the second electrode of the sixth transistor is coupled to the light emitting device. One end of the light emitting device is coupled to the second pole of the sixth transistor.
  • the pixel circuit may further include a capacitor. One end of the capacitor is coupled to the first voltage signal input end, and the other end of the capacitor is coupled to the first node.
  • a method for driving a pixel circuit of the first or second aspect of the present disclosure includes: providing an initialization signal from the initialization signal input terminal to the first node and one end of the light emitting device under control of a reset signal from the reset signal input terminal; under the control of the strobe signal from the strobe signal input terminal, The data signal at the input end of the data signal is supplied to the third node, and the second node is coupled to the first node, and under the control of the voltage of the first node, the driving transistor provides a driving current, and the driving current flows from the second node to the first a node, causing a voltage of the first node to rise; providing a first voltage signal from the input of the first voltage signal to the second node under control of a control signal from the input of the control signal, under the control of the voltage of the first node The driving transistor supplies a driving current, and the light emitting device emits light according to the driving current.
  • an array substrate is provided.
  • the array substrate may include a plurality of pixel circuits of the first aspect or the second aspect of the present disclosure.
  • a display device may include the array substrate of the fourth aspect of the present disclosure.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel circuit
  • FIG. 2 is a schematic diagram of another circuit structure of a pixel circuit
  • FIG. 3 is a schematic block diagram of a pixel circuit in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a schematic block diagram of a pixel circuit in accordance with another embodiment of the present disclosure.
  • FIG. 5 is an exemplary circuit diagram of a pixel circuit in accordance with an embodiment of the present disclosure.
  • FIG. 6 is an exemplary circuit diagram of a pixel circuit in accordance with an embodiment of the present disclosure.
  • FIG. 7 is a timing diagram of signals of a pixel circuit in accordance with an embodiment of the present disclosure.
  • FIG. 8 is an equivalent circuit diagram of a pixel circuit in a first stage according to an embodiment of the present disclosure
  • FIG. 9 is an equivalent circuit diagram of a pixel circuit in a second stage in accordance with an embodiment of the present disclosure.
  • FIG. 10 is an equivalent circuit diagram of a pixel circuit in a third stage according to an embodiment of the present disclosure.
  • FIG. 11 is an exemplary flow chart of a driving method in accordance with an embodiment of the present disclosure.
  • connection is disassembled or connected in one piece; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium.
  • connection is disassembled or connected in one piece; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium.
  • AMOLED Active-matrix organic light emitting diode
  • LCD Liquid Crystal Display
  • LTPS Low Temperature Poly-silicon
  • Figures 1 and 2 show two pixel circuit designs, respectively.
  • the pixel circuits shown in FIGS. 1 and 2 respectively include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a driving transistor DTFT, and a capacitor Cst.
  • the first voltage signal input terminal ELVDD, the data signal input terminal Data, the strobe signal input terminal Gate, the reset signal input terminal Reset, the initialization signal input terminal Vint and the control signal input terminal EM are coupled to control the pixel circuit. The working process.
  • the negative electrode of the light emitting device D is coupled to the second voltage signal input terminal ELVSS (eg, ground), and the positive electrode of the light emitting device D receives the voltage signal input by the first voltage signal input terminal ELVDD, and the light emitting device D emits light.
  • ELVSS the second voltage signal input terminal
  • the positive electrode of the light emitting device D receives the voltage signal input by the first voltage signal input terminal ELVDD, and the light emitting device D emits light.
  • ELVSS eg, ground
  • the stabilization of the gate voltage of the driving transistor DTFT is the key to ensuring uniform brightness of the light-emitting device D.
  • the gate (eg, the gate) of the driving transistor DTFT in the pixel circuit shown in FIG. 1 is coupled to the node A, and the first pole (eg, the source or the drain) of the driving transistor DTFT is coupled to the node B. Then, the second electrode (eg, the drain or the source) of the driving transistor DTFT is coupled to the node C.
  • the node A is also coupled to the first pole of the second transistor M2, and the node C is also coupled to the second pole of the second transistor M2.
  • the gate of the driving transistor DTFT in the pixel circuit shown in FIG. 2 is coupled to the node A.
  • the first electrode of the driving transistor DTFT is coupled to the first voltage signal input terminal ELVDD, and the second electrode of the driving transistor DTFT is coupled to the node C.
  • the node A is also coupled to the first pole of the second transistor M2, and the node C is also coupled to the second pole of the second transistor M2.
  • the voltage of the node A is about the voltage VELVDD of the first voltage signal input terminal ELVDD, and the voltage of the node C is about 0, so that the voltage difference between the node A and the node C is large, and leakage current is easily generated. . Therefore, the voltage of the gate electrode of the driving transistor DTFT is unstable, making the light emission unstable. In addition, the writing position of the data signal input terminal Data of the pixel circuit of FIG. 2 is far from the anode of the LED D, which makes the circuit step difficult.
  • FIG. 3 shows a schematic block diagram of a pixel circuit in accordance with some embodiments of the present disclosure.
  • the pixel circuit 100 may include a reset circuit 10, a driving transistor DTFT, a data signal writing circuit 20, a compensation circuit 30, a voltage supply circuit 40, a control circuit 50, and a light emitting device D.
  • the reset circuit 10 may be coupled to the reset signal input terminal, the initialization signal input terminal, the first node N1, and one end (eg, the positive electrode) of the light emitting device D, respectively.
  • the reset circuit 10 can supply the initialization signal Vint to the first node N1 and one end (for example, the positive electrode) of the light emitting device D under the control of the reset signal Reset from the reset signal input terminal, respectively.
  • a control electrode (eg, a gate) of the driving transistor DTFT is coupled to the first node N1, and a first electrode (eg, a source or a drain) of the driving transistor DTFT is coupled to the second node N2, and a second of the driving transistor DTFT A pole (eg, a drain or a source) is coupled to the third node N3.
  • the driving transistor DTFT can supply a driving current under the control of the voltage of the first node N1.
  • the drive transistor DTFT is a P-type field effect transistor.
  • the drive current of the drive transistor DTFT is related to the voltage difference between the first node N1 and the second node N2.
  • the first pole of the driving transistor DTFT is the drain, and the second pole is Source. Accordingly, the drive current of the drive transistor DTFT is related to the voltage difference between the first node N1 and the third node N3.
  • the data signal writing circuit 20 can be coupled to the strobe signal input terminal, the data signal input terminal, and the third node N3, respectively.
  • the data signal writing circuit 20 can supply the data signal Data from the data signal input terminal to the third node N3 under the control of the selected communication signal Gate from the strobe signal input terminal.
  • the compensation circuit 30 can be coupled to the strobe signal input terminal, the second node N2, and the first node N1, respectively.
  • the compensation circuit 30 can couple the second node N2 to the first node N1 under the strobe signal Gate from the strobe signal input to form a current path.
  • the voltage supply circuit 40 can be coupled to the control signal input terminal, the first voltage signal input terminal, and the second node N2, respectively.
  • the voltage supply circuit 40 can supply the first voltage signal ELVDD from the first voltage signal input terminal to the second node N2 under the control of the control signal EM from the control signal input terminal.
  • the control circuit 50 can be coupled to the control signal input terminal, the third node N3, and the anode of the light emitting device D, respectively.
  • the control circuit 50 can supply the driving current supplied from the driving transistor DTFT to one end (for example, the positive electrode) of the light emitting device D under the control of the control signal EM from the input of the control signal.
  • the control circuit 50 in a state where the data signal writing circuit 20 operates, the control circuit 50 can be controlled to be turned off to prevent the data signal Data from being output to the positive electrode of the light emitting device D, so that the light emitting device D emits light.
  • One end of the light emitting device D (eg, the positive electrode) may be coupled to the control circuit 50, and the other end (eg, the negative electrode) may be coupled to the second voltage signal to receive the second voltage signal ELVSS.
  • the light emitting device D can emit light according to a driving current supplied from the driving transistor DTFT under the control of the control circuit 50 (for example, when the control circuit 50 is turned on).
  • the first node N1 and one end of the light emitting device D are initialized by the reset circuit 10.
  • the data signal Data is written to the third node N3 through the data signal writing circuit 20, so that the voltage of the third node N3 is higher than the voltage of the second node N2, and the driving current supplied from the driving transistor DTFT is The third node N3 flows to the second node N2.
  • the second node N2 is coupled to the first node N2 through the compensation circuit 30, and the driving current supplied from the driving transistor DTFT flows from the second node N2 to the first node N1 to raise the voltage of the first node N1.
  • the voltage of the data signal is Vdata.
  • the driving transistor DTFT is turned off, where Vth is the threshold voltage of the driving transistor DTFT. Then, under the control of the control signal EM, the first voltage signal ELVDD is supplied to the second node N2 through the voltage supply circuit 40, so that the direction of the current supplied from the driving transistor DTFT changes, flowing from the second node N2 to the third node N3.
  • the light emitting device D in turn emits light in accordance with the driving current.
  • the driving current is independent of the threshold voltage of the driving transistor DTFT during the light emission, thereby avoiding the influence of the luminance unevenness on the display due to the deviation and drift of the threshold voltage of the driving transistor DTFT. Since the voltage of the first node N1 (Data+Vth) and the voltage of the second node N2 (ELVDD) are small, the leakage of the compensation circuit 30 can be reduced, thereby facilitating the improvement of the voltage holding capability of the first node N1. Thereby, the voltage of the gate electrode of the driving transistor DTFT is stabilized, so that the light emission of the light emitting device D is stabilized. In addition, the writing position of the data signal Data is one end of the driving transistor DTFT close to the light emitting device D, which can reduce the layout difficulty of the pixel circuit.
  • FIG. 4 shows a schematic block diagram of a pixel circuit in accordance with another embodiment of the present disclosure.
  • the pixel circuit 200 may include a reset circuit 10, a drive transistor DTFT, a data signal write circuit 20, a compensation circuit 30, a voltage supply circuit 40, a control circuit 50, a light emitting device D, and a voltage stabilization circuit 60.
  • the voltage stabilizing circuit 60 can be coupled to the first voltage signal input terminal and the first node N1 to stabilize the voltage of the first node N1. Except for this, the pixel circuit 200 in FIG. 4 has the same structure as the pixel circuit 100 in FIG. 3 and will not be described in detail.
  • the voltage stabilizing circuit 60 can make the voltage of the first node N1 more stable, further stabilizing the voltage of the control electrode of the driving transistor DTFT, thereby making the light emission of the light emitting device D more stable.
  • FIG. 5 illustrates an exemplary circuit diagram of a pixel circuit, such as the pixel circuit 100 illustrated in FIG. 3, in accordance with an embodiment of the present disclosure.
  • the transistor employed may be an N-type transistor or a P-type transistor.
  • the transistor may be an N-type or P-type field effect transistor (MOSFET), or an N-type or P-type bipolar transistor (BJT).
  • MOSFET N-type or P-type field effect transistor
  • BJT N-type or P-type bipolar transistor
  • the gate of the transistor is referred to as the gate. Since the source and the drain of the transistor are symmetrical, the source and the drain are not distinguished, that is, the source of the transistor can be the first pole (or the second pole), and the drain can be the second pole (or the One pole).
  • a P-type field effect transistor (PMOS) is taken as an example for detailed description.
  • the reset circuit 10 may include a first transistor T1 and a second transistor T2.
  • the control electrode of the third transistor T1 is coupled to the reset signal input terminal Reset, the first electrode of the third transistor T1 is coupled to the initialization signal input terminal Vint, and the second electrode of the third transistor T3 is coupled to the first node N1.
  • the control electrode of the second transistor T2 is coupled to the reset signal input terminal Reset, the first electrode of the second transistor T2 is coupled to the initialization signal input terminal Vint, and the second electrode of the second transistor T2 is coupled to the anode of the light emitting device D.
  • the reset signal input to the reset signal input terminal Reset is a low level signal
  • the first transistor T1 and the second transistor T2 are turned on.
  • the initialization signals received from the initialization signal input terminal Vint may be respectively output to the anodes of the first node N1 and the light emitting device D, so that before the next frame data signal is written, The voltage signal of the previous frame is cleared, and the voltages of the positive electrodes of the first node N1 and the light-emitting device D are the voltages of the initialization signals, so as to avoid affecting the writing of the data signals.
  • the data signal writing circuit 20 may include a third transistor T3.
  • the control electrode of the third transistor T3 is coupled to the gate signal input terminal Gate, the first pole of the third transistor T3 is coupled to the data signal input terminal Data, and the second pole of the third transistor T3 is coupled to the third node N3.
  • the third transistor T3 is turned on.
  • the compensation circuit 30 can include a fourth transistor T4.
  • the control electrode of the fourth transistor T4 is coupled to the gate signal input terminal Gate, the first pole of the fourth transistor T4 is coupled to the second node N2, and the second pole of the fourth transistor T4 is coupled to the first node N1.
  • the fourth transistor T4 is turned on.
  • the voltage supply circuit 40 may include a fifth transistor T5.
  • the control electrode of the fifth transistor T5 is coupled to the control signal input terminal EM
  • the first electrode of the fifth transistor T5 is coupled to the first voltage signal input terminal ELVDD
  • the second electrode of the fifth transistor T5 is coupled to the second node N2. .
  • the fifth transistor T5 is turned on.
  • Control circuit 50 can include a sixth transistor T6.
  • the control electrode of the sixth transistor T6 is coupled to the control signal input terminal EM, the first electrode of the sixth transistor T6 is coupled to the third node N3, and the second electrode of the sixth transistor T6 is coupled to the positive electrode of the light emitting device D.
  • the sixth transistor T6 is turned on.
  • the light emitting device D is a light emitting diode such as an organic light emitting diode OLED and an active matrix organic light emitting diode AMOLED.
  • an N-type transistor can also be used to implement the above circuit structure. Accordingly, a high level signal can be employed to control the conduction of each circuit.
  • FIG. 6 shows an exemplary circuit diagram of a pixel circuit, such as pixel circuit 200 as shown in FIG. 4, in accordance with an embodiment of the present invention.
  • the transistor employed may be an N-type transistor or a P-type transistor.
  • the transistor may be an N-type or P-type field effect transistor (MOSFET), or an N-type or P-type bipolar transistor (BJT).
  • MOSFET N-type or P-type field effect transistor
  • BJT N-type or P-type bipolar transistor
  • the gate of the transistor is referred to as the gate. Since the source and the drain of the transistor are symmetrical, the source and the drain are not distinguished, that is, the source of the transistor can be the first pole (or the second pole), and the drain can be the second pole (or the One pole).
  • a P-type field effect transistor (PMOS) is taken as an example for detailed description.
  • the voltage stabilizing circuit 5 may include a capacitor C.
  • a plate of the capacitor C is coupled to the first voltage signal input terminal ELVDD, and the other plate of the capacitor C is coupled to the first node N1.
  • Capacitor C has the function of storing energy. Since the capacitor C needs to charge and discharge for a certain period of time, the voltage across the capacitor C does not change, so that the capacitor C can function as a voltage regulator.
  • FIG. 7 shows a timing diagram of signals in a pixel circuit in accordance with an embodiment of the present disclosure.
  • the working process of the pixel circuit will be briefly described below with reference to the timing relationship of each signal, in conjunction with the equivalent circuit diagram of the pixel circuit shown in FIGS. 8-10.
  • Time1 (initialization phase)
  • the reset signal Reset and the data signal Data are at a low level
  • the strobe signal Gate and the control signal EM are at a high level.
  • the first transistor T1 and the second transistor T2 are turned on.
  • the third transistor T3, the fourth transistor T4, the fifth transistor T5, the driving transistor DTFT, and the sixth transistor T6 are all turned off.
  • the equivalent circuit diagram is shown in Fig. 8. " ⁇ " indicates conduction, and " ⁇ " indicates shutdown.
  • the initialization signal input terminal Vint inputs the initialization signal.
  • the initialization signal is output to the first node N1 through the first transistor T1, and the voltage of the first node N1 is reset to reset the voltage of the first node N1.
  • the initialization signal is output to the positive electrode of the light-emitting device D through the second transistor T2, and the voltage of the positive electrode of the light-emitting device D is reset, and the voltage of the positive electrode of the light-emitting device D is reset.
  • the voltage of the initialization signal is Vvint
  • the voltage of the first node N1 and the anode of the light-emitting device D is Vvint, for example, a low level.
  • the strobe signal Gate is at a low level, and the reset signal Reset, the control signal EM, and the data signal Data are at a high level.
  • the third transistor T3 and the fourth transistor T4 are turned on.
  • the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned off.
  • the equivalent circuit diagram is shown in Fig. 7, " ⁇ " indicates conduction, and " ⁇ " indicates shutdown.
  • the data signal input terminal Data inputs a data signal, and the data signal is supplied to the third node N3 via the third transistor T3.
  • the voltage of the second electrode of the driving transistor DTFT is higher than the voltage of the first electrode, and thus the second source of the driving transistor DTFT coupled to the third node N3.
  • the gate of the driving transistor DTFT is the voltage Vvint (for example, a low level) of the initialization signal, and the driving transistor DTFT is turned on because the voltage difference between the gate and the source is high.
  • the driving current supplied from the driving transistor DTFT flows from the third node N3 to the second node N2, and further flows to the first node N1, so that the voltage of the first node N1 rises.
  • the voltage of the data signal is Vdata.
  • the driving transistor DTFT is turned off, where Vth is the threshold voltage of the driving transistor DTFT.
  • Time3 Time3 (lighting phase)
  • the control signal EM and the data signal Data are at a low level
  • the reset signal Reset and the strobe signal Gate are at a high level.
  • the fifth transistor T5, the driving transistor DTFT, and the sixth transistor T6 are turned on.
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned off.
  • the equivalent circuit diagram is shown in Fig. 8. " ⁇ " indicates conduction, and " ⁇ " indicates shutdown.
  • the first voltage signal input terminal ELVDD supplies the first voltage signal to the second node N2, and the first electrode of the driving transistor DTFT coupled to the second node N2 becomes the source.
  • the direction of the drive current supplied from the driving transistor DTFT changes, which flows from the second node N2 to the third node N3, and is supplied to the light emitting device D via the sixth transistor T6.
  • the light emitting device D emits light in accordance with the driving current.
  • the voltage of the first voltage signal is VELVDD
  • the voltage of the second node N2 is VELVDD.
  • the voltage of the first node N1 maintains the voltage of the Time2 phase, that is, VData+Vth.
  • the driving current IOLED ⁇ CoxW(Vgs ⁇ Vth) 2 /(2L).
  • IOLED ⁇ CoxW(VData-VELVDD) 2 /(2L).
  • the compensation circuit 30 between the first node N1 and the second node N2 of the pixel circuit, when the compensation circuit 30 is turned on, the second node N2 is coupled to the first node N1, and When the voltage supply circuit 40 is turned on, the first voltage signal is output to the second node N2.
  • the voltage difference across the compensation circuit 30 is small during the illumination process, which can reduce the leakage of the compensation circuit 30.
  • the writing position of the data signal is one end of the driving transistor DTFT close to the light emitting device D, which can reduce the layout difficulty of the pixel circuit.
  • the reset circuit 10 By setting the reset circuit 10, the voltages of the anodes of the first node N1 and the light-emitting device D are cleared, and the voltages of the anodes of the first node N1 and the light-emitting device D are the voltages of the initialization signals, so as to avoid affecting the writing of the data signals of the next frame.
  • the voltage stabilizing circuit 60 the voltage of the first node N1 is stabilized, so that the light emission of the light-emitting device D is more stable.
  • FIG. 11 illustrates a method for driving a pixel circuit, such as the pixel circuit 100 and the pixel circuit 200 described above, etc., according to an embodiment of the present disclosure. As shown in Figure 11, the specific process of the method is as follows:
  • Step S901 The initialization signal from the initialization signal input terminal is supplied to the first node and one end of the light emitting device under the control of the reset signal from the reset signal input terminal to initialize the voltage of the first node and the voltage of one end of the light emitting device. .
  • This step corresponds to the first stage of the above embodiment.
  • Step S902 The data signal from the data signal input terminal is supplied to the third node under control of the strobe signal from the strobe signal input terminal, and the second node is coupled to the first node.
  • the drive transistor provides a drive current under the control of the voltage of the first node and the voltage of the third node.
  • the driving current flows from the third node to the second node, and then flows to the first node, so that the voltage of the first node rises.
  • This step corresponds to the second phase of the above embodiment.
  • Step S903 providing a first voltage signal from the first voltage signal input terminal to the second node under the control of the control signal from the control signal input terminal.
  • the drive transistor provides a drive current under the control of the voltage of the first node and the voltage of the second node. The direction of the drive current changes, flowing from the second node to the third node.
  • the light emitting device emits light according to the driving current.
  • This step corresponds to the third stage of the above embodiment.
  • the voltage of the first node and the anode of the light emitting device is cleared by the step S901, and the voltages of the anode of the first node and the light emitting device are voltages of the initialization signal, so as to avoid affecting the data signal.
  • write Through step S902, a data signal is input and the voltage of the first node is increased.
  • the first voltage signal is output to the second node, so that in the low gray level, during the process of illuminating, the voltage difference applied across the compensation circuit is small, and the leakage of the compensation circuit can be reduced.
  • the driving current supplied from the driving transistor is independent of its threshold voltage, thereby avoiding the influence of luminance unevenness caused by deviation or drift of the threshold voltage, thereby making the light emission of the light emitting device stable.
  • an array substrate including a plurality of the above pixel circuits is also provided.
  • a plurality of pixel circuits may be arranged in a matrix shape.
  • inventions of the present disclosure also provide a display device including the above array substrate.
  • the display device can be, for example, a display screen, a mobile phone, a tablet computer, a camera, a wearable device, or the like.

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Abstract

本公开实施例提供了像素电路及其驱动方法、阵列基板和显示装置。像素电路包括：复位电路、驱动晶体管、数据信号写入电路、补偿电路、电压提供电路、控制电路和发光器件。复位电路在复位信号的控制下，将初始化信号提供到第一节点和发光器件的一端。驱动晶体管在第一节点的电压的控制下，提供驱动电流。数据信号写入电路在选通信号的控制下，将数据信号提供到第三节点。补偿电路在选通信号的控制下，将第二节点耦接到第一节点。电压提供电路在控制信号的控制下，将第一电压信号提供到第二节点。控制电路在控制信号的控制下，将驱动晶体管提供的驱动电流提供到发光器件。发光器件根据驱动电流而发光。

Description

像素电路及其驱动方法、阵列基板和显示装置
相关申请的交叉引用
本申请要求于2017年6月22日递交的申请号为201710481256.2的中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及像素电路技术领域，特别是涉及像素电路、阵列基板及显示装置、驱动方法。
背景技术
随着显示技术的进步，相对于传统的液晶显示(Liquid Crystal Display，LCD)装置，新一代的有机发光二极管(Organic Light Emitting Diode，OLED)显示装置具有更低的制造成本，更快的反应速度，更高的对比度，更广的视角，更大的工作温度范围，不需要背光单元，色彩鲜艳及轻薄等优点。因此，OLED显示技术成为当前发展最快的显示技术。
发明内容
本公开实施例提供了像素电路、阵列基板及显示装置、驱动方法。
根据本公开的第一方面，提供了一种像素电路。像素电路可包括复位电路、驱动晶体管、数据信号写入电路、补偿电路、电压提供电路、控制电路和发光器件。复位电路可在来自复位信号输入端的复位信号的控制下，将来自初始化信号输入端的初始化信号提供到第一节点和发光器件的一端。驱动晶体管的控制极与第一节点耦接，驱动晶体管的第一极与第二节点耦接，驱动晶体管的第二极与第三节点耦接，驱动晶体管可在第一节点的电压的控制下，提供驱动电流。数据信号写入电路可在来自选通信号输入端的选通信号的控制下，将来自数据信号输入端的数据信号提供到第三节点。 补偿电路可选通信号的控制下，将第二节点耦接到第一节点。电压提供电路可在来自控制信号输入端的控制信号的控制下，将来自第一电压信号输入端的第一电压信号提供到第二节点。控制电路可在控制信号的控制下，将驱动晶体管提供的驱动电流提供到发光器件。发光器件可根据驱动电流而发光。
在本公开的实施例中，复位电路可包括第一晶体管和第二晶体管。第一晶体管的控制极与复位信号输入端耦接，第一晶体管的第一极与初始化信号输入端耦接，第一晶体管的第二极与第一节点耦接。第二晶体管的控制极与复位信号输入端耦接，第二晶体管的第一极与初始化信号输入端耦接，第二晶体管的第二极与发光器件耦接。
在本公开的实施例中，数据信号写入电路可包括第三晶体管。第三晶体管的控制极与选通信号输入端耦接，第三晶体管的第一极与数据信号输入端耦接，第三晶体管的第二极与第三节点耦接。
在本公开的实施例中，补偿电路可包括第四晶体管。第四晶体管的控制极与选通信号输入端耦接，第四晶体管的第一极与第二节点耦接，第四晶体管的第二极与第一节点耦接。
在本公开的实施例中，电压提供电路可包括第五晶体管。第五晶体管的控制极与控制信号输入端耦接，第五晶体管的第一极与第一电压信号输入端耦接，第五晶体管的第二极与第二节点耦接。
在本公开的实施例中，控制电路可包括第六晶体管。第六晶体管的控制极与控制信号输入端耦接，第六晶体管的第一极与第三节点耦接，第六晶体管的第二极与发光器件耦接。
在本公开的实施例中，像素电路还可包括稳压电路。稳压电路被配置为稳定第一节点的电压。
在本公开的实施例中，稳压电路可包括电容。电容的一端与第一电压信号输入端耦接，电容的另一端与第一节点耦接。
根据本公开的第二方面，提供了一种像素电路。像素电路包括第一晶体管、驱动晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和发光器件。第一晶体管的控制极与复位信号输入端耦接，第一晶体管的第一极与初始化信号输入端耦接，第一晶体管的第二极与第一 节点耦接。驱动晶体管的控制极与第一节点耦接，驱动晶体管的第一极与第二节点耦接，驱动晶体管的第二极与第三节点耦接。第二晶体管的控制极与复位信号输入端耦接，第二晶体管的第一极与初始化信号输入端耦接，第二晶体管的第二极与发光器件耦接。第三晶体管的控制极与选通信号输入端耦接，第二晶体管的第一极与数据信号输入端耦接，第二晶体管的第二极与第三节点耦接。第四晶体管的控制极与选通信号输入端耦接，第四晶体管的第一极与第二节点耦接，第四晶体管的第二极与第一节点耦接。第五晶体管的控制极与控制信号输入端耦接，第五晶体管的第一极与第一电压信号输入端耦接，第五晶体管的第二极与第二节点耦接。第六晶体管的控制极与控制信号输入端耦接，第六晶体管的第一极与第三节点耦接，第六晶体管的第二极与发光器件耦接。发光器件的一端耦接第六晶体管的第二极。
在本公开的实施例中，像素电路还可包括电容。电容的一端与第一电压信号输入端耦接，电容的另一端与第一节点耦接。
根据本公开的第三方面，提供了一种用于驱动本公开的第一方面或第二方面的像素电路的方法。方法包括：在来自复位信号输入端的复位信号的控制下，将来自初始化信号输入端的初始化信号提供到第一节点和发光器件的一端；在来自选通信号输入端的选通信号的控制下，将来自数据信号输入端的数据信号提供到第三节点，并将第二节点耦接到第一节点，以及在第一节点的电压的控制下，驱动晶体管提供驱动电流，驱动电流从第二节点流向第一节点，使得第一节点的电压升高；在来自控制信号输入端的控制信号的控制下，将来自第一电压信号输入端的第一电压信号提供至第二节点，在第一节点的电压的控制下，驱动晶体管提供驱动电流，发光器件根据驱动电流而发光。
根据本公开的第四方面，提供了一种阵列基板。阵列基板可包括多个本公开的第一方面或第二方面的像素电路。
根据本公开的第五方面，提供了一种显示装置。显示装置可包括本公开的第四方面的阵列基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例结合附图而进行简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，而非对本公开实施例的限制，在附图中：
图1是像素电路的一种电路结构示意图；
图2是像素电路的另一种电路结构示意图；
图3是根据本公开实施例的像素电路的示意性框图；
图4是根据本公开的另一实施例的像素电路的示意性框图；
图5是根据本公开实施例的像素电路的示例性电路图；
图6是根据本公开实施例的像素电路的示例性电路图；
图7是根据本公开实施例的像素电路的信号的时序图；
图8是根据本公开实施例的像素电路在第一阶段的等效电路示意图；
图9是根据本公开实施例的像素电路在第二阶段的等效电路示意图；
图10是根据本公开实施例的像素电路在第三阶段的等效电路示意图；
图11是根据本公开实施例的驱动方法的示例性流程图。
具体实施方式
为了使本发明的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本发明的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本发明的一部分实施例，而并非全部的实施例。基于所描述的实施例，本领域的普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本发明的范围。
在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上；术语“上”、“下”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的机或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“连接”、“耦接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
由于柔性显示的市场需求，AMOLED(Active-matrix organic light emitting diode，主动矩阵有机发光二极管)显示技术正在逐步取代传统的LCD(Liquid Crystal Display，液晶显示器)技术。目前其主流的驱动方式是LTPS(Low Temperature Poly-silicon，低温多晶硅)技术。但由于其成膜无法做到完全均匀，所以要对像素电路进行补偿。
图1和图2分别示出了两种像素电路设计。图1和图2示出的像素电路分别包括第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、驱动晶体管DTFT和电容Cst，通过如图所示地与第一电压信号输入端ELVDD、数据信号输入端Data、选通信号输入端Gate、复位信号输入端Reset、初始化信号输入端Vint和控制信号输入端EM耦接，控制像素电路的工作过程。
对于这两种像素电路，发光器件D的负极耦接第二电压信号输入端ELVSS(例如，接地)，发光器件D的正极接收第一电压信号输入端ELVDD输入的电压信号后，发光器件D发光。在低灰阶下，如果发光器件D发光不稳定，则对显示效果的影响较严重。驱动晶体管DTFT的控制极电压的稳定是保证发光器件D的亮度均匀的关键。
具体地，图1示出的像素电路中的驱动晶体管DTFT的控制极(例如，栅极)与节点A耦接，驱动晶体管DTFT的第一极(例如，源极或漏极)与节点B耦接，驱动晶体管DTFT的第二极(例如，漏极或源极)与节点C耦接。节点A还耦接第二晶体管M2的第一极，节点C还耦接第二晶体管M2的第二极。
图2示出的像素电路中的驱动晶体管DTFT的控制极耦接节点A，驱动晶体管DTFT的第一极与第一电压信号输入端ELVDD耦接，驱动晶体 管DTFT的第二极与节点C耦接。节点A还耦接第二晶体管M2的第一极，节点C还耦接第二晶体管M2的第二极。
当发光器件D发光时，节点A的电压约为第一电压信号输入端ELVDD的电压VELVDD，节点C的电压约为0，使得节点A和节点C之间的压差较大，容易产生漏电流。因此，驱动晶体管DTFT的控制极的电压不稳定，使得发光不稳定。此外，图2的像素电路的数据信号输入端Data的写入位置距离发光二极管D的正极较远，使得电路步局难度较大。
图3示出了根据本公开的一些实施例的像素电路的示意性框图。如图3所示，像素电路100可包括复位电路10、驱动晶体管DTFT、数据信号写入电路20、补偿电路30、电压提供电路40、控制电路50和发光器件D。
在本公开的实施例中，复位电路10可分别与复位信号输入端、初始化信号输入端、第一节点N1和发光器件D的一端(例如，正极)耦接。复位电路10可在来自复位信号输入端的复位信号Reset的控制下，将初始化信号Vint分别提供到第一节点N1和发光器件D的一端(例如，正极)。
驱动晶体管DTFT的控制极(例如，栅极)与第一节点N1耦接，驱动晶体管DTFT的第一极(例如，源极或漏极)与第二节点N2耦接，驱动晶体管DTFT的第二极(例如，漏极或源极)与第三节点N3耦接。驱动晶体管DTFT可在第一节点N1的电压的控制下，提供驱动电流。在本发明的实施例中，驱动晶体管DTFT是P型场效应晶体管。在第二节点N2(驱动晶体管DTFT的第一极)的电压高于第三节点N3(驱动晶体管DTFT的第二极)的电压时，驱动晶体管DTFT的第一极是源极，第二极是漏极。此时，驱动晶体管DTFT的驱动电流与第一节点N1和第二节点N2的电压差相关。在第二节点N2(驱动晶体管DTFT的第一极)的电压低于第三节点N3(驱动晶体管DTFT的第二极)的电压时，驱动晶体管DTFT的第一极是漏极，第二极是源极。相应地，驱动晶体管DTFT的驱动电流与第一节点N1和第三节点N3的电压差相关。
数据信号写入电路20可分别与选通信号输入端、数据信号输入端和第三节点N3耦接。数据信号写入电路20可在来自选通信号输入端的选通信 号Gate的控制下，将来自数据信号输入端的数据信号Data提供到第三节点N3。
补偿电路30可分别与选通信号输入端、第二节点N2和第一节点N1耦接。补偿电路30可在来自选通信号输入端的选通信号Gate下，将第二节点N2耦接到第一节点N1，以形成电流路径。
电压提供电路40可分别与控制信号输入端、第一电压信号输入端和第二节点N2耦接。电压提供电路40可在来自控制信号输入端的控制信号EM的控制下，将来自第一电压信号输入端的第一电压信号ELVDD提供到第二节点N2。
控制电路50可分别与控制信号输入端、第三节点N3和发光器件D的正极耦接。控制电路50可在来自控制信号输入端的控制信号EM的控制下，将驱动晶体管DTFT提供的驱动电流提供到发光器件D的一端(例如，正极)。在本发明的实施例中，在数据信号写入电路20工作的状态下，可控制该控制电路50关断，以避免数据信号Data输出到发光器件D的正极，使发光器件D发光。
发光器件D的一端(例如，正极)可耦接控制电路50，另一端(例如，负极)可第二电压信号输入端以接收第二电压信号ELVSS。发光器件D可在控制电路50的控制下(例如，控制电路50导通时)，根据驱动晶体管DTFT提供的驱动电流而发光。
在本发明的实施例中，通过复位电路10对第一节点N1和发光器件D的一端进行初始化。在选通信号Gate的控制下，通过数据信号写入电路20向第三节点N3提供数据信号Data，使得第三节点N3的电压高于第二节点N2的电压，驱动晶体管DTFT提供的驱动电流从第三节点N3流向第二节点N2。此外，通过补偿电路30将第二节点N2耦接到第一节点N2，驱动晶体管DTFT提供的驱动电流从第二节点N2流向第一节点N1，以使第一节点N1的电压升高。数据信号的电压为Vdata。直到第一节点N1的电压升高至VData+Vth，驱动晶体管DTFT关断，其中Vth是驱动晶体管DTFT的阈值电压。然后，在控制信号EM的控制下，通过电压提供电路 40将第一电压信号ELVDD提供到第二节点N2，使得驱动晶体管DTFT提供的电流方向改变，从第二节点N2流向第三节点N3。驱动晶体管DTFT提供的电流与栅源电压(第一节点的电压(VData+Vth)和第二节点的电压(ELVDD)的差)和阈值电压Vth之间的电压差相关，即VData+Vth-ELVDD-Vth＝VData-ELVDD。发光器件D进而根据驱动电流而发光。
因此，在低灰阶下，在发光的过程中，驱动电流与驱动晶体管DTFT的阈值电压无关，从而避免由于驱动晶体管DTFT的阈值电压的偏差和漂移对显示造成亮度不均匀的影响。由于第一节点N1的电压(Data+Vth)和第二节点N2的电压(ELVDD)相差较小，可减少补偿电路30出现漏电的情况，从而有利于提高第一节点N1的电压的保持能力。由此，驱动晶体管DTFT的控制极的电压稳定，从而使得发光器件D的发光稳定。此外，数据信号Data的写入位置为驱动晶体管DTFT靠近发光器件D的一端，可降低像素电路的布局难度。
图4示出了根据本公开的另一实施例的像素电路的示意性框图。如图4所示，像素电路200可包括复位电路10、驱动晶体管DTFT、数据信号写入电路20、补偿电路30、电压提供电路40、控制电路50、发光器件D、以及稳压电路60。稳压电路60可与第一电压信号输入端和第一节点N1耦接，以稳定第一节点N1的电压。除此之外，图4中的像素电路200与图3中的像素电路100的结构相同，不再详细描述。
稳压电路60可使第一节点N1的电压更加稳定，进一步使得驱动晶体管DTFT的控制极的电压稳定，从而使得发光器件D的发光更加稳定。
图5示出了根据本公开的实施例的像素电路的示例性电路图，像素电路例如是图3所示的像素电路100。在实施例中，所采用的晶体管可以是N型晶体管或者P型晶体管。具体地，晶体管可以是N型或P型场效应晶体管(MOSFET)，或者N型或P型双极性晶体管(BJT)。在本发明的实施例中，晶体管的栅极被称为控制极。由于晶体管的源极和漏极是对称的，因此对源极和漏极不做区分，即晶体管的源极可以为第一极(或第二极)， 漏极可以为第二极(或第一极)。
在本发明的实施例中，以P型场效应晶体管(PMOS)为例进行详细的描述。
如图5所示，复位电路10可包括第一晶体管T1和第二晶体管T2。第三晶体管T1的控制极与复位信号输入端Reset耦接，第三晶体管T1的第一极与初始化信号输入端Vint耦接，第三晶体管T3的第二极与第一节点N1耦接。第二晶体管T2的控制极与复位信号输入端Reset耦接，第二晶体管T2的第一极与初始化信号输入端Vint耦接，第二晶体管T2的第二极与发光器件D的正极耦接。在复位信号输入端Reset输入的复位信号为低电平信号时，第一晶体管T1和第二晶体管T2导通。第一晶体管T1和第二晶体管T2导通后，可将从初始化信号输入端Vint接收的初始化信号分别输出到第一节点N1和发光器件D的正极，使得在下一帧数据信号写入之前，对上一帧的电压信号进行清除，第一节点N1和发光器件D的正极的电压均为初始化信号的电压，避免影响数据信号的写入。
数据信号写入电路20可包括第三晶体管T3。第三晶体管T3的控制极与选通信号输入端Gate耦接，第三晶体管T3的第一极与数据信号输入端Data耦接，第三晶体管T3的第二极与第三节点N3耦接。在选通信号输入端Gate输入的选通信号为低电平信号时，第三晶体管T3导通。
补偿电路30可包括第四晶体管T4。第四晶体管T4的控制极与选通信号输入端Gate耦接，第四晶体管T4的第一极与第二节点N2耦接，第四晶体管T4的第二极与第一节点N1耦接。在选通信号输入端Gate输入的选通信号为低电平信号时，第四晶体管T4导通。
电压提供电路40可包括第五晶体管T5。第五晶体管T5的控制极与控制信号输入端EM耦接，第五晶体管T5的第一极与第一电压信号输入端ELVDD耦接，第五晶体管T5的第二极与第二节点N2耦接。在控制信号输入端EM输入的控制信号为低电平信号时，第五晶体管T5导通。
控制电路50可包括第六晶体管T6。第六晶体管T6的控制极与控制信号输入端EM耦接，第六晶体管T6的第一极与第三节点N3耦接，第六晶 体管T6的第二极与发光器件D的正极耦接。在控制信号输入端EM输入的控制信号为低电平信号时，第六晶体管T6导通。
发光器件D为发光二极管，例如有机发光二极管OLED和主动矩阵有机发光二极管AMOLED等。
此外，也可采用N型晶体管来实现上述电路结构。相应地，可采用高电平信号来控制各电路的导通。
图6示出了根据本发明的实施例的像素电路的示例性电路图，像素电路例如是如图4所示的像素电路200。在实施例中，所采用的晶体管可以是N型晶体管或者P型晶体管。具体地，晶体管可以是N型或P型场效应晶体管(MOSFET)，或者N型或P型双极性晶体管(BJT)。在本发明的实施例中，晶体管的栅极被称为控制极。由于晶体管的源极和漏极是对称的，因此对源极和漏极不做区分，即晶体管的源极可以为第一极(或第二极)，漏极可以为第二极(或第一极)。
在本发明的实施例中，以P型场效应晶体管(PMOS)为例进行详细的描述。
如图6所示，稳压电路5可包括电容C。电容C的一极板与第一电压信号输入端ELVDD耦接，电容C的另一极板与第一节点N1耦接。电容C具有储能的作用。由于电容C充电和放电都需要一定的时间，因此电容C两端的电压不会突变，使得电容C可以起到稳压的作用。
图6所示的像素电路的其它部分已在上文中描述，在此不再赘述。
图7示出了根据本公开实施例的像素电路中的信号的时序图。下面对各信号的时序关系，结合图8～10示出的像素电路在各个阶段的等效电路示意图，对像素电路的工作过程进行简要说明。
在第一阶段Time1(初始化阶段)，复位信号Reset和数据信号Data处于低电平，选通信号Gate和控制信号EM处于高电平。第一晶体管T1和第二晶体管T2导通。第三晶体管T3、第四晶体管T4、第五晶体管T5、驱动晶体管DTFT和第六晶体管T6均关断。等效电路示意图如图8所示，“○”表示导通，“×”表示关断。在Time1阶段，初始化信号输入端Vint 输入初始化信号。该初始化信号通过第一晶体管T1输出到第一节点N1，对第一节点N1的电压进行重置，使第一节点N1的电压复位。此外，初始化信号通过第二晶体管T2输出到发光器件D的正极，对发光器件D的正极的电压进行重置，使发光器件D的正极的电压复位。在示例中，初始化信号的电压为Vvint，则第一节点N1和发光器件D的正极的电压为Vvint，例如为低电平。
在第二阶段Time2(补偿阶段)，选通信号Gate处于低电平，复位信号Reset、控制信号EM和数据信号Data处于高电平。第三晶体管T3和第四晶体管T4导通。第一晶体管T1、第二晶体管T2、第五晶体管T5和第六晶体管T6关断。等效电路示意图如图7所示，“○”表示导通，“×”表示关断。在Time2阶段，数据信号输入端Data输入数据信号，数据信号经由第三晶体管T3被提供到第三节点N3。此时，驱动晶体管DTFT的第二极的电压比第一极的电压高，因此与第三节点N3耦接的驱动晶体管DTFT的第二极为源极。开始时，驱动晶体管DTFT的栅极为初始化信号的电压Vvint(例如，低电平)，由于栅极与源极之间的电压差较高，驱动晶体管DTFT导通。驱动晶体管DTFT提供的驱动电流从第三节点N3流向第二节点N2，进而流向第一节点N1，使得第一节点N1的电压升高。数据信号的电压为Vdata。在第一节点N1的电压升高至VData+Vth时，驱动晶体管DTFT关断，其中Vth是驱动晶体管DTFT的阈值电压。
在第三阶段Time3(发光阶段)，控制信号EM和数据信号Data处于低电平，复位信号Reset和选通信号Gate处于高电平。第五晶体管T5、驱动晶体管DTFT和第六晶体管T6导通。第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4均关断。等效电路示意图如图8所示，“○”表示导通，“×”表示关断。在Time3阶段，第一电压信号输入端ELVDD将第一电压信号提供到第二节点N2，与第二节点N2耦接的驱动晶体管DTFT的第一极成为源极。驱动晶体管DTFT提供的驱动电流的方向改变，其从第二节点N2流向第三节点N3，并且经由第六晶体管T6被提供到发光器件D。发光器件D根据驱动电流而发光。第一电压信号的电压为 VELVDD，则第二节点N2的电压为VELVDD。第一节点N1的电压保持Time2阶段的电压，即VData+Vth。驱动电流IOLED＝μCoxW(Vgs-Vth) 2/(2L)。其中，Vgs＝Vg-Vs＝VData+Vth-VELVDD，则Vgs-Vth＝VData+Vth-VELVDD-Vth＝VData-VELVDD，IOLED＝μCoxW(VData-VELVDD) 2/(2L)。由此，驱动电流IOLED不会受到驱动晶体管DTFT的阈值电压的影响，进一步提高了发光的稳定性。在低灰阶的情况下，要求IOLED较小，从而控制VData与VELVDD的差值较小，来实现较小的IOLED。由于降低了第一节点N1和第二节点N2之间的电压差，因此可减少第四晶体管T4出现漏电的情况。
根据本公开实施例，通过在像素电路的第一节点N1和第二节点N2之间设置补偿电路30，在补偿电路30导通时，将第二节点N2耦接到第一节点N1，并且在电压提供电路40导通时，将第一电压信号输出到第二节点N2。由此，在低灰阶下，在发光的过程中，补偿电路30两端的电压差较小，可减少补偿电路30出现漏电的情况。以此方式，有利于提高第一节点N1的电压的保持能力，使得驱动晶体管DTFT的控制极的电压稳定，从而使得发光器件D的发光稳定。此外，数据信号的写入位置为驱动晶体管DTFT靠近发光器件D的一端，可降低像素电路的布局难度。通过设置复位电路10，对第一节点N1和发光器件D的正极的电压进行清除，第一节点N1和发光器件D的正极的电压均为初始化信号的电压，避免影响下一帧数据信号的写入。此外，通过设置稳压电路60，稳定第一节点N1的电压，使得发光器件D的发光更加稳定。
图11示出了根据本公开实施例的用于驱动像素电路的方法，像素电路例如是以上描述的像素电路100和像素电路200等。如图11所示，该方法的具体过程如下：
步骤S901：在来自复位信号输入端的复位信号的控制下，将来自初始化信号输入端的初始化信号提供到第一节点和发光器件的一端，以对第一节点的电压和发光器件的一端的电压进行初始化。
该步骤对应上述实施例的第一阶段。
步骤S902：在来自选通信号输入端的选通信号的控制下，将来自数据信号输入端的数据信号提供到第三节点，并将第二节点耦接到第一节点。在第一节点的电压和第三节点的电压的控制下，驱动晶体管提供驱动电流。驱动电流从第三节点流向第二节点，进而流向第一节点，使得第一节点的电压升高。
该步骤对应上述实施例的第二阶段。
步骤S903：在来自控制信号输入端的控制信号的控制下，将来自第一电压信号输入端的第一电压信号提供至第二节点。在第一节点的电压和第二节点的电压的控制下，驱动晶体管提供驱动电流。驱动电流的方向改变，从第二节点流向第三节点。发光器件根据驱动电流而发光。
该步骤对应上述实施例的第三阶段。
综上，本公开实施例的方法，通过步骤S901，对第一节点和发光器件的正极的电压进行清除，第一节点和发光器件的正极的电压均为初始化信号的电压，避免影响数据信号的写入。通过步骤S902，输入数据信号，并提高第一节点的电压。通过步骤S903，将第一电压信号输出到第二节点，从而使得低灰阶下，在发光的过程中，加载在补偿电路两端的压差较小，可减少补偿电路出现漏电的情况。由此，有利于提高第一节点的电压的保持能力，使得驱动晶体管的控制极的电压稳定。此外，驱动晶体管提供的驱动电流与其阈值电压无关，从而避免阈值电压的偏差或漂移造成的亮度不均匀的影响，从而使得发光器件的发光稳定。
根据本公开的实施例，还提供了包括多个上述像素电路的阵列基板。在实施例中，多个像素电路可被设置为矩阵状。
另一方面，本公开实施例还提供了一种包括以上阵列基板的显示装置。显示装置例如可以是显示屏、移动电话、平板计算机、照相机、可穿戴式设备等。
在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含” 或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者终端设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者终端设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者终端设备中还存在另外的相同要素。
以上对本发明的若干实施方式进行了详细描述，但本发明的保护范围并不限于此。显然，对于本领域的普通技术人员来说，在不脱离本发明的精神和范围的情况下，可以对本发明的实施例进行各种修改、替换或变形。本发明的保护范围由所附权利要求限定。

Claims (13)

  1. 一种像素电路，包括：复位电路、驱动晶体管、数据信号写入电路、补偿电路、电压提供电路、控制电路和发光器件；其中，
    所述复位电路被配置为在来自复位信号输入端的复位信号的控制下，将来自初始化信号输入端的初始化信号提供到第一节点和所述发光器件的一端；
    所述驱动晶体管的控制极与所述第一节点耦接，所述驱动晶体管的第一极与第二节点耦接，所述驱动晶体管的第二极与第三节点耦接，所述驱动晶体管被配置为在所述第一节点的电压的控制下，提供驱动电流；
    所述数据信号写入电路被配置为在来自选通信号输入端的选通信号的控制下，将来自数据信号输入端的数据信号提供到所述第三节点；
    所述补偿电路被配置为在所述选通信号的控制下，将所述第二节点耦接到所述第一节点；
    所述电压提供电路被配置为在来自控制信号输入端的控制信号的控制下，将来自第一电压信号输入端的第一电压信号提供到所述第二节点；
    所述控制电路被配置为在所述控制信号的控制下，将所述驱动晶体管提供的驱动电流提供到所述发光器件；
    所述发光器件被配置为根据所述驱动电流而发光。
  2. 根据权利要求1所述的像素电路，其中，所述复位电路包括：
    第一晶体管，所述第一晶体管的控制极与所述复位信号输入端耦接，所述第一晶体管的第一极与所述初始化信号输入端耦接，所述第一晶体管的第二极与所述第一节点耦接；以及
    第二晶体管，所述第二晶体管的控制极与所述复位信号输入端耦接，所述第二晶体管的第一极与所述初始化信号输入端耦接，所述第二晶体管的第二极与所述发光器件耦接。
  3. 根据权利要求1所述的像素电路，其中，所述数据信号写入电路包括：
    第三晶体管，所述第三晶体管的控制极与所述选通信号输入端耦接，所述第三晶体管的第一极与所述数据信号输入端耦接，所述第三晶体管的 第二极与所述第三节点耦接。
  4. 根据权利要求1所述的像素电路，其中，所述补偿电路包括：
    第四晶体管，所述第四晶体管的控制极与所述选通信号输入端耦接，所述第四晶体管的第一极与所述第二节点耦接，所述第四晶体管的第二极与所述第一节点耦接。
  5. 根据权利要求1所述的像素电路，其中，所述电压提供电路包括：
    第五晶体管，所述第五晶体管的控制极与所述控制信号输入端耦接，所述第五晶体管的第一极与所述第一电压信号输入端耦接，所述第五晶体管的第二极与所述第二节点耦接。
  6. 根据权利要求1所述的像素电路，其中，所述控制电路包括：
    第六晶体管，所述第六晶体管的控制极与所述控制信号输入端耦接，所述第六晶体管的第一极与所述第三节点耦接，所述第六晶体管的第二极与所述发光器件耦接。
  7. 根据权利要求1至6任一项所述的像素电路，还包括：
    稳压电路，所述稳压电路被配置为稳定所述第一节点的电压。
  8. 根据权利要求7所述的像素电路，其中，所述稳压电路包括：
    电容，所述电容的一端与所述第一电压信号输入端耦接，所述电容的另一端与所述第一节点耦接。
  9. 一种像素电路，包括：
    第一晶体管，所述第一晶体管的控制极与复位信号输入端耦接，所述第一晶体管的第一极与初始化信号输入端耦接，所述第一晶体管的第二极与第一节点耦接；
    驱动晶体管，所述驱动晶体管的控制极与所述第一节点耦接，所述驱动晶体管的第一极与第二节点耦接，所述驱动晶体管的第二极与第三节点耦接；
    第二晶体管，所述第二晶体管的控制极与所述复位信号输入端耦接，所述第二晶体管的第一极与所述初始化信号输入端耦接，所述第二晶体管的第二极与发光器件耦接；
    第三晶体管，所述第三晶体管的控制极与选通信号输入端耦接，所述 第二晶体管的第一极与数据信号输入端耦接，所述第二晶体管的第二极与所述第三节点耦接；
    第四晶体管，所述第四晶体管的控制极与所述选通信号输入端耦接，所述第四晶体管的第一极与所述第二节点耦接，所述第四晶体管的第二极与所述第一节点耦接；
    第五晶体管，所述第五晶体管的控制极与所述控制信号输入端耦接，所述第五晶体管的第一极与所述第一电压信号输入端耦接，所述第五晶体管的第二极与所述第二节点耦接；
    第六晶体管，所述第六晶体管的控制极与所述控制信号输入端耦接，所述第六晶体管的第一极与所述第三节点耦接，所述第六晶体管的第二极与所述发光器件耦接；以及
    发光器件，所述发光器件的一端耦接所述第六晶体管的第二极。
  10. 根据权利要求9所述的像素电路，还包括：
    电容，所述电容的一端与所述第一电压信号输入端耦接，所述电容的另一端与所述第一节点耦接。
  11. 一种方法，用于驱动如权利要求1至10任一项所述的像素电路，所述方法包括：
    在来自复位信号输入端的复位信号的控制下，将来自初始化信号输入端的初始化信号提供到第一节点和发光器件的一端；
    在来自选通信号输入端的选通信号的控制下，将来自数据信号输入端的数据信号提供到第三节点，并将第二节点耦接到所述第一节点，以及在所述第一节点的电压的控制下，驱动晶体管提供驱动电流，所述驱动电流从所述第二节点流向所述第一节点，使得所述第一节点的电压升高；以及
    在来自控制信号输入端的控制信号的控制下，将来自第一电压信号输入端的第一电压信号提供至所述第二节点，在所述第一节点的电压的控制下，所述驱动晶体管提供驱动电流，发光器件根据所述驱动电流而发光。
  12. 一种阵列基板，包括：多个如权利要求1至10任一项所述的像素电路。
  13. 一种显示装置，包括：如权利要求13所述的阵列基板。
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