WO2018010496A1 - 发光二极管显示阵列及其制作方法、可穿戴设备 - Google Patents

发光二极管显示阵列及其制作方法、可穿戴设备 Download PDF

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Publication number
WO2018010496A1
WO2018010496A1 PCT/CN2017/085884 CN2017085884W WO2018010496A1 WO 2018010496 A1 WO2018010496 A1 WO 2018010496A1 CN 2017085884 W CN2017085884 W CN 2017085884W WO 2018010496 A1 WO2018010496 A1 WO 2018010496A1
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unit
metal block
substrate
pixel
units
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PCT/CN2017/085884
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English (en)
French (fr)
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张博
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京东方科技集团股份有限公司
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Priority to US15/566,054 priority Critical patent/US10263153B2/en
Publication of WO2018010496A1 publication Critical patent/WO2018010496A1/zh

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Definitions

  • Embodiments of the present disclosure relate to a light emitting diode display array, a method of fabricating the same, and a wearable device.
  • small electronic devices are small in size, such as wearable devices. Due to the small size of small electronic devices, the display screen of small electronic devices is also small, and the LED display array can make a smaller display screen, so small electronic devices can use the LED display array to make the display screen.
  • Embodiments of the present disclosure relate to a light emitting diode display array, a method of fabricating the same, and a wearable device, which can solve the problem that the LED display array is developed to a smaller size due to a pressure welding process.
  • an LED display array comprising:
  • first substrate and a second substrate are oppositely disposed;
  • each pixel unit on the first substrate corresponds to a driving unit on the second substrate
  • a metal block is formed between each of the pixel units and a corresponding driving unit thereof, and the metal block electrically connects the pixel unit and its corresponding driving unit.
  • a first adhesion layer is formed between each of the pixel units and the corresponding metal block;
  • a second adhesive layer is formed between each of the driving units and the corresponding metal block.
  • the material of the first adhesive layer is a solder paste, and the material of the second adhesive layer is a nickel gold alloy; or the material of the first adhesive layer is a nickel gold alloy, and the material of the second adhesive layer is tin. paste.
  • a common electrode layer is further formed on a side of the first substrate facing the second substrate;
  • the at least one pixel unit and the at least one electrode unit are formed on the common electrode layer, and each electrode unit on the common electrode layer corresponds to a driving unit on the second substrate,
  • the at least one pixel unit is disposed on the common electrode layer in one or more rows, each row further includes an electrode unit at an end position of the row, and the electrode units are all located in the same column;
  • a metal block is formed between each of the electrode units and the corresponding driving unit, and is configured to electrically connect the electrode unit and its corresponding driving unit.
  • the shape of the metal block is a sphere.
  • the material of the metal block is metal indium.
  • each of the pixel units includes a light emitting layer and a reflective layer
  • the light emitting layer is formed on a side of the first substrate facing the second substrate, and the reflective layer is formed on a side of the light emitting layer away from the first substrate.
  • Embodiments of the present disclosure also provide a wearable device that includes the light emitting diode display array.
  • An embodiment of the present disclosure further provides a method for fabricating an LED display array, the method comprising:
  • each pixel unit on the first substrate corresponding to a driving unit on the second substrate;
  • a metal block is formed between each of the pixel units and a corresponding driving unit thereof, the metal block electrically connecting the pixel unit and its corresponding driving unit.
  • a metal block is formed on each of the at least one pixel unit; a metal block on each of the pixel units is respectively docked with a corresponding driving unit of each of the pixel units, so that the a metal block is located between the pixel unit and a corresponding driving unit of the pixel unit; performing a reflow soldering process on the pixel unit, a driving unit corresponding to the pixel unit, and a metal block located therebetween
  • the metal block electrically connects the pixel unit and its corresponding drive unit.
  • a first adhesion layer is formed on each of the at least one pixel unit
  • a metal block is formed on the first adhesion layer on each of the pixel units.
  • the metal blocks on each of the pixel units are respectively docked with the second adhesive layer on the driving unit corresponding to each of the pixel units.
  • a layer of solder resist is coated on the first adhesion layer on each of the pixel units.
  • a metal block of a cubic structure is formed on the first adhesion layer on each of the pixel units,
  • the metal block on each of the pixel units is formed into a spherical structure by a reflow annealing process under the aid of a solder resist.
  • the material of the first adhesive layer is a nickel gold alloy
  • the material of the second adhesive layer is a solder paste.
  • a second adhesive layer is formed on each of the at least one driving unit
  • a metal block is formed on the second adhesive layer on each of the driving units.
  • the metal blocks on each of the driving units are respectively docked with the first adhesive layer on the pixel unit corresponding to each of the driving units.
  • a layer of solder resist is applied to the second adhesion layer on each of the driving units.
  • a metal block of a cubic structure is formed on the second adhesion layer on each of the driving units,
  • the metal block on each of the driving units is formed into a spherical structure by a reflow annealing process under the aid of a solder resist.
  • the material of the second adhesive layer is a nickel gold alloy
  • the material of the first adhesive layer is a solder paste
  • a common electrode layer is formed on one side of the first substrate
  • each electrode unit on the common electrode layer corresponding to a driving unit on the second substrate, the at least one pixel
  • the unit is disposed on the common electrode layer in one or more rows, each row further including An electrode unit located at the end of the row, the electrode units are all in the same column;
  • a metal block is formed between each of the electrode units and a drive unit corresponding thereto, the metal block electrically connecting the electrode unit and its corresponding drive unit.
  • FIG. 1 is a schematic structural view of a cross section of an LED display array according to Embodiment 1 of the present disclosure
  • FIG. 2 is a schematic structural view showing a cross section of a partial structure of an LED display array according to Embodiment 1 of the present disclosure
  • FIG. 3 is a schematic structural view showing a cross section of a partial structure of an LED display array according to Embodiment 1 of the present disclosure
  • FIG. 4 is a schematic structural view of a cross section of an LED display array according to Embodiment 1 of the present disclosure
  • FIG. 5 is a schematic structural view of a cross section of an LED display array according to Embodiment 1 of the present disclosure
  • FIG. 6 is a flow chart of a method for fabricating an LED display array according to Embodiment 3 of the present disclosure
  • FIG. 7 is a schematic structural view of a cross section of a first substrate, a pixel unit, and an electrode unit according to Embodiment 3 and Embodiment 4 of the present disclosure
  • FIG. 8 is a schematic structural view of a cross section of a second substrate and a driving unit according to Embodiment 3 and Embodiment 4 of the present disclosure
  • FIG. 9 is a flow chart of a method for fabricating an LED display array according to Embodiment 3 of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a manufacturing process of an LED display array according to Embodiment 3 of the present disclosure.
  • FIG. 12 is a flow chart of a method for fabricating an LED display array according to Embodiment 3 of the present disclosure
  • FIG. 13 to FIG. 14 are schematic structural diagrams of a process of fabricating an LED display array according to Embodiment 3 of the present disclosure.
  • FIG. 16 are flowcharts of a method for fabricating an LED display array according to Embodiment 4 of the present disclosure.
  • FIG. 17 to FIG. 18 are schematic structural diagrams showing a manufacturing process of an LED display array according to Embodiment 4 of the present disclosure.
  • FIG. 19 is a flow chart of a method for fabricating an LED display array according to Embodiment 4 of the present disclosure.
  • FIG. 20 is a schematic structural diagram of a manufacturing process of an LED display array according to Embodiment 4 of the present disclosure.
  • the current LED display array includes: a first substrate and a second substrate, wherein the first substrate and the second substrate are oppositely disposed, at least one pixel unit is formed on one side of the first substrate facing the second substrate, and the second substrate faces the first substrate At least one driving unit is formed on one side, and each of the at least one pixel unit corresponds to one of the at least one driving unit, and each of the pixel units is connected to the corresponding driving unit by a wire.
  • each pixel unit and its corresponding driving unit need to be connected by using a wire, the two ends of the wire are respectively soldered on the pixel unit and the corresponding driving unit by a pressure welding process, due to the pressure welding process.
  • the limitation is that the size of the pixel unit and its corresponding driving unit can be minimized to a millimeter level, which limits the development of the LED display array to a smaller size.
  • an embodiment of the present disclosure provides an LED display array, the LED display array. include:
  • first substrate 1 and a second substrate 2 are oppositely disposed;
  • At least one driving unit 21 is formed on one side of the second substrate 2 facing the first substrate 1, and each pixel unit 11 on the first substrate 1 corresponds to one driving unit 21 on the second substrate 2;
  • a metal block 3 is formed between each pixel unit 11 and its corresponding driving unit 21, and the metal block 3 electrically connects the pixel unit 11 and its corresponding driving unit 21.
  • the metal block 3 between each pixel unit 11 and its corresponding driving unit 21 is formed by a patterning process.
  • one metal block 3 is formed between each pixel unit 11 and its corresponding driving unit 21, and the metal block 3 is formed by a patterning process, even for the pixel unit 11 and the driving unit 21
  • the size is small, and the metal block 3 having a smaller size can also be formed by a patterning process, so that each pixel unit 11 and its corresponding driving unit 21 are electrically connected by the metal block 3, and the wire is used by using a wire bonding process.
  • the pixel unit 11 and its corresponding driving unit 21 are electrically connected.
  • the size of the pixel unit 11 and the corresponding driving unit 21 are not limited by the pressure welding process, and therefore, the size can be made more.
  • the size of the small pixel unit 11 and its corresponding driving unit 21 is such that the LED display array can be developed to a smaller size; at the same time, since each pixel unit 11 and its corresponding driving unit 21 are electrically connected by a metal block 3 The connection can remove the switching circuit structure such as the wire, and reduce the resistance between each pixel unit 11 and its corresponding driving unit 21, also making the signal The problem of delay is improved; for a large-sized LED display array, each of the pixel units 11 can also be electrically connected to its corresponding driving unit 21 using the metal block 3 to reduce each of the pixel units 11 and its corresponding driving unit 21 The resistance between them and the problem of improving signal delay.
  • each pixel unit 11, a corresponding driving unit 21 of each pixel unit 11, and each The pixel unit 11 and the metal block 3 located between the pixel unit 11 and the corresponding driving unit 21 are subjected to a reflow soldering process. After the reflow soldering process, the metal block 3 electrically connects the pixel unit 11 with its corresponding driving unit 21,
  • embodiments of the present disclosure are not limited thereto, and other processing processes may be selected to electrically connect the pixel unit 11 through the metal block 3 to its corresponding driving unit 21.
  • the metal block 3 may be disposed on each of the pixel units 11 on the first substrate 1. As shown in FIG. 3, it may also be disposed on each of the driving units 21 on the second substrate 2.
  • the material of the metal block 3 may be metal indium, but the embodiment of the present disclosure is not limited thereto, and may be other metal materials.
  • each pixel unit 11 is electrically connected to its corresponding driving unit 21 through a metal block 3, and therefore, each driving unit 21 can drive the pixel unit 11 corresponding thereto to emit light through the metal block 3, The light emitted from the pixel unit 11 is reflected out through the first substrate 1.
  • the first substrate 1 may be, for example, a sapphire substrate, but the embodiment of the present disclosure is not limited thereto, and other materials that can reflect light emitted from the pixel unit 11 may be selected.
  • each of the pixel units 11 includes a light emitting layer 111 and a reflective layer 112.
  • the light emitting layer 111 is formed on one side of the first substrate 1 facing the second substrate 2, and the reflective layer 112 is formed on a side of the light emitting layer 111 away from the first substrate 1.
  • a part of the light emitted by the light-emitting layer 111 in the embodiment of the present disclosure may be emitted through the first substrate 1, and another portion is emitted from the first substrate 1 through the reflection of the reflective layer 112, thereby improving the brightness of the LED display array.
  • the material of the reflective layer 112 in the embodiment of the present disclosure may be metallic silver or metallic aluminum, but embodiments of the present disclosure are not limited thereto.
  • a common electrode layer 12 is further formed on a side of the first substrate 1 facing the second substrate 2;
  • At least one pixel unit 11 and at least one electrode unit 13 are formed on the common electrode layer 12.
  • Each electrode unit 13 on the common electrode layer 12 corresponds to one driving unit 21 on the second substrate 2, and at least one pixel unit 11 is at the common electrode.
  • the layer 12 is arranged in one or more rows, each row further comprises an electrode unit 13 and is located at an end position of the row, and the electrode units 13 are all located in the same column;
  • a metal block 3 is formed between each electrode unit 13 and its corresponding drive unit 21 for electrically connecting the electrode unit 13 and its corresponding drive unit 21.
  • a current is generated by the common electrode layer 12 on the first substrate 1 and the at least one electrode unit 13 and the driving unit 21 on the second substrate 2, and current flows through the metal block 3 at each of the pixel units 11 and Transmission between the corresponding driving units 21 is possible such that the light-emitting layer 111 of each of the pixel units 11 emits light.
  • each of the electrode units 13 and its corresponding driving unit 21 are also electrically connected by the metal block 3, and the metal block 3 is formed by a patterning process, and therefore, the size of the electrode unit 13 can also be Made smaller, making the LED display array smaller Inch development.
  • the metal block 3 may be formed on each of the electrode units 13 on the first substrate 1, as shown in FIG. 3, or on each of the driving units 21 on the second substrate 2.
  • the substrate may be a flexible substrate made of plastic, but embodiments of the present disclosure are not limited thereto.
  • the shape of the metal block 3 may be, for example, a sphere.
  • the shape of the metal block 3 is set as a sphere, and when the reflow soldering process is performed, the metal block 3 of the sphere becomes molten, and the molten metal block 3 of the sphere has self-alignment. Pulling effect, when the molten metal ball has an interface with different affinities on both surfaces, one of the interfaces with weak surface affinity can be pulled to another by the surface tension of the metal ball The process on the interface with good surface affinity enables each pixel unit 11 and its corresponding driving unit 21 to be more accurately butted together by the metal block 3 in the sphere.
  • a spherical shape metal block 3 may be formed by a reflow annealing process, and if a spherical shape metal block 3 is formed on each of the pixel units 11 on the first substrate 1, it may be first in each pixel A metal layer is formed on the unit 11, and the metal layer is structured as a cubic metal block 3, and the metal block 3 of the cubic structure is formed into a spherical structure by a reflow annealing process. If the metal block 3 of the spherical structure is formed on each of the driving units 21 on the second substrate 2, a cubic metal block 3 may be formed on each of the driving units 21, and then the cubic structure is formed by a reflow annealing process.
  • the metal block 3 forms a structure of a sphere. As shown in FIG. 4, the shape of the metal block 3 may also be formed into a cylindrical structure, for example, but the embodiment of the present disclosure is not limited to a sphere and a cylinder, and may be other shapes.
  • a first adhesion layer 4 is formed between each pixel unit 11 and its corresponding metal block 3; between each driving unit 21 and its corresponding metal block 3 A second adhesive layer 5 is formed.
  • the first adhesive layer 4 is used to adhere the pixel unit 11 and its corresponding metal block 3 for adhering the driving unit 21 with its corresponding metal block 3.
  • a first adhesion layer 4 is formed on each of the pixel units 11, and a second adhesion layer 5 is formed on each of the driving units 21, and the metal block 3 is formed on the first paste.
  • the metal block 3 may be disposed on the first adhesive layer 4, as shown in FIG. 3, or may be disposed on the second adhesive layer 5.
  • the adhesion between the metal block 3 and the pixel unit 11 can be increased, and by providing the second adhesive layer 5, the adhesion between the metal block 3 and the driving unit 21 can be increased, It is helpful to fix the metal block 3 between the pixel unit 11 and its corresponding driving unit 21.
  • the first adhesive layer 4 and the second adhesive layer 5 have electrical conductivity The conductive paste of the particles is made, and therefore, does not affect the electrical connection between the metal block 3 and the pixel unit 11 and the drive unit 21.
  • the material of the first adhesive layer 4 is a solder paste
  • the material of the second adhesive layer 5 is a nickel gold alloy; or the material of the first adhesive layer 4 is a nickel gold alloy.
  • the material of the second adhesive layer 5 is a solder paste.
  • the materials of the first adhesive layer 4 and the second adhesive layer 5 can be selected according to the position at which the metal block 3 is disposed, which will be described in detail below.
  • the material of the first adhesion layer 4 may be selected from a nickel-gold alloy because reflow annealing is used.
  • the nickel-gold alloy can help the metal layer to form a sphere, and at the same time, the nickel-gold alloy can make the metal block 3 electrically connect with the corresponding pixel unit 11 during the reflow annealing; the second adhesion
  • the material of the layer 5 can be selected from solder paste.
  • the solder paste has a certain viscosity, so that the metal block 3 of the sphere can be more stably fixed on the driving unit 21, and in the process of reflow soldering, the solder paste can make the metal block 3
  • the corresponding drive unit 21 completes the electrical connection.
  • the material of the second adhesive layer 5 may be selected from a nickel-gold alloy;
  • the material of the adhesion layer 4 can be selected from solder paste.
  • the metal block 3 by forming a metal block 3 between each pixel unit 11 and its corresponding driving unit 21, and the metal block 3 is formed by a patterning process, even the size of the pixel unit 11 and the driving unit 21 Smaller, the metal block 3 having a smaller size can also be formed by a patterning process, so that each pixel unit 11 and its corresponding driving unit 21 are electrically connected by the metal block 3.
  • the size of the pixel unit 11 and the corresponding driving unit 21 are not subjected to pressure welding, with respect to electrically connecting the pixel unit 11 and its corresponding driving unit 21 by a wire bonding process.
  • the pixel unit 11 and its corresponding driving unit 21 can be made smaller, so that the LED display array can be developed to a smaller size; since each pixel unit 11 and its corresponding driving unit 21 By electrically connecting one metal block 3, the switching circuit structure such as a wire can be removed, the resistance between each pixel unit 11 and its corresponding driving unit 21 is reduced, and the problem of signal delay is also improved; for large size LED array display, metal block 3 can also be used to electrically connect each pixel unit 11 with its corresponding driving unit 21 to reduce the resistance between each pixel unit 11 and its corresponding driving unit 21, improving the signal delay problem. .
  • Embodiments of the present disclosure provide a wearable device including the light emitting diode display array described in Embodiment 1.
  • the wearable device may be an Augmented Reality (AR) device, a Virtual Reality (VR) device, a smart watch, a smart glasses, or the like.
  • AR Augmented Reality
  • VR Virtual Reality
  • a light emitting diode display array in an embodiment of the present disclosure by forming a metal block 3 between each pixel unit 11 and its corresponding driving unit 21, and the metal block 3 is formed by a patterning process, even if the pixel unit 11 and The size of the driving unit 21 is small, and the metal block 3 having a smaller size can also be formed by a patterning process, so that each pixel unit 11 and its corresponding driving unit 21 are electrically connected by the metal block 3, relative to the process of passing the pressure welding.
  • the size of the pixel unit 11 and the driving unit 21 corresponding thereto are not limited by the pressure welding process, and therefore, The size of the smaller-sized pixel unit 11 and its corresponding driving unit 21 can be made such that the LED display array can be developed to a smaller size, enabling the wearable device to develop to a smaller size; and, since each pixel unit 11 is electrically connected to the corresponding driving unit 21 through a metal block 3, which can remove the switching circuit structure such as the wire, and reduces each Resistor 21 between the pixel unit driving unit 11 corresponding thereto, such that the same problem of signal delay is improved to improve the performance of a wearable device.
  • Embodiments of the present disclosure provide a method of fabricating an LED display array, as shown in FIG. 6, including the following steps.
  • Step 101 As shown in FIG. 7, a common electrode layer 12 is formed on one side of the first substrate 1;
  • Step 102 As shown in FIG. 7, at least one pixel unit 11 and at least one electrode unit 13 are formed on the common electrode layer 12;
  • each of the at least one pixel unit 11 includes a light emitting layer 111 and a reflective layer 112. .
  • At least one light emitting layer 111 may be formed on the common electrode layer 12 by one patterning process, and then one reflective layer 112 may be formed on each of the at least one light emitting layer 111 by one patterning process. It is also possible to simultaneously form the light-emitting layer 111 and the reflective layer 112 included in each of the pixel units 11 by only one patterning process.
  • At least one pixel unit 11 is disposed on one or more rows on the common electrode layer 12, each row further including one electrode unit 13 and the electrode unit 13 is located at an end position of the row.
  • the electrode units 13 are all located in the same column.
  • each row includes electrode units 13 at the right end of the row, and the electrode units 13 are arranged in a row on the right end of the first substrate 1.
  • Step 103 As shown in FIG. 8, at least one driving unit 21 is formed on one side of the second substrate 2;
  • each pixel unit 11 on the common electrode layer 12 corresponds to one driving unit 21 on the second substrate 2
  • each electrode unit 13 on the common electrode layer 12 corresponds to one on the second substrate 2.
  • Drive unit 21 As shown in FIG. 7, the height of the electrode unit 13 on the common electrode layer 12 is smaller than the height of the pixel unit 11, and in order to make the height between the first substrate 1 and the second substrate 2 uniform, the second substrate 2 and the electrode may be The height of the drive unit 21 corresponding to the unit 13 is increased.
  • the embodiment of the present disclosure is not limited thereto, and for example, the height of the electrode unit 13 and the drive unit 21 corresponding thereto may also be selected from other designs.
  • Step 104 Forming a metal block 3 on each of the at least one pixel unit 11 and on each of the at least one electrode unit 13.
  • the shape of the metal block 3 may be a sphere or a cylinder, and embodiments of the present disclosure are not limited thereto.
  • step of step 104 may include, for example, the following steps.
  • Step 1041 As shown in FIG. 7, and referring to FIG. 10, a first adhesion layer 4 is formed on each of the pixel units 11 and on each of the electrode units 13;
  • a first adhesion layer 4 may be formed on each of the pixel units 11 and on each of the electrode units 13 by a patterning process.
  • the material of the first adhesion layer 4 may be a nickel gold alloy.
  • Step 1042 applying a solder resist on each of the pixel units 11 and the first adhesive layer 4 on each of the driving units 21;
  • Step 1043 As shown in Figure 10, and see Figure 11, a metal block 3 is formed on the first adhesion layer 4 coated with solder resist;
  • a metal layer which is a metal block 3 of a cubic structure may be formed on each of the first adhesion layer 4 coated with the solder resist by a patterning process.
  • Step 1044 As shown in FIG. 11, and referring to FIG. 2, the cubic metal block 3 on each of the first adhesion layers 4 is formed into a spherical structure by a reflow annealing process.
  • the material of the first adhesion layer 4 is a nickel gold alloy, and the first adhesion layer 4 is coated with a solder resist, the nickel gold alloy and the solder resist may contribute to the formation of the metal block 3 of the cube during the reflow annealing process.
  • Step 105 docking the metal blocks 3 on each of the pixel units 11 with the driving unit 21 corresponding to each of the pixel units 11, and the metal blocks 3 on each of the electrode units 13 respectively corresponding to the driving units of each of the electrode units 13 21 docking;
  • step 105 may include, for example, the following steps:
  • Step 1051 As shown in Figure 13, a second adhesion layer 5 is formed on each of the at least one drive unit 21;
  • the material of the second adhesive layer 5 may be a solder paste.
  • a layer of solder paste may be applied to each of the drive units 21 by screen printing.
  • Step 1052 As shown in FIG. 14, and referring to FIG. 5, the second adhesive layer on the driving unit 21 corresponding to each of the pixel units 11 and the metal block 3 on each of the electrode units 13 and the corresponding pixel unit 11 respectively 5 docking.
  • Step 106 As shown in FIG. 5, the pixel unit 11, the driving unit 21 corresponding to the pixel unit 11, and the metal block 3 located therebetween, the electrode unit 13, the driving unit 21 corresponding to the electrode unit 13, and both The metal block 3 is subjected to a reflow soldering process to electrically connect the metal block 3 to the pixel unit 11 and its corresponding driving unit 21 and to the electrical connection electrode unit 13 and its corresponding driving unit 21.
  • the metal block 3 completes the electrical connection between its corresponding driving unit 21 through the second adhesive layer 5, so that the metal block 3 electrically connects the pixel unit 11, the corresponding driving unit 21, and the electrical connection.
  • the electrode unit 13 has a drive unit 21 corresponding thereto.
  • a light emitting diode display array in an embodiment of the present disclosure by forming a metal block 3 by a patterning process between each pixel unit 11 and a driving unit 21 corresponding thereto, even if the pixel unit 11 and the driving unit 21 are small in size It is also possible to form the metal blocks 3 having a smaller size by a patterning process, so that each of the pixel units 11 and the corresponding driving unit 21 are electrically connected by the metal block 3.
  • the pixel unit 11 and the drive unit 21 corresponding thereto are not subjected to pressure welding in the embodiment of the present disclosure with respect to the electric connection of the pixel unit 11 and the corresponding drive unit 21 by the wire bonding process.
  • the pixel unit 11 and its corresponding driving unit 21 can be made smaller, so that the LED display array can be made smaller in size, thereby making it possible to wear
  • the device is developed to a smaller size; and, since each pixel unit 11 is electrically connected to its corresponding driving unit 21 through a metal block 3, the switching circuit structure such as a wire can be removed, and each pixel unit can be reduced.
  • the resistance between the drive unit 21 and its corresponding drive unit 21 also improves the problem of signal delay and improves the performance of the wearable device.
  • Embodiments of the present disclosure provide a method for fabricating an LED display array, as shown in FIG. 15, including the following steps.
  • Step 201 As shown in FIG. 7, a common electrode layer 12 is formed on one side of the first substrate 1;
  • Step 202 As shown in FIG. 7, at least one pixel unit 11 and at least one electrode unit 13 are formed on the common electrode layer 12;
  • each of the at least one pixel unit 11 includes a light emitting layer 111 and a reflective layer 112.
  • the at least one luminescent layer 111 may be formed on the common electrode layer 12 by one patterning process, and then one reflective layer 112 may be formed on each of the at least one luminescent layer 111 by one patterning process;
  • the patterning process simultaneously forms the light-emitting layer 111 and the reflective layer 112 included in each of the pixel units 11;
  • At least one pixel unit 11 is disposed on one or more rows on the common electrode layer 12, each row further includes one electrode unit 13 and the electrode unit 13 is located at an end position of the row, and the electrode unit 13 is located The same column.
  • each row includes electrode units 13 at the right end of the row, and electrode units 13 are arranged in a row on the right end of the first substrate 1.
  • Step 203 As shown in Figure 8, at least one drive unit 21 is formed on one side of the second substrate 2;
  • At least one driving unit 21 may be formed on one side of the second substrate 2 by a patterning process.
  • each pixel unit 11 on the common electrode layer 12 corresponds to one driving unit 21 on the second substrate 2
  • each electrode unit 13 on the common electrode layer 12 corresponds to one on the second substrate 2.
  • Drive unit 21 As shown in FIG. 7, the height of the electrode unit 13 on the common electrode layer 12 is smaller than the height of the pixel unit 11, and in order to make the height between the first substrate 1 and the second substrate 2 uniform, the second substrate 2 and the electrode may be The height of the drive unit 21 corresponding to the unit 13 is increased.
  • the embodiment of the present disclosure is not limited thereto, and for example, the height of the electrode unit 13 and the drive unit 21 corresponding thereto may also be selected from other designs.
  • Step 204 forming a metal block 3 on each of the at least one driving unit 21;
  • the shape of the metal block 3 may be a sphere or a cylinder, and embodiments of the present disclosure are not limited thereto.
  • step 204 may include, for example, the following steps:
  • Step 2041 As shown in Figure 8, and see Figure 17, a second adhesion layer 5 is formed on each drive unit 21;
  • a second adhesion layer 5 may be formed on each of the pixel units 11 and on each of the electrode units 13 by a patterning process.
  • the material of the second adhesive layer 5 may be a nickel gold alloy.
  • Step 2042 coating a second solder resist layer on each of the driving units 21 with a solder resist
  • Step 2043 As shown in Figure 17, and see Figure 18, on the second adhesion layer 5 coated with solder resist to form a cubic metal block 3;
  • a metal layer which is a metal block 3 of a cubic structure may be formed on each of the second adhesion layer 5 coated with the solder resist by a patterning process.
  • Step 2044 As shown in FIG. 18, and referring to FIG. 5, the cubic metal block 3 on each of the second adhesion layers 5 is formed into a spherical structure by a reflow annealing process.
  • the material of the second adhesive layer 5 is a nickel gold alloy, and the second adhesive layer 5 is coated with a solder resist, and the nickel gold alloy and the solder resist contribute to the formation of a spherical structure of the cubic metal block 3 during the reflow annealing process. And during the reflow annealing, the metal block 3 is electrically connected to the driving unit 21 through the second adhesive layer 5.
  • Step 205 docking the metal blocks 3 on each of the driving units 21 with the pixel units 11 or the electrode units 13 corresponding to each of the driving units 21;
  • step 205 can include, for example:
  • Step 2051 As shown in FIG. 20, a first adhesion layer 4 is formed on each of the pixel units 11 and at least one of the electrode units 13 in at least one pixel unit 11;
  • the material of the first adhesive layer 4 may be a solder paste.
  • a layer of solder paste may be applied to each of the drive units 21 by screen printing.
  • Step 2052 As shown in FIG. 21, and referring to FIG. 1, the metal blocks 3 on each driving unit 21 are respectively docked with the pixel unit 11 corresponding to each driving unit 21 or the first adhesive layer 4 on the electrode unit 13. .
  • Step 206 As shown in FIG. 1, the pixel unit 11, the driving unit 21 corresponding to the pixel unit 11, and the metal block 3 located therebetween, the electrode unit 13, the driving unit 21 corresponding to the electrode unit 13, and both are located
  • the metal block 3 is subjected to a reflow soldering process to electrically connect the metal block 3 to the pixel unit 11 and its corresponding driving unit 21 and to the electrical connection electrode unit 13 and its corresponding driving unit 21.
  • the metal block 3 completes the electrical connection between its corresponding driving unit 21 through the first adhesive layer 4, and finally causes the metal block 3 to electrically connect the pixel unit 11 and the corresponding driving unit 21, and the electric The electrode unit 13 and the drive unit 21 corresponding thereto are connected.
  • the light emitting diode display array in the embodiment of the present disclosure by forming a metal block 3 by a patterning process between each of the pixel units 11 and the corresponding driving unit 21, even if the size of the pixel unit 11 and the driving unit 21 are compared Small, it is also possible to form a small-sized metal block 3 by a patterning process, so that each pixel unit 11 and its corresponding driving unit 21 are electrically connected by a metal block 3, and the pixel is used with respect to a wire by a pressure welding process.
  • the size of the pixel unit 11 and the corresponding driving unit 21 are not limited by the pressure welding process, and therefore, the size can be made more.
  • the small pixel unit 11 and its corresponding driving unit 21 enable the LED display array to be developed to a smaller size, so that the wearable device is developed to a smaller size; and, since each pixel unit 11 and its corresponding drive
  • the cells 21 are electrically connected by a metal block 3, and the switching circuit structure such as a wire can be removed, and each pixel unit 11 and its pair are reduced.
  • the resistance between the drive units 21 is such that the problem of signal delay is also improved, improving the usability of the wearable device.

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Abstract

一种发光二极管显示阵列及其制作方法、可穿戴设备。所述发光二极管显示阵列包括：第一基板和第二基板，第一基板和第二基板相对设置。第一基板面向第二基板的一面上形成有至少一个像素单元。第二基板面向第一基板的一面上形成有至少一个驱动单元，且第一基板上的每个像素单元对应第二基板上的一个驱动单元。每个像素单元和与其对应的驱动单元之间形成有一个金属块，金属块使像素单元和其对应的驱动单元电连接。

Description

发光二极管显示阵列及其制作方法、可穿戴设备 技术领域
本公开的实施例涉及一种发光二极管显示阵列及其制作方法、可穿戴设备。
背景技术
随着电子技术的发展，出现了很多小型电子设备，小型电子设备的尺寸较小，例如像可穿戴设备。由于小型电子设备的尺寸小，导致小型电子设备的显示屏也较小，而发光二极管显示阵列可以制作尺寸较小的显示屏，所以小型电子设备可以用发光二极管显示阵列来制作显示屏。
发明内容
本公开的实施例涉及一种发光二极管显示阵列及其制作方法、可穿戴设备，可以解决由于压焊工艺限制了发光二极管显示阵列向更小的尺寸发展的问题。
根据本公开的至少一个实施例，提供了一种发光二极管显示阵列，所述发光二极管显示阵列包括：
第一基板和第二基板，所述第一基板和所述第二基板相对设置；
所述第一基板面向所述第二基板的一面上形成有至少一个像素单元；
所述第二基板面向所述第一基板的一面上形成有至少一个驱动单元，且所述第一基板上的每个像素单元对应所述第二基板上的一个驱动单元；
所述每个像素单元和与其对应的驱动单元之间形成有一个金属块，所述金属块使所述像素单元和其对应的驱动单元电连接。
例如，所述每个像素单元和与其对应的金属块之间形成有一第一粘附层；
所述每个驱动单元和与其对应的金属块之间形成有一第二粘附层。
例如，所述第一粘附层的材料为锡膏，第二粘附层的材料为镍金合金；或者，第一粘附层的材料为镍金合金，第二粘附层的材料为锡膏。
例如，所述第一基板面向所述第二基板的一面上还形成有公共电极层；
所述公共电极层上形成有所述至少一个像素单元和所述至少一个电极单元，所述公共电极层上的每个电极单元对应所述第二基板上的一个驱动单元， 所述至少一个像素单元在所述公共电极层上以一行或多行设置，每行还包括一个位于行的端部位置的电极单元，电极单元均位于同一列；
所述每个电极单元和与其对应的驱动单元之间形成有一个金属块，配置来使所述电极单元和其对应的驱动单元电连接。
例如，所述金属块的形状为球体。
例如，所述金属块的材料为金属铟。
例如，所述每个像素单元包括发光层和反射层；
所述发光层形成在所述第一基板面向所述第二基板的一面上，所述反射层形成在所述发光层远离所述第一基板的一面上。
本公开的实施例还提供了一种可穿戴设备，所述可穿戴设备包括所述发光二极管显示阵列。
本公开的实施例还提供了一种发光二极管显示阵列的制作方法，所述方法包括：
在第一基板的一面上形成至少一个像素单元；
在第二基板面向所述第一基板的一面上形成至少一个驱动单元，所述第一基板上的每个像素单元对应所述第二基板上的一个驱动单元；
在所述每个像素单元和与其对应的驱动单元之间形成一个金属块，所述金属块电连接所述像素单元和其对应的驱动单元。
例如，在所述至少一个像素单元中的每个像素单元上形成一个金属块；将所述每个像素单元上的金属块分别与所述每个像素单元对应的驱动单元对接，以使所述金属块位于所述像素单元和所述像素单元对应的驱动单元之间；对所述像素单元、所述像素单元对应的驱动单元，以及位于两者之间的金属块进行回流焊接工艺处理，使所述金属块电连接所述像素单元和其对应的驱动单元。
例如，在所述至少一个像素单元中的每个像素单元上形成一第一粘附层；
在所述每个像素单元上的所述第一粘附层上形成一个金属块。
在所述至少一个驱动单元中的每个驱动单元上形成一个第二粘附层；
将所述每个像素单元上的金属块分别与所述每个像素单元对应的驱动单元上的第二粘附层对接。
例如，在所述每个像素单元上的第一粘附层上形成一个金属块之前，
在所述每个像素单元上的所述第一粘附层上涂覆一层阻焊剂。
例如，在所述每个像素单元上的所述第一粘附层上形成一个立方体结构的金属块，
在阻焊剂的辅助作用下，通过回流退火工艺使所述每个像素单元上的金属块形成球体结构。
例如，所述第一粘附层的材料为镍金合金，所述第二粘附层的材料为锡膏。
例如，在所述至少一个驱动单元中的每个驱动单元上形成一个金属块；
将所述每个驱动单元上的金属块分别与所述每个驱动单元对应的像素单元对接，以使所述金属块位于所述驱动单元和所述驱动单元对应的像素单元之间；
对所述像素单元、所述像素单元对应的驱动单元，以及位于两者之间的金属块进行回流焊接工艺处理，使所述金属块电连接所述像素单元和与其对应的驱动单元。
例如，在所述至少一个驱动单元中的每个驱动单元上形成一第二粘附层；
在所述每个驱动单元上的所述第二粘附层上形成一个金属块。
在所述至少一个像素单元中的每个像素单元上形成一所述第一粘附层；
将所述每个驱动单元上的金属块分别与所述每个驱动单元对应的像素单元上的所述第一粘附层对接。
例如，在所述每个驱动单元上的第二粘附层上形成一个金属块之前，
在所述每个驱动单元上的所述第二粘附层上涂覆一层阻焊剂。
例如，在所述每个驱动单元上的所述第二粘附层上形成一个立方体结构的金属块，
在阻焊剂的辅助作用下，通过回流退火工艺使所述每个驱动单元上的金属块形成球体结构。
例如，所述第二粘附层的材料为镍金合金，所述第一粘附层的材料为锡膏。
例如，在所述第一基板的一面上形成一层公共电极层；
在所述公共电极层上形成所述至少一个像素单元和所述至少一个电极单元，所述公共电极层上的每个电极单元对应所述第二基板上的一个驱动单元，所述至少一个像素单元在所述公共电极层上以一行或多行设置，每行还包括 一个位于行的端部位置的电极单元，电极单元均位于同一列；
在所述每个电极单元和与其对应的驱动单元之间形成一个金属块，所述金属块电连接所述电极单元和其对应的驱动单元。
附图说明
以下将结合附图对本公开的实施例进行更详细的说明，以使本领域普通技术人员更加清楚地理解本公开的实施例，其中：
图1是本公开的实施例一提供的一种发光二极管显示阵列的横截面的结构示意图；
图2是本公开的实施例一提供的一种发光二极管显示阵列的部分结构的横截面的结构示意图；
图3是本公开的实施例一提供的一种发光二极管显示阵列的部分结构的横截面的结构示意图；
图4是本公开的实施例一提供的一种发光二极管显示阵列的横截面的结构示意图；
图5是本公开的实施例一提供的一种发光二极管显示阵列的横截面的结构示意图；
图6是本公开的实施例三提供的一种发光二极管显示阵列的制作方法流程图；
图7是本公开的实施例三和实施例四提供的第一基板与像素单元、以及电极单元的横截面的结构示意图；
图8是本公开的实施例三和实施例四提供的第二基板与驱动单元的横截面的结构示意图；
图9是本公开的实施例三提供的一种发光二极管显示阵列的制作方法流程图；
图10至图11是本公开的实施例三提供的一种发光二极管显示阵列的制作过程的结构示意图；
图12是本公开的实施例三提供的一种发光二极管显示阵列的制作方法流程图；
图13至图14是本公开的实施例三提供的一种发光二极管显示阵列的制作过程的结构示意图；
图15至图16是本公开的实施例四提供的一种发光二极管显示阵列的制作方法流程图；
图17至图18是本公开的实施例四提供的一种发光二极管显示阵列的制作过程的结构示意图；
图19是本公开的实施例四提供的一种发光二极管显示阵列的制作方法流程图；
图20至图21是本公开的实施例四提供的一种发光二极管显示阵列的制作过程的结构示意图。
具体实施方式
下面将结合本公开的实施例中的附图，对本公开的实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在无须做出创造性劳动前提下所获得的所有其它实施例，都应属于本公开保护的范围。
目前的发光二极管显示阵列包括：第一基板和第二基板，第一基板和第二基板相对设置，第一基板面向第二基板的一面上形成有至少一个像素单元，第二基板面向第一基板的一面上形成有至少一个驱动单元，至少一个像素单元中的每个像素单元均对应至少一个驱动单元中的一个驱动单元，且每个像素单元与其对应的驱动单元通过金属丝连接起来。
发明人发现至少存在以下问题：
由于每个像素单元与其对应的驱动单元之间需要通过使用金属丝连接起来，而金属丝的两端是通过压焊工艺分别焊接在像素单元和与其对应的驱动单元上的，由于压焊工艺的限制，使得像素单元与其对应的驱动单元的尺寸最小只能做到毫米级别，限制了发光二极管显示阵列向更小的尺寸发展。
实施例一
为了避免由于压焊工艺的限制而限制了发光二极管显示阵列向更小的尺寸发展的问题，如图1所示，本公开的一实施例提供了一种发光二极管显示阵列，该发光二极管显示阵列包括：
第一基板1和第二基板2，第一基板1和第二基板2相对设置；
第一基板1面向第二基板2的一面上形成有至少一个像素单元11；
第二基板2面向第一基板1的一面上形成有至少一个驱动单元21，且第一基板1上的每个像素单元11对应第二基板2上的一个驱动单元21；
每个像素单元11与其对应的驱动单元21之间形成有一个金属块3，金属块3使像素单元11和其对应的驱动单元21电连接。
每个像素单元11与其对应的驱动单元21之间的金属块3是通过构图工艺形成的。
在本公开的实施例中，通过在每个像素单元11与其对应的驱动单元21之间形成一个金属块3，并且金属块3是通过构图工艺形成的，既使像素单元11和驱动单元21的尺寸较小，也可以通过构图工艺来形成尺寸较小的金属块3，使每个像素单元11与其对应的驱动单元21之间通过金属块3电连接，相对于通过压焊工艺利用金属丝将像素单元11和其对应的驱动单元21电连接来说，在本公开的实施例中，像素单元11和与其对应的驱动单元21的尺寸不会受到压焊工艺的限制，因此，可以制作尺寸更小的像素单元11和其对应的驱动单元21的尺寸，使得发光二极管显示阵列可以向更小的尺寸发展；同时，由于每个像素单元11与其对应的驱动单元21之间通过一个金属块3电连接，可以去除金属丝等转接电路结构，减小了每个像素单元11与其对应的驱动单元21之间的电阻，同样使得信号延迟的问题得到改善；对于大尺寸的发光二极管显示阵列，也可以使用金属块3使每个像素单元11与其对应的驱动单元21电连接，以减小每个像素单元11与其对应的驱动单元21之间的电阻以及改善信号延迟的问题。
本公开的实施例中，在每个像素单元11与其对应的驱动单元21之间形成一个金属块3之后，可以对每个像素单元11，每个像素单元11对应的驱动单元21，以及每个像素单元11以及位于像素单元11和对应的驱动单元21之间的金属块3进行回流焊接工艺处理，经过回流焊接处理工艺后，金属块3会使像素单元11与其对应的驱动单元21电连接，但是，本公开的实施例并不限于此，也可以选择其它的处理工艺来使像素单元11通过金属块3与其对应的驱动单元21电连接。
在本公开的实施例中，如图2所示，金属块3可以设置在位于第一基板1上的每个像素单元11上。如图3所示，也可以设置在位于第二基板2上的每个驱动单元21上。
在本公开的实施例中，金属块3的材料可以为金属铟，但是，本公开的实施例并不限于此，也可以为其它金属材料。
在本公开的实施例中，每个像素单元11与其对应的驱动单元21之间通过一个金属块3电连接，因此，每个驱动单元21可以通过金属块3驱动与其对应的像素单元11发光，像素单元11发出的光通过第一基板1反射出去。第一基板1例如可以为蓝宝石基板，但是本公开的实施例并不限于此，也可以选择可以将像素单元11发出的光反射出去的其它材料。
如图1所示，在本公开的实施例中，每个像素单元11包括发光层111和反射层112。
发光层111形成在第一基板1面向第二基板2的一面上，反射层112形成在发光层111远离第一基板1的一面上。
本公开的实施例中的发光层111发出的光一部分可以通过第一基板1出射，另一部分经过反射层112的反射从第一基板1出射出去，提高发光二极管显示阵列的亮度。
本公开的实施例中的反射层112的材料可以为金属银或者金属铝，但是本公开的实施例并不限于此。
如图1所示，在本公开的实施例中，第一基板1面向第二基板2的一面上还形成有公共电极层12；
公共电极层12上形成有至少一个像素单元11和至少一个电极单元13，公共电极层12上的每个电极单元13对应第二基板2上的一个驱动单元21，至少一个像素单元11在公共电极层12上分一行或多行设置，每行还包括一个电极单元13且位于行的端部位置，电极单元13均位于同一列；
每个电极单元13与其对应的驱动单元21之间形成有一个金属块3，用于使电极单元13和其对应的驱动单元21电连接。
在本公开的实施例中，通过第一基板1上的公共电极层12和至少一个电极单元13以及第二基板2上的驱动单元21产生电流，电流通过金属块3在每个像素单元11和其对应的驱动单元21之间可以进行传输，使得每个像素单元11的发光层111发光。
在本公开的实施例中，每个电极单元13与其对应的驱动单元21之间也通过金属块3电连接，并且，金属块3是通过构图工艺形成的，因此，电极单元13的尺寸也可以制作得更小，使得发光二极管显示阵列可以向更小的尺 寸发展。如图2所示，金属块3可以形成在位于第一基板1上的每个电极单元13上，如图3所示，也可以形成在位于第二基板2上的每个驱动单元21上。
例如，基板可以为塑料制的柔性基板，但本公开的实施例并不限于此。
如图1所示，在本公开的实施例中，金属块3的形状例如可以为球体。
在本公开的实施例中，将金属块3的形状设置成球体，在进行回流焊接工艺处理时，球体的金属块3会变成熔融态，熔融态的呈球体的金属块3具有自对准拉拽效应，该自对准拉拽效应为熔融态的金属球在两个表面具有不同亲和力的界面上时，可以通过金属球的表面张力将其中一个表面亲和力较弱的界面拉拽到另一个表面亲和力好的界面上的过程，使得每个像素单元11与其对应的驱动单元21可以通过呈球体的金属块3更精准地对接在一起。
在本公开的实施例中，可通过回流退火工艺形成球体形状的金属块3，若球体形状的金属块3形成在位于第一基板1上的每个像素单元11上，可以先在每个像素单元11上形成一个金属层，该金属层的结构为一个立方体结构的金属块3，再通过回流退火工艺使立方体结构的金属块3形成球体的结构。若球体结构的金属块3形成在位于第二基板2上的每个驱动单元21上，可以先在每个驱动单元21上形成一个立方体结构的金属块3，再通过回流退火工艺使立方体结构的金属块3形成球体的结构。如图4所示，金属块3的形状也可以形成为圆柱体的结构，例如，但本公开的实施例并不限于球体和圆柱体，还可以是其它形状。
如图1所示，在本公开的实施例中，每个像素单元11与其对应的金属块3之间形成有一个第一粘附层4；每个驱动单元21与其对应的金属块3之间形成有一个第二粘附层5。该第一粘附层4用于粘附像素单元11与其对应的金属块3，该第二粘附层5用于粘附驱动单元21与其对应的金属块3。
在本公开的实施例中，在每个像素单元11上形成有一个第一粘附层4，每个驱动单元21上形成有一个第二粘附层5，则金属块3形成在第一粘附层4和第二粘附层5之间。如图2所示，金属块3可以设置在第一粘附层4上，如图3所示，也可以设置在第二粘附层5上。通过设置第一粘附层4，可以增加金属块3与像素单元11之间的粘附性，通过设置第二粘附层5，可以增加金属块3与驱动单元21之间的粘附性，有助于将金属块3固定在像素单元11与其对应的驱动单元21之间。第一粘附层4和第二粘附层5有含有导电 颗粒的导电胶制成，因此，不会影响金属块3与像素单元11以及驱动单元21之间的电连接。
在本公开的实施例中，例如，第一粘附层4的材料为锡膏，第二粘附层5的材料为镍金合金；或者，第一粘附层4的材料为镍金合金，第二粘附层5的材料为锡膏。例如，若要形成形状为球体的金属块3时，可根据金属块3的设置位置选择第一粘附层4和第二粘附层5的材料，下面进行详细说明。
如图2所示，且参见图5，若要在每个第一粘附层4上形成球体的金属块3，则第一粘附层4的材料可以选择镍金合金，因为在使用回流退火工艺使金属层形成球体的过程中，镍金合金可以帮助金属层形成球体，同时，镍金合金在回流退火的过程中可以使金属块3与其对应的像素单元11完成电连接；第二粘附层5的材料可以选择锡膏，锡膏有一定的粘度，可以使球体的金属块3更稳定的固定在驱动单元21上，并且，在回流焊接的过程中，锡膏可以使金属块3与其对应的驱动单元21完成电连接。
同理，如图3所示，且参见图1，若要在每个第二粘附层5上形成球体的金属块3，则第二粘附层5的材料可以选择镍金合金；第一粘附层4的材料可以选择锡膏。
在本公开的实施例中，通过在每个像素单元11与其对应的驱动单元21之间形成一个金属块3，并且金属块3是通过构图工艺形成的，即使像素单元11和驱动单元21的尺寸较小，也可以通过构图工艺来形成尺寸较小的金属块3，使每个像素单元11与其对应的驱动单元21之间通过金属块3电连接。相对于通过压焊工艺利用金属丝将像素单元11和其对应的驱动单元21电连接来说，在本公开的实施例中，像素单元11和与其对应的驱动单元21的尺寸不会受到压焊工艺的限制，因此，可以制作尺寸更小的像素单元11和其对应的驱动单元21，使得发光二极管显示阵列可以向更小的尺寸发展；由于每个像素单元11与其对应的驱动单元21之间通过一个金属块3电连接，可以去除金属丝等转接电路结构，减小了每个像素单元11与其对应的驱动单元21之间的电阻，同样使得信号延迟的问题得到改善；对于大尺寸的发光二极管显示阵列，也可以使用金属块3使每个像素单元11与其对应的驱动单元21电连接，以减小每个像素单元11与其对应的驱动单元21之间的电阻，改善信号延迟的问题。
实施例二
本公开的实施例提供了一种可穿戴设备，该可穿戴设备包括实施例一中描述的发光二极管显示阵列。该可穿戴设备可以为增强现实(AR，Augmented Reality)设备、虚拟现实(VR，Virtual Reality)设备、智能手表以及智能眼镜等。
在本公开的实施例中的发光二极管显示阵列，通过在每个像素单元11与其对应的驱动单元21之间形成一个金属块3，并且金属块3是通过构图工艺形成的，即使像素单元11和驱动单元21的尺寸较小，也可以通过构图工艺来形成尺寸较小的金属块3，使每个像素单元11与其对应的驱动单元21之间通过金属块3电连接，相对于通过压焊工艺利用金属丝将像素单元11和其对应的驱动单元21电连接来说，在本公开的实施例中，像素单元11和与其对应的驱动单元21的尺寸不会受到压焊工艺的限制，因此，可以制作尺寸更小的像素单元11和其对应的驱动单元21的尺寸，使得发光二极管显示阵列可以向更小的尺寸发展，使得可穿戴设备向更小的尺寸发展；并且，由于每个像素单元11与其对应的驱动单元21之间通过一个金属块3电连接，可以去除金属丝等转接电路结构，减小了每个像素单元11与其对应的驱动单元21之间的电阻，同样使得信号延迟的问题得到改善，提高了可穿戴设备的使用性能。
实施例三
本公开的实施例提供了一种发光二极管显示阵列的制作方法，如图6所示，包括以下步骤。
步骤101：如图7所示，在第一基板1的一面上形成一层公共电极层12；
步骤102：如图7所示，在公共电极层12上形成至少一个像素单元11和至少一个电极单元13；
图7为第一基板1的横截面的结构示意图，如图7所示，在本公开的实施例中，至少一个像素单元11中的每个像素单元11均包括一个发光层111和反射层112。可先通过一次构图工艺在公共电极层12上形成至少一个发光层111，再通过一次构图工艺在至少一个发光层111中的每个发光层111上形成一个反射层112。也可以仅通过一次构图工艺同时形成每个像素单元11包括的发光层111和反射层112。
在本公开的实施例中，至少一个像素单元11在公共电极层12上以一行或多行设置，每行还包括一个电极单元13且电极单元13位于行的端部位置。电极单元13均位于同一列。在此图7中，每行包括的电极单元13位于行的右端，电极单元13在第一基板1上右端排成一列。
步骤103：如图8所示，在第二基板2的一面上形成至少一个驱动单元21；
在本公开的实施例中，公共电极层12上的每个像素单元11对应第二基板2上的一个驱动单元21，公共电极层12上的每个电极单元13对应第二基板2上的一个驱动单元21。如图7所示，公共电极层12上的电极单元13的高度小于像素单元11的高度，为了使得第一基板1和第二基板2之间的高度一致，可以将第二基板2上与电极单元13对应的驱动单元21的高度增高。本公开的实施例并不限于此，例如，电极单元13和与其对应的驱动单元21的高度也可以选择其它的设计。
步骤104：在至少一个像素单元11中的每个像素单元11上以及至少一个电极单元13中的每个电极单元13上形成一个金属块3。
在本公开的实施例中，金属块3的形状可以为球体，也可以为圆柱体，本公开的实施例并不限于此。
当金属块3的形状为球体时，如图9所示，步骤104的步骤例如可以包括如下步骤。
步骤1041：如图7所示，且参见图10，在每个像素单元11上以及每个电极单元13上形成一个第一粘附层4；
例如，可以通过构图工艺在每个像素单元11上以及每个电极单元13上形成一个第一粘附层4。第一粘附层4的材料可以为镍金合金。
步骤1042：在每个像素单元11以及每个驱动单元21上的第一粘附层4上涂覆一层阻焊剂；
步骤1043：如图10所示，且参见图11，在涂覆了阻焊剂的第一粘附层4上形成一个立方体的金属块3；
例如，可以通过构图工艺在每个涂覆了阻焊剂的第一粘附层4上形成一个金属层，该金属层为一个立方体结构的金属块3。
步骤1044：如图11所示，且参见图2，通过回流退火工艺使每个第一粘附层4上的立方体的金属块3形成球体结构。
由于第一粘附层4的材料为镍金合金，且第一粘附层4上涂覆有阻焊剂，镍金合金以及阻焊剂在回流退火的过程中会有助于立方体的金属块3形成球体结构，同时在回流退火的过程中，金属块3通过第一粘附层4与像素单元11或者电极单元13之间完成电连接。
步骤105：将每个像素单元11上的金属块3分别与每个像素单元11对应的驱动单元21对接，以及每个电极单元13上的金属块3分别与每个电极单元13对应的驱动单元21对接；
如图12所示，步骤105例如可以包括如下步骤：
步骤1051：如图13所示，在至少一个驱动单元21中的每个驱动单元21上形成一个第二粘附层5；
例如，第二粘附层5的材料可以为锡膏。可以通过丝网印刷的方法在每个驱动单元21上涂覆一层锡膏。
步骤1052：如图14所示，且参见图5，将每个像素单元11以及每个电极单元13上的金属块3分别与每个像素单元11对应的驱动单元21上的第二粘附层5对接。
步骤106：如图5所示，对像素单元11、像素单元11对应的驱动单元21，以及位于两者之间的金属块3，电极单元13、电极单元13对应的驱动单元21以及位于两者之间的金属块3进行回流焊接工艺处理，使金属块3电连接像素单元11和其对应的驱动单元21以及电连接电极单元13和其对应的驱动单元21。
在回流焊接的过程中，金属块3通过第二粘附层5完成与其对应的驱动单元21之间的电连接，使得金属块3电连接像素单元11，与其对应的驱动单元21，以及电连接电极单元13与其对应的驱动单元21。
本公开的实施例中的发光二极管显示阵列，通过在每个像素单元11和与其对应的驱动单元21之间通过构图工艺形成一个金属块3，既使像素单元11和驱动单元21的尺寸较小，也可以通过构图工艺来形成尺寸较小的金属块3，使每个像素单元11与其对应的驱动单元21之间通过金属块3电连接。相对于通过压焊工艺利用金属丝将像素单元11和与其对应的驱动单元21电连接来说，在本公开的实施例中，像素单元11和与其对应的驱动单元21的尺寸不会受到压焊工艺的限制，因此，可以制作尺寸更小的像素单元11和其对应的驱动单元21，使得发光二极管显示阵列可以向更小的尺寸，进而使得可穿 戴设备向更小的尺寸发展；并且，由于每个像素单元11与其对应的驱动单元21之间通过一个金属块3电连接，可以去除金属丝等转接电路结构，减小了每个像素单元11与其对应的驱动单元21之间的电阻，同样使得信号延迟的问题得到改善，提高了可穿戴设备的使用性能。
实施例四
本公开的实施例提供了一种发光二极管显示阵列的制作方法，如图15所示，包括如下步骤。
步骤201：如图7所示，在第一基板1的一面上形成一层公共电极层12；
步骤202：如图7所示，在公共电极层12上形成至少一个像素单元11和至少一个电极单元13；
图7为第一基板1的横截面的结构示意图，如图7所示，在本公开的实施例中，至少一个像素单元11中的每个像素单元11均包括一个发光层111和反射层112，可先通过一次构图工艺在公共电极层12上形成至少一个发光层111，再通过一次构图工艺在至少一个发光层111中的每个发光层111上形成一个反射层112；也可以仅通过一次构图工艺同时形成每个像素单元11包括的发光层111和反射层112；
在本公开的实施例中，至少一个像素单元11在公共电极层12上以一行或多行设置，每行还包括一个电极单元13且电极单元13位于行的端部位置，电极单元13均位于同一列。在图7中，每行包括的电极单元13位于行的右端，电极单元13在第一基板1上右端排成一列。
步骤203：如图8所示，在第二基板2的一面上形成至少一个驱动单元21；
例如，可通过构图工艺在第二基板2的一面上形成至少一个驱动单元21。
在本公开的实施例中，公共电极层12上的每个像素单元11对应第二基板2上的一个驱动单元21，公共电极层12上的每个电极单元13对应第二基板2上的一个驱动单元21。如图7所示，公共电极层12上的电极单元13的高度小于像素单元11的高度，为了使得第一基板1和第二基板2之间的高度一致，可以将第二基板2上与电极单元13对应的驱动单元21的高度增高。本公开的实施例并不限于此，例如，电极单元13和与其对应的驱动单元21的高度也可以选择其它的设计。
步骤204：在至少一个驱动单元21中的每个驱动单元21上形成一个金属块3；
在本公开的实施例中，金属块3的形状可以为球体，也可以为圆柱体，本公开的实施例并不限于此。
当金属块3的形状为球体时，如图16所示，步骤204的步骤例如可以包括如下步骤：
步骤2041：如图8所示，且参见图17，在每个驱动单元21上形成一个第二粘附层5；
例如，可以通过构图工艺在每个像素单元11上以及每个电极单元13上形成一个第二粘附层5。第二粘附层5的材料可以为镍金合金。
步骤2042：在每个驱动单元21上的第二粘附层5上涂覆一层阻焊剂；
步骤2043：如图17所示，且参见图18，在涂覆了阻焊剂的第二粘附层5上形成一个立方体的金属块3；
例如，可以通过构图工艺在每个涂覆了阻焊剂的第二粘附层5上形成一个金属层，该金属层为一个立方体结构的金属块3。
步骤2044：如图18所示，且参见图5，通过回流退火工艺使每个第二粘附层5上的立方体的金属块3形成球体结构。
第二粘附层5的材料为镍金合金，且第二粘附层5上涂覆有阻焊剂，镍金合金以及阻焊剂在回流退火的过程中有助于立方体的金属块3形成球体结构，并且在回流退火的过程中，金属块3通过第二粘附层5与驱动单元21之间完成电连接。
步骤205：将每个驱动单元21上的金属块3分别与每个驱动单元21对应的像素单元11或者电极单元13对接；
如图19所示，步骤205例如可以包括：
步骤2051：如图20所示，在至少一个像素单元11中的每个像素单元11以及至少一个电极单元13中的每个电极单元13上形成一个第一粘附层4；
例如，第一粘附层4的材料可以为锡膏。可以通过丝网印刷的方法在每个驱动单元21上涂覆一层锡膏。
步骤2052：如图21所示，且参见图1，将每个驱动单元21上的金属块3分别与每个驱动单元21对应的像素单元11或者电极单元13上的第一粘附层4对接。
步骤206：如图1所示，对像素单元11、像素单元11对应的驱动单元21，以及位于两者之间的金属块3，电极单元13、电极单元13对应的驱动单元21以及位于两者之间的金属块3进行回流焊接工艺处理，使金属块3电连接像素单元11和其对应的驱动单元21以及电连接电极单元13和其对应的驱动单元21。
在回流焊接的过程中，金属块3通过第一粘附层4完成与其对应的驱动单元21之间的电连接，最终使得金属块3电连接像素单元11和与其对应的驱动单元21，以及电连接电极单元13和与其对应的驱动单元21。
在本公开的实施例中的发光二极管显示阵列，通过在每个像素单元11和与其对应的驱动单元21之间通过构图工艺形成一个金属块3，既使像素单元11和驱动单元21的尺寸较小，也可以通过构图工艺来形成尺寸较小的金属块3，使每个像素单元11和与其对应的驱动单元21之间通过金属块3电连接，相对于通过压焊工艺利用金属丝将像素单元11和与其对应的驱动单元21的电连接来说，在本公开的实施例中，像素单元11和与其对应的驱动单元21的尺寸不会受到压焊工艺的限制，因此，可以制作尺寸更小的像素单元11和其对应的驱动单元21，使得发光二极管显示阵列可以向更小的尺寸发展，使得可穿戴设备向更小的尺寸发展；并且，由于每个像素单元11和与其对应的驱动单元21之间通过一个金属块3电连接，可以去除金属丝等转接电路结构，减小了每个像素单元11和与其对应的驱动单元21之间的电阻，使得信号延迟的问题也得到改善，提高了可穿戴设备的使用性能。
以上所述仅为本公开的示例实施例，并不用以限制本公开，凡在本公开的实施例的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。
本申请要求于2016年07月13日向SIPO提交的名称为“一种发光二极管显示阵列及其制作方法、可穿戴设备”的中国专利申请No.201610550925.2的优先权，其全文通过引用合并于本文。

Claims (20)

  1. 一种发光二极管显示阵列，包括：
    第一基板和第二基板，所述第一基板和所述第二基板相对设置；其中
    所述第一基板面向所述第二基板的一面上形成有至少一个像素单元；
    所述第二基板面向所述第一基板的一面上形成有至少一个驱动单元，且所述第一基板上的每个像素单元对应所述第二基板上的一个驱动单元；以及
    所述每个像素单元和与其对应的驱动单元之间形成有一个金属块，所述金属块使所述像素单元和与其对应的驱动单元电连接。
  2. 根据权利要求1所述的发光二极管显示阵列，其中，
    所述每个像素单元和与其对应的金属块之间形成有一第一粘附层；以及
    所述每个驱动单元和与其对应的金属块之间形成有一第二粘附层。
  3. 根据权利要求2所述的发光二极管显示阵列，其中，所述第一粘附层的材料为锡膏，所述第二粘附层的材料为镍金合金；或者，所述第一粘附层的材料为镍金合金，所述第二粘附层的材料为锡膏。
  4. 根据权利要求1-3任一项所述的发光二极管显示阵列，其中，
    所述第一基板面向所述第二基板的一面上还形成有公共电极层；
    所述公共电极层上形成有所述至少一个像素单元和至少一个电极单元，所述公共电极层上的每个电极单元对应所述第二基板上的一个驱动单元，所述至少一个像素单元在所述公共电极层上以一行或多行设置，每行还包括一个位于行的端部位置的电极单元，电极单元均位于同一列；以及
    所述每个电极单元和与其对应的驱动单元之间形成有一个金属块，配置来使所述电极单元和其对应的驱动单元电连接。
  5. 根据权利要求1至4任一项权利要求所述的发光二极管显示阵列，其中所述金属块的形状为球体。
  6. 根据权利要求4或5所述的发光二极管显示阵列，其中所述金属块的 材料为金属铟。
  7. 根据权利要求1-6任一项权利要求所述的发光二极管显示阵列，其中，所述每个像素单元包括发光层和反射层；
    所述发光层形成在所述第一基板面向所述第二基板的一面上，所述反射层形成在所述发光层远离所述第一基板的一面上。
  8. 一种可穿戴设备，包括权利要求1-7任一项权利要求所述的发光二极管显示阵列。
  9. 一种发光二极管显示阵列的制作方法，包括：
    在第一基板的一面上形成至少一个像素单元；
    在第二基板面对所述第一基板的一面上形成至少一个驱动单元，所述第一基板上的每个像素单元对应所述第二基板上的一个驱动单元；以及
    在所述每个像素单元和与其对应的驱动单元之间形成一个金属块，所述金属块电连接所述像素单元和其对应的驱动单元。
  10. 根据权利要求9所述的制作方法，还包括：
    在所述至少一个像素单元中的每个像素单元上形成一个金属块；
    将所述每个像素单元上的金属块分别与所述每个像素单元对应的驱动单元对接，以使所述金属块位于所述像素单元和所述像素单元对应的驱动单元之间；以及
    对所述像素单元、所述像素单元对应的驱动单元，以及位于两者之间的金属块进行回流焊接工艺处理，使所述金属块电连接所述像素单元和其对应的驱动单元。
  11. 根据权利要求10所述的制作方法，还包括：
    在所述至少一个像素单元中的每个像素单元上形成一第一粘附层；
    在所述每个像素单元上的所述第一粘附层上形成一个金属块；
    在所述至少一个驱动单元中的每个驱动单元上形成一第二粘附层；以及
    将所述每个像素单元上的金属块分别与所述每个像素单元对应的驱动单 元上的所述第二粘附层对接。
  12. 根据权利要求11所述的制作方法，还包括：在所述每个像素单元上的第一粘附层上形成一个金属块之前，在所述每个像素单元上的所述第一粘附层上涂覆一层阻焊剂。
  13. 根据权利要求12所述的制作方法，还包括：
    在所述每个像素单元上的所述第一粘附层上形成一个立方体结构的金属块，以及
    在阻焊剂的辅助作用下，通过回流退火工艺使所述每个像素单元上的金属块形成球体结构。
  14. 根据权利要求12所述的制作方法，其中，所述第一粘附层的材料为镍金合金，所述第二粘附层的材料为锡膏。
  15. 根据权利要求9所述的制作方法，还包括：
    在所述至少一个驱动单元中的每个驱动单元上形成一金属块；
    将所述每个驱动单元上的所述金属块分别与所述每个驱动单元对应的像素单元对接，以使所述金属块位于所述驱动单元和所述驱动单元对应的像素单元之间；以及
    对所述像素单元、所述像素单元对应的驱动单元，以及位于两者之间的金属块进行回流焊接工艺处理，使所述金属块电连接所述像素单元和其对应的驱动单元。
  16. 根据权利要求15所述的制作方法，还包括：
    在所述至少一个驱动单元中的每个驱动单元上形成一第二粘附层；
    在所述每个驱动单元上的所述第二粘附层上形成一个金属块；
    在所述至少一个像素单元中的每个像素单元上形成一第一粘附层；以及
    将所述每个驱动单元上的金属块分别与所述每个驱动单元对应的像素单元上的所述第一粘附层对接。
  17. 根据权利要求16所述的制作方法，还包括：在所述每个驱动单元上的第二粘附层上形成一个金属块之前，在所述每个驱动单元上的所述第二粘附层上涂覆一层阻焊剂。
  18. 根据权利要求17所述的制作方法，还包括：
    在所述每个驱动单元上的所述第二粘附层上形成一个立方体结构的金属块，以及
    在阻焊剂的辅助作用下，通过回流退火工艺使所述每个驱动单元上的金属块形成球体结构。
  19. 根据权利要求17所述的制作方法，其中所述第二粘附层的材料为镍金合金，以及所述第一粘附层的材料为锡膏。
  20. 根据权利要求10至19任一项权利要求所述的制作方法，还包括：
    在所述第一基板的一面上形成一层公共电极层；
    在所述公共电极层上形成所述至少一个像素单元和至少一个电极单元，所述公共电极层上的每个电极单元对应所述第二基板上的一个驱动单元，所述至少一个像素单元在所述公共电极层上以一行或多行设置，每行还包括一个位于行的端部位置的电极单元，电极单元均位于同一列；
    所述制作方法还包括：
    在所述每个电极单元和与其对应的驱动单元之间形成一个金属块，所述金属块电连接所述电极单元和其对应的驱动单元。
PCT/CN2017/085884 2016-07-13 2017-05-25 发光二极管显示阵列及其制作方法、可穿戴设备 WO2018010496A1 (zh)

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106129028B (zh) * 2016-07-13 2018-10-19 京东方科技集团股份有限公司 一种发光二极管显示阵列及其制作方法、可穿戴设备
WO2018117361A1 (ko) * 2016-12-23 2018-06-28 주식회사 루멘스 마이크로 엘이디 모듈 및 그 제조방법
TWI658307B (zh) * 2017-10-30 2019-05-01 錼創科技股份有限公司 發光二極體顯示器
KR102655343B1 (ko) * 2018-11-15 2024-04-04 엘지디스플레이 주식회사 표시 장치 및 표시 장치의 제조 방법
CN109980078B (zh) * 2019-04-18 2020-06-23 京东方科技集团股份有限公司 发光模组及其制造方法、显示装置
WO2020242053A1 (en) 2019-05-28 2020-12-03 Samsung Electronics Co., Ltd. Display apparatus, source substrate structure, driving substrate structure, and method of manufacturing display apparatus
US20220190223A1 (en) * 2020-12-15 2022-06-16 Samsung Electronics Co., Ltd. Display apparatus and method of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101097911A (zh) * 2006-06-30 2008-01-02 Lg.菲利浦Lcd株式会社 有机发光二极管显示装置及其制造方法
CN101174675A (zh) * 2006-10-31 2008-05-07 株式会社半导体能源研究所 半导体装置的制造方法以及半导体装置
CN103165038A (zh) * 2012-11-16 2013-06-19 映瑞光电科技(上海)有限公司 一种led显示屏及其制作方法
CN106129028A (zh) * 2016-07-13 2016-11-16 京东方科技集团股份有限公司 一种发光二极管显示阵列及其制作方法、可穿戴设备

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5621225A (en) * 1996-01-18 1997-04-15 Motorola Light emitting diode display package
CN1507069A (zh) * 2002-12-11 2004-06-23 铼宝科技股份有限公司 有机电激发光二极管面板的封装工艺
KR20060096253A (ko) * 2005-03-04 2006-09-11 삼성전자주식회사 표시 장치 및 이의 제조 방법
JP2006243724A (ja) 2005-03-04 2006-09-14 Samsung Electronics Co Ltd 駆動チップ、表示装置及びその製造方法
US7990060B2 (en) * 2007-05-31 2011-08-02 Lg Display Co., Ltd. Organic light emitting display device and method of manufacturing the same
US8441123B1 (en) * 2009-08-13 2013-05-14 Amkor Technology, Inc. Semiconductor device with metal dam and fabricating method
KR101319348B1 (ko) 2009-12-21 2013-10-16 엘지디스플레이 주식회사 표시 장치 및 이의 제조 방법
US9646923B2 (en) * 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
US20130328191A1 (en) * 2012-06-12 2013-12-12 Intel Mobile Communications GmbH Cte adaption in a semiconductor package
US9570648B2 (en) * 2012-06-15 2017-02-14 Intersil Americas LLC Wafer level optical proximity sensors and systems including wafer level optical proximity sensors
SG10201610943TA (en) * 2012-07-03 2017-02-27 Heptagon Micro Optics Pte Ltd Use of vacuum chucks to hold a wafer or wafer sub-stack
EP2919142B1 (en) * 2014-03-14 2023-02-22 Samsung Electronics Co., Ltd. Electronic apparatus and method for providing health status information

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101097911A (zh) * 2006-06-30 2008-01-02 Lg.菲利浦Lcd株式会社 有机发光二极管显示装置及其制造方法
CN101174675A (zh) * 2006-10-31 2008-05-07 株式会社半导体能源研究所 半导体装置的制造方法以及半导体装置
CN103165038A (zh) * 2012-11-16 2013-06-19 映瑞光电科技(上海)有限公司 一种led显示屏及其制作方法
CN106129028A (zh) * 2016-07-13 2016-11-16 京东方科技集团股份有限公司 一种发光二极管显示阵列及其制作方法、可穿戴设备

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