WO2018003312A1 - Semiconductor processing sheet - Google Patents

Semiconductor processing sheet Download PDF

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Publication number
WO2018003312A1
WO2018003312A1 PCT/JP2017/017966 JP2017017966W WO2018003312A1 WO 2018003312 A1 WO2018003312 A1 WO 2018003312A1 JP 2017017966 W JP2017017966 W JP 2017017966W WO 2018003312 A1 WO2018003312 A1 WO 2018003312A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor processing
processing sheet
sheet
semiconductor
length
Prior art date
Application number
PCT/JP2017/017966
Other languages
French (fr)
Japanese (ja)
Inventor
優智 中村
尚哉 佐伯
小野 義友
Original Assignee
リンテック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by リンテック株式会社 filed Critical リンテック株式会社
Priority to CN201780027304.9A priority Critical patent/CN109075048A/en
Priority to KR1020237014195A priority patent/KR20230066116A/en
Priority to JP2018524941A priority patent/JPWO2018003312A1/en
Priority to KR1020187025068A priority patent/KR102528636B1/en
Publication of WO2018003312A1 publication Critical patent/WO2018003312A1/en
Priority to JP2022007739A priority patent/JP7336548B2/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J201/00Adhesives based on unspecified macromolecular compounds
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00Adhesives in the form of films or foils
    • C09J7/20Adhesives in the form of films or foils characterised by their carriers
    • C09J7/22Plastics; Metallised plastics
    • C09J7/25Plastics; Metallised plastics based on macromolecular compounds obtained otherwise than by reactions involving only carbon-to-carbon unsaturated bonds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2203/00Applications of adhesives in processes or use of adhesives in the form of films or foils
    • C09J2203/326Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2301/00Additional features of adhesives in the form of films or foils
    • C09J2301/30Additional features of adhesives in the form of films or foils characterized by the chemical, physicochemical or physical properties of the adhesive or the carrier
    • C09J2301/312Additional features of adhesives in the form of films or foils characterized by the chemical, physicochemical or physical properties of the adhesive or the carrier parameters being the characterizing feature
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Definitions

  • the present invention relates to a sheet for semiconductor processing, and preferably relates to a sheet for semiconductor processing used to increase the interval between a plurality of semiconductor chips.
  • CSP chip scale package
  • WLP wafer Level Package
  • WLP Wafer Level Package
  • a semiconductor chip is covered with a sealing member so as to be an area larger than the chip size. Then, the rewiring layer and the external electrode are formed not only on the circuit surface of the semiconductor chip but also on the surface region of the sealing member.
  • Patent Document 1 for a plurality of semiconductor chips separated from a semiconductor wafer, an extended wafer is formed by surrounding the periphery using a molding member, leaving a circuit formation surface, and in a region outside the semiconductor chip.
  • a method for manufacturing a semiconductor package formed by extending a rewiring pattern is described.
  • the semiconductor chip before enclosing a plurality of individual semiconductor chips with a mold member, the semiconductor chip is replaced with an expandable wafer mount tape, and the wafer mount tape is spread to expand the plurality of semiconductor chips. The distance between them is expanding.
  • the semiconductor chips need to be sufficiently separated from each other in order to form the above-described rewiring pattern or the like in a region outside the semiconductor chip.
  • This invention is made
  • the present invention provides a semiconductor processing sheet having at least a base material, wherein the recovery rate of the semiconductor processing sheet is 70% or more and 100% or less, and the restoration is performed.
  • the test piece obtained by cutting the semiconductor processing sheet into 150 mm ⁇ 15 mm both ends in the length direction are gripped with a gripping tool so that the length between the gripping tools is 100 mm, and then the length between the gripping tools is measured. Is pulled at a speed of 200 mm / min until the length becomes 200 mm, and is held for 1 minute in a state where the length between the grips is expanded to 200 mm, and then 200 mm until the length between the grips reaches 100 mm.
  • invention 1 it becomes possible to extend
  • the present invention is a semiconductor processing sheet comprising at least a base material, wherein the base material at 23 ° C. is 100% stress of the semiconductor processing sheet measured in the CD direction of the base material at 23 ° C.
  • the ratio of 100% stress of the semiconductor processing sheet measured in the MD direction is 0.8 or more and 1.2 or less, and the 100% stress is obtained by cutting the semiconductor processing sheet into 150 mm ⁇ 15 mm.
  • both ends in the length direction are gripped by the grip so that the length between the grips is 100 mm, and then pulled in the length direction at a speed of 200 mm / min, and the length between the grips is 200 mm.
  • a sheet for semiconductor processing characterized in that it is a value obtained by dividing the measured value of the tensile force at that time by the cross-sectional area of the sheet for semiconductor processing (Invention 2).
  • the film when the ratio of 100% stress is in the above range, the film can be stretched greatly. Therefore, for example, it can be suitably used for applications where semiconductor chips need to be sufficiently separated from each other, such as in the manufacture of FO-WLP.
  • the present invention is a semiconductor processing sheet comprising at least a base material, and the tensile modulus of the semiconductor processing sheet measured in the MD direction and the CD direction of the base material at 23 ° C. is 10 MPa or more, respectively. 350 MPa or less, and 100% stress of the semiconductor processing sheet measured in the MD direction and CD direction of the base material at 23 ° C. is 3 MPa or more and 20 MPa or less, respectively.
  • a test piece obtained by cutting a processing sheet into a size of 150 mm ⁇ 15 mm both ends in the length direction are gripped with a grip so that the length between the grips is 100 mm, and then pulled in the length direction at a speed of 200 mm / min.
  • invention 3 it becomes possible to extend
  • the substrate preferably contains a thermoplastic elastomer (Invention 5).
  • thermoplastic elastomer is preferably a urethane elastomer (Invention 6).
  • the semiconductor processing sheet is used to increase the interval between adjacent semiconductor chips in a plurality of semiconductor chips stacked on one side of the semiconductor processing sheet to 200 ⁇ m or more and 6000 ⁇ m or less. Is preferable (Invention 7).
  • a semiconductor processing sheet is provided by applying tension in the four directions of the + X axis direction, the ⁇ X axis direction, the + Y axis direction, and the ⁇ Y axis direction of the X axis and Y axis perpendicular to each other It is preferably used to widen the interval between a plurality of semiconductor chips stacked on one side of the semiconductor processing sheet by extending the length (Invention 8).
  • the semiconductor processing sheet according to the present invention can be stretched greatly, and the semiconductor chips can be sufficiently separated from each other.
  • the semiconductor processing sheet according to the present embodiment is configured to include at least a base material.
  • the restoration rate of the semiconductor processing sheet according to the present embodiment is preferably 70% or more and 100% or less.
  • the restoration rate is calculated as follows. First, a semiconductor processing sheet is cut out to 150 mm ⁇ 15 mm to obtain a test piece. The cutting is performed so that the MD direction of the base material in the semiconductor processing sheet matches the length direction of the test piece. Next, the both ends in the length direction of the test piece are grasped with the grasping tool so that the distance between the grasping tools is 100 mm. The length between the grips at this time is defined as a length L0 (mm) between the initial grips.
  • the length between the grips is pulled in the length direction at a speed of 200 mm / min, and is held for 1 minute in a state where the distance between the grips is 200 mm.
  • the length between the grips is returned at a speed of 200 mm / min, and is held for 1 minute with the distance between the grips being 100 mm (ie, L0 (mm)).
  • the length between the grips is pulled in the length direction at a speed of 60 mm / min, and the length between the grips when the measured value of the tensile force indicates 0.1 N / 15 mm is recorded.
  • L2 (mm) is obtained by subtracting the length L0 (mm) between the initial grippers from the length.
  • the restoration rate (%) can be obtained.
  • Restoration rate (%) ⁇ 1 ⁇ (L2 ⁇ L1) ⁇ ⁇ 100 (I)
  • the thickness of the test piece is not particularly limited, and may be the same as the thickness of the semiconductor processing sheet to be tested. Moreover, the specific measuring method is as showing in the test example mentioned later.
  • the semiconductor processing sheet according to the present embodiment for semiconductor processing measured in the MD direction of the substrate at 23 ° C. with respect to 100% stress of the semiconductor processing sheet measured in the CD direction of the substrate at 23 ° C.
  • the ratio of 100% stress of the sheet is preferably 0.8 or more and 1.2 or less.
  • the MD direction refers to the flow direction during manufacture of the substrate
  • the CD direction refers to a direction perpendicular to the MD direction.
  • 100% stress means the one calculated as follows.
  • a test piece obtained by cutting a semiconductor processing sheet into 150 mm ⁇ 15 mm hold both ends in the length direction with a grip so that the distance between grips is 100 mm, and pull in the length direction at a speed of 200 mm / min.
  • 100% stress (MPa) is obtained. can get.
  • the cutting is performed so that the flow direction (MD direction) or the direction orthogonal to the MD direction (CD direction) during the manufacture of the semiconductor processing sheet coincides with the length direction of the test piece.
  • the thickness of the test piece is not particularly limited, and may be the same as the thickness of the semiconductor processing sheet to be tested.
  • the specific measuring method is as showing in the test example mentioned later.
  • the tensile modulus of the semiconductor processing sheet measured in the MD direction and the CD direction of the base material at 23 ° C. is 10 MPa or more and 350 MPa or less, respectively.
  • 100% stress of the semiconductor processing sheet measured in the MD direction and CD direction of the substrate is 3 MPa or more and 20 MPa or less, respectively, and the semiconductor processing is measured in the MD direction and CD direction of the substrate at 23 ° C. It is preferable that the breaking elongation of each sheet is 100% or more.
  • the semiconductor processing sheet according to the present embodiment has the above-described physical properties, so that the semiconductor processing sheet can be easily stretched without causing breakage.
  • the restoration rate when the restoration rate is in the above range, it means that the semiconductor processing sheet is easily restored even after being largely stretched.
  • the sheet having a yield point when a sheet having a yield point is stretched beyond the yield point, the sheet undergoes plastic deformation, and a portion where plastic deformation has occurred, that is, an extremely stretched portion is unevenly distributed. If the sheet in such a state is further stretched, the expanded portion becomes non-uniform even if the above extremely stretched portion breaks or does not break.
  • the slope dx / dy does not take a stress value that changes from a positive value to 0 or a negative value, and a clear yield point. Even if the sheet does not show, the sheet undergoes plastic deformation as the tensile amount increases, and similarly, the sheet breaks or the expansion becomes non-uniform. On the other hand, when elastic deformation occurs instead of plastic deformation, the sheet can be easily restored to its original shape by removing the stress.
  • the restoration rate which is an index indicating how much to restore after 100% elongation, which is a sufficiently large tensile amount, is in the above range
  • the plastic deformation of the film is minimized when the semiconductor processing sheet is stretched greatly. It is suppressed to the limit, and breakage hardly occurs, and uniform expansion is possible.
  • the semiconductor processing sheet is stretched in the MD direction and CD direction of the substrate.
  • stretching may be referred to as “biaxial stretching”.
  • the semiconductor chips can be separated until the distance between the semiconductor chips reaches 200 ⁇ m or more.
  • a semiconductor processing sheet can be suitably used in a method for manufacturing a semiconductor device that requires a sufficiently wide interval between semiconductor chips, such as a method for manufacturing FO-WLP.
  • the restoration rate is preferably 70% or more, particularly preferably 80% or more, and more preferably 85% or more. preferable.
  • the restoration rate is preferably 100% or less.
  • the semiconductor processing sheet measured in the MD direction of the substrate at 23 ° C. with respect to 100% stress of the semiconductor processing sheet measured in the CD direction of the substrate at 23 ° C.
  • the ratio of 100% stress is preferably 0.8 or more, particularly preferably 0.83 or more, and more preferably 0.85 or more.
  • the ratio is preferably 1.2 or less, particularly preferably 1.17 or less, and more preferably 1.15 or less.
  • the breaking elongation of the semiconductor processing sheet measured in the CD direction of the base material at 23 ° C. is preferably 100% or more, particularly 150% or more. Preferably, it is preferably 200% or more.
  • the breaking elongation is preferably 1200% or less, and particularly preferably 1000% or less.
  • the semiconductor processing sheet can be greatly stretched in the CD direction of the substrate.
  • the method for measuring the breaking elongation in the CD direction is as shown in the test examples described later.
  • the breaking elongation of the semiconductor processing sheet measured in the MD direction of the base material at 23 ° C. is preferably 100% or more, particularly 150% or more. Preferably, it is preferably 200% or more.
  • the breaking elongation is preferably 1200% or less, and particularly preferably 1000% or less.
  • the semiconductor processing sheet can be greatly stretched in the MD direction of the base material.
  • the measuring method of the breaking elongation of MD direction is as showing to the test example mentioned later.
  • the tensile modulus of the semiconductor processing sheet measured in the CD direction of the base material at 23 ° C. is preferably 10 MPa or more, particularly preferably 20 MPa or more, Further, it is preferably 25 MPa or more.
  • the tensile elastic modulus is preferably 350 MPa or less, particularly preferably 300 MPa or less, and further preferably 250 MPa or less.
  • the tensile elastic modulus is 10 MPa or more, when a semiconductor chip or the like is laminated on the semiconductor processing sheet, the semiconductor chip or the like can be favorably supported.
  • the tensile elastic modulus is 350 MPa or less, the semiconductor processing sheet has moderate flexibility, and the semiconductor processing sheet can be more easily stretched.
  • the measuring method of the said tensile elasticity modulus is as showing to the test example mentioned later.
  • the tensile modulus of the semiconductor processing sheet measured in the MD direction of the substrate at 23 ° C. is preferably 10 MPa or more, particularly preferably 20 MPa or more, Further, it is preferably 25 MPa or more.
  • the tensile elastic modulus is preferably 350 MPa or less, particularly preferably 300 MPa or less, and further preferably 250 MPa or less.
  • the tensile elastic modulus is 10 MPa or more, when a semiconductor chip or the like is laminated on the semiconductor processing sheet, the semiconductor chip or the like can be favorably supported.
  • the tensile elastic modulus is 350 MPa or less, the semiconductor processing sheet has moderate flexibility, and the semiconductor processing sheet can be more easily stretched.
  • the measuring method of the said tensile elasticity modulus is as showing to the test example mentioned later.
  • the 100% stress of the semiconductor processing sheet measured in the CD direction of the substrate at 23 ° C. is preferably 3 MPa or more, particularly preferably 5 MPa or more, Furthermore, it is preferable that it is 6 MPa or more.
  • the 100% stress is preferably 20 MPa or less, particularly preferably 18 MPa or less, and more preferably 16 MPa or less.
  • the breaking elongation is 20 MPa or less, it is possible to greatly stretch the semiconductor processing sheet without imposing an excessive load on the expanding device. Even if the device is used continuously over a long period of time, the device fails. Can be expected to prevent.
  • the method for measuring 100% stress in the CD direction is as shown in the test examples described later.
  • the 100% stress of the semiconductor processing sheet measured in the MD direction of the substrate at 23 ° C. is preferably 3 MPa or more, particularly preferably 5 MPa or more, Furthermore, it is preferable that it is 6 MPa or more.
  • the 100% stress is 3 MPa or more, even if the thickness of the base material is reduced by greatly stretching the semiconductor processing sheet, the force necessary to support the separated chips can be maintained. This makes it possible to greatly stretch the semiconductor processing sheet in the CD direction of the substrate.
  • the 100% stress is preferably 20 MPa or less, particularly preferably 18 MPa or less, and more preferably 16 MPa or less.
  • the breaking elongation is 20 MPa or less, it is possible to greatly stretch the semiconductor processing sheet without imposing an excessive load on the expanding device. Even if the device is used continuously over a long period of time, the device fails. Can be expected to prevent.
  • the measuring method of 100% stress in the MD direction is as shown in a test example described later.
  • the semiconductor processing sheet according to the present embodiment preferably has adhesiveness on at least one surface. Thereby, it becomes possible to stick and fix a semiconductor chip etc. on the said surface.
  • the surface of the semiconductor processing sheet that has adhesiveness and is attached with a semiconductor chip or the like may be referred to as an “adhesive surface”.
  • the adhesive strength of the semiconductor processing sheet according to the present embodiment is preferably 300 mN / 25 mm or more, particularly preferably 800 mN / 25 mm or more, and more preferably 1000 mN / 25 mm or more.
  • the adhesive strength is preferably 30000 mN / 25 mm or less, particularly preferably 15000 mN / 25 mm or less, and more preferably 10000 mN / 25 mm or less.
  • the adhesive force is 300 mN / 25 mm or more, a semiconductor chip or the like can be satisfactorily adhered and fixed to the adhesive surface.
  • the adhesive force is 30000 mN / 25 mm or less, the semiconductor processing sheet according to the present embodiment is replaced with another semiconductor sheet or the like, and the semiconductor processing sheet according to the present embodiment is changed to a semiconductor.
  • the adhesive strength is an adhesive strength (mN / 25 mm) measured by a 180 ° peeling method according to JIS Z0237: 2009 using a silicon mirror wafer as an adherend.
  • the adhesive strength is measured on one surface of the base material, and the semiconductor processing sheet according to the present embodiment is based on the base material.
  • adhesive force shall be measured about the surface on the opposite side to the base material in the said adhesive layer.
  • the semiconductor processing sheet according to the present embodiment preferably has heat resistance.
  • the semiconductor chip may be sealed with a sealing member on the semiconductor processing sheet according to the present embodiment.
  • a thermosetting material is used as the sealing member, and the material is heated at the time of sealing.
  • the thickness of the semiconductor processing sheet according to this embodiment is preferably 30 ⁇ m or more, and particularly preferably 50 ⁇ m or more. Further, the thickness is preferably 300 ⁇ m or less, and particularly preferably 250 ⁇ m or less.
  • the base material of the semiconductor processing sheet according to the present embodiment is not particularly limited as long as the semiconductor processing sheet can achieve the above-described physical properties.
  • a resin-based material is a main material. It is comprised from the film.
  • a thermoplastic elastomer it is particularly preferred to use a thermoplastic elastomer.
  • a resin having a relatively low glass transition temperature (Tg) as a constituent material of the base material.
  • the glass transition temperature ( Tg) is preferably 90 ° C. or lower, particularly preferably 80 ° C. or lower, and more preferably 70 ° C. or lower.
  • thermoplastic elastomers examples include urethane elastomers, olefin elastomers, vinyl chloride elastomers, polyester elastomers, styrene elastomers, acrylic elastomers, and amide elastomers.
  • urethane elastomers examples include urethane elastomers, olefin elastomers, vinyl chloride elastomers, polyester elastomers, styrene elastomers, acrylic elastomers, and amide elastomers.
  • urethane elastomers examples include urethane elastomers, olefin elastomers, vinyl chloride elastomers, polyester elastomers, styrene elastomers, acrylic elastomers, and amide elastomers.
  • a urethane-based elastomer is generally obtained by reacting a long-chain polyol, a chain extender and a diisocyanate, and a soft segment having a structural unit derived from a long-chain polyol, and a reaction between the chain extender and the diisocyanate. From a hard segment having a polyurethane structure.
  • urethane-based elastomers When urethane-based elastomers are classified according to the type of long-chain polyol used as the soft segment component, they can be classified into polyester-based polyurethane elastomers, polyether-based polyurethane elastomers, polycarbonate-based polyurethane elastomers, and the like. In the semiconductor processing sheet according to the present embodiment, among these, it is preferable to use a polyether-based polyurethane elastomer from the viewpoint of easily achieving the above-described physical properties.
  • long-chain polyol examples include polyester polyols such as lactone polyester polyols and adipate polyester polyols; polyether polyols such as polypropylene (ethylene) polyol and polytetramethylene ether glycol; polycarbonate polyols and the like.
  • polyester polyols such as lactone polyester polyols and adipate polyester polyols
  • polyether polyols such as polypropylene (ethylene) polyol and polytetramethylene ether glycol
  • polycarbonate polyols and the like it is preferable to use an adipate polyester polyol from the viewpoint of easily achieving the above-described physical properties.
  • diisocyanate examples include 2,4-toluene diisocyanate, 2,6-toluene diisocyanate, 4,4'-diphenylmethane diisocyanate, hexamethylene diisocyanate, and the like. Among these, it is preferable to use hexamethylene diisocyanate from the viewpoint of easily achieving the physical properties described above.
  • chain extender examples include low molecular weight polyhydric alcohols such as 1,4-butanediol and 1,6-hexanediol, and aromatic diamines. Of these, 1,6-hexanediol is preferably used from the viewpoint of easily achieving the above-described physical properties.
  • olefin elastomers examples include ethylene / ⁇ -olefin copolymers, propylene / ⁇ -olefin copolymers, butene / ⁇ -olefin copolymers, ethylene / propylene / ⁇ -olefin copolymers, ethylene / butene / ⁇ - At least selected from the group consisting of olefin copolymers, propylene / butene- ⁇ olefin copolymers, ethylene / propylene / butene / ⁇ / olefin copolymers, styrene / isoprene copolymers and styrene / ethylene / butylene copolymers.
  • the thing containing 1 type of resin is mentioned.
  • the density of the olefin-based elastomer is not particularly limited, but is 0.860 g / cm 3 or more from the viewpoint of more stably obtaining a substrate excellent in unevenness followability when a semiconductor wafer is attached to a semiconductor processing sheet. It is preferably less than .905g / cm 3, more preferably less than 0.862 g / cm 3 or more 0.900 g / cm 3, less than 0.864 g / cm 3 or more 0.895 g / cm 3 Is particularly preferred.
  • the olefin-based elastomer has a mass ratio (also referred to as “olefin content” in the present specification) of a monomer composed of an olefin-based compound of all monomers used for forming the elastomer of 50 to 100. It is preferable that it is mass%.
  • the olefin content is excessively low, properties as an elastomer containing structural units derived from olefins are hardly exhibited, and flexibility and rubber elasticity are hardly exhibited. From the viewpoint of stably obtaining such an effect, the olefin content is preferably 50% by mass or more, and more preferably 60% by mass or more.
  • styrene elastomer examples include styrene-conjugated diene copolymer and styrene-olefin copolymer.
  • Specific examples of the styrene-conjugated diene copolymer include styrene-butadiene copolymer, styrene-butadiene-styrene copolymer (SBS), styrene-butadiene-butylene-styrene copolymer, styrene-isoprene copolymer, Unhydrogenated styrene-conjugated diene copolymers such as styrene-isoprene-styrene copolymer (SIS) and styrene-ethylene-isoprene-styrene copolymer; styrene-ethylene / propylene-styrene copoly
  • the styrene elastomer may be a hydrogenated product or an unhydrogenated product.
  • rubber materials include natural rubber, synthetic isoprene rubber (IR), butadiene rubber (BR), styrene-butadiene rubber (SBR), chloroprene rubber (CR), acrylonitrile-butadiene copolymer rubber (NBR), butyl rubber ( IIR), halogenated butyl rubber, acrylic rubber, urethane rubber, polysulfide rubber and the like, and these can be used alone or in combination of two or more.
  • IR synthetic isoprene rubber
  • BR butadiene rubber
  • SBR styrene-butadiene rubber
  • CR chloroprene rubber
  • NBR acrylonitrile-butadiene copolymer rubber
  • IIR butyl rubber
  • halogenated butyl rubber acrylic rubber, urethane rubber, polysulfide rubber and the like, and these can be used alone or in combination of two or more.
  • a film in which a plurality of films made of the above materials are laminated can be used. Moreover, what laminated
  • a film having a high contribution rate in achieving the above-described physical properties is arranged in the center with a relatively thick thickness, and the film is formed with a relatively thin thickness with a low contribution rate. It can be configured to be sandwiched between different films.
  • the use of a resin having a relatively low glass transition temperature (Tg) is preferable for achieving the above-described physical properties.
  • Tg glass transition temperature
  • a resin film having a relatively low glass transition temperature (Tg) is sandwiched between resin films having a relatively high glass transition temperature (Tg), or a glass transition temperature relative to a resin film having a relatively low glass transition temperature (Tg).
  • Tg glass transition temperature
  • Tg glass transition temperature
  • the base material preferably has adhesiveness.
  • the said adhesiveness is what is exhibited by a normal state, it is preferable to use what has self-adhesiveness as a base material.
  • the semiconductor processing sheet according to the present embodiment is composed of only a base material and the base material is formed by laminating a plurality of films, among the plurality of laminated films, the sheet is positioned in the outermost layer. Only the film to perform or only one of them may have adhesiveness. For example, by laminating a resin film with a relatively high glass transition temperature (Tg) on one surface of a resin film with a relatively low glass transition temperature (Tg), it exhibits adhesiveness only on that one surface. Can be made.
  • Tg glass transition temperature
  • Tg relatively low glass transition temperature
  • the outermost layer of the semiconductor processing sheet in this specification does not include a release sheet or the like that is removed during use.
  • various additives such as pigments, dyes, flame retardants, plasticizers, antistatic agents, lubricants, fillers, and the like may be included in the film mainly composed of the resin material.
  • the pigment include titanium dioxide and carbon black.
  • the filler include organic materials such as melamine resin, inorganic materials such as fumed silica, and metal materials such as nickel particles.
  • the content of such an additive is not particularly limited, but it is preferable to keep the content within a range in which the base material can exhibit a desired function.
  • the base material is formed on one surface or both surfaces as desired by an oxidation method or an unevenness method for the purpose of improving adhesion with the pressure-sensitive adhesive layer laminated on the surface.
  • the surface treatment by the above, or the primer treatment for forming the primer layer can be performed.
  • the oxidation method include corona discharge treatment, plasma discharge treatment, chromium oxidation treatment (wet), flame treatment, hot air treatment, ozone, ultraviolet irradiation treatment, and the like.
  • Examples include a thermal spraying method.
  • the substrate has transparency to energy rays.
  • the substrate preferably has transparency to ultraviolet rays
  • electron beams are used as energy rays
  • the substrate may have electron beam transparency. preferable.
  • the substrate production method is not particularly limited.
  • a cast molding method (melt casting method), a melt extrusion method such as a T-die method or an inflation method, a calendar method, or the like. Any method may be used.
  • the coating is cured to form a film. It is preferable that can be manufactured.
  • the thickness of the substrate is not limited as long as the semiconductor processing sheet can function properly in a desired process.
  • the thickness of the substrate is preferably 20 ⁇ m or more, and particularly preferably 40 ⁇ m or more. Further, the thickness is preferably 250 ⁇ m or less, and particularly preferably 200 ⁇ m or less.
  • the standard deviation of the thickness of the base material when the thickness is measured at intervals of 2 cm is preferably 2 ⁇ m or less, particularly preferably 1.5 ⁇ m or less, and further preferably 1 ⁇ m or less.
  • the semiconductor processing sheet has a highly accurate thickness, and the semiconductor processing sheet can be uniformly stretched.
  • the semiconductor processing sheet according to the present embodiment preferably further includes an adhesive layer laminated on at least one surface of the substrate.
  • the semiconductor processing sheet easily exhibits desired adhesiveness on the surface on the pressure-sensitive adhesive layer side, and a semiconductor chip or the like can be satisfactorily adhered to the surface.
  • the pressure-sensitive adhesive layer is not particularly limited as long as the physical properties described above can be achieved in the semiconductor processing sheet.
  • the pressure-sensitive adhesive layer may be composed of a non-energy ray curable pressure sensitive adhesive or an energy ray curable pressure sensitive adhesive.
  • the non-energy ray curable pressure-sensitive adhesive those having desired adhesive strength and removability are preferable.
  • Polyvinyl ether-based pressure-sensitive adhesives can be used. Among these, an acrylic pressure-sensitive adhesive that can effectively suppress dropping of a semiconductor chip or the like when the semiconductor processing sheet is stretched is preferable.
  • the energy ray curable adhesive is cured by energy ray irradiation and its adhesive strength is reduced. Therefore, when it is desired to separate the semiconductor chip and the semiconductor processing sheet, it can be easily separated by irradiating the energy ray. be able to.
  • the energy ray-curable pressure-sensitive adhesive constituting the pressure-sensitive adhesive layer may be mainly composed of a polymer having energy ray-curability, or a non-energy ray-curable polymer (polymer not having energy ray-curability). And a mixture of a monomer and / or an oligomer having at least one energy ray curable group. Further, it may be a mixture of a polymer having energy ray curable properties and a non-energy ray curable polymer, a polymer having energy ray curable properties and a monomer having at least one energy ray curable group and / or It may be a mixture with an oligomer or a mixture of these three.
  • the energy ray-curable pressure-sensitive adhesive is composed mainly of a polymer having energy ray-curability.
  • the polymer having energy ray curability is a (meth) acrylic acid ester (co) polymer (A) (hereinafter referred to as “energy ray”) in which a functional group having energy ray curability (energy ray curable group) is introduced into the side chain. It may be referred to as “curable polymer (A)”).
  • This energy beam curable polymer (A) reacts an acrylic copolymer (a1) having a functional group-containing monomer unit with an unsaturated group-containing compound (a2) having a functional group bonded to the functional group. It is preferable that it is obtained.
  • (meth) acrylic acid ester means both acrylic acid ester and methacrylic acid ester. The same applies to other similar terms.
  • the acrylic copolymer (a1) preferably contains a structural unit derived from a functional group-containing monomer and a structural unit derived from a (meth) acrylic acid ester monomer or a derivative thereof.
  • the functional group-containing monomer as a constituent unit of the acrylic copolymer (a1) contains a polymerizable double bond and a functional group such as a hydroxy group, a carboxy group, an amino group, a substituted amino group, and an epoxy group in the molecule. It is preferable that the monomer has
  • hydroxy group-containing monomer examples include 2-hydroxyethyl (meth) acrylate, 2-hydroxypropyl (meth) acrylate, 3-hydroxypropyl (meth) acrylate, 2-hydroxybutyl (meth) acrylate, 3-hydroxybutyl ( Examples thereof include meth) acrylate and 4-hydroxybutyl (meth) acrylate, and these are used alone or in combination of two or more.
  • carboxy group-containing monomer examples include ethylenically unsaturated carboxylic acids such as acrylic acid, methacrylic acid, crotonic acid, maleic acid, itaconic acid, and citraconic acid. These may be used alone or in combination of two or more.
  • carboxylic acids such as acrylic acid, methacrylic acid, crotonic acid, maleic acid, itaconic acid, and citraconic acid. These may be used alone or in combination of two or more.
  • amino group-containing monomer or substituted amino group-containing monomer examples include aminoethyl (meth) acrylate and n-butylaminoethyl (meth) acrylate. These may be used alone or in combination of two or more.
  • Examples of the (meth) acrylic acid ester monomer constituting the acrylic copolymer (a1) include an alkyl (meth) acrylate having an alkyl group having 1 to 20 carbon atoms, and an alicyclic structure in the molecule, for example.
  • the monomer (alicyclic structure-containing monomer) is preferably used.
  • alkyl (meth) acrylate examples include alkyl (meth) acrylates having an alkyl group having 1 to 18 carbon atoms, such as methyl (meth) acrylate, ethyl (meth) acrylate, propyl (meth) acrylate, n-butyl ( (Meth) acrylate, 2-ethylhexyl (meth) acrylate and the like are preferably used. These may be used individually by 1 type and may be used in combination of 2 or more type.
  • Examples of the alicyclic structure-containing monomer include cyclohexyl (meth) acrylate, dicyclopentanyl (meth) acrylate, adamantyl (meth) acrylate, isobornyl (meth) acrylate, and dicyclopentenyl (meth) acrylate.
  • Dicyclopentenyloxyethyl (meth) acrylate and the like are preferably used. These may be used individually by 1 type and may be used in combination of 2 or more type.
  • the acrylic copolymer (a1) contains the structural unit derived from the functional group-containing monomer, preferably in an amount of 1% by mass or more, particularly preferably 5% by mass or more, and more preferably 10% by mass or more.
  • the acrylic copolymer (a1) preferably contains a constituent unit derived from the functional group-containing monomer in a proportion of 35% by mass or less, particularly preferably 30% by mass or less, and more preferably 25% by mass or less. To do.
  • the acrylic copolymer (a1) preferably contains 50% by mass or more, particularly preferably 60% by mass or more, and further preferably 70% by mass of a structural unit derived from a (meth) acrylic acid ester monomer or a derivative thereof. It contains in the above ratio.
  • the acrylic copolymer (a1) preferably contains 99% by mass or less, particularly preferably 95% by mass or less, and more preferably 90% by mass of a structural unit derived from a (meth) acrylic acid ester monomer or a derivative thereof. Contains in the following proportions.
  • the acrylic copolymer (a1) can be obtained by copolymerizing a functional group-containing monomer as described above with a (meth) acrylic acid ester monomer or a derivative thereof in a conventional manner. Dimethylacrylamide, vinyl formate, vinyl acetate, styrene and the like may be copolymerized.
  • an energy beam curable polymer (A ) Is obtained.
  • the functional group of the unsaturated group-containing compound (a2) can be appropriately selected according to the type of functional group of the functional group-containing monomer unit of the acrylic copolymer (a1).
  • the functional group of the acrylic copolymer (a1) is a hydroxy group, an amino group or a substituted amino group
  • the functional group of the unsaturated group-containing compound (a2) is preferably an isocyanate group or an epoxy group.
  • the functional group that the system copolymer (a1) has is an epoxy group
  • the functional group that the unsaturated group-containing compound (a2) has is preferably an amino group, a carboxy group, or an aziridinyl group.
  • the unsaturated group-containing compound (a2) contains at least one, preferably 1-6, more preferably 1-4, energy-polymerizable carbon-carbon double bonds in one molecule. ing.
  • Specific examples of such unsaturated group-containing compound (a2) include, for example, 2-methacryloyloxyethyl isocyanate, meta-isopropenyl- ⁇ , ⁇ -dimethylbenzyl isocyanate, methacryloyl isocyanate, allyl isocyanate, 1,1- ( Bisacryloyloxymethyl) ethyl isocyanate; acryloyl monoisocyanate compound obtained by reaction of diisocyanate compound or polyisocyanate compound with hydroxyethyl (meth) acrylate; diisocyanate compound or polyisocyanate compound, polyol compound, and hydroxyethyl (meth) Acryloyl monoisocyanate compound obtained by reaction with acrylate; glycidyl (meth)
  • the unsaturated group-containing compound (a2) is preferably at least 50 mol%, particularly preferably at least 60 mol%, more preferably 70 mol, based on the number of moles of the functional group-containing monomer of the acrylic copolymer (a1). % Is used at a rate of at least%.
  • the unsaturated group-containing compound (a2) is preferably 95 mol% or less, particularly preferably 93 mol% or less, more preferably, relative to the number of moles of the functional group-containing monomer of the acrylic copolymer (a1). It is used at a ratio of 90 mol% or less.
  • the functional group of the acrylic copolymer (a1) and the functional group of the unsaturated group-containing compound (a2) Depending on the combination, the reaction temperature, pressure, solvent, time, presence / absence of catalyst, and type of catalyst can be appropriately selected. As a result, the functional group present in the acrylic copolymer (a1) reacts with the functional group in the unsaturated group-containing compound (a2), so that the unsaturated group is contained in the acrylic copolymer (a1). It introduce
  • the weight average molecular weight (Mw) of the energy ray curable polymer (A) thus obtained is preferably 10,000 or more, particularly preferably 150,000 or more, and more preferably 200,000 or more. Is preferred.
  • the weight average molecular weight (Mw) is preferably 1.5 million or less, and particularly preferably 1 million or less.
  • the weight average molecular weight (Mw) in this specification is the value of standard polystyrene conversion measured by the gel permeation chromatography method (GPC method).
  • the energy ray curable adhesive is mainly composed of an energy ray curable polymer such as an energy ray curable polymer (A)
  • the energy ray curable adhesive is an energy ray curable monomer.
  • oligomer (B) may further be contained.
  • the energy ray-curable monomer and / or oligomer (B) for example, an ester of a polyhydric alcohol and (meth) acrylic acid or the like can be used.
  • Examples of the energy ray-curable monomer and / or oligomer (B) include monofunctional acrylic acid esters such as cyclohexyl (meth) acrylate and isobornyl (meth) acrylate, trimethylolpropane tri (meth) acrylate, penta Erythritol tri (meth) acrylate, pentaerythritol tetra (meth) acrylate, dipentaerythritol hexa (meth) acrylate, 1,4-butanediol di (meth) acrylate, 1,6-hexanediol di (meth) acrylate, polyethylene glycol Polyfunctional acrylic esters such as di (meth) acrylate and dimethyloltricyclodecane di (meth) acrylate, polyester oligo (meth) acrylate, polyurethane oligo (meta Acrylate, and the like.
  • monofunctional acrylic acid esters such as
  • the energy ray curable monomer (B) When the energy ray curable monomer (B) is blended with the energy ray curable polymer (A), the energy ray curable monomer and / or oligomer (B) in the energy ray curable adhesive is used.
  • Content is preferably more than 0 parts by mass, particularly preferably 60 parts by mass or more, with respect to 100 parts by mass of the energy ray-curable polymer (A).
  • the content is preferably 250 parts by mass or less, particularly preferably 200 parts by mass or less, with respect to 100 parts by mass of the energy beam curable polymer (A).
  • photopolymerization initiator (C) examples include benzophenone, acetophenone, benzoin, benzoin methyl ether, benzoin ethyl ether, benzoin isopropyl ether, benzoin isobutyl ether, benzoin benzoic acid, benzoin methyl benzoate, benzoin dimethyl ketal, 2,4-diethylthioxanthone, 1-hydroxycyclohexyl phenyl ketone, benzyldiphenyl sulfide, tetramethylthiuram monosulfide, azobisisobutyronitrile, benzyl, dibenzyl, diacetyl, ⁇ -chloranthraquinone, (2,4 6-trimethylbenzyldiphenyl) phosphine oxide, 2-benzothiazole-N, N-diethyldithiocarbamate, oligo ⁇ 2-hydroxy-2-me Le-1- [4-
  • the photopolymerization initiator (C) is energy beam curable copolymer (A) (when energy beam curable monomer and / or oligomer (B) is blended, energy beam curable copolymer (A).
  • the total amount of the energy ray-curable monomer and / or oligomer (B) is 100 parts by mass) and is preferably used in an amount of 0.1 parts by mass or more, particularly 0.5 parts by mass or more with respect to 100 parts by mass.
  • the photopolymerization initiator (C) is energy beam curable copolymer (A) (when energy beam curable monomer and / or oligomer (B) is blended, energy beam curable copolymer (
  • the total amount of A) and energy ray-curable monomer and / or oligomer (B) is 100 parts by mass) and is preferably used in an amount of 10 parts by mass or less, particularly 6 parts by mass or less.
  • other components may be appropriately blended in addition to the above components.
  • other components include a non-energy ray curable polymer component or oligomer component (D), and a crosslinking agent (E).
  • non-energy ray curable polymer component or oligomer component (D) examples include polyacrylates, polyesters, polyurethanes, polycarbonates, polyolefins, etc., and polymers or oligomers having a weight average molecular weight (Mw) of 3000 to 2.5 million. Is preferred.
  • Mw weight average molecular weight
  • strength after hardening, the adhesiveness with another layer, storage stability, etc. can be improved.
  • the compounding quantity of the said component (D) is not specifically limited, It determines suitably in the range of more than 0 mass part and 50 mass parts or less with respect to 100 mass parts of energy-beam curable copolymers (A).
  • crosslinking agent (E) a polyfunctional compound having reactivity with the functional group of the energy beam curable copolymer (A) or the like can be used.
  • polyfunctional compounds include isocyanate compounds, epoxy compounds, amine compounds, melamine compounds, aziridine compounds, hydrazine compounds, aldehyde compounds, oxazoline compounds, metal alkoxide compounds, metal chelate compounds, metal salts, ammonium salts, A reactive phenol resin etc. can be mentioned.
  • the amount of the crosslinking agent (E) is preferably 0.01 parts by mass or more, particularly 0.03 parts by mass or more, with respect to 100 parts by mass of the energy ray curable copolymer (A). More preferably, it is 0.04 parts by mass or more.
  • the amount of the crosslinking agent (E) is preferably 8 parts by mass or less, particularly preferably 5 parts by mass or less, with respect to 100 parts by mass of the energy ray curable copolymer (A). Furthermore, it is preferable that it is 3.5 mass parts or less.
  • the energy beam curable pressure-sensitive adhesive is mainly composed of a mixture of a non-energy beam curable polymer component and a monomer and / or oligomer having at least one energy beam curable group will be described below. .
  • non-energy ray curable polymer component for example, the same components as the acrylic copolymer (a1) described above can be used.
  • the same one as the above-mentioned component (B) can be selected.
  • the blending ratio of the non-energy ray curable polymer component and the monomer and / or oligomer having at least one energy ray curable group is at least one or more with respect to 100 parts by mass of the non-energy ray curable polymer component.
  • the amount of the monomer and / or oligomer having an energy ray-curable group is preferably 1 part by mass or more, and particularly preferably 60 parts by mass or more.
  • the blending ratio is preferably not more than 200 parts by mass of monomers and / or oligomers having at least one energy ray-curable group with respect to 100 parts by mass of the non-energy ray-curable polymer component. It is preferably less than or equal to parts by mass.
  • the photopolymerization initiator (C) and the crosslinking agent (E) can be appropriately blended as described above.
  • the thickness of the pressure-sensitive adhesive layer is not particularly limited, and is preferably, for example, 3 ⁇ m or more, and particularly preferably 5 ⁇ m or more.
  • the thickness is preferably 50 ⁇ m or less, and particularly preferably 40 ⁇ m or less.
  • the semiconductor processing sheet according to the present embodiment may be laminated with a release sheet for the purpose of protecting the adhesive surface until the adhesive surface is attached to an adherend such as a semiconductor chip.
  • the configuration of the release sheet is arbitrary, and examples include a release film of a plastic film with a release agent.
  • Specific examples of the plastic film include polyester films such as polyethylene terephthalate, polybutylene terephthalate, and polyethylene naphthalate, and polyolefin films such as polypropylene and polyethylene.
  • the release agent silicone-based, fluorine-based, long-chain alkyl-based, and the like can be used, and among these, a silicone-based material that is inexpensive and provides stable performance is preferable.
  • the thickness of the release sheet is not particularly limited, but is usually about 20 to 250 ⁇ m.
  • the semiconductor processing sheet according to this embodiment can be manufactured in the same manner as a conventional semiconductor processing sheet.
  • a method for producing a semiconductor processing sheet comprising a substrate and a pressure-sensitive adhesive layer a detailed method is particularly suitable if a pressure-sensitive adhesive layer formed from the above-mentioned pressure-sensitive adhesive composition can be laminated on one surface of the substrate. It is not limited.
  • a pressure-sensitive adhesive composition constituting the pressure-sensitive adhesive layer and, if desired, a coating liquid further containing a solvent or a dispersion medium are prepared, and a die coater, a curtain coater, and a spray are formed on one surface of the substrate.
  • the pressure-sensitive adhesive layer can be formed by applying the coating solution with a coater, slit coater, knife coater or the like to form a coating film and drying the coating film.
  • the properties of the coating liquid are not particularly limited as long as it can be applied, and may contain a component for forming the pressure-sensitive adhesive layer as a solute or a dispersoid.
  • a coating liquid is apply
  • a laminate of the semiconductor processing sheet and the release sheet may be obtained by forming a laminate made of the above and affixing the surface opposite to the release sheet side of the adhesive layer of the laminate to the substrate. .
  • the release sheet in this laminate may be peeled off as a process material, or the adhesive layer may be protected until being attached to an adherend such as a semiconductor chip or a semiconductor wafer.
  • the non-energy ray-curable acrylic adhesive in the coating film can be changed by changing the drying conditions (temperature, time, etc.) or by separately providing a heat treatment.
  • the crosslinking reaction between the agent (N) or the energy ray-curable pressure-sensitive adhesive (A) and the crosslinking agent may be advanced to form a crosslinked structure at a desired density in the pressure-sensitive adhesive layer.
  • the obtained semiconductor processing sheet is placed in an environment of, for example, 23 ° C. and a relative humidity of 50% for several days. Curing such as leaving still may be performed.
  • the semiconductor processing sheet according to the present embodiment can be used, for example, to increase the interval between a plurality of semiconductor chips stacked on one side of the semiconductor processing sheet.
  • the interval between adjacent semiconductor chips in a plurality of semiconductor chips stacked on one side of the semiconductor processing sheet is preferably used to increase the interval between adjacent semiconductor chips in a plurality of semiconductor chips stacked on one side of the semiconductor processing sheet by 200 ⁇ m or more.
  • the upper limit of the interval is not particularly limited, but may be 6000 ⁇ m, for example.
  • the semiconductor processing sheet according to the present embodiment can also be used when the interval between a plurality of semiconductor chips stacked on one side of the semiconductor processing sheet is expanded by at least biaxial stretching.
  • the semiconductor processing sheet is stretched by applying tension in four directions of the + X axis direction, the ⁇ X axis direction, the + Y axis direction, and the ⁇ Y axis direction on the X axis and the Y axis orthogonal to each other. More specifically, the film is stretched in the MD direction and the CD direction, respectively.
  • the biaxial stretching as described above can be performed using, for example, a separation device that applies tension in the X-axis direction and the Y-axis direction.
  • the X axis and the Y axis are orthogonal to each other, and one of the directions parallel to the X axis is the + X axis direction, the opposite direction to the + X axis direction is the ⁇ X axis direction, and the direction parallel to the Y axis.
  • One of them is defined as a + Y axis direction
  • a direction opposite to the + Y axis direction is defined as a ⁇ Y axis direction.
  • the spacing device applies tension to the semiconductor processing sheet in four directions of + X axis direction, -X axis direction, + Y axis direction, and -Y axis direction, and a plurality of holding means in each of these four directions And a plurality of tension applying means corresponding to them.
  • the number of holding means and tension applying means in each direction may be, for example, about 3 or more and 10 or less, depending on the size of the semiconductor processing sheet.
  • each holding means includes a holding member that holds the semiconductor processing sheet. It is preferable that each tension applying means applies a tension to the semiconductor processing sheet by moving the holding member corresponding to the tension applying means in the + X-axis direction. And it is preferable that the several tension
  • the same configuration is also applied to three groups including a plurality of holding means and a plurality of tension applying means provided for applying tension in the ⁇ X axis direction, the + Y axis direction, and the ⁇ Y axis direction, respectively. It is preferable to have.
  • the said separation apparatus can give tension
  • the composite sheet includes these composite directions (for example, the composite direction of the + X axis direction and the + Y axis direction, the composite direction of the + Y axis direction and the ⁇ X axis direction, the ⁇ X axis direction and the ⁇ Y axis)
  • the tension is also applied to the composite direction with the direction and the composite direction of the ⁇ Y axis direction and the + X axis direction).
  • the plurality of tension applying means independently apply tension to the semiconductor processing sheet in each of the + X axis direction, the ⁇ X axis direction, the + Y axis direction, and the ⁇ Y axis direction. Therefore, the semiconductor processing sheet can be stretched so that the difference between the inner side and the outer side of the semiconductor processing sheet as described above is eliminated. As a result, the interval between the semiconductor chips can be adjusted accurately.
  • the spacing device further includes a measuring unit that measures the mutual spacing of the semiconductor chips.
  • the tension applying means is provided so that a plurality of holding members can be individually moved based on the measurement result of the measuring means. Thereby, based on the measurement result of the interval between the semiconductor chips by the measuring means, the interval can be further adjusted, and as a result, the interval between the semiconductor chips can be adjusted more accurately.
  • the holding means may be a chuck means such as a mechanical chuck or a chuck cylinder, a pressure reducing means such as a vacuum pump or a vacuum ejector, or a semiconductor processing sheet by an adhesive, magnetic force, or the like.
  • the structure which supports may be sufficient.
  • the holding member in the chuck means for example, a lower support member that supports the semiconductor processing sheet from below, a drive device supported by the lower support member, and an output shaft of the drive device, the drive device is driven. By doing so, what has the structure provided with the upper support member which can press down the sheet
  • Examples of the drive device include electric devices such as a rotation motor, a linear motion motor, a linear motor, a single-axis robot, and an articulated robot, and actuators such as an air cylinder, a hydraulic cylinder, a rodless cylinder, and a rotary cylinder. .
  • the tension applying means may include a driving device, and the holding member may be moved by the driving device.
  • the driving device those described above can be used.
  • the tension applying means includes a linear motion motor as a drive device, and an output shaft interposed between the linear motion motor and the holding member, and the driven linear motion motor moves the holding member via the output shaft. It may be a configuration.
  • the interval may be increased from a state where the semiconductor chips are in contact with each other, or a state where the interval between the semiconductor chips is hardly increased, or The distance between the semiconductor chips may be further increased from the state in which the distance between the semiconductor chips is already increased to a predetermined distance.
  • the semiconductor chips are in contact with each other or the gap between the semiconductor chips is not widened.
  • a plurality of semiconductor chips can be transferred from the dicing sheet to the semiconductor processing sheet according to the present embodiment, and then the interval between the semiconductor chips can be increased.
  • the interval between the semiconductor chips can be increased.
  • the semiconductor chip can be further expanded by using another semiconductor processing sheet, preferably the semiconductor processing sheet according to the present embodiment.
  • the semiconductor chip is transferred from the sheet to the semiconductor processing sheet according to the present embodiment, and then the semiconductor processing sheet according to the present embodiment is stretched to extend the semiconductor chip. Can be further widened.
  • Such transfer of the semiconductor chip and stretching of the semiconductor processing sheet may be repeated a plurality of times until the distance between the semiconductor chips reaches a desired distance.
  • the semiconductor processing sheet according to the present embodiment is preferably used for applications that require a relatively large gap between the semiconductor chips. Examples of such applications include fan-out type semiconductor wafer levels.
  • a method for producing a package (FO-WLP) is preferred. Examples of such a method for producing FO-WLP include a first aspect and a second aspect described below.
  • FIG. 1A shows a semiconductor wafer W adhered to the first adhesive sheet 10.
  • the semiconductor wafer W has a circuit surface W1, and a circuit W2 is formed on the circuit surface W1.
  • the first adhesive sheet 10 is attached to the back surface W3 of the semiconductor wafer W opposite to the circuit surface W1.
  • the first pressure-sensitive adhesive sheet 10 has a first base film 11 and a first pressure-sensitive adhesive layer 12.
  • the first pressure-sensitive adhesive layer 12 is laminated on the first base film 11.
  • FIG. 1B shows a plurality of semiconductor chips CP held on the first pressure-sensitive adhesive sheet 10.
  • the semiconductor wafer W held on the first adhesive sheet 10 is divided into pieces by dicing, and a plurality of semiconductor chips CP are formed.
  • a cutting means such as a dicing saw is used for dicing.
  • the cutting depth at the time of dicing is set to a depth that takes into account the total thickness of the semiconductor wafer W, the first pressure-sensitive adhesive layer 12, and the wear of the dicing saw.
  • the first pressure-sensitive adhesive layer 12 is also cut into the same size as the semiconductor chip CP by dicing. Furthermore, a cut may be formed in the first base film 11 by dicing.
  • dicing may be performed by irradiating the semiconductor wafer W with laser light instead of using the above-described cutting means such as a dicing saw.
  • the semiconductor wafer W may be completely divided by laser light irradiation and separated into a plurality of semiconductor chips CP.
  • the first adhesive sheet 10 is stretched in the first expanding step described later, so that the semiconductor wafer W is positioned at the modified layer position. It may be broken and separated into semiconductor chips CP (stealth dicing).
  • laser light irradiation is performed such that infrared laser light is focused on a focal point set inside the semiconductor wafer W.
  • laser light irradiation may be performed from any side of the semiconductor wafer W.
  • FIG. 1C shows a diagram for explaining a process of extending the first pressure-sensitive adhesive sheet 10 that holds a plurality of semiconductor chips CP (hereinafter also referred to as “first expanding process”).
  • the first adhesive sheet 10 is stretched to widen the interval between the plurality of semiconductor chips CP. Further, when stealth dicing is performed, the first adhesive sheet 10 is stretched to break the semiconductor wafer W at the position of the modified layer and separate into a plurality of semiconductor chips CP. Increase the spacing between CPs.
  • the method for extending the first pressure-sensitive adhesive sheet 10 in the first expanding step is not particularly limited. Examples of the method of stretching the first pressure-sensitive adhesive sheet 10 include a method of stretching the first pressure-sensitive adhesive sheet 10 by pressing an annular or circular expander, and an outer peripheral portion of the second pressure-sensitive adhesive sheet using a gripping member or the like. For example, a method of grabbing and stretching.
  • the first pressure-sensitive adhesive sheet 10 preferably has a tensile elastic modulus suitable for the dicing process described above and also suitable for the first expanding process. From this viewpoint, the first pressure-sensitive adhesive sheet 10 preferably has a higher tensile elastic modulus than the second pressure-sensitive adhesive sheet 20 described later. Thereby, the 1st adhesive sheet 10 can exhibit predetermined expandability, without impairing the performance at the time of dicing, and the 2nd adhesive sheet 20 can exhibit the further excellent expandability. .
  • the distance between the semiconductor chips CP is D1.
  • the distance D1 is preferably 15 ⁇ m or more and 110 ⁇ m or less, for example.
  • FIG. 2A is a diagram for explaining a step of transferring a plurality of semiconductor chips CP to the second pressure-sensitive adhesive sheet 20 (hereinafter sometimes referred to as “transfer step”) after the first expanding step.
  • transfer step After extending the first adhesive sheet 10 to increase the distance D1 between the plurality of semiconductor chips CP, the second adhesive sheet 20 is adhered to the circuit surface W1 of the semiconductor chip CP.
  • the semiconductor processing sheet according to the present embodiment is used as the second pressure-sensitive adhesive sheet 20.
  • the second pressure-sensitive adhesive sheet 20 has a second base film 21 and a second pressure-sensitive adhesive layer 22. It is preferable that the 2nd adhesive sheet 20 is stuck so that the circuit surface W1 may be covered with the 2nd adhesive layer 22.
  • FIG. 1 A first figure.
  • the adhesive force of the second adhesive layer 22 is larger than the adhesive force of the first adhesive layer 12. If the adhesive force of the second pressure-sensitive adhesive layer 22 is greater, the first pressure-sensitive adhesive sheet 10 can be easily peeled after the plurality of semiconductor chips CP are transferred to the second pressure-sensitive adhesive sheet 20.
  • the second adhesive sheet 20 may be adhered to the second ring frame together with the plurality of semiconductor chips CP.
  • the second ring frame is placed on the second pressure-sensitive adhesive layer 22 of the second pressure-sensitive adhesive sheet 20, and this is lightly pressed and fixed. Thereafter, the second pressure-sensitive adhesive layer 22 exposed inside the ring shape of the second ring frame is pressed against the circuit surface W1 of the semiconductor chip CP to fix the plurality of semiconductor chips CP to the second pressure-sensitive adhesive sheet 20. To do.
  • the back surfaces W3 of the plurality of semiconductor chips CP are exposed. Even after the first pressure-sensitive adhesive sheet 10 is peeled, it is preferable that the distance D1 between the plurality of semiconductor chips CP expanded in the first expanding step is maintained.
  • FIG. 2B shows a diagram for explaining a process of extending the second pressure-sensitive adhesive sheet 20 that holds a plurality of semiconductor chips CP (hereinafter also referred to as “second expanding process”).
  • the interval between the plurality of semiconductor chips CP is further expanded.
  • the method of extending the second adhesive sheet 20 in the second expanding step is not particularly limited.
  • the method for stretching the second pressure-sensitive adhesive sheet 20 include a method of stretching the second pressure-sensitive adhesive sheet 20 by pressing an annular or circular expander, and an outer peripheral portion of the second pressure-sensitive adhesive sheet using a gripping member or the like.
  • a method of grabbing and stretching As the latter method, for example, a biaxial stretching method using the above-described separation device or the like can be mentioned.
  • the method of biaxial stretching is preferable from the viewpoint that the interval between the semiconductor chips CP can be greatly increased.
  • the interval between the semiconductor chips CP after the second expanding step is D2.
  • the distance D2 is larger than the distance D1.
  • the distance D2 is preferably 200 ⁇ m or more and 6000 ⁇ m or less.
  • FIG. 2C shows a diagram illustrating a process of sealing a plurality of semiconductor chips CP using the sealing member 60 (hereinafter also referred to as “sealing process”).
  • the sealing process is performed after the second expanding process.
  • the sealing body 3 is formed by covering the plurality of semiconductor chips CP with the sealing member 60 while leaving the circuit surface W1.
  • the sealing member 60 is also filled between the plurality of semiconductor chips CP.
  • the circuit surface W1 and the circuit W2 are covered with the second adhesive sheet 20, it is possible to prevent the circuit surface W1 from being covered with the sealing member 60.
  • the sealing body 3 in which a plurality of semiconductor chips CP separated by a predetermined distance are embedded in the sealing member 60 is obtained.
  • the plurality of semiconductor chips CP are preferably covered with the sealing member 60 while the distance D2 is maintained.
  • FIG. 3A shows a cross-sectional view of the sealing body 3 after the second pressure-sensitive adhesive sheet 20 is peeled off.
  • a rewiring layer forming step for forming a rewiring layer and a step for connecting an external terminal electrode to the formed rewiring layer are sequentially performed on the sealing body 3.
  • the internal terminal electrode W4 is shown as the circuit W2 shown in FIG. 2C in more detail.
  • An electrode 6 is formed. Specifically, it is formed as follows. First, the first insulating layer 4A is formed on the circuit surface W1 of the semiconductor chip CP and the surface 3A of the sealing body 3. Subsequently, the rewiring layer 5 is formed so as to be electrically connected to the internal terminal electrode W4. Further, a second insulating layer 4B that covers the rewiring layer 5 is formed. At this time, the rewiring layer 5 is covered with the second insulating layer 4B leaving the external electrode pad 5A. Finally, the external terminal electrode 6 such as a solder ball is placed on the external electrode pad 5A, and the external terminal electrode 6 and the external electrode pad 5A are electrically connected by solder bonding or the like.
  • the external terminal electrode 6 such as a solder ball is placed on
  • FIG. 3C shows a cross-sectional view for explaining a process of separating the sealing body 3 to which the external terminal electrode 6 is connected (hereinafter also referred to as “second dicing process”). Yes.
  • the sealing body 3 is separated into individual semiconductor chips CP.
  • the method for dividing the sealing body 3 into individual pieces is not particularly limited.
  • the sealing body 3 can be separated into pieces by adopting a method similar to the method of dicing the semiconductor wafer W described above.
  • the step of dividing the sealing body 3 into pieces may be performed by sticking the sealing body 3 to an adhesive sheet such as a dicing sheet.
  • the semiconductor package 1 of the semiconductor chip CP unit is manufactured by separating the sealing body 3 into pieces. As described above, the semiconductor package 1 in which the external terminal electrode 6 is connected to the external electrode pad 5A fanned out outside the region of the semiconductor chip CP is manufactured as a fan-out type wafer level package (FO-WLP).
  • FO-WLP fan-out type wafer level package
  • FIG. 4A shows a semiconductor wafer W attached to a protective sheet 30 as a third adhesive sheet.
  • the semiconductor wafer W has a circuit surface W1 as a first surface, and a circuit W2 is formed on the circuit surface W1.
  • the protective sheet 30 is attached to the circuit surface W1 of the semiconductor wafer W.
  • the protection sheet 30 protects the circuit surface W1 and the circuit W2.
  • the protective sheet 30 has a third base film 31 and a third pressure-sensitive adhesive layer 32.
  • the third pressure-sensitive adhesive layer 32 is laminated on the third base film 31.
  • FIG. 4B shows a diagram for explaining a step of forming a groove having a predetermined depth from the circuit surface W1 side of the semiconductor wafer W (hereinafter also referred to as “groove forming step”).
  • the semiconductor wafer W is cut from the protective sheet 30 side using a dicing blade of a dicing apparatus.
  • the protective sheet 30 is completely cut, and a groove W5 is formed by making a cut with a depth shallower than the thickness of the semiconductor wafer W from the circuit surface W1 of the semiconductor wafer W.
  • the groove W5 is formed so as to partition a plurality of circuits W2 formed on the circuit surface W1 of the semiconductor wafer W.
  • the depth of the groove W5 is not particularly limited as long as it is a little deeper than the thickness of the target semiconductor chip.
  • FIG. 4C shows a diagram for explaining a process of grinding the back surface W6 as the second surface of the semiconductor wafer W (hereinafter sometimes referred to as “grinding process”) after forming the groove W5. ing.
  • the first pressure-sensitive adhesive sheet 10 is adhered to the protective sheet 30 side before grinding.
  • the semiconductor wafer W is ground from the back surface W 6 side using the grinder 50.
  • the thickness of the semiconductor wafer W is reduced and finally divided into a plurality of semiconductor chips CP. Grinding is performed from the back surface W6 side until the bottom of the groove W5 is removed, and the semiconductor wafer W is separated into pieces for each circuit W2. Thereafter, back grinding is further performed as necessary to obtain a semiconductor chip CP having a predetermined thickness.
  • grinding is performed until the back surface W3 as the third surface is exposed.
  • FIG. 4D shows a state in which a plurality of divided semiconductor chips CP are held by the protective sheet 30 and the first adhesive sheet 10.
  • the method of dividing the semiconductor wafer W into the semiconductor chips CP by providing the groove W5 in advance and then grinding the back surface is referred to as “front dicing method”. There is a case.
  • FIG. 5A shows a diagram for explaining a step of sticking the second pressure-sensitive adhesive sheet 20 to a plurality of semiconductor chips CP (hereinafter also referred to as “sticking step”) after the grinding step. Yes.
  • the second adhesive sheet 20 is adhered to the back surface W3 of the semiconductor chip CP.
  • the second pressure-sensitive adhesive sheet 20 has a second base film 21 and a second pressure-sensitive adhesive layer 22.
  • the semiconductor processing sheet according to the present embodiment is used as the second pressure-sensitive adhesive sheet 20.
  • the adhesive force of the second adhesive layer 22 to the semiconductor wafer W is larger than the adhesive force of the third adhesive layer 32 to the semiconductor wafer W. If the adhesive force of the second pressure-sensitive adhesive layer 22 is greater, the first pressure-sensitive adhesive sheet 10 and the protective sheet 30 can be easily peeled off.
  • the second adhesive sheet 20 may be attached to the ring frame together with the plurality of semiconductor chips CP.
  • a ring frame is placed on the second pressure-sensitive adhesive layer 22 of the second pressure-sensitive adhesive sheet 20, and this is lightly pressed and fixed. Thereafter, the second adhesive layer 22 exposed inside the ring shape of the ring frame is pressed against the circuit surface W1 of the semiconductor chip CP to fix the plurality of semiconductor chips CP to the second adhesive sheet 20.
  • FIG. 5B illustrates a step of peeling the first pressure-sensitive adhesive sheet 10 and the protective sheet 30 (hereinafter sometimes referred to as “peeling step”) after attaching the second pressure-sensitive adhesive sheet 20. It is shown.
  • the cut protective sheet 30 is accompanied and peeled off.
  • the circuit surfaces W1 of the plurality of semiconductor chips CP are exposed.
  • the distance between the semiconductor chips CP divided by the previous dicing method is D1.
  • the distance D1 is preferably 15 ⁇ m or more and 110 ⁇ m or less.
  • FIG. 5C shows a diagram illustrating a process of extending the second pressure-sensitive adhesive sheet 20 that holds a plurality of semiconductor chips CP (hereinafter sometimes referred to as an “expanding process”).
  • the interval between the plurality of semiconductor chips CP is further expanded.
  • the method for extending the second pressure-sensitive adhesive sheet 20 in the expanding step is not particularly limited.
  • Examples of the method of stretching the second pressure-sensitive adhesive sheet 20 include a method of stretching the second pressure-sensitive adhesive sheet 20 by pressing an annular or circular expander, and an outer peripheral portion of the second pressure-sensitive adhesive sheet using a gripping member or the like.
  • a method of grabbing and stretching As the latter method, for example, a biaxial stretching method using the above-described separation device or the like can be mentioned.
  • the method of biaxial stretching is preferable from the viewpoint that the interval between the semiconductor chips CP can be greatly increased.
  • the distance between the semiconductor chips CP after the expanding process is D2.
  • the distance D2 is larger than the distance D1.
  • the distance D2 is preferably 200 ⁇ m or more and 6000 ⁇ m or less.
  • FIG. 6 is a diagram for explaining a process of sealing a plurality of semiconductor chips CP using the sealing member 60 (hereinafter also referred to as “sealing process”).
  • FIG. 6 (A) shows a diagram illustrating a process of attaching a surface protection sheet 40 as a fourth pressure-sensitive adhesive sheet to a plurality of semiconductor chips CP after the expanding process.
  • the surface protective sheet 40 is attached to the circuit surface W1 of the semiconductor chip CP.
  • the surface protection sheet 40 includes a fourth base film 41 and a fourth pressure-sensitive adhesive layer 42. It is preferable that the surface protection sheet 40 is stuck so that the circuit surface W1 may be covered with the fourth pressure-sensitive adhesive layer 42.
  • the second pressure-sensitive adhesive sheet 20 When the second pressure-sensitive adhesive sheet 20 is peeled off after the surface protective sheet 40 is adhered, the back surfaces W3 of the plurality of semiconductor chips CP are exposed. It is preferable that the distance D2 between the plurality of semiconductor chips CP expanded in the expanding process is maintained even after the second pressure-sensitive adhesive sheet 20 is peeled off.
  • the energy ray polymerizable compound is blended in the second pressure-sensitive adhesive layer 22, the second pressure-sensitive adhesive layer 22 is irradiated with energy rays from the second base film 21 side, and the energy ray polymerizable compound is irradiated. It is preferable to peel the second pressure-sensitive adhesive sheet 20 after curing.
  • FIG. 6B shows a diagram for explaining a process of sealing a plurality of semiconductor chips CP held by the surface protection sheet 40.
  • the sealing body 3 is formed by covering the plurality of semiconductor chips CP with the sealing member 60 while leaving the circuit surface W1.
  • the sealing member 60 is also filled between the plurality of semiconductor chips CP.
  • the circuit surface W1 and the circuit W2 are covered by the surface protection sheet 40, it is possible to prevent the circuit surface W1 from being covered by the sealing member 60.
  • a sealing body 3 in which a plurality of semiconductor chips CP separated by a predetermined distance are embedded in a sealing member is obtained.
  • the plurality of semiconductor chips CP are preferably covered with the sealing member 60 while the distance D2 is maintained.
  • a step of peeling only the first pressure-sensitive adhesive sheet 10 may be performed following the step of attaching the second pressure-sensitive adhesive sheet 20. That is, in the second embodiment described above, when the first pressure-sensitive adhesive sheet 10 is peeled off, the cut protective sheet 30 is accompanied and peeled, whereas in the present modification, the protective sheet 30 is attached to the semiconductor chip CP. The first adhesive sheet 10 is peeled off while remaining on the circuit surface W1. By peeling off the first pressure-sensitive adhesive sheet 10, as shown in FIG. 7A, a plurality of semiconductor chips CP to which the cut protective sheet 30 is attached are stacked on the second pressure-sensitive adhesive sheet 20. Become.
  • the expanding process described above is performed. That is, the second adhesive sheet 20 is stretched in a state where the cut protective sheet 30 is attached to the circuit surface W1 of the semiconductor chip CP, and the space between the plurality of semiconductor chips CP is expanded to the distance D2.
  • a process of sealing a plurality of semiconductor chips CP is performed.
  • the semiconductor chip CP is sealed on the surface protection sheet 40 as shown in FIG. 6B, whereas in this modification, as shown in FIG.
  • the semiconductor chip CP is sealed using the sealing member 60.
  • the protective sheet 30 is adhered to the circuit surface W1, the surface protective sheet 40 may not be adhered, and the second adhesive sheet is adhered to the back surface W3 of the semiconductor chip CP.
  • the sealing body 3 is formed by covering the plurality of semiconductor chips CP with the sealing member 60 while leaving the circuit surface W1. It is preferable that the surface 3S of the sealing body 3 and the circuit surface W1 of the semiconductor chip CP are the same surface.
  • the protective sheet 30 and the second adhesive sheet 20 are peeled off. Then, the FO-WLP is obtained by performing the above-described rewiring layer forming step, connecting step with the external terminal electrode, and second dicing step.
  • the semiconductor processing sheet according to the present embodiment can be stretched greatly, it can be suitably used for applications where the interval between semiconductor chips needs to be greatly expanded as described above.
  • the semiconductor processing sheet has a configuration including a base material and a pressure-sensitive adhesive layer
  • another layer may be interposed between the base material and the pressure-sensitive adhesive layer.
  • the energy ray curable polymer had a weight average molecular weight (Mw) of 600,000.
  • Example 2 A semiconductor processing sheet was produced in the same manner as in Example 1 except that a polypropylene film (PP, manufactured by Diaplus Film Co., Ltd., product name “LT01-06051”) having a thickness of 80 ⁇ m was used as a base material.
  • PP polypropylene film
  • Test Example 1 (Tensile test) The semiconductor processing sheets produced in the examples and comparative examples were cut into 15 mm ⁇ 140 mm, and the release sheet was peeled off to obtain test pieces. About the said test piece, based on JISK7161: 2014 and JISK7127: 1999, the elongation at break and tensile elastic modulus in 23 degreeC were measured. Specifically, the test piece was set to a distance between chucks of 100 mm with a tensile tester (manufactured by Shimadzu Corporation, product name “Autograph AG-IS 500N”), and then subjected to a tensile test at a speed of 200 mm / min. The elongation at break (%) and the tensile modulus (MPa) were measured. The measurement was performed in both the flow direction (MD) during production of the substrate and the direction perpendicular to the flow direction (CD). The results are shown in Table 1.
  • MD flow direction
  • CD direction perpendicular to the flow direction
  • Test Example 2 (Measurement of 100% stress and restoration rate)
  • the semiconductor processing sheet obtained in the example or comparative example was cut into 150 mm ⁇ 15 mm, and the release sheet was peeled off to obtain a test piece.
  • both ends in the length direction of the test piece were fixed with a gripping tool of a tensile tester (manufactured by Shimazu Seisakusho, product name “Autograph AG-IS 50N”). At this time, the test piece was gripped with the gripping tool so that the length between the gripping tools was 100 mm.
  • This length was defined as the length L0 (mm) between the initial grippers. And it pulled 100 mm in the length direction at a speed
  • the length obtained by subtracting the length L0 (mm) (that is, 100 mm) between the initial grippers from this length was defined as the extended length L1 (mm).
  • the test force at this time was measured, and the 100% strength (N) in the tensile test was determined to obtain the 100% strength (N) in the MD direction. And 100% strength (MPa) of MD direction was calculated
  • the grips are returned at a speed of 200 mm / min until the length between the grips reaches L0 (mm).
  • the length was maintained for 1 minute in a state of L0 (mm).
  • a value obtained by subtracting the length L0 (mm) between the initial grippers from this length was defined as L2 (mm).
  • the semiconductor processing sheet obtained in the example or the comparative example was cut into 150 mm ⁇ 15 mm so that the direction (CD direction) perpendicular to the flow direction at the time of manufacture was the length direction of the test piece.
  • the test piece obtained by peeling the release sheet was also measured for 100% strength (N) and 100% stress (MPa) in the same manner as described above, and 100% strength (N) and CD direction in the CD direction, respectively. 100% stress (MPa).
  • the results are shown in Table 1.
  • the ratio of 100% stress (MPa) in the MD direction to 100% stress (MPa) in the CD direction was calculated. The results are also shown in Table 1.
  • UV irradiation device manufactured by Lintec Corporation, product name “RAD-2000m / 12"
  • UV irradiation (illuminance: 120mW / cm 2, the amount of light: 70mJ / cm 2)
  • ⁇ Dicing blade manufactured by Disco Corporation, product name “NBC-ZH205O 27HECC”
  • the semiconductor processing sheet obtained in the example or the comparative example was cut into a square size of 210 mm ⁇ 210 mm. At this time, each side of the cut sheet was cut so as to be parallel or perpendicular to the MD direction of the substrate in the semiconductor processing sheet. Next, the release sheet was peeled off, and all of the silicon chips obtained by the dicing were transferred to the exposed adhesive surface. At this time, transfer was performed so that a group of silicon chips were located in the center of the semiconductor processing sheet. Further, the dicing line when the silicon wafer was separated into pieces was transferred so as to be parallel or perpendicular to each side of the semiconductor processing sheet.
  • FIG. 8 shows a plan view for explaining the expanding apparatus 100.
  • the X axis and the Y axis are orthogonal to each other.
  • the positive direction of the X axis is the + X axis direction
  • the negative direction of the X axis is the ⁇ X axis direction
  • the positive direction of the Y axis Is the + Y axis direction
  • the negative direction of the Y axis is the -Y axis direction.
  • the semiconductor processing sheet 200 was installed in the expanding apparatus 100 so that each side was parallel to the X axis or the Y axis.
  • the MD direction of the base material in the semiconductor processing sheet 200 is parallel to the X axis or the Y axis.
  • the silicon chip is omitted.
  • the expanding apparatus 100 includes five holding means 101 (20 holding means 101 in total) in each of the + X axis direction, the ⁇ X axis direction, the + Y axis direction, and the ⁇ Y axis direction.
  • the holding means 101A the one located at both ends is the holding means 101A
  • the one located in the center is the holding means 101C
  • the one located between the holding means 101A and the holding means 101C is the holding means. 101B.
  • Each side of the semiconductor processing sheet 200 was held by these holding means 101.
  • one side of the semiconductor processing sheet 200 is 210 mm.
  • the interval between the holding means 101 on each side is 40 mm.
  • the distance between the end portion (the apex of the sheet) on one side of the semiconductor processing sheet 200 and the holding means 101A closest to the end portion is 25 mm.
  • a plurality of tension applying means (not shown) corresponding to each of the holding means 101 were driven to move the holding means 101 independently of each other.
  • the five holding units 101 that grip one side of the semiconductor processing sheet 200 on the + X-axis direction side were moved in the + X-axis direction at a stretching speed of 2.5 mm / sec for 40 seconds.
  • the holding means 101A and the holding means 101B were moved in the direction away from the holding means 101C (that is, the + Y axis direction or the ⁇ Y axis direction).
  • the holding means 101A was moved at a stretching speed: 2/3 of 2.5 mm / sec, and the holding means 101B was moved at a stretching speed: 1/3 of 2.5 mm / sec.
  • the holding means 101C was not moved in the + Y axis direction and the ⁇ Y axis direction.
  • the movement in each direction and the holding means 101A and the holding means 101B are moved from the holding means 101C in the same manner as the + X-axis direction. Moved away.
  • the semiconductor processing sheet 200 is stretched by 100 mm each in the + X-axis direction and the ⁇ X-axis direction, and 100 mm each in the + Y-axis direction and the ⁇ Y-axis direction. It was stretched. That is, the semiconductor processing sheet 200 was stretched by 200 mm on each side. As a result, the length of each side of the stretched semiconductor processing sheet 200 was 410 mm.
  • the outer diameter of the substantially circular shape composed of a plurality of silicon chips in the stretched state of the semiconductor processing sheet 200 was measured as the length corresponding to the wafer outer diameter (mm). The results are shown in Table 1.
  • Chip interval (mm) ⁇ length corresponding to wafer outer diameter (mm) ⁇ 150 mm (silicon wafer diameter) ⁇ ⁇ 49 (number of dicing lines) (II)
  • the number of dicing lines is 49.
  • a silicon wafer having a diameter of 150 mm is diced into a chip size of 3 mm ⁇ 3 mm, the silicon wafer is in one direction and in a direction perpendicular to the direction. Dicing is performed at intervals of 3 mm, and each direction is divided into a maximum of 50, based on the fact that the number of dicing lines at that time is 49 in each direction.
  • the semiconductor processing sheet according to the present invention is suitably used for manufacturing, for example, FO-WLP.
  • W Semiconductor wafer W1 ... Circuit surface W2 ... Circuit W3 ... Back surface W4 ... Internal terminal electrode W5 ... Groove W6 ... Back surface CP ... Semiconductor chip 1 ... Semiconductor package 3 ... Sealing body 4A ... First insulating layer 4B ... Second Insulating layer 5 ... Rewiring layer 5A ... External electrode pad 6 ... External terminal electrode 10 ... First adhesive sheet 11 ... First base film 12 ... First adhesive layer 20 ... Second adhesive sheet 21 ... First Second base film 22 ... second adhesive layer 30 ... protective sheet 40 ... surface protective sheet 41 ... fourth base film 42 ... fourth adhesive layer 50 ... grinder 60 ... sealing member 100 ... expanding device 101, 101A, 101B, 101C ... Holding means 200 ... Semiconductor processing sheet

Abstract

A semiconductor processing sheet comprising at least a base material, wherein: the semiconductor processing sheet has a recovery rate of not less than 70% and not more than 100%; or the ratio of a 100% stress measured in an MD direction of the base material at 23°C to the 100% stress measured in a CD direction of the base material at 23°C is not less than 0.8 and not more than 1.2; or the tensile elasticity measured in the MD direction and the CD direction of the base material at 23°C is in each case not less than 10 MPa and not more than 350 MPa, the 100% stress measured in the MD direction and the CD direction of the base material at 23°C is in each case not less than 3 MPa and not more than 20 MPa, and the rupture elongation measured in the MD direction and the CD direction of the base material at 23°C is in each case not less than 100%. The semiconductor processing sheet can be greatly stretched, allowing semiconductor chips to be moved apart from each other sufficiently.

Description

半導体加工用シートSemiconductor processing sheet
 本発明は、半導体加工用シートに関し、好ましくは、複数の半導体チップの間隔を拡げるために使用される半導体加工用シートに関するものである。 The present invention relates to a sheet for semiconductor processing, and preferably relates to a sheet for semiconductor processing used to increase the interval between a plurality of semiconductor chips.
 近年、電子機器の小型化、軽量化、および高機能化が進んでいる。電子機器に搭載される半導体装置にも、小型化、薄型化、および高密度化が求められている。半導体チップは、そのサイズに近いパッケージに実装されることがある。このようなパッケージは、チップスケールパッケージ(Chip Scale Package;CSP)と称されることもある。CSPの一つとして、ウエハレベルパッケージ(Wafer Level Package;WLP)が挙げられる。WLPにおいては、ダイシングにより個片化する前に、ウエハに外部電極などを形成し、最終的にはウエハをダイシングして、個片化する。WLPとしては、ファンイン(Fan-In)型とファンアウト(Fan-Out)型が挙げられる。ファンアウト型のWLP(以下、「FO-WLP」と略記する場合がある。)においては、半導体チップを、チップサイズよりも大きな領域となるように封止部材で覆って半導体チップ封止体を形成し、再配線層や外部電極を、半導体チップの回路面だけでなく封止部材の表面領域においても形成する。 In recent years, electronic devices are becoming smaller, lighter, and more functional. Semiconductor devices mounted on electronic devices are also required to be smaller, thinner, and higher in density. A semiconductor chip may be mounted in a package close to its size. Such a package may be referred to as a chip scale package (CSP). One of CSPs is a wafer level package (Wafer Level Package; WLP). In WLP, before dicing into individual pieces, external electrodes and the like are formed on the wafer, and finally the wafer is diced into individual pieces. As WLP, there are a fan-in type and a fan-out type. In a fan-out type WLP (hereinafter sometimes abbreviated as “FO-WLP”), a semiconductor chip is covered with a sealing member so as to be an area larger than the chip size. Then, the rewiring layer and the external electrode are formed not only on the circuit surface of the semiconductor chip but also on the surface region of the sealing member.
 例えば、特許文献1には、半導体ウエハから個片化された複数の半導体チップについて、その回路形成面を残し、モールド部材を用いて周りを囲んで拡張ウエハを形成し、半導体チップ外の領域に再配線パターンを延在させて形成する半導体パッケージの製造方法が記載されている。特許文献1に記載の製造方法において、個片化された複数の半導体チップをモールド部材で囲う前に、エキスパンド用のウエハマウントテープに貼り替え、ウエハマウントテープを展延して複数の半導体チップの間の距離を拡大させている。 For example, in Patent Document 1, for a plurality of semiconductor chips separated from a semiconductor wafer, an extended wafer is formed by surrounding the periphery using a molding member, leaving a circuit formation surface, and in a region outside the semiconductor chip. A method for manufacturing a semiconductor package formed by extending a rewiring pattern is described. In the manufacturing method described in Patent Document 1, before enclosing a plurality of individual semiconductor chips with a mold member, the semiconductor chip is replaced with an expandable wafer mount tape, and the wafer mount tape is spread to expand the plurality of semiconductor chips. The distance between them is expanding.
国際公開第2010/058646号International Publication No. 2010/058646
 上記のようなFO-WLPの製造方法では、半導体チップ外の領域に上述した再配線パターン等を形成するために、半導体チップ同士を十分に離間させる必要がある。 In the FO-WLP manufacturing method as described above, the semiconductor chips need to be sufficiently separated from each other in order to form the above-described rewiring pattern or the like in a region outside the semiconductor chip.
 本発明は、上記のような実状に鑑みてなされたものであり、半導体チップ同士を十分に離間させる必要がある用途に好適な、大きく延伸することが可能な半導体加工用シートを提供することを目的とする。 This invention is made | formed in view of the above actual conditions, and provides the semiconductor processing sheet which can be extended | stretched large suitable for the use which needs to fully space | separate semiconductor chips. Objective.
 上記目的を達成するために、第1に本発明は、少なくとも基材を備える半導体加工用シートであって、前記半導体加工用シートの復元率が、70%以上、100%以下であり、前記復元率は、前記半導体加工用シートを150mm×15mmに切り出した試験片において、長さ方向の両端を、つかみ具間の長さが100mmとなるようにつかみ具でつかみ、その後、つかみ具間の長さが200mmとなるまで200mm/minの速度で引張り、つかみ具間の長さが200mmに拡張された状態で1分間保持し、その後、つかみ具間の長さが100mmとなるまで200mm/minの速度で長さ方向に戻し、つかみ具間の長さが100mmに戻された状態で1分間保持し、その後、60mm/minの速度で長さ方向に引張り、引張力の測定値が0.1N/15mmを示した時のつかみ具間の長さを測定し、当該長さから初期のつかみ具間の長さ100mmを引いた長さをL2(mm)とし、前記拡張された状態におけるつかみ具間の長さ200mmから初期のつかみ具間の長さ100mmを引いた長さをL1(mm)としたとき、次式(I)
 復元率(%)={1-(L2÷L1)}×100 ・・・ (I)
から算出される値であることを特徴とする半導体加工用シートを提供する(発明1)。
In order to achieve the above object, first, the present invention provides a semiconductor processing sheet having at least a base material, wherein the recovery rate of the semiconductor processing sheet is 70% or more and 100% or less, and the restoration is performed. In the test piece obtained by cutting the semiconductor processing sheet into 150 mm × 15 mm, both ends in the length direction are gripped with a gripping tool so that the length between the gripping tools is 100 mm, and then the length between the gripping tools is measured. Is pulled at a speed of 200 mm / min until the length becomes 200 mm, and is held for 1 minute in a state where the length between the grips is expanded to 200 mm, and then 200 mm until the length between the grips reaches 100 mm. Return to the length direction at the speed, hold for 1 minute with the length between the grippers returned to 100 mm, then pull in the length direction at a speed of 60 mm / min to measure the tensile force. The length between grips when the value indicates 0.1 N / 15 mm is measured, and the length obtained by subtracting the length of 100 mm between the initial grips from the length is defined as L2 (mm). When the length obtained by subtracting the length of 100 mm between the initial gripping tools from the length of 200 mm between the gripping tools in the state of being taken as L1 (mm), the following formula (I)
Restoration rate (%) = {1− (L2 ÷ L1)} × 100 (I)
A semiconductor processing sheet characterized in that the value is calculated from the above (Invention 1).
 上記発明(発明1)によれば、復元率が上記範囲であることで、大きく延伸することが可能となる。そのため、例えば、FO-WLPの製造といった、半導体チップ同士を十分に離間させる必要がある用途に好適に使用することができる。 According to the said invention (invention 1), it becomes possible to extend | stretch largely because a restoration rate is the said range. Therefore, for example, it can be suitably used for applications where semiconductor chips need to be sufficiently separated from each other, such as in the manufacture of FO-WLP.
 第2に本発明は、少なくとも基材を備える半導体加工用シートであって、23℃において前記基材のCD方向に測定される前記半導体加工用シートの100%応力に対する、23℃において前記基材のMD方向に測定される前記半導体加工用シートの100%応力の比が、0.8以上、1.2以下であり、前記100%応力は、前記半導体加工用シートを150mm×15mmに切り出した試験片において、長さ方向の両端を、つかみ具間の長さが100mmとなるようにつかみ具でつかみ、その後、速度200mm/minで長さ方向に引張り、つかみ具間の長さが200mmとなったときの引張力の測定値を、半導体加工用シートの断面積で除算することで得られる値であることを特徴とする半導体加工用シートを提供する(発明2)。 Secondly, the present invention is a semiconductor processing sheet comprising at least a base material, wherein the base material at 23 ° C. is 100% stress of the semiconductor processing sheet measured in the CD direction of the base material at 23 ° C. The ratio of 100% stress of the semiconductor processing sheet measured in the MD direction is 0.8 or more and 1.2 or less, and the 100% stress is obtained by cutting the semiconductor processing sheet into 150 mm × 15 mm. In the test piece, both ends in the length direction are gripped by the grip so that the length between the grips is 100 mm, and then pulled in the length direction at a speed of 200 mm / min, and the length between the grips is 200 mm. Provided is a sheet for semiconductor processing, characterized in that it is a value obtained by dividing the measured value of the tensile force at that time by the cross-sectional area of the sheet for semiconductor processing (Invention 2).
 上記発明(発明2)によれば、100%応力の比が上記範囲であることで、大きく延伸することが可能となる。そのため、例えば、FO-WLPの製造といった、半導体チップ同士を十分に離間させる必要がある用途に好適に使用することができる。 According to the above invention (Invention 2), when the ratio of 100% stress is in the above range, the film can be stretched greatly. Therefore, for example, it can be suitably used for applications where semiconductor chips need to be sufficiently separated from each other, such as in the manufacture of FO-WLP.
 第3に本発明は、少なくとも基材を備える半導体加工用シートであって、23℃において前記基材のMD方向およびCD方向に測定される前記半導体加工用シートの引張弾性率が、それぞれ10MPa以上、350MPa以下であり、23℃において前記基材のMD方向およびCD方向に測定される前記半導体加工用シートの100%応力が、それぞれ3MPa以上、20MPa以下であり、前記100%応力は、前記半導体加工用シートを150mm×15mmに切り出した試験片において、長さ方向の両端を、つかみ具間の長さが100mmとなるようにつかみ具でつかみ、その後、速度200mm/minで長さ方向に引張り、つかみ具間の長さが200mmとなったときの引張力の測定値を、半導体加工用シートの断面積で除算することで得られる値であり、23℃において前記基材のMD方向およびCD方向に測定される前記半導体加工用シートの破断伸度が、それぞれ100%以上であることを特徴とする半導体加工用シートを提供する(発明3)。 Third, the present invention is a semiconductor processing sheet comprising at least a base material, and the tensile modulus of the semiconductor processing sheet measured in the MD direction and the CD direction of the base material at 23 ° C. is 10 MPa or more, respectively. 350 MPa or less, and 100% stress of the semiconductor processing sheet measured in the MD direction and CD direction of the base material at 23 ° C. is 3 MPa or more and 20 MPa or less, respectively. In a test piece obtained by cutting a processing sheet into a size of 150 mm × 15 mm, both ends in the length direction are gripped with a grip so that the length between the grips is 100 mm, and then pulled in the length direction at a speed of 200 mm / min. Then, divide the measured value of the tensile force when the length between grips is 200 mm by the cross-sectional area of the semiconductor processing sheet. The breaking elongation of the semiconductor processing sheet measured in the MD direction and CD direction of the base material at 23 ° C. is 100% or more, respectively. (Invention 3).
 上記発明(発明3)によれば、引張弾性率および破断伸度が上記範囲であることで、大きく延伸することが可能となる。そのため、例えば、FO-WLPの製造といった、半導体チップ同士を十分に離間させる必要がある用途に好適に使用することができる。 According to the said invention (invention 3), it becomes possible to extend | stretch largely because a tensile elasticity modulus and breaking elongation are the said ranges. Therefore, for example, it can be suitably used for applications where semiconductor chips need to be sufficiently separated from each other, such as in the manufacture of FO-WLP.
 上記発明(発明1~3)においては、前記基材の少なくとも一方の面に積層された粘着剤層をさらに備えることが好ましい(発明4)。 In the above inventions (Inventions 1 to 3), it is preferable to further comprise an adhesive layer laminated on at least one surface of the substrate (Invention 4).
 上記発明(発明1~4)において、前記基材は、熱可塑性エラストマーを含有することが好ましい(発明5)。 In the above inventions (Inventions 1 to 4), the substrate preferably contains a thermoplastic elastomer (Invention 5).
 上記発明(発明5)において、前記熱可塑性エラストマーは、ウレタン系エラストマーであることが好ましい(発明6)。 In the above invention (Invention 5), the thermoplastic elastomer is preferably a urethane elastomer (Invention 6).
 上記発明(発明1~6)においては、前記半導体加工用シートの片面に積層された複数の半導体チップにおける隣り合う半導体チップの相互の間隔を、200μm以上、6000μm以下まで拡げるために使用されることが好ましい(発明7)。 In the above inventions (Inventions 1 to 6), the semiconductor processing sheet is used to increase the interval between adjacent semiconductor chips in a plurality of semiconductor chips stacked on one side of the semiconductor processing sheet to 200 μm or more and 6000 μm or less. Is preferable (Invention 7).
 上記発明(発明1~7)においては、互いに直交するX軸およびY軸における+X軸方向、-X軸方向、+Y軸方向および-Y軸方向の4方向に張力を付与して半導体加工用シートを引き延ばすことにより、前記半導体加工用シートの片面に積層された複数の半導体チップの間隔を拡げるために使用されることが好ましい(発明8)。 In the above inventions (Inventions 1 to 7), a semiconductor processing sheet is provided by applying tension in the four directions of the + X axis direction, the −X axis direction, the + Y axis direction, and the −Y axis direction of the X axis and Y axis perpendicular to each other It is preferably used to widen the interval between a plurality of semiconductor chips stacked on one side of the semiconductor processing sheet by extending the length (Invention 8).
 上記発明(発明1~8)においては、粘着シートの片面に、個片化された複数の半導体チップを設ける工程と、前記粘着シートを引き延ばして、前記複数の前記半導体チップ同士の間隔を拡げる工程とを備える半導体装置の製造方法において、前記粘着シートとして使用されることが好ましい(発明9)。 In the above inventions (Inventions 1 to 8), the step of providing a plurality of individual semiconductor chips on one side of the pressure-sensitive adhesive sheet, and the step of extending the pressure-sensitive adhesive sheet to widen the interval between the plurality of semiconductor chips Is preferably used as the pressure-sensitive adhesive sheet (Invention 9).
 上記発明(発明1~9)においては、ファンアウト型の半導体ウエハレベルパッケージを製造するために使用されることが好ましい(発明10)。 In the above inventions (Inventions 1 to 9), it is preferably used for manufacturing a fan-out type semiconductor wafer level package (Invention 10).
 本発明に係る半導体加工用シートは、大きく延伸することができ、半導体チップ同士を十分に離間させることができる。 The semiconductor processing sheet according to the present invention can be stretched greatly, and the semiconductor chips can be sufficiently separated from each other.
本発明の一実施形態に係る半導体加工用シートの使用方法の第1態様を説明する断面図である。It is sectional drawing explaining the 1st aspect of the usage method of the sheet | seat for semiconductor processing which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体加工用シートの使用方法の第1態様を説明する断面図である。It is sectional drawing explaining the 1st aspect of the usage method of the sheet | seat for semiconductor processing which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体加工用シートの使用方法の第1態様を説明する断面図である。It is sectional drawing explaining the 1st aspect of the usage method of the sheet | seat for semiconductor processing which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体加工用シートの使用方法の第2態様を説明する断面図である。It is sectional drawing explaining the 2nd aspect of the usage method of the sheet | seat for semiconductor processing which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体加工用シートの使用方法の第2態様を説明する断面図である。It is sectional drawing explaining the 2nd aspect of the usage method of the sheet | seat for semiconductor processing which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体加工用シートの使用方法の第2態様を説明する断面図である。It is sectional drawing explaining the 2nd aspect of the usage method of the sheet | seat for semiconductor processing which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体加工用シートの使用方法の第2態様を説明する断面図である。It is sectional drawing explaining the 2nd aspect of the usage method of the sheet | seat for semiconductor processing which concerns on one Embodiment of this invention. 実施例で使用した2軸延伸エキスパンド装置を説明する平面図である。It is a top view explaining the biaxial stretching expand apparatus used in the Example.
 以下、本発明の実施形態について説明する。
 本実施形態に係る半導体加工用シートは、少なくとも基材を備えて構成される。
Hereinafter, embodiments of the present invention will be described.
The semiconductor processing sheet according to the present embodiment is configured to include at least a base material.
 本実施形態に係る半導体加工用シートの復元率は、70%以上、100%以下であることが好ましい。
 本明細書において、復元率とは、次のように算出されるものをいう。まず、半導体加工用シートを150mm×15mmに切り出し、試験片を得る。当該切り出しは、半導体加工用シートにおける基材のMD方向と、試験片の長さ方向とが一致するように行う。次に、試験片の長さ方向の両端を、つかみ具間が100mmとなるようにつかみ具でつかむ。このときのつかみ具間の長さを、初期つかみ具間の長さL0(mm)とする。次に、200mm/minの速度でつかみ具間を長さ方向に引張り、つかみ具間が200mmとなった状態で1分間保持する。200mmまで拡張した後のつかみ具間の長さから初期つかみ具間の長さL0(mm)(すなわち100mm)を引いた長さを、拡張長さL1(mm)(=100mm)とする。1分間の保持の後、200mm/minの速度でつかみ具間の長さを戻し、つかみ具間が100mm(すなわちL0(mm))となった状態で1分間保持する。その後、60mm/minの速度でつかみ具間を長さ方向に引張り、引張力の測定値が0.1N/15mmを示した時点でのつかみ具間の長さを記録する。当該長さから初期つかみ具間の長さL0(mm)を引いた値を、L2(mm)する。以上のようにして得られたL1およびL2の値を下記式(I)にあてはめることで、復元率(%)が得られる。
 復元率(%)={1-(L2÷L1)}×100 ・・・ (I)
なお、この引張試験において、試験片の厚さは特別に制限されず、試験の対象とする半導体加工用シートの厚さと同じであってよい。また、具体的な測定方法は、後述する試験例に示す通りである。
The restoration rate of the semiconductor processing sheet according to the present embodiment is preferably 70% or more and 100% or less.
In the present specification, the restoration rate is calculated as follows. First, a semiconductor processing sheet is cut out to 150 mm × 15 mm to obtain a test piece. The cutting is performed so that the MD direction of the base material in the semiconductor processing sheet matches the length direction of the test piece. Next, the both ends in the length direction of the test piece are grasped with the grasping tool so that the distance between the grasping tools is 100 mm. The length between the grips at this time is defined as a length L0 (mm) between the initial grips. Next, the length between the grips is pulled in the length direction at a speed of 200 mm / min, and is held for 1 minute in a state where the distance between the grips is 200 mm. The length obtained by subtracting the length L0 (mm) (that is, 100 mm) between the initial grippers from the length between the grips after being expanded to 200 mm is defined as an expansion length L1 (mm) (= 100 mm). After holding for 1 minute, the length between the grips is returned at a speed of 200 mm / min, and is held for 1 minute with the distance between the grips being 100 mm (ie, L0 (mm)). Thereafter, the length between the grips is pulled in the length direction at a speed of 60 mm / min, and the length between the grips when the measured value of the tensile force indicates 0.1 N / 15 mm is recorded. L2 (mm) is obtained by subtracting the length L0 (mm) between the initial grippers from the length. By applying the values of L1 and L2 obtained as described above to the following formula (I), the restoration rate (%) can be obtained.
Restoration rate (%) = {1− (L2 ÷ L1)} × 100 (I)
In this tensile test, the thickness of the test piece is not particularly limited, and may be the same as the thickness of the semiconductor processing sheet to be tested. Moreover, the specific measuring method is as showing in the test example mentioned later.
 また、本実施形態に係る半導体加工用シートでは、23℃において基材のCD方向に測定される半導体加工用シートの100%応力に対する、23℃において基材のMD方向に測定される半導体加工用シートの100%応力の比が、0.8以上、1.2以下であることが好ましい。ここで、MD方向とは、基材の製造時における流れ方向をいい、CD方向とは、MD方向に対して垂直な方向をいう。 Moreover, in the semiconductor processing sheet according to the present embodiment, for semiconductor processing measured in the MD direction of the substrate at 23 ° C. with respect to 100% stress of the semiconductor processing sheet measured in the CD direction of the substrate at 23 ° C. The ratio of 100% stress of the sheet is preferably 0.8 or more and 1.2 or less. Here, the MD direction refers to the flow direction during manufacture of the substrate, and the CD direction refers to a direction perpendicular to the MD direction.
 本明細書において、100%応力とは、次のように算出されるものをいう。半導体加工用シートを150mm×15mmに切り出した試験片において、長さ方向の両端を、つかみ具間が100mmとなるようにつかみ具でつかみ、速度200mm/minで長さ方向に引張り、つかみ具間の長さが200mmとなったときの引張力の強さ(引張力の測定値)として表される100%強度を、半導体加工シートの断面積で除算することで、100%応力(MPa)が得られる。当該切り出しは、半導体加工用シートの製造時における流れ方向(MD方向)またはMD方向に直交する方向(CD方向)と、試験片の長さ方向とが一致するように行う。なお、この引張試験において、試験片の厚さは特別に制限されず、試験の対象とする半導体加工用シートの厚さと同じであってよい。また、具体的な測定方法は、後述する試験例に示す通りである。 In this specification, 100% stress means the one calculated as follows. In a test piece obtained by cutting a semiconductor processing sheet into 150 mm × 15 mm, hold both ends in the length direction with a grip so that the distance between grips is 100 mm, and pull in the length direction at a speed of 200 mm / min. By dividing the 100% strength expressed as the strength of tensile force (measured value of tensile force) when the length of the sheet becomes 200 mm by the cross-sectional area of the semiconductor processed sheet, 100% stress (MPa) is obtained. can get. The cutting is performed so that the flow direction (MD direction) or the direction orthogonal to the MD direction (CD direction) during the manufacture of the semiconductor processing sheet coincides with the length direction of the test piece. In this tensile test, the thickness of the test piece is not particularly limited, and may be the same as the thickness of the semiconductor processing sheet to be tested. Moreover, the specific measuring method is as showing in the test example mentioned later.
 また、本実施形態に係る半導体加工用シートでは、23℃において基材のMD方向およびCD方向に測定される半導体加工用シートの引張弾性率が、それぞれ10MPa以上、350MPa以下であり、23℃において基材のMD方向およびCD方向に測定される半導体加工用シートの100%応力が、それぞれ3MPa以上、20MPa以下であり、且つ、23℃において基材のMD方向およびCD方向に測定される半導体加工用シートの破断伸度が、それぞれ100%以上であることが好ましい。 Further, in the semiconductor processing sheet according to the present embodiment, the tensile modulus of the semiconductor processing sheet measured in the MD direction and the CD direction of the base material at 23 ° C. is 10 MPa or more and 350 MPa or less, respectively. 100% stress of the semiconductor processing sheet measured in the MD direction and CD direction of the substrate is 3 MPa or more and 20 MPa or less, respectively, and the semiconductor processing is measured in the MD direction and CD direction of the substrate at 23 ° C. It is preferable that the breaking elongation of each sheet is 100% or more.
 本実施形態に係る半導体加工用シートは、上述した物性を有することにより、破断が生じることなく延伸し易くなる結果、大きく延伸することが可能となる。 The semiconductor processing sheet according to the present embodiment has the above-described physical properties, so that the semiconductor processing sheet can be easily stretched without causing breakage.
 特に、上記復元率が上記範囲である場合、半導体加工用シートは大きく延伸された後においても復元し易いことを意味する。一般に、降伏点を有するシートを降伏点以上に延伸すると、シートは塑性変形を起こし、塑性変形を起こした部分、即ち極端に延伸された部分が偏在した状態となる。そのような状態のシートをさらに延伸すると、上記の極端に延伸された部分から破断が生じたり、破断が生じなくても、エキスパンドが不均一になる。また、ひずみをx軸、伸びをy軸にそれぞれプロットした応力-ひずみ線図において、傾きdx/dyが、正の値から0又は負の値に変化する応力値をとらず、明確な降伏点を示さないシートであっても、引張量が大きくなるにつれてシートは塑性変形を起こし、同様に破断が生じたり、エキスパンドが不均一になる。一方、塑性変形ではなく弾性変形が生じる場合には、応力を取り除くことでシートが元の形状に復元し易い。そこで、十分大きい引張量である100%伸長後にどの程度復元するかを表す指標である復元率が、上記範囲であることにより、半導体加工用シートを大きく延伸する際に、フィルムの塑性変形が最小限に抑えられ、破断が生じ難く、且つ均一なエキスパンドが可能となる。 In particular, when the restoration rate is in the above range, it means that the semiconductor processing sheet is easily restored even after being largely stretched. In general, when a sheet having a yield point is stretched beyond the yield point, the sheet undergoes plastic deformation, and a portion where plastic deformation has occurred, that is, an extremely stretched portion is unevenly distributed. If the sheet in such a state is further stretched, the expanded portion becomes non-uniform even if the above extremely stretched portion breaks or does not break. In addition, in the stress-strain diagram in which the strain is plotted on the x-axis and the elongation is plotted on the y-axis, the slope dx / dy does not take a stress value that changes from a positive value to 0 or a negative value, and a clear yield point. Even if the sheet does not show, the sheet undergoes plastic deformation as the tensile amount increases, and similarly, the sheet breaks or the expansion becomes non-uniform. On the other hand, when elastic deformation occurs instead of plastic deformation, the sheet can be easily restored to its original shape by removing the stress. Therefore, when the restoration rate, which is an index indicating how much to restore after 100% elongation, which is a sufficiently large tensile amount, is in the above range, the plastic deformation of the film is minimized when the semiconductor processing sheet is stretched greatly. It is suppressed to the limit, and breakage hardly occurs, and uniform expansion is possible.
 また、100%応力の比が上記範囲である場合、ならびに、引張弾性率、100%応力および破断伸度が上記である場合、半導体加工用シートを、基材のMD方向およびCD方向に延伸する際に(以下、このような延伸を「2軸延伸」という場合がある。)、破断が生じ難く、大きく延伸することが可能となる。 Further, when the ratio of 100% stress is within the above range, and when the tensile modulus, 100% stress and breaking elongation are as described above, the semiconductor processing sheet is stretched in the MD direction and CD direction of the substrate. In this case (hereinafter, such stretching may be referred to as “biaxial stretching”), it is difficult to cause breakage and it is possible to stretch the film greatly.
 上記のような半導体加工用シートでは、具体的には、半導体チップの相互の間隔が200μm以上といった距離になるまで離間させることが可能となる。このような半導体加工用シートは、FO-WLPの製造方法等の半導体チップ同士の間隔を十分に拡げることが求められる半導体装置の製造方法に好適に使用することができる。 In the semiconductor processing sheet as described above, specifically, the semiconductor chips can be separated until the distance between the semiconductor chips reaches 200 μm or more. Such a semiconductor processing sheet can be suitably used in a method for manufacturing a semiconductor device that requires a sufficiently wide interval between semiconductor chips, such as a method for manufacturing FO-WLP.
1.半導体加工用シートの物性等
 本実施形態に係る半導体加工用シートでは、復元率が、70%以上であることが好ましく、特に80%以上であることが好ましく、さらには85%以上であることが好ましい。また、当該復元率は、100%以下であることが好ましい。復元率が上記範囲であることで、前述した通り、半導体加工用シートを大きく延伸することが可能となる。
1. Physical properties of semiconductor processing sheet, etc. In the semiconductor processing sheet according to the present embodiment, the restoration rate is preferably 70% or more, particularly preferably 80% or more, and more preferably 85% or more. preferable. The restoration rate is preferably 100% or less. When the restoration rate is in the above range, the semiconductor processing sheet can be greatly stretched as described above.
 本実施形態に係る半導体加工用シートでは、23℃において基材のCD方向に測定される半導体加工用シートの100%応力に対する、23℃において基材のMD方向に測定される半導体加工用シートの100%応力の比が、0.8以上であることが好ましく、特に0.83以上であることが好ましく、さらには0.85以上であることが好ましい。また、当該比は、1.2以下であることが好ましく、特に1.17以下であることが好ましく、さらには1.15以下であることが好ましい。100%応力の比が上記範囲であることで、半導体加工用シートを2軸延伸する場合のように、特定の方向のみに応力がかかり易い場合であっても、半導体加工用シートの破断が発生することが抑制される。その結果、半導体加工用シートをより大きく延伸することが可能となる。 In the semiconductor processing sheet according to the present embodiment, the semiconductor processing sheet measured in the MD direction of the substrate at 23 ° C. with respect to 100% stress of the semiconductor processing sheet measured in the CD direction of the substrate at 23 ° C. The ratio of 100% stress is preferably 0.8 or more, particularly preferably 0.83 or more, and more preferably 0.85 or more. The ratio is preferably 1.2 or less, particularly preferably 1.17 or less, and more preferably 1.15 or less. When the ratio of 100% stress is within the above range, the semiconductor processing sheet breaks even when stress is easily applied only in a specific direction, such as when the semiconductor processing sheet is biaxially stretched. Is suppressed. As a result, the semiconductor processing sheet can be stretched more greatly.
 本実施形態に係る半導体加工用シートでは、23℃において基材のCD方向に測定される半導体加工用シートの破断伸度が、100%以上であることが好ましく、特に150%以上であることが好ましく、さらには200%以上であることが好ましい。また、当該破断伸度は、1200%以下であることが好ましく、特に1000%以下であることが好ましい。当該破断伸度が上記範囲であることで、半導体加工用シートを、基材のCD方向に大きく延伸することが可能となる。なお、CD方向の破断伸度の測定方法は、後述する試験例に示す通りである。 In the semiconductor processing sheet according to the present embodiment, the breaking elongation of the semiconductor processing sheet measured in the CD direction of the base material at 23 ° C. is preferably 100% or more, particularly 150% or more. Preferably, it is preferably 200% or more. The breaking elongation is preferably 1200% or less, and particularly preferably 1000% or less. When the breaking elongation is in the above range, the semiconductor processing sheet can be greatly stretched in the CD direction of the substrate. The method for measuring the breaking elongation in the CD direction is as shown in the test examples described later.
 本実施形態に係る半導体加工用シートでは、23℃において基材のMD方向に測定される半導体加工用シートの破断伸度が、100%以上であることが好ましく、特に150%以上であることが好ましく、さらには200%以上であることが好ましい。また、当該破断伸度は、1200%以下であることが好ましく、特に1000%以下であることが好ましい。当該破断伸度が上記範囲であることで、半導体加工用シートを、基材のMD方向に大きく延伸することが可能となる。なお、MD方向の破断伸度の測定方法は、後述する試験例に示す通りである。 In the semiconductor processing sheet according to the present embodiment, the breaking elongation of the semiconductor processing sheet measured in the MD direction of the base material at 23 ° C. is preferably 100% or more, particularly 150% or more. Preferably, it is preferably 200% or more. The breaking elongation is preferably 1200% or less, and particularly preferably 1000% or less. When the breaking elongation is within the above range, the semiconductor processing sheet can be greatly stretched in the MD direction of the base material. In addition, the measuring method of the breaking elongation of MD direction is as showing to the test example mentioned later.
 本実施形態に係る半導体加工用シートでは、23℃において基材のCD方向に測定される半導体加工用シートの引張弾性率が、10MPa以上であることが好ましく、特に20MPa以上であることが好ましく、さらには25MPa以上であることが好ましい。また、当該引張弾性率は、350MPa以下であることが好ましく、特に300MPa以下であることが好ましく、さらには250MPa以下であることが好ましい。上記引張弾性率が10MPa以上であることで、半導体加工用シート上に半導体チップ等を積層した場合に、その半導体チップ等を良好に支持することが可能となる。また、上記引張弾性率が350MPa以下であることで、半導体加工用シートが適度な柔軟性を有するものとなり、半導体加工用シートをより大きく延伸し易くなる。なお、上記引張弾性率の測定方法は、後述する試験例に示す通りである。 In the semiconductor processing sheet according to the present embodiment, the tensile modulus of the semiconductor processing sheet measured in the CD direction of the base material at 23 ° C. is preferably 10 MPa or more, particularly preferably 20 MPa or more, Further, it is preferably 25 MPa or more. The tensile elastic modulus is preferably 350 MPa or less, particularly preferably 300 MPa or less, and further preferably 250 MPa or less. When the tensile elastic modulus is 10 MPa or more, when a semiconductor chip or the like is laminated on the semiconductor processing sheet, the semiconductor chip or the like can be favorably supported. In addition, when the tensile elastic modulus is 350 MPa or less, the semiconductor processing sheet has moderate flexibility, and the semiconductor processing sheet can be more easily stretched. In addition, the measuring method of the said tensile elasticity modulus is as showing to the test example mentioned later.
 本実施形態に係る半導体加工用シートでは、23℃において基材のMD方向に測定される半導体加工用シートの引張弾性率が、10MPa以上であることが好ましく、特に20MPa以上であることが好ましく、さらには25MPa以上であることが好ましい。また、当該引張弾性率は、350MPa以下であることが好ましく、特に300MPa以下であることが好ましく、さらには250MPa以下であることが好ましい。上記引張弾性率が10MPa以上であることで、半導体加工用シート上に半導体チップ等を積層した場合に、その半導体チップ等を良好に支持することが可能となる。また、上記引張弾性率が350MPa以下であることで、半導体加工用シートが適度な柔軟性を有するものとなり、半導体加工用シートをより大きく延伸し易くなる。なお、上記引張弾性率の測定方法は、後述する試験例に示す通りである。 In the semiconductor processing sheet according to the present embodiment, the tensile modulus of the semiconductor processing sheet measured in the MD direction of the substrate at 23 ° C. is preferably 10 MPa or more, particularly preferably 20 MPa or more, Further, it is preferably 25 MPa or more. The tensile elastic modulus is preferably 350 MPa or less, particularly preferably 300 MPa or less, and further preferably 250 MPa or less. When the tensile elastic modulus is 10 MPa or more, when a semiconductor chip or the like is laminated on the semiconductor processing sheet, the semiconductor chip or the like can be favorably supported. In addition, when the tensile elastic modulus is 350 MPa or less, the semiconductor processing sheet has moderate flexibility, and the semiconductor processing sheet can be more easily stretched. In addition, the measuring method of the said tensile elasticity modulus is as showing to the test example mentioned later.
 本実施形態に係る半導体加工用シートでは、23℃において基材のCD方向に測定される半導体加工用シートの100%応力が、3MPa以上であることが好ましく、特に5MPa以上であることが好ましく、さらには6MPa以上であることが好ましい。当該100%応力が3MPa以上であることで、半導体加工用シートを大きく延伸することで基材の厚みが低減しても、離間した状態のチップを支持するのに必要な力を保持することが可能となる。また、当該100%応力は、20MPa以下であることが好ましく、特に18MPa以下であることが好ましく、さらには16MPa以下であることが好ましい。当該破断伸度が20MPa以下であることで、エキスパンド装置に過度な負荷をかけることなく半導体加工用シートを大きく延伸することが可能であり、長期間にわたって連続で装置を使用しても装置の故障を防ぐことが期待できる。なお、CD方向の100%応力の測定方法は、後述する試験例に示す通りである。 In the semiconductor processing sheet according to the present embodiment, the 100% stress of the semiconductor processing sheet measured in the CD direction of the substrate at 23 ° C. is preferably 3 MPa or more, particularly preferably 5 MPa or more, Furthermore, it is preferable that it is 6 MPa or more. When the 100% stress is 3 MPa or more, even if the thickness of the base material is reduced by greatly stretching the semiconductor processing sheet, the force necessary to support the separated chips can be maintained. It becomes possible. The 100% stress is preferably 20 MPa or less, particularly preferably 18 MPa or less, and more preferably 16 MPa or less. When the breaking elongation is 20 MPa or less, it is possible to greatly stretch the semiconductor processing sheet without imposing an excessive load on the expanding device. Even if the device is used continuously over a long period of time, the device fails. Can be expected to prevent. The method for measuring 100% stress in the CD direction is as shown in the test examples described later.
 本実施形態に係る半導体加工用シートでは、23℃において基材のMD方向に測定される半導体加工用シートの100%応力が、3MPa以上であることが好ましく、特に5MPa以上であることが好ましく、さらには6MPa以上であることが好ましい。当該100%応力が3MPa以上であることで、半導体加工用シートを大きく延伸することで基材の厚みが低減しても、離間した状態のチップを支持するのに必要な力を保持することが可能となり、半導体加工用シートを、基材のCD方向に大きく延伸することが可能となる。また、当該100%応力は、20MPa以下であることが好ましく、特に18MPa以下であることが好ましく、さらには16MPa以下であることが好ましい。当該破断伸度が20MPa以下であることで、エキスパンド装置に過度な負荷をかけることなく半導体加工用シートを大きく延伸することが可能であり、長期間にわたって連続で装置を使用しても装置の故障を防ぐことが期待できる。なお、MD方向の100%応力の測定方法は、後述する試験例に示す通りである。 In the semiconductor processing sheet according to the present embodiment, the 100% stress of the semiconductor processing sheet measured in the MD direction of the substrate at 23 ° C. is preferably 3 MPa or more, particularly preferably 5 MPa or more, Furthermore, it is preferable that it is 6 MPa or more. When the 100% stress is 3 MPa or more, even if the thickness of the base material is reduced by greatly stretching the semiconductor processing sheet, the force necessary to support the separated chips can be maintained. This makes it possible to greatly stretch the semiconductor processing sheet in the CD direction of the substrate. The 100% stress is preferably 20 MPa or less, particularly preferably 18 MPa or less, and more preferably 16 MPa or less. When the breaking elongation is 20 MPa or less, it is possible to greatly stretch the semiconductor processing sheet without imposing an excessive load on the expanding device. Even if the device is used continuously over a long period of time, the device fails. Can be expected to prevent. In addition, the measuring method of 100% stress in the MD direction is as shown in a test example described later.
 本実施形態に係る半導体加工用シートは、少なくとも一方の面が粘着性を有することが好ましい。これにより、当該面に半導体チップ等を貼付して固定することが可能となる。なお、本明細書では、半導体加工用シートにおける、粘着性を有し、半導体チップ等が貼付される面を「粘着面」という場合がある。本実施形態に係る半導体加工用シートの粘着力は、300mN/25mm以上であることが好ましく、特に800mN/25mm以上であることが好ましく、さらには1000mN/25mm以上であることが好ましい。また、当該粘着力は、30000mN/25mm以下であることが好ましく、特に15000mN/25mm以下であることが好ましく、さらには10000mN/25mm以下であることが好ましい。当該粘着力が300mN/25mm以上であることで粘着面に半導体チップ等を良好に貼付して固定することができる。また、当該粘着力が30000mN/25mm以下であることで、本実施形態に係る半導体加工用シートからその他の粘着シートへの半導体チップ等の貼りかえ、本実施形態に係る半導体加工用シートから、半導体チップ等を吸着保持可能な保持部材への半導体チップ等の転写、本実施形態に係る半導体加工用シートからの半導体チップのピックアップ等を良好に行うことが可能となる。なお、本明細書における粘着力は、シリコン製のミラーウエハを被着体とし、JIS Z0237:2009に準じた180°引き剥がし法により測定した粘着力(mN/25mm)とする。また、本実施形態に係る半導体加工用シートが基材のみからなる場合には、粘着力は、当該基材の一方の面について測定されたものとし、本実施形態に係る半導体加工用シートが基材と後述する粘着剤層とからなる場合には、粘着力は、当該粘着剤層における基材とは反対の面について測定されたものとする。 The semiconductor processing sheet according to the present embodiment preferably has adhesiveness on at least one surface. Thereby, it becomes possible to stick and fix a semiconductor chip etc. on the said surface. In the present specification, the surface of the semiconductor processing sheet that has adhesiveness and is attached with a semiconductor chip or the like may be referred to as an “adhesive surface”. The adhesive strength of the semiconductor processing sheet according to the present embodiment is preferably 300 mN / 25 mm or more, particularly preferably 800 mN / 25 mm or more, and more preferably 1000 mN / 25 mm or more. The adhesive strength is preferably 30000 mN / 25 mm or less, particularly preferably 15000 mN / 25 mm or less, and more preferably 10000 mN / 25 mm or less. When the adhesive force is 300 mN / 25 mm or more, a semiconductor chip or the like can be satisfactorily adhered and fixed to the adhesive surface. In addition, when the adhesive force is 30000 mN / 25 mm or less, the semiconductor processing sheet according to the present embodiment is replaced with another semiconductor sheet or the like, and the semiconductor processing sheet according to the present embodiment is changed to a semiconductor. Transfer of the semiconductor chip or the like to a holding member capable of attracting and holding the chip or the like, pickup of the semiconductor chip from the semiconductor processing sheet according to the present embodiment, and the like can be performed satisfactorily. In the present specification, the adhesive strength is an adhesive strength (mN / 25 mm) measured by a 180 ° peeling method according to JIS Z0237: 2009 using a silicon mirror wafer as an adherend. In addition, when the semiconductor processing sheet according to the present embodiment is composed only of a base material, the adhesive strength is measured on one surface of the base material, and the semiconductor processing sheet according to the present embodiment is based on the base material. When it consists of a material and the adhesive layer mentioned later, adhesive force shall be measured about the surface on the opposite side to the base material in the said adhesive layer.
 本実施形態に係る半導体加工用シートは、耐熱性を有することが好ましい。本実施形態に係る半導体加工用シートを使用してウエハレベルパッケージを製造する場合、本実施形態に係る半導体加工用シート上において、半導体チップを封止部材により封止することがある。一般に、封止部材としては熱硬化性の材料が使用され、封止の際には、当該材料が加熱される。半導体加工用シートが耐熱性を有することで、当該加熱による半導体加工用シートの変形を抑制することが可能となる。 The semiconductor processing sheet according to the present embodiment preferably has heat resistance. When a wafer level package is manufactured using the semiconductor processing sheet according to the present embodiment, the semiconductor chip may be sealed with a sealing member on the semiconductor processing sheet according to the present embodiment. Generally, a thermosetting material is used as the sealing member, and the material is heated at the time of sealing. When the semiconductor processing sheet has heat resistance, it is possible to suppress deformation of the semiconductor processing sheet due to the heating.
 本実施形態に係る半導体加工用シートの厚さは、30μm以上であることが好ましく、特に50μm以上であることが好ましい。また、当該厚さは、300μm以下であることが好ましく、特に250μm以下であることが好ましい。 The thickness of the semiconductor processing sheet according to this embodiment is preferably 30 μm or more, and particularly preferably 50 μm or more. Further, the thickness is preferably 300 μm or less, and particularly preferably 250 μm or less.
2.基材
 本実施形態に係る半導体加工用シートの基材は、半導体加工用シートが前述の物性を達成できるものであれば、その構成材料は特に限定されず、通常は樹脂系の材料を主材料とするフィルムから構成される。特に、前述した物性を達成し易いという観点から、基材の材料としては、熱可塑性エラストマーまたはゴム系材料を使用することが好ましく、これらの中でも、前述した物性をより達成し易いという観点から、熱可塑性エラストマーを使用することが特に好ましい。また、前述した物性を達成し易いという観点から、基材の構成材料としては、ガラス転移温度(Tg)が比較的低い樹脂を使用することが好ましく、特に、このような樹脂のガラス転移温度(Tg)は、90℃以下であることが好ましく、特に80℃以下であることが好ましく、さらには70℃以下であることが好ましい。
2. Base Material The base material of the semiconductor processing sheet according to the present embodiment is not particularly limited as long as the semiconductor processing sheet can achieve the above-described physical properties. Usually, a resin-based material is a main material. It is comprised from the film. In particular, from the viewpoint of easily achieving the above-described physical properties, it is preferable to use a thermoplastic elastomer or a rubber-based material as the base material. Among these, from the viewpoint of easily achieving the above-described physical properties, It is particularly preferred to use a thermoplastic elastomer. In addition, from the viewpoint of easily achieving the above-described physical properties, it is preferable to use a resin having a relatively low glass transition temperature (Tg) as a constituent material of the base material. In particular, the glass transition temperature ( Tg) is preferably 90 ° C. or lower, particularly preferably 80 ° C. or lower, and more preferably 70 ° C. or lower.
 熱可塑性エラストマーとしては、ウレタン系エラストマー、オレフィン系エラストマー、塩化ビニル系エラストマー、ポリエステル系エラストマー、スチレン系エラストマー、アクリル系エラストマー、アミド系エラストマー等が挙げられる。これらの中でも、前述した物性をより達成し易いという観点から、ウレタン系エラストマーを使用することが好ましい。 Examples of thermoplastic elastomers include urethane elastomers, olefin elastomers, vinyl chloride elastomers, polyester elastomers, styrene elastomers, acrylic elastomers, and amide elastomers. Among these, it is preferable to use a urethane elastomer from the viewpoint that the above-described physical properties are more easily achieved.
 ウレタン系エラストマーとは、一般に、長鎖ポリオール、鎖延長剤およびジイソシアネートを反応させて得られるものであり、長鎖ポリオールから誘導される構成単位を有するソフトセグメントと、鎖延長剤とジイソシアネートとの反応から得られるポリウレタン構造を有するハードセグメントとからなる。 A urethane-based elastomer is generally obtained by reacting a long-chain polyol, a chain extender and a diisocyanate, and a soft segment having a structural unit derived from a long-chain polyol, and a reaction between the chain extender and the diisocyanate. From a hard segment having a polyurethane structure.
 ウレタン系エラストマーを、そのソフトセグメント成分として用いる長鎖ポリオールの種類によって分類すると、ポリエステル系ポリウレタンエラストマー、ポリエーテル系ポリウレタンエラストマー、ポリカーボネート系ポリウレタンエラストマーなどに分けられる。本実施形態に係る半導体加工用シートでは、これらのうち、前述した物性を達成し易いという観点から、ポリエーテル系ポリウレタンエラストマーを使用することが好ましい。 When urethane-based elastomers are classified according to the type of long-chain polyol used as the soft segment component, they can be classified into polyester-based polyurethane elastomers, polyether-based polyurethane elastomers, polycarbonate-based polyurethane elastomers, and the like. In the semiconductor processing sheet according to the present embodiment, among these, it is preferable to use a polyether-based polyurethane elastomer from the viewpoint of easily achieving the above-described physical properties.
 上記長鎖ポリオールの例としては、ラクトン系ポリエステルポリオール、アジペート系ポリエステルポリオールなどのポリエステルポリオール;ポリプロピレン(エチレン)ポリオール、ポリテトラメチレンエーテルグリコールなどのポリエーテルポリオール;ポリカーボネートポリオールなどが挙げられる。これらのうち、前述した物性を達成し易いという観点から、アジペート系ポリエステルポリオールを使用することが好ましい。 Examples of the long-chain polyol include polyester polyols such as lactone polyester polyols and adipate polyester polyols; polyether polyols such as polypropylene (ethylene) polyol and polytetramethylene ether glycol; polycarbonate polyols and the like. Among these, it is preferable to use an adipate polyester polyol from the viewpoint of easily achieving the above-described physical properties.
 上記ジイソシアネートの例としては、2,4-トルエンジイソシアネート、2,6-トルエンジイソシアネート、4,4’-ジフェニルメタンジイソシアネート、ヘキサメチレンジイソシアネートなどが挙げられる。これらのうち、前述した物性を達成し易いという観点から、ヘキサメチレンジイソシアネートを使用することが好ましい。 Examples of the diisocyanate include 2,4-toluene diisocyanate, 2,6-toluene diisocyanate, 4,4'-diphenylmethane diisocyanate, hexamethylene diisocyanate, and the like. Among these, it is preferable to use hexamethylene diisocyanate from the viewpoint of easily achieving the physical properties described above.
 上記鎖延長剤としては、1,4-ブタンジオール、1,6-ヘキサンジオールなどの低分子多価アルコール、芳香族ジアミンなどが挙げられる。これらのうち、前述した物性を達成し易いという観点から、1,6-ヘキサンジオールを使用することが好ましい。 Examples of the chain extender include low molecular weight polyhydric alcohols such as 1,4-butanediol and 1,6-hexanediol, and aromatic diamines. Of these, 1,6-hexanediol is preferably used from the viewpoint of easily achieving the above-described physical properties.
 オレフィン系エラストマーとしては、エチレン・α-オレフィン共重合体、プロピレン・α-オレフィン共重合体、ブテン・α-オレフィン共重合体、エチレン・プロピレン・α-オレフィン共重合体、エチレン・ブテン・α-オレフィン共重合体、プロピレン・ブテン-αオレフィン共重合体、エチレン・プロピレン・ブテン-α・オレフィン共重合体、スチレン・イソプレン共重合体およびスチレン・エチレン・ブチレン共重合体からなる群より選ばれる少なくとも1種の樹脂を含むものが挙げられる。 Examples of olefin elastomers include ethylene / α-olefin copolymers, propylene / α-olefin copolymers, butene / α-olefin copolymers, ethylene / propylene / α-olefin copolymers, ethylene / butene / α- At least selected from the group consisting of olefin copolymers, propylene / butene-α olefin copolymers, ethylene / propylene / butene / α / olefin copolymers, styrene / isoprene copolymers and styrene / ethylene / butylene copolymers. The thing containing 1 type of resin is mentioned.
 オレフィン系エラストマーの密度は、特に限定されないが、半導体ウエハを半導体加工用シートに貼付する時の凹凸追従性に優れる基材をより安定的に得るなどの観点から、0.860g/cm以上0.905g/cm未満であることが好ましく、0.862g/cm以上0.900g/cm未満であることがより好ましく、0.864g/cm以上0.895g/cm未満であることが特に好ましい。 The density of the olefin-based elastomer is not particularly limited, but is 0.860 g / cm 3 or more from the viewpoint of more stably obtaining a substrate excellent in unevenness followability when a semiconductor wafer is attached to a semiconductor processing sheet. it is preferably less than .905g / cm 3, more preferably less than 0.862 g / cm 3 or more 0.900 g / cm 3, less than 0.864 g / cm 3 or more 0.895 g / cm 3 Is particularly preferred.
 オレフィン系エラストマーは、このエラストマーを形成するために用いた全単量体のうち、オレフィン系化合物からなる単量体の質量比率(本明細書において「オレフィン含有率」ともいう。)が50~100質量%であることが好ましい。オレフィン含有率が過度に低い場合には、オレフィンに由来する構造単位を含むエラストマーとしての性質が現れにくくなり、柔軟性やゴム弾性を示しにくくなる。かかる効果を安定的に得る観点から、オレフィン含有率は50質量%以上であることが好ましく、60質量%以上であることがより好ましい。 The olefin-based elastomer has a mass ratio (also referred to as “olefin content” in the present specification) of a monomer composed of an olefin-based compound of all monomers used for forming the elastomer of 50 to 100. It is preferable that it is mass%. When the olefin content is excessively low, properties as an elastomer containing structural units derived from olefins are hardly exhibited, and flexibility and rubber elasticity are hardly exhibited. From the viewpoint of stably obtaining such an effect, the olefin content is preferably 50% by mass or more, and more preferably 60% by mass or more.
 スチレン系エラストマーとしては、スチレン-共役ジエン共重合体およびスチレン-オレフィン共重合体などが挙げられる。スチレン-共役ジエン共重合体の具体例としては、スチレン-ブタジエン共重合体、スチレン-ブタジエン-スチレン共重合体(SBS)、スチレン-ブタジエン-ブチレン-スチレン共重合体、スチレン-イソプレン共重合体、スチレン-イソプレン-スチレン共重合体(SIS)、スチレン-エチレン-イソプレン-スチレン共重合体等の未水添スチレン-共役ジエン共重合体;スチレン-エチレン/プロピレン-スチレン共重合体(SEPS、スチレン-イソプレン-スチレン共重合体の水添加物)、スチレン-エチレン-ブチレン-スチレン共重合体(SEBS、スチレン-ブタジエン共重合体の水素添加物)等の水添スチレン-共役ジエン共重合体などを挙げることができる。また、工業的には、タフプレン(旭化成社製)、クレイトン(クレイトンポリマージャパン社製)、住友TPE-SB(住友化学社製)、エポフレンド(ダイセル化学工業社製)、ラバロン(三菱化学社製)、セプトン(クラレ社製)、タフテック(旭化成社製)などの商品名が挙げられる。スチレン系エラストマーは、水素添加物でも未水添物であってもよい。 Examples of the styrene elastomer include styrene-conjugated diene copolymer and styrene-olefin copolymer. Specific examples of the styrene-conjugated diene copolymer include styrene-butadiene copolymer, styrene-butadiene-styrene copolymer (SBS), styrene-butadiene-butylene-styrene copolymer, styrene-isoprene copolymer, Unhydrogenated styrene-conjugated diene copolymers such as styrene-isoprene-styrene copolymer (SIS) and styrene-ethylene-isoprene-styrene copolymer; styrene-ethylene / propylene-styrene copolymer (SEPS, styrene- Hydrogenated styrene-conjugated diene copolymers such as isoprene-styrene copolymer water additives) and styrene-ethylene-butylene-styrene copolymers (SEBS, hydrogenated styrene-butadiene copolymers). be able to. Industrially, Tufprene (Asahi Kasei), Clayton (Clayton Polymer Japan), Sumitomo TPE-SB (Sumitomo Chemical), Epofriend (Daicel Chemical Industries), Lavalon (Mitsubishi Chemical) ), Septon (manufactured by Kuraray), Tuftec (manufactured by Asahi Kasei), and the like. The styrene elastomer may be a hydrogenated product or an unhydrogenated product.
 ゴム系材料としては、例えば、天然ゴム、合成イソプレンゴム(IR)、ブタジエンゴム(BR)、スチレン-ブタジエンゴム(SBR)、クロロプレンゴム(CR)、アクリロニトリル-ブタジエン共重合ゴム(NBR)、ブチルゴム(IIR)、ハロゲン化ブチルゴム、アクリルゴム、ウレタンゴム、多硫化ゴム等が挙げられ、これらの1種を単独でまたは2種以上を組み合わせて使用することができる。 Examples of rubber materials include natural rubber, synthetic isoprene rubber (IR), butadiene rubber (BR), styrene-butadiene rubber (SBR), chloroprene rubber (CR), acrylonitrile-butadiene copolymer rubber (NBR), butyl rubber ( IIR), halogenated butyl rubber, acrylic rubber, urethane rubber, polysulfide rubber and the like, and these can be used alone or in combination of two or more.
 基材として、上記のような材料からなるフィルムが複数層積層されたものを使用することもできる。また、上記のような材料からなるフィルムと、その他のフィルムとが積層されたものを使用することもできる。 As the base material, a film in which a plurality of films made of the above materials are laminated can be used. Moreover, what laminated | stacked the film which consists of the above materials, and another film can also be used.
 フィルムを複数層積層する場合、前述した物性を達成する上で寄与率の高いフィルムを、比較的厚い厚さで中央に配置し、そのフィルムを、上記寄与率の低い、比較的薄い厚さの別のフィルムで挟む構成にすることができる。また、ガラス転移温度(Tg)が比較的低い樹脂の使用は、前述した物性を達成する上で好ましいものの、そのような樹脂は粘着性が高いため、そのような樹脂を半導体加工用シートの表面に設ける場合、半導体加工用シートの製造時または使用時における取り扱いが困難になる可能性がある。そこで、ガラス転移温度(Tg)が比較的低い樹脂フィルムを、ガラス転移温度(Tg)が比較的高い樹脂フィルムで挟んだり、ガラス転移温度(Tg)が比較的低い樹脂フィルムに対してガラス転移温度(Tg)が比較的高い樹脂フィルムを積層したりすることにより、前述した物性の達成と、取り扱い性とを両立することができる。 In the case of laminating a plurality of layers of films, a film having a high contribution rate in achieving the above-described physical properties is arranged in the center with a relatively thick thickness, and the film is formed with a relatively thin thickness with a low contribution rate. It can be configured to be sandwiched between different films. In addition, the use of a resin having a relatively low glass transition temperature (Tg) is preferable for achieving the above-described physical properties. However, since such a resin has high adhesiveness, such a resin is used on the surface of a semiconductor processing sheet. When it is provided, it may be difficult to handle the semiconductor processing sheet during manufacture or use. Therefore, a resin film having a relatively low glass transition temperature (Tg) is sandwiched between resin films having a relatively high glass transition temperature (Tg), or a glass transition temperature relative to a resin film having a relatively low glass transition temperature (Tg). By laminating a resin film having a relatively high (Tg), it is possible to achieve both the achievement of the above-described physical properties and the handleability.
 本実施形態に係る半導体加工用シートが基材のみから構成される場合、当該基材は粘着性を有することが好ましい。当該粘着性が常態で発揮されるものである場合、基材として、自己粘着性を有するものを使用することが好ましい。 When the semiconductor processing sheet according to the present embodiment is composed only of a base material, the base material preferably has adhesiveness. When the said adhesiveness is what is exhibited by a normal state, it is preferable to use what has self-adhesiveness as a base material.
 また、本実施形態に係る半導体加工用シートが基材のみから構成され、且つ当該基材が複数のフィルムを積層してなるものである場合、積層される複数のフィルムのうち、最外層に位置するフィルムのみまたはそれらの一方のみが粘着性を有するものであってもよい。例えば、ガラス転移温度(Tg)が比較的低い樹脂フィルムの一方の面に対して、ガラス転移温度(Tg)が比較的高い樹脂フィルムを積層することで、その一方の面のみにおいて粘着性を発揮させることができる。なお、本明細書における半導体加工用シートの最外層には、剥離シート等、使用時に除去されるものを含まないものとする。 In addition, when the semiconductor processing sheet according to the present embodiment is composed of only a base material and the base material is formed by laminating a plurality of films, among the plurality of laminated films, the sheet is positioned in the outermost layer. Only the film to perform or only one of them may have adhesiveness. For example, by laminating a resin film with a relatively high glass transition temperature (Tg) on one surface of a resin film with a relatively low glass transition temperature (Tg), it exhibits adhesiveness only on that one surface. Can be made. The outermost layer of the semiconductor processing sheet in this specification does not include a release sheet or the like that is removed during use.
 本実施形態における基材では、上記の樹脂系材料を主材料とするフィルム内に、顔料、染料、難燃剤、可塑剤、帯電防止剤、滑剤、フィラー等の各種添加剤が含まれていてもよい。顔料としては、例えば、二酸化チタン、カーボンブラック等が挙げられる。また、フィラーとしては、メラミン樹脂のような有機系材料、ヒュームドシリカのような無機系材料およびニッケル粒子のような金属系材料が例示される。こうした添加剤の含有量は特に限定されないが、基材が所望の機能を発揮し得る範囲に留めることが好ましい。 In the base material in the present embodiment, various additives such as pigments, dyes, flame retardants, plasticizers, antistatic agents, lubricants, fillers, and the like may be included in the film mainly composed of the resin material. Good. Examples of the pigment include titanium dioxide and carbon black. Examples of the filler include organic materials such as melamine resin, inorganic materials such as fumed silica, and metal materials such as nickel particles. The content of such an additive is not particularly limited, but it is preferable to keep the content within a range in which the base material can exhibit a desired function.
 半導体加工用シートが後述する粘着剤層を有する場合、基材は、その表面に積層される粘着剤層との密着性を向上させる目的で、所望により片面または両面に、酸化法や凹凸化法などによる表面処理、あるいはプライマー層を形成するプライマー処理を施すことができる。上記酸化法としては、例えばコロナ放電処理、プラズマ放電処理、クロム酸化処理(湿式)、火炎処理、熱風処理、オゾン、紫外線照射処理などが挙げられ、また、凹凸化法としては、例えばサンドブラスト法、溶射処理法などが挙げられる。 When the semiconductor processing sheet has a pressure-sensitive adhesive layer described later, the base material is formed on one surface or both surfaces as desired by an oxidation method or an unevenness method for the purpose of improving adhesion with the pressure-sensitive adhesive layer laminated on the surface. The surface treatment by the above, or the primer treatment for forming the primer layer can be performed. Examples of the oxidation method include corona discharge treatment, plasma discharge treatment, chromium oxidation treatment (wet), flame treatment, hot air treatment, ozone, ultraviolet irradiation treatment, and the like. Examples include a thermal spraying method.
 また、粘着剤層がエネルギー線硬化性粘着剤を含有する場合、基材は、エネルギー線に対する透過性を有することが好ましい。特に、エネルギー線として紫外線を用いる場合には、基材は紫外線に対して透過性を有することが好ましく、エネルギー線として電子線を用いる場合には、基材は電子線の透過性を有することが好ましい。 Further, when the pressure-sensitive adhesive layer contains an energy ray-curable pressure-sensitive adhesive, it is preferable that the substrate has transparency to energy rays. In particular, when ultraviolet rays are used as energy rays, the substrate preferably has transparency to ultraviolet rays, and when electron beams are used as energy rays, the substrate may have electron beam transparency. preferable.
 本実施形態に係る半導体加工用シートにおいて、基材の製造方法は特に制限されず、例えば、キャスト成型法(溶融流延法)、Tダイ法やインフレーション法のような溶融押出法、カレンダー法など、いずれの方法を用いてもよい。なかでも、厚さのバラツキを抑制することが容易であるという観点から、キャスト成型法により基材を製造することが好ましい。この場合、基材の材料となる液状の配合物(硬化前の樹脂、樹脂の溶液等)を、工程シート上に薄膜状にキャストした後に、塗膜を硬化させてフィルム化することで基材を製造できることが好ましい。 In the semiconductor processing sheet according to the present embodiment, the substrate production method is not particularly limited. For example, a cast molding method (melt casting method), a melt extrusion method such as a T-die method or an inflation method, a calendar method, or the like. Any method may be used. Especially, it is preferable to manufacture a base material by the cast molding method from a viewpoint that it is easy to suppress variation in thickness. In this case, after casting a liquid compound (resin before curing, resin solution, etc.) into a thin film on the process sheet, the coating is cured to form a film. It is preferable that can be manufactured.
 基材の厚さは、半導体加工用シートが所望の工程において適切に機能できる限り、限定されない。基材の厚さは、20μm以上であることが好ましく、特に40μm以上であることが好ましい。また、当該厚さは、250μm以下であることが好ましく、特に200μm以下であることが好ましい。 The thickness of the substrate is not limited as long as the semiconductor processing sheet can function properly in a desired process. The thickness of the substrate is preferably 20 μm or more, and particularly preferably 40 μm or more. Further, the thickness is preferably 250 μm or less, and particularly preferably 200 μm or less.
 また、2cm間隔で厚みを測定した際の、基材の厚さの標準偏差は、2μm以下であることが好ましく、特に1.5μm以下であることが好ましく、さらには1μm以下であることが好ましい。当該標準偏差が2μm以下であることで、半導体加工用シートが精度の高い厚さを有するものとなり、半導体加工用シートを均一に延伸することが可能となる。 Further, the standard deviation of the thickness of the base material when the thickness is measured at intervals of 2 cm is preferably 2 μm or less, particularly preferably 1.5 μm or less, and further preferably 1 μm or less. . When the standard deviation is 2 μm or less, the semiconductor processing sheet has a highly accurate thickness, and the semiconductor processing sheet can be uniformly stretched.
3.粘着剤層
 本実施形態に係る半導体加工用シートは、基材の少なくとも一方の面に積層された粘着剤層をさらに備えることが好ましい。これにより、半導体加工用シートは、当該粘着剤層側の面において所望の粘着性を発揮し易くなり、当該面に半導体チップ等を良好に貼付することが可能となる。
3. Adhesive Layer The semiconductor processing sheet according to the present embodiment preferably further includes an adhesive layer laminated on at least one surface of the substrate. Thereby, the semiconductor processing sheet easily exhibits desired adhesiveness on the surface on the pressure-sensitive adhesive layer side, and a semiconductor chip or the like can be satisfactorily adhered to the surface.
 粘着剤層は、半導体加工用シートにおいて前述した物性が達成できるものであれば、特に限定されない。当該粘着剤層は、非エネルギー線硬化性粘着剤から構成されてもよいし、エネルギー線硬化性粘着剤から構成されてもよい。非エネルギー線硬化性粘着剤としては、所望の粘着力および再剥離性を有するものが好ましく、例えば、アクリル系粘着剤、ゴム系粘着剤、シリコーン系粘着剤、ウレタン系粘着剤、ポリエステル系粘着剤、ポリビニルエーテル系粘着剤等を使用することができる。これらの中でも、半導体加工用シートを延伸した際に半導体チップ等の脱落を効果的に抑制することのできるアクリル系粘着剤が好ましい。 The pressure-sensitive adhesive layer is not particularly limited as long as the physical properties described above can be achieved in the semiconductor processing sheet. The pressure-sensitive adhesive layer may be composed of a non-energy ray curable pressure sensitive adhesive or an energy ray curable pressure sensitive adhesive. As the non-energy ray curable pressure-sensitive adhesive, those having desired adhesive strength and removability are preferable. For example, acrylic pressure-sensitive adhesive, rubber-based pressure-sensitive adhesive, silicone-based pressure-sensitive adhesive, urethane-based pressure-sensitive adhesive, and polyester-based pressure-sensitive adhesive Polyvinyl ether-based pressure-sensitive adhesives can be used. Among these, an acrylic pressure-sensitive adhesive that can effectively suppress dropping of a semiconductor chip or the like when the semiconductor processing sheet is stretched is preferable.
 一方、エネルギー線硬化性粘着剤は、エネルギー線照射により硬化して粘着力が低下するため、半導体チップと半導体加工用シートとを分離させたいときに、エネルギー線照射することにより、容易に分離させることができる。 On the other hand, the energy ray curable adhesive is cured by energy ray irradiation and its adhesive strength is reduced. Therefore, when it is desired to separate the semiconductor chip and the semiconductor processing sheet, it can be easily separated by irradiating the energy ray. be able to.
 粘着剤層を構成するエネルギー線硬化性粘着剤は、エネルギー線硬化性を有するポリマーを主成分とするものであってもよいし、非エネルギー線硬化性ポリマー(エネルギー線硬化性を有しないポリマー)と少なくとも1つ以上のエネルギー線硬化性基を有するモノマーおよび/またはオリゴマーとの混合物を主成分とするものであってもよい。また、エネルギー線硬化性を有するポリマーと非エネルギー線硬化性ポリマーとの混合物であってもよいし、エネルギー線硬化性を有するポリマーと少なくとも1つ以上のエネルギー線硬化性基を有するモノマーおよび/またはオリゴマーとの混合物であってもよいし、それら3種の混合物であってもよい。 The energy ray-curable pressure-sensitive adhesive constituting the pressure-sensitive adhesive layer may be mainly composed of a polymer having energy ray-curability, or a non-energy ray-curable polymer (polymer not having energy ray-curability). And a mixture of a monomer and / or an oligomer having at least one energy ray curable group. Further, it may be a mixture of a polymer having energy ray curable properties and a non-energy ray curable polymer, a polymer having energy ray curable properties and a monomer having at least one energy ray curable group and / or It may be a mixture with an oligomer or a mixture of these three.
 最初に、エネルギー線硬化性粘着剤が、エネルギー線硬化性を有するポリマーを主成分とする場合について、以下説明する。 First, the case where the energy ray-curable pressure-sensitive adhesive is composed mainly of a polymer having energy ray-curability will be described below.
 エネルギー線硬化性を有するポリマーは、側鎖にエネルギー線硬化性を有する官能基(エネルギー線硬化性基)が導入された(メタ)アクリル酸エステル(共)重合体(A)(以下「エネルギー線硬化型重合体(A)」という場合がある。)であることが好ましい。このエネルギー線硬化型重合体(A)は、官能基含有モノマー単位を有するアクリル系共重合体(a1)と、その官能基に結合する官能基を有する不飽和基含有化合物(a2)とを反応させて得られるものであることが好ましい。なお、本明細書において、(メタ)アクリル酸エステルとは、アクリル酸エステル及びメタクリル酸エステルの両方を意味する。他の類似用語も同様である。 The polymer having energy ray curability is a (meth) acrylic acid ester (co) polymer (A) (hereinafter referred to as “energy ray”) in which a functional group having energy ray curability (energy ray curable group) is introduced into the side chain. It may be referred to as “curable polymer (A)”). This energy beam curable polymer (A) reacts an acrylic copolymer (a1) having a functional group-containing monomer unit with an unsaturated group-containing compound (a2) having a functional group bonded to the functional group. It is preferable that it is obtained. In this specification, (meth) acrylic acid ester means both acrylic acid ester and methacrylic acid ester. The same applies to other similar terms.
 アクリル系共重合体(a1)は、官能基含有モノマーから導かれる構成単位と、(メタ)アクリル酸エステルモノマーまたはその誘導体から導かれる構成単位とを含むことが好ましい。 The acrylic copolymer (a1) preferably contains a structural unit derived from a functional group-containing monomer and a structural unit derived from a (meth) acrylic acid ester monomer or a derivative thereof.
 アクリル系共重合体(a1)の構成単位としての官能基含有モノマーは、重合性の二重結合と、ヒドロキシ基、カルボキシ基、アミノ基、置換アミノ基、エポキシ基等の官能基とを分子内に有するモノマーであることが好ましい。 The functional group-containing monomer as a constituent unit of the acrylic copolymer (a1) contains a polymerizable double bond and a functional group such as a hydroxy group, a carboxy group, an amino group, a substituted amino group, and an epoxy group in the molecule. It is preferable that the monomer has
 ヒドロキシ基含有モノマーとしては、例えば、2-ヒドロキシエチル(メタ)アクリレート、2-ヒドロキシプロピル(メタ)アクリレート、3-ヒドロキシプロピル(メタ)アクリレート、2-ヒドロキシブチル(メタ)アクリレート、3-ヒドロキシブチル(メタ)アクリレート、4-ヒドロキシブチル(メタ)アクリレート等が挙げられ、これらは単独でまたは2種以上を組み合わせて用いられる。 Examples of the hydroxy group-containing monomer include 2-hydroxyethyl (meth) acrylate, 2-hydroxypropyl (meth) acrylate, 3-hydroxypropyl (meth) acrylate, 2-hydroxybutyl (meth) acrylate, 3-hydroxybutyl ( Examples thereof include meth) acrylate and 4-hydroxybutyl (meth) acrylate, and these are used alone or in combination of two or more.
 カルボキシ基含有モノマーとしては、例えば、アクリル酸、メタクリル酸、クロトン酸、マレイン酸、イタコン酸、シトラコン酸等のエチレン性不飽和カルボン酸が挙げられる。これらは単独で用いてもよいし、2種以上を組み合わせて用いてもよい。 Examples of the carboxy group-containing monomer include ethylenically unsaturated carboxylic acids such as acrylic acid, methacrylic acid, crotonic acid, maleic acid, itaconic acid, and citraconic acid. These may be used alone or in combination of two or more.
 アミノ基含有モノマーまたは置換アミノ基含有モノマーとしては、例えば、アミノエチル(メタ)アクリレート、n-ブチルアミノエチル(メタ)アクリレート等が挙げられる。これらは単独で用いてもよいし、2種以上を組み合わせて用いてもよい。 Examples of the amino group-containing monomer or substituted amino group-containing monomer include aminoethyl (meth) acrylate and n-butylaminoethyl (meth) acrylate. These may be used alone or in combination of two or more.
 アクリル系共重合体(a1)を構成する(メタ)アクリル酸エステルモノマーとしては、アルキル基の炭素数が1~20であるアルキル(メタ)アクリレートの他、例えば、分子内に脂環式構造を有するモノマー(脂環式構造含有モノマー)が好ましく用いられる。 Examples of the (meth) acrylic acid ester monomer constituting the acrylic copolymer (a1) include an alkyl (meth) acrylate having an alkyl group having 1 to 20 carbon atoms, and an alicyclic structure in the molecule, for example. The monomer (alicyclic structure-containing monomer) is preferably used.
 アルキル(メタ)アクリレートとしては、特にアルキル基の炭素数が1~18であるアルキル(メタ)アクリレート、例えば、メチル(メタ)アクリレート、エチル(メタ)アクリレート、プロピル(メタ)アクリレート、n-ブチル(メタ)アクリレート、2-エチルヘキシル(メタ)アクリレート等が好ましく用いられる。これらは、1種を単独で用いてもよいし、2種以上を組み合わせて用いてもよい。 Examples of the alkyl (meth) acrylate include alkyl (meth) acrylates having an alkyl group having 1 to 18 carbon atoms, such as methyl (meth) acrylate, ethyl (meth) acrylate, propyl (meth) acrylate, n-butyl ( (Meth) acrylate, 2-ethylhexyl (meth) acrylate and the like are preferably used. These may be used individually by 1 type and may be used in combination of 2 or more type.
 脂環式構造含有モノマーとしては、例えば、(メタ)アクリル酸シクロヘキシル、(メタ)アクリル酸ジシクロペンタニル、(メタ)アクリル酸アダマンチル、(メタ)アクリル酸イソボルニル、(メタ)アクリル酸ジシクロペンテニル、(メタ)アクリル酸ジシクロペンテニルオキシエチル等が好ましく用いられる。これらは、1種を単独で用いてもよいし、2種以上を組み合わせて用いてもよい。 Examples of the alicyclic structure-containing monomer include cyclohexyl (meth) acrylate, dicyclopentanyl (meth) acrylate, adamantyl (meth) acrylate, isobornyl (meth) acrylate, and dicyclopentenyl (meth) acrylate. , Dicyclopentenyloxyethyl (meth) acrylate and the like are preferably used. These may be used individually by 1 type and may be used in combination of 2 or more type.
 アクリル系共重合体(a1)は、上記官能基含有モノマーから導かれる構成単位を、好ましくは1質量%以上、特に好ましくは5質量%以上、さらに好ましくは10質量%以上の割合で含有する。また、アクリル系共重合体(a1)は、上記官能基含有モノマーから導かれる構成単位を、好ましくは35質量%以下、特に好ましくは30質量%以下、さらに好ましくは25質量%以下の割合で含有する。 The acrylic copolymer (a1) contains the structural unit derived from the functional group-containing monomer, preferably in an amount of 1% by mass or more, particularly preferably 5% by mass or more, and more preferably 10% by mass or more. The acrylic copolymer (a1) preferably contains a constituent unit derived from the functional group-containing monomer in a proportion of 35% by mass or less, particularly preferably 30% by mass or less, and more preferably 25% by mass or less. To do.
 さらに、アクリル系共重合体(a1)は、(メタ)アクリル酸エステルモノマーまたはその誘導体から導かれる構成単位を、好ましくは50質量%以上、特に好ましくは60質量%以上、さらに好ましくは70質量%以上の割合で含有する。また、アクリル系共重合体(a1)は、(メタ)アクリル酸エステルモノマーまたはその誘導体から導かれる構成単位を、好ましくは99質量%以下、特に好ましくは95質量%以下、さらに好ましくは90質量%以下の割合で含有する。 Furthermore, the acrylic copolymer (a1) preferably contains 50% by mass or more, particularly preferably 60% by mass or more, and further preferably 70% by mass of a structural unit derived from a (meth) acrylic acid ester monomer or a derivative thereof. It contains in the above ratio. The acrylic copolymer (a1) preferably contains 99% by mass or less, particularly preferably 95% by mass or less, and more preferably 90% by mass of a structural unit derived from a (meth) acrylic acid ester monomer or a derivative thereof. Contains in the following proportions.
 アクリル系共重合体(a1)は、上記のような官能基含有モノマーと、(メタ)アクリル酸エステルモノマーまたはその誘導体とを常法で共重合することにより得られるが、これらモノマーの他にもジメチルアクリルアミド、蟻酸ビニル、酢酸ビニル、スチレン等が共重合されてもよい。 The acrylic copolymer (a1) can be obtained by copolymerizing a functional group-containing monomer as described above with a (meth) acrylic acid ester monomer or a derivative thereof in a conventional manner. Dimethylacrylamide, vinyl formate, vinyl acetate, styrene and the like may be copolymerized.
 上記官能基含有モノマー単位を有するアクリル系共重合体(a1)を、その官能基に結合する官能基を有する不飽和基含有化合物(a2)と反応させることにより、エネルギー線硬化型重合体(A)が得られる。 By reacting the acrylic copolymer (a1) having the functional group-containing monomer unit with an unsaturated group-containing compound (a2) having a functional group bonded to the functional group, an energy beam curable polymer (A ) Is obtained.
 不飽和基含有化合物(a2)が有する官能基は、アクリル系共重合体(a1)が有する官能基含有モノマー単位の官能基の種類に応じて、適宜選択することができる。例えば、アクリル系共重合体(a1)が有する官能基がヒドロキシ基、アミノ基または置換アミノ基の場合、不飽和基含有化合物(a2)が有する官能基としてはイソシアネート基またはエポキシ基が好ましく、アクリル系共重合体(a1)が有する官能基がエポキシ基の場合、不飽和基含有化合物(a2)が有する官能基としてはアミノ基、カルボキシ基またはアジリジニル基が好ましい。 The functional group of the unsaturated group-containing compound (a2) can be appropriately selected according to the type of functional group of the functional group-containing monomer unit of the acrylic copolymer (a1). For example, when the functional group of the acrylic copolymer (a1) is a hydroxy group, an amino group or a substituted amino group, the functional group of the unsaturated group-containing compound (a2) is preferably an isocyanate group or an epoxy group. When the functional group that the system copolymer (a1) has is an epoxy group, the functional group that the unsaturated group-containing compound (a2) has is preferably an amino group, a carboxy group, or an aziridinyl group.
 また上記不飽和基含有化合物(a2)には、エネルギー線重合性の炭素-炭素二重結合が、1分子中に少なくとも1個、好ましくは1~6個、さらに好ましくは1~4個含まれている。このような不飽和基含有化合物(a2)の具体例としては、例えば、2-メタクリロイルオキシエチルイソシアネート、メタ-イソプロペニル-α,α-ジメチルベンジルイソシアネート、メタクリロイルイソシアネート、アリルイソシアネート、1,1-(ビスアクリロイルオキシメチル)エチルイソシアネート;ジイソシアネート化合物またはポリイソシアネート化合物と、ヒドロキシエチル(メタ)アクリレートとの反応により得られるアクリロイルモノイソシアネート化合物;ジイソシアネート化合物またはポリイソシアネート化合物と、ポリオール化合物と、ヒドロキシエチル(メタ)アクリレートとの反応により得られるアクリロイルモノイソシアネート化合物;グリシジル(メタ)アクリレート;(メタ)アクリル酸、2-(1-アジリジニル)エチル(メタ)アクリレート、2-ビニル-2-オキサゾリン、2-イソプロペニル-2-オキサゾリン等が挙げられる。 The unsaturated group-containing compound (a2) contains at least one, preferably 1-6, more preferably 1-4, energy-polymerizable carbon-carbon double bonds in one molecule. ing. Specific examples of such unsaturated group-containing compound (a2) include, for example, 2-methacryloyloxyethyl isocyanate, meta-isopropenyl-α, α-dimethylbenzyl isocyanate, methacryloyl isocyanate, allyl isocyanate, 1,1- ( Bisacryloyloxymethyl) ethyl isocyanate; acryloyl monoisocyanate compound obtained by reaction of diisocyanate compound or polyisocyanate compound with hydroxyethyl (meth) acrylate; diisocyanate compound or polyisocyanate compound, polyol compound, and hydroxyethyl (meth) Acryloyl monoisocyanate compound obtained by reaction with acrylate; glycidyl (meth) acrylate; (meth) acrylic acid, 2- (1 -Aziridinyl) ethyl (meth) acrylate, 2-vinyl-2-oxazoline, 2-isopropenyl-2-oxazoline and the like.
 上記不飽和基含有化合物(a2)は、上記アクリル系共重合体(a1)の官能基含有モノマーモル数に対して、好ましくは50モル%以上、特に好ましくは60モル%以上、さらに好ましくは70モル%以上の割合で用いられる。また、上記不飽和基含有化合物(a2)は、上記アクリル系共重合体(a1)の官能基含有モノマーモル数に対して、好ましくは95モル%以下、特に好ましくは93モル%以下、さらに好ましくは90モル%以下の割合で用いられる。 The unsaturated group-containing compound (a2) is preferably at least 50 mol%, particularly preferably at least 60 mol%, more preferably 70 mol, based on the number of moles of the functional group-containing monomer of the acrylic copolymer (a1). % Is used at a rate of at least%. In addition, the unsaturated group-containing compound (a2) is preferably 95 mol% or less, particularly preferably 93 mol% or less, more preferably, relative to the number of moles of the functional group-containing monomer of the acrylic copolymer (a1). It is used at a ratio of 90 mol% or less.
 アクリル系共重合体(a1)と不飽和基含有化合物(a2)との反応においては、アクリル系共重合体(a1)が有する官能基と不飽和基含有化合物(a2)が有する官能基との組合せに応じて、反応の温度、圧力、溶媒、時間、触媒の有無、触媒の種類を適宜選択することができる。これにより、アクリル系共重合体(a1)中に存在する官能基と、不飽和基含有化合物(a2)中の官能基とが反応し、不飽和基がアクリル系共重合体(a1)中の側鎖に導入され、エネルギー線硬化型重合体(A)が得られる。 In the reaction between the acrylic copolymer (a1) and the unsaturated group-containing compound (a2), the functional group of the acrylic copolymer (a1) and the functional group of the unsaturated group-containing compound (a2) Depending on the combination, the reaction temperature, pressure, solvent, time, presence / absence of catalyst, and type of catalyst can be appropriately selected. As a result, the functional group present in the acrylic copolymer (a1) reacts with the functional group in the unsaturated group-containing compound (a2), so that the unsaturated group is contained in the acrylic copolymer (a1). It introduce | transduces into a side chain and an energy-beam curable polymer (A) is obtained.
 このようにして得られるエネルギー線硬化型重合体(A)の重量平均分子量(Mw)は、1万以上であるのが好ましく、特に15万以上であるのが好ましく、さらには20万以上であるのが好ましい。また、当該重量平均分子量(Mw)は、150万以下であるのが好ましく、特に100万以下であるのが好ましい。なお、本明細書における重量平均分子量(Mw)は、ゲルパーミエーションクロマトグラフィー法(GPC法)により測定した標準ポリスチレン換算の値である。 The weight average molecular weight (Mw) of the energy ray curable polymer (A) thus obtained is preferably 10,000 or more, particularly preferably 150,000 or more, and more preferably 200,000 or more. Is preferred. The weight average molecular weight (Mw) is preferably 1.5 million or less, and particularly preferably 1 million or less. In addition, the weight average molecular weight (Mw) in this specification is the value of standard polystyrene conversion measured by the gel permeation chromatography method (GPC method).
 エネルギー線硬化性粘着剤が、エネルギー線硬化型重合体(A)といったエネルギー線硬化性を有するポリマーを主成分とする場合であっても、エネルギー線硬化性粘着剤は、エネルギー線硬化性のモノマーおよび/またはオリゴマー(B)をさらに含有してもよい。 Even when the energy ray curable adhesive is mainly composed of an energy ray curable polymer such as an energy ray curable polymer (A), the energy ray curable adhesive is an energy ray curable monomer. And / or the oligomer (B) may further be contained.
 エネルギー線硬化性のモノマーおよび/またはオリゴマー(B)としては、例えば、多価アルコールと(メタ)アクリル酸とのエステル等を使用することができる。 As the energy ray-curable monomer and / or oligomer (B), for example, an ester of a polyhydric alcohol and (meth) acrylic acid or the like can be used.
 かかるエネルギー線硬化性のモノマーおよび/またはオリゴマー(B)としては、例えば、シクロヘキシル(メタ)アクリレート、イソボルニル(メタ)アクリレート等の単官能性アクリル酸エステル類、トリメチロールプロパントリ(メタ)アクリレート、ペンタエリスリトールトリ(メタ)アクリレート、ペンタエリスリトールテトラ(メタ)アクリレート、ジペンタエリスリトールヘキサ(メタ)アクリレート、1,4-ブタンジオールジ(メタ)アクリレート、1,6-ヘキサンジオールジ(メタ)アクリレート、ポリエチレングリコールジ(メタ)アクリレート、ジメチロールトリシクロデカンジ(メタ)アクリレート等の多官能性アクリル酸エステル類、ポリエステルオリゴ(メタ)アクリレート、ポリウレタンオリゴ(メタ)アクリレート等が挙げられる。 Examples of the energy ray-curable monomer and / or oligomer (B) include monofunctional acrylic acid esters such as cyclohexyl (meth) acrylate and isobornyl (meth) acrylate, trimethylolpropane tri (meth) acrylate, penta Erythritol tri (meth) acrylate, pentaerythritol tetra (meth) acrylate, dipentaerythritol hexa (meth) acrylate, 1,4-butanediol di (meth) acrylate, 1,6-hexanediol di (meth) acrylate, polyethylene glycol Polyfunctional acrylic esters such as di (meth) acrylate and dimethyloltricyclodecane di (meth) acrylate, polyester oligo (meth) acrylate, polyurethane oligo (meta Acrylate, and the like.
 エネルギー線硬化型重合体(A)に対し、エネルギー線硬化性のモノマーおよび/またはオリゴマー(B)を配合する場合、エネルギー線硬化性粘着剤中におけるエネルギー線硬化性のモノマーおよび/またはオリゴマー(B)の含有量は、エネルギー線硬化型重合体(A)100質量部に対して、0質量部超であることが好ましく、特に60質量部以上であることが好ましい。また、当該含有量は、エネルギー線硬化型重合体(A)100質量部に対して、250質量部以下であることが好ましく、特に200質量部以下であることが好ましい。 When the energy ray curable monomer (B) is blended with the energy ray curable polymer (A), the energy ray curable monomer and / or oligomer (B) in the energy ray curable adhesive is used. ) Content is preferably more than 0 parts by mass, particularly preferably 60 parts by mass or more, with respect to 100 parts by mass of the energy ray-curable polymer (A). In addition, the content is preferably 250 parts by mass or less, particularly preferably 200 parts by mass or less, with respect to 100 parts by mass of the energy beam curable polymer (A).
 ここで、エネルギー線硬化性粘着剤を硬化させるためのエネルギー線として紫外線を用いる場合には、光重合開始剤(C)を添加することが好ましく、この光重合開始剤(C)の使用により、重合硬化時間および光線照射量を少なくすることができる。 Here, when using ultraviolet rays as energy rays for curing the energy ray-curable pressure-sensitive adhesive, it is preferable to add a photopolymerization initiator (C), and by using this photopolymerization initiator (C), The polymerization curing time and the amount of light irradiation can be reduced.
 光重合開始剤(C)としては、具体的には、ベンゾフェノン、アセトフェノン、ベンゾイン、ベンゾインメチルエーテル、ベンゾインエチルエーテル、ベンゾインイソプロピルエーテル、ベンゾインイソブチルエーテル、ベンゾイン安息香酸、ベンゾイン安息香酸メチル、ベンゾインジメチルケタール、2,4-ジエチルチオキサンソン、1-ヒドロキシシクロヘキシルフェニルケトン、ベンジルジフェニルサルファイド、テトラメチルチウラムモノサルファイド、アゾビスイソブチロニトリル、ベンジル、ジベンジル、ジアセチル、β-クロールアンスラキノン、(2,4,6-トリメチルベンジルジフェニル)フォスフィンオキサイド、2-ベンゾチアゾール-N,N-ジエチルジチオカルバメート、オリゴ{2-ヒドロキシ-2-メチル-1-[4-(1-プロペニル)フェニル]プロパノン}、2,2-ジメトキシ-1,2-ジフェニルエタン-1-オンなどが挙げられる。これらは単独で用いてもよいし、2種以上を併用してもよい。 Specific examples of the photopolymerization initiator (C) include benzophenone, acetophenone, benzoin, benzoin methyl ether, benzoin ethyl ether, benzoin isopropyl ether, benzoin isobutyl ether, benzoin benzoic acid, benzoin methyl benzoate, benzoin dimethyl ketal, 2,4-diethylthioxanthone, 1-hydroxycyclohexyl phenyl ketone, benzyldiphenyl sulfide, tetramethylthiuram monosulfide, azobisisobutyronitrile, benzyl, dibenzyl, diacetyl, β-chloranthraquinone, (2,4 6-trimethylbenzyldiphenyl) phosphine oxide, 2-benzothiazole-N, N-diethyldithiocarbamate, oligo {2-hydroxy-2-me Le-1- [4- (1-propenyl) phenyl] propanone}, and 2,2-dimethoxy-1,2-and the like. These may be used alone or in combination of two or more.
 光重合開始剤(C)は、エネルギー線硬化型共重合体(A)(エネルギー線硬化性のモノマーおよび/またはオリゴマー(B)を配合する場合には、エネルギー線硬化型共重合体(A)およびエネルギー線硬化性のモノマーおよび/またはオリゴマー(B)の合計量100質量部)100質量部に対して0.1質量部以上、特に0.5質量部以上の量で用いられることが好ましい。また、光重合開始剤(C)は、エネルギー線硬化型共重合体(A)(エネルギー線硬化性のモノマーおよび/またはオリゴマー(B)を配合する場合には、エネルギー線硬化型共重合体(A)およびエネルギー線硬化性のモノマーおよび/またはオリゴマー(B)の合計量100質量部)100質量部に対して10質量部以下、特に6質量部以下の量で用いられることが好ましい。 The photopolymerization initiator (C) is energy beam curable copolymer (A) (when energy beam curable monomer and / or oligomer (B) is blended, energy beam curable copolymer (A). The total amount of the energy ray-curable monomer and / or oligomer (B) is 100 parts by mass) and is preferably used in an amount of 0.1 parts by mass or more, particularly 0.5 parts by mass or more with respect to 100 parts by mass. The photopolymerization initiator (C) is energy beam curable copolymer (A) (when energy beam curable monomer and / or oligomer (B) is blended, energy beam curable copolymer ( The total amount of A) and energy ray-curable monomer and / or oligomer (B) is 100 parts by mass) and is preferably used in an amount of 10 parts by mass or less, particularly 6 parts by mass or less.
 エネルギー線硬化性粘着剤においては、上記成分以外にも、適宜他の成分を配合してもよい。他の成分としては、例えば、非エネルギー線硬化性ポリマー成分またはオリゴマー成分(D)、架橋剤(E)等が挙げられる。 In the energy ray-curable pressure-sensitive adhesive, other components may be appropriately blended in addition to the above components. Examples of other components include a non-energy ray curable polymer component or oligomer component (D), and a crosslinking agent (E).
 非エネルギー線硬化性ポリマー成分またはオリゴマー成分(D)としては、例えば、ポリアクリル酸エステル、ポリエステル、ポリウレタン、ポリカーボネート、ポリオレフィン等が挙げられ、重量平均分子量(Mw)が3000~250万のポリマーまたはオリゴマーが好ましい。当該成分(D)をエネルギー線硬化性粘着剤に配合することにより、硬化前における粘着性および剥離性、硬化後の強度、他の層との接着性、保存安定性などを改善し得る。当該成分(D)の配合量は特に限定されず、エネルギー線硬化型共重合体(A)100質量部に対して0質量部超、50質量部以下の範囲で適宜決定される。 Examples of the non-energy ray curable polymer component or oligomer component (D) include polyacrylates, polyesters, polyurethanes, polycarbonates, polyolefins, etc., and polymers or oligomers having a weight average molecular weight (Mw) of 3000 to 2.5 million. Is preferred. By mix | blending the said component (D) with energy-beam curable adhesive, the adhesiveness and peelability before hardening, the intensity | strength after hardening, the adhesiveness with another layer, storage stability, etc. can be improved. The compounding quantity of the said component (D) is not specifically limited, It determines suitably in the range of more than 0 mass part and 50 mass parts or less with respect to 100 mass parts of energy-beam curable copolymers (A).
 架橋剤(E)としては、エネルギー線硬化型共重合体(A)等が有する官能基との反応性を有する多官能性化合物を用いることができる。このような多官能性化合物の例としては、イソシアネート化合物、エポキシ化合物、アミン化合物、メラミン化合物、アジリジン化合物、ヒドラジン化合物、アルデヒド化合物、オキサゾリン化合物、金属アルコキシド化合物、金属キレート化合物、金属塩、アンモニウム塩、反応性フェノール樹脂等を挙げることができる。 As the crosslinking agent (E), a polyfunctional compound having reactivity with the functional group of the energy beam curable copolymer (A) or the like can be used. Examples of such polyfunctional compounds include isocyanate compounds, epoxy compounds, amine compounds, melamine compounds, aziridine compounds, hydrazine compounds, aldehyde compounds, oxazoline compounds, metal alkoxide compounds, metal chelate compounds, metal salts, ammonium salts, A reactive phenol resin etc. can be mentioned.
 架橋剤(E)の配合量は、エネルギー線硬化型共重合体(A)100質量部に対して、0.01質量部以上であることが好ましく、特に0.03質量部以上であることが好ましく、さらには0.04質量部以上であることが好ましい。また、架橋剤(E)の配合量は、エネルギー線硬化型共重合体(A)100質量部に対して、8質量部以下であることが好ましく、特に5質量部以下であることが好ましく、さらには3.5質量部以下であることが好ましい。 The amount of the crosslinking agent (E) is preferably 0.01 parts by mass or more, particularly 0.03 parts by mass or more, with respect to 100 parts by mass of the energy ray curable copolymer (A). More preferably, it is 0.04 parts by mass or more. The amount of the crosslinking agent (E) is preferably 8 parts by mass or less, particularly preferably 5 parts by mass or less, with respect to 100 parts by mass of the energy ray curable copolymer (A). Furthermore, it is preferable that it is 3.5 mass parts or less.
 次に、エネルギー線硬化性粘着剤が、非エネルギー線硬化性ポリマー成分と少なくとも1つ以上のエネルギー線硬化性基を有するモノマーおよび/またはオリゴマーとの混合物を主成分とする場合について、以下説明する。 Next, the case where the energy beam curable pressure-sensitive adhesive is mainly composed of a mixture of a non-energy beam curable polymer component and a monomer and / or oligomer having at least one energy beam curable group will be described below. .
 非エネルギー線硬化性ポリマー成分としては、例えば、前述したアクリル系共重合体(a1)と同様の成分が使用できる。 As the non-energy ray curable polymer component, for example, the same components as the acrylic copolymer (a1) described above can be used.
 少なくとも1つ以上のエネルギー線硬化性基を有するモノマーおよび/またはオリゴマーとしては、前述の成分(B)と同じものが選択できる。非エネルギー線硬化性ポリマー成分と少なくとも1つ以上のエネルギー線硬化性基を有するモノマーおよび/またはオリゴマーとの配合比は、非エネルギー線硬化性ポリマー成分100質量部に対して、少なくとも1つ以上のエネルギー線硬化性基を有するモノマーおよび/またはオリゴマー1質量部以上であるのが好ましく、特に60質量部以上であるのが好ましい。また、当該配合比は、非エネルギー線硬化性ポリマー成分100質量部に対して、少なくとも1つ以上のエネルギー線硬化性基を有するモノマーおよび/またはオリゴマー200質量部以下であるのが好ましく、特に160質量部以下であるのが好ましい。 As the monomer and / or oligomer having at least one energy ray curable group, the same one as the above-mentioned component (B) can be selected. The blending ratio of the non-energy ray curable polymer component and the monomer and / or oligomer having at least one energy ray curable group is at least one or more with respect to 100 parts by mass of the non-energy ray curable polymer component. The amount of the monomer and / or oligomer having an energy ray-curable group is preferably 1 part by mass or more, and particularly preferably 60 parts by mass or more. The blending ratio is preferably not more than 200 parts by mass of monomers and / or oligomers having at least one energy ray-curable group with respect to 100 parts by mass of the non-energy ray-curable polymer component. It is preferably less than or equal to parts by mass.
 この場合においても、上記と同様に、光重合開始剤(C)や架橋剤(E)を適宜配合することができる。 Also in this case, the photopolymerization initiator (C) and the crosslinking agent (E) can be appropriately blended as described above.
 粘着剤層の厚さは、特に限定されず、例えば、3μm以上であることが好ましく、特に5μm以上であることが好ましい。また、当該厚さは、50μm以下であることが好ましく、特に40μm以下であることが好ましい。 The thickness of the pressure-sensitive adhesive layer is not particularly limited, and is preferably, for example, 3 μm or more, and particularly preferably 5 μm or more. The thickness is preferably 50 μm or less, and particularly preferably 40 μm or less.
4.剥離シート
 本実施形態に係る半導体加工用シートは、その粘着面を半導体チップといった被着体に貼付するまでの間、粘着面を保護する目的で、当該面に剥離シートが積層されていてもよい。剥離シートの構成は任意であり、プラスチックフィルムを剥離剤等により剥離処理したものが例示される。プラスチックフィルムの具体例としては、ポリエチレンテレフタレート、ポリブチレンテレフタレート、ポリエチレンナフタレート等のポリエステルフィルム、およびポリプロピレンやポリエチレン等のポリオレフィンフィルムが挙げられる。剥離剤としては、シリコーン系、フッ素系、長鎖アルキル系等を用いることができ、これらの中で、安価で安定した性能が得られるシリコーン系が好ましい。剥離シートの厚さについては特に制限はないが、通常20~250μm程度である。
4). Release sheet The semiconductor processing sheet according to the present embodiment may be laminated with a release sheet for the purpose of protecting the adhesive surface until the adhesive surface is attached to an adherend such as a semiconductor chip. . The configuration of the release sheet is arbitrary, and examples include a release film of a plastic film with a release agent. Specific examples of the plastic film include polyester films such as polyethylene terephthalate, polybutylene terephthalate, and polyethylene naphthalate, and polyolefin films such as polypropylene and polyethylene. As the release agent, silicone-based, fluorine-based, long-chain alkyl-based, and the like can be used, and among these, a silicone-based material that is inexpensive and provides stable performance is preferable. The thickness of the release sheet is not particularly limited, but is usually about 20 to 250 μm.
5.半導体加工用シートの製造方法
 本実施形態に係る半導体加工用シートは、従来の半導体加工用シートと同様に製造することができる。特に、基材と粘着剤層とからなる半導体加工用シートの製造方法としては、前述の粘着性組成物から形成される粘着剤層を基材の一の面に積層できれば、詳細な方法は特に限定されない。一例を挙げれば、粘着剤層を構成する粘着性組成物、および所望によりさらに溶媒または分散媒を含有する塗工液を調製し、基材の一の面上に、ダイコーター、カーテンコーター、スプレーコーター、スリットコーター、ナイフコーター等によりその塗工液を塗布して塗膜を形成し、当該塗膜を乾燥させることにより、粘着剤層を形成することができる。塗工液は、塗布を行うことが可能であればその性状は特に限定されず、粘着剤層を形成するための成分を溶質として含有する場合もあれば、分散質として含有する場合もある。
5). Manufacturing Method of Semiconductor Processing Sheet The semiconductor processing sheet according to this embodiment can be manufactured in the same manner as a conventional semiconductor processing sheet. In particular, as a method for producing a semiconductor processing sheet comprising a substrate and a pressure-sensitive adhesive layer, a detailed method is particularly suitable if a pressure-sensitive adhesive layer formed from the above-mentioned pressure-sensitive adhesive composition can be laminated on one surface of the substrate. It is not limited. For example, a pressure-sensitive adhesive composition constituting the pressure-sensitive adhesive layer and, if desired, a coating liquid further containing a solvent or a dispersion medium are prepared, and a die coater, a curtain coater, and a spray are formed on one surface of the substrate. The pressure-sensitive adhesive layer can be formed by applying the coating solution with a coater, slit coater, knife coater or the like to form a coating film and drying the coating film. The properties of the coating liquid are not particularly limited as long as it can be applied, and may contain a component for forming the pressure-sensitive adhesive layer as a solute or a dispersoid.
 また、半導体加工用シートの製造方法の別の一例としては、前述の剥離シートの剥離面上に塗工液を塗布して塗膜を形成し、これを乾燥させて粘着剤層と剥離シートとからなる積層体を形成し、この積層体の粘着剤層における剥離シート側の面と反対側の面を基材に貼付して、半導体加工用シートと剥離シートとの積層体を得てもよい。この積層体における剥離シートは工程材料として剥離してもよいし、半導体チップ、半導体ウエハ等の被着体に貼付するまでの間、粘着剤層を保護していてもよい。 Moreover, as another example of the manufacturing method of the sheet | seat for semiconductor processing, a coating liquid is apply | coated on the peeling surface of the above-mentioned peeling sheet, a coating film is formed, this is dried, an adhesive layer and a peeling sheet, A laminate of the semiconductor processing sheet and the release sheet may be obtained by forming a laminate made of the above and affixing the surface opposite to the release sheet side of the adhesive layer of the laminate to the substrate. . The release sheet in this laminate may be peeled off as a process material, or the adhesive layer may be protected until being attached to an adherend such as a semiconductor chip or a semiconductor wafer.
 塗工液が架橋剤を含有する場合には、上記の乾燥の条件(温度、時間など)を変えることにより、または加熱処理を別途設けることにより、塗膜内の非エネルギー線硬化性アクリル系粘着剤(N)またはエネルギー線硬化性粘着剤(A)と架橋剤との架橋反応を進行させ、粘着剤層内に所望の存在密度で架橋構造を形成させればよい。この架橋反応を十分に進行させるために、上記の方法などによって基材に粘着剤層を積層させた後、得られた半導体加工用シートを、例えば23℃、相対湿度50%の環境に数日間静置するといった養生を行ってもよい。 When the coating solution contains a cross-linking agent, the non-energy ray-curable acrylic adhesive in the coating film can be changed by changing the drying conditions (temperature, time, etc.) or by separately providing a heat treatment. The crosslinking reaction between the agent (N) or the energy ray-curable pressure-sensitive adhesive (A) and the crosslinking agent may be advanced to form a crosslinked structure at a desired density in the pressure-sensitive adhesive layer. In order to sufficiently proceed with the crosslinking reaction, after the pressure-sensitive adhesive layer is laminated on the base material by the above-described method, the obtained semiconductor processing sheet is placed in an environment of, for example, 23 ° C. and a relative humidity of 50% for several days. Curing such as leaving still may be performed.
6.半導体加工用シートの使用方法
 本実施形態に係る半導体加工用シートは、例えば、半導体加工用シートの片面に積層された複数の半導体チップの間隔を拡げるために使用することができる。
6). Method for Using Semiconductor Processing Sheet The semiconductor processing sheet according to the present embodiment can be used, for example, to increase the interval between a plurality of semiconductor chips stacked on one side of the semiconductor processing sheet.
 特に、半導体加工用シートの片面に積層された複数の半導体チップにおける隣り合う半導体チップの相互の間隔を、200μm以上拡げるために使用することが好ましい。なお、当該間隔の上限は特に制限されないものの、例えば6000μmであってもよい。 In particular, it is preferably used to increase the interval between adjacent semiconductor chips in a plurality of semiconductor chips stacked on one side of the semiconductor processing sheet by 200 μm or more. The upper limit of the interval is not particularly limited, but may be 6000 μm, for example.
 また、本実施形態に係る半導体加工用シートは、少なくとも2軸延伸によって、半導体加工用シートの片面に積層された複数の半導体チップの間隔を拡げる場合にも使用することができる。この場合、半導体加工用シートは、例えば、互いに直交するX軸およびY軸における+X軸方向、-X軸方向、+Y軸方向および-Y軸方向の4方向に張力を付与して引き延ばされ、より具体的には、基材におけるMD方向およびCD方向にそれぞれ引き延ばされる。 Further, the semiconductor processing sheet according to the present embodiment can also be used when the interval between a plurality of semiconductor chips stacked on one side of the semiconductor processing sheet is expanded by at least biaxial stretching. In this case, for example, the semiconductor processing sheet is stretched by applying tension in four directions of the + X axis direction, the −X axis direction, the + Y axis direction, and the −Y axis direction on the X axis and the Y axis orthogonal to each other. More specifically, the film is stretched in the MD direction and the CD direction, respectively.
 上記のような2軸延伸は、例えば、X軸方向およびY軸方向に張力を付与する離間装置を使用して行うことができる。ここで、X軸およびY軸は直交するものとし、X軸に平行な方向のうちの1つを+X軸方向、当該+X軸方向に反対の方向を-X軸方向、Y軸に平行な方向のうちの1つを+Y軸方向、当該+Y軸方向に反対の方向を-Y軸方向とする。 The biaxial stretching as described above can be performed using, for example, a separation device that applies tension in the X-axis direction and the Y-axis direction. Here, the X axis and the Y axis are orthogonal to each other, and one of the directions parallel to the X axis is the + X axis direction, the opposite direction to the + X axis direction is the −X axis direction, and the direction parallel to the Y axis. One of them is defined as a + Y axis direction, and a direction opposite to the + Y axis direction is defined as a −Y axis direction.
 上記離間装置は、半導体加工用シートに対して、+X軸方向、-X軸方向、+Y軸方向および-Y軸方向の4方向に張力を付与し、この4方向のそれぞれについて、複数の保持手段と、それらに対応する複数の張力付与手段とを備えることが好ましい。各方向における、保持手段および張力付与手段の数は、半導体加工用シートの大きさにもよるものの、例えば、3個以上、10個以下程度であってもよい。 The spacing device applies tension to the semiconductor processing sheet in four directions of + X axis direction, -X axis direction, + Y axis direction, and -Y axis direction, and a plurality of holding means in each of these four directions And a plurality of tension applying means corresponding to them. The number of holding means and tension applying means in each direction may be, for example, about 3 or more and 10 or less, depending on the size of the semiconductor processing sheet.
 ここで、例えば+X軸方向に張力を付与するために備えられた、複数の保持手段と複数の張力付与手段とを含む群において、それぞれの保持手段は、半導体加工用シートを保持する保持部材を備え、それぞれの張力付与手段は、当該張力付与手段に対応した保持部材を+X軸方向に移動させて半導体加工用シートに張力を付与することが好ましい。そして、複数の張力付与手段は、それぞれ独立に、保持手段を+X軸方向に移動させるように設けられていることが好ましい。また、-X軸方向、+Y軸方向および-Y軸方向にそれぞれ張力を付与するために備えられた、複数の保持手段と複数の張力付与手段とを含む3つの群においても、同様の構成を有することが好ましい。これにより、上記離間装置は、各方向に直交する方向の領域ごとに、半導体加工用シートに対して異なる大きさの張力を付与することができる。 Here, for example, in a group including a plurality of holding means and a plurality of tension applying means provided for applying tension in the + X-axis direction, each holding means includes a holding member that holds the semiconductor processing sheet. It is preferable that each tension applying means applies a tension to the semiconductor processing sheet by moving the holding member corresponding to the tension applying means in the + X-axis direction. And it is preferable that the several tension | tensile_strength provision means is provided so that a holding | maintenance means may be moved to + X-axis direction each independently. The same configuration is also applied to three groups including a plurality of holding means and a plurality of tension applying means provided for applying tension in the −X axis direction, the + Y axis direction, and the −Y axis direction, respectively. It is preferable to have. Thereby, the said separation apparatus can give tension | tensile_strength of a magnitude | size different with respect to the sheet | seat for semiconductor processing for every area | region of the direction orthogonal to each direction.
 一般に、4つの保持部材を用いて半導体加工用シートを、+X軸方向、-X軸方向、+Y軸方向および-Y軸方向の4方向からそれぞれ保持し、当該4方向に延伸する場合、半導体加工用シートにはこれら4方向に加え、これらの合成方向(例えば、+X軸方向と+Y軸方向との合成方向、+Y軸方向と-X軸方向との合成方向、-X軸方向と-Y軸方向との合成方向および-Y軸方向と+X軸方向との合成方向)にも張力が付与される。その結果、半導体加工用シートの内側における半導体チップの間隔と外側における半導体チップとの間隔に違いが生じることがある。 In general, when a semiconductor processing sheet is held from four directions of + X axis direction, -X axis direction, + Y axis direction, and -Y axis direction using four holding members and stretched in the four directions, semiconductor processing In addition to these four directions, the composite sheet includes these composite directions (for example, the composite direction of the + X axis direction and the + Y axis direction, the composite direction of the + Y axis direction and the −X axis direction, the −X axis direction and the −Y axis) The tension is also applied to the composite direction with the direction and the composite direction of the −Y axis direction and the + X axis direction). As a result, there may be a difference in the distance between the semiconductor chips inside the semiconductor processing sheet and the distance between the semiconductor chips outside.
 しかしながら、上述した離間装置では、+X軸方向、-X軸方向、+Y軸方向および-Y軸方向のそれぞれの方向において、複数の張力付与手段がそれぞれ独立に半導体加工用シートに張力を付与することができるため、上述したような半導体加工用シートの内側と外側との間隔の違いが解消されるように、半導体加工用シートを延伸することができる。その結果、半導体チップの間隔を正確に調整することができる。 However, in the above-described separation device, the plurality of tension applying means independently apply tension to the semiconductor processing sheet in each of the + X axis direction, the −X axis direction, the + Y axis direction, and the −Y axis direction. Therefore, the semiconductor processing sheet can be stretched so that the difference between the inner side and the outer side of the semiconductor processing sheet as described above is eliminated. As a result, the interval between the semiconductor chips can be adjusted accurately.
 上記離間装置は、半導体チップの相互間隔を測定する測定手段をさらに備えることが好ましい。ここにおいて、上記張力付与手段は、測定手段の測定結果を基に、複数の保持部材を個別に移動可能に設けられていることが好ましい。これにより、上記測定手段による半導体チップの間隔の測定結果に基づいて、当該間隔をさらに調整することが可能となる結果、半導体チップの間隔をより正確に調整することが可能となる。 It is preferable that the spacing device further includes a measuring unit that measures the mutual spacing of the semiconductor chips. Here, it is preferable that the tension applying means is provided so that a plurality of holding members can be individually moved based on the measurement result of the measuring means. Thereby, based on the measurement result of the interval between the semiconductor chips by the measuring means, the interval can be further adjusted, and as a result, the interval between the semiconductor chips can be adjusted more accurately.
 なお、上記離間装置において、保持手段としては、メカチャック、チャックシリンダ等のチャック手段や、減圧ポンプ、真空エジェクタ等の減圧手段であってもよく、または、接着剤、磁力等で半導体加工用シートを支持する構成であってもよい。また、チャック手段における保持部材としては、例えば、半導体加工用シートを下から支持する下支持部材と、下支持部材に支持された駆動機器と、駆動機器の出力軸に支持され、駆動機器が駆動することで半導体加工用シートを上から押さえつけることが可能な上支持部材とを備えた構成を有するものを使用することができる。当該駆動機器としては、例えば、回動モータ、直動モータ、リニアモータ、単軸ロボット、多関節ロボット等の電動機器、エアシリンダ、油圧シリンダ、ロッドレスシリンダおよびロータリシリンダ等のアクチュエータ等が挙げられる。 In the spacing device, the holding means may be a chuck means such as a mechanical chuck or a chuck cylinder, a pressure reducing means such as a vacuum pump or a vacuum ejector, or a semiconductor processing sheet by an adhesive, magnetic force, or the like. The structure which supports may be sufficient. Further, as the holding member in the chuck means, for example, a lower support member that supports the semiconductor processing sheet from below, a drive device supported by the lower support member, and an output shaft of the drive device, the drive device is driven. By doing so, what has the structure provided with the upper support member which can press down the sheet | seat for semiconductor processing from the top can be used. Examples of the drive device include electric devices such as a rotation motor, a linear motion motor, a linear motor, a single-axis robot, and an articulated robot, and actuators such as an air cylinder, a hydraulic cylinder, a rodless cylinder, and a rotary cylinder. .
 また、上記離間装置において、張力付与手段は、駆動機器を備え、当該駆動機器により保持部材を移動させるものであってよい。当該駆動機器としては、上述したものを使用することができる。例えば、張力付与手段は、駆動機器としての直動モータと、直動モータと保持部材との間に介在する出力軸とを備え、駆動した直動モータが出力軸を介して保持部材を移動させる構成であってよい。 Further, in the above separating apparatus, the tension applying means may include a driving device, and the holding member may be moved by the driving device. As the driving device, those described above can be used. For example, the tension applying means includes a linear motion motor as a drive device, and an output shaft interposed between the linear motion motor and the holding member, and the driven linear motion motor moves the holding member via the output shaft. It may be a configuration.
 本実施形態に係る半導体加工用シートを用いて半導体チップの間隔を拡げる場合、半導体チップ同士が接触した状態、または半導体チップの間隔が殆ど拡げられていない状態からその間隔を拡げてもよく、あるいは、半導体チップ同士の間隔が既に所定の間隔まで拡げられた状態から、さらにその間隔を拡げてもよい。 When the interval between the semiconductor chips is increased using the semiconductor processing sheet according to the present embodiment, the interval may be increased from a state where the semiconductor chips are in contact with each other, or a state where the interval between the semiconductor chips is hardly increased, or The distance between the semiconductor chips may be further increased from the state in which the distance between the semiconductor chips is already increased to a predetermined distance.
 半導体チップ同士が接触した状態、または半導体チップの間隔が殆ど拡げられていない状態からその間隔を拡げる場合としては、例えば、ダイシングシート上において半導体ウエハを分割することで複数の半導体チップを得た後、当該ダイシングシートから本実施形態に係る半導体加工用シートに複数の半導体チップを転写し、続いて、当該半導体チップの間隔を拡げることができる。あるいは、本実施形態に係る半導体加工用シート上において半導体ウエハを分割して複数の半導体チップを得た後、当該半導体チップの間隔を拡げることもできる。 For example, after obtaining a plurality of semiconductor chips by dividing a semiconductor wafer on a dicing sheet, the semiconductor chips are in contact with each other or the gap between the semiconductor chips is not widened. A plurality of semiconductor chips can be transferred from the dicing sheet to the semiconductor processing sheet according to the present embodiment, and then the interval between the semiconductor chips can be increased. Alternatively, after the semiconductor wafer is divided on the semiconductor processing sheet according to the present embodiment to obtain a plurality of semiconductor chips, the interval between the semiconductor chips can be increased.
 半導体チップ同士の間隔が既に所定の間隔まで拡げられた状態から、さらにその間隔を拡げる場合としては、その他の半導体加工用シート、好ましくは本実施形態に係る半導体加工用シートを用いて半導体チップ同士の間隔を所定の間隔まで拡げた後、当該シートから本実施形態に係る半導体加工用シートに半導体チップを転写し、続いて、本実施形態に係る半導体加工用シートを延伸することで、半導体チップの間隔をさらに拡げることができる。なお、このような半導体チップの転写と半導体加工用シートの延伸は、半導体チップの間隔が所望の距離となるまで複数回繰り返してもよい。 In the case where the distance between the semiconductor chips is already expanded to a predetermined distance, the semiconductor chip can be further expanded by using another semiconductor processing sheet, preferably the semiconductor processing sheet according to the present embodiment. The semiconductor chip is transferred from the sheet to the semiconductor processing sheet according to the present embodiment, and then the semiconductor processing sheet according to the present embodiment is stretched to extend the semiconductor chip. Can be further widened. Such transfer of the semiconductor chip and stretching of the semiconductor processing sheet may be repeated a plurality of times until the distance between the semiconductor chips reaches a desired distance.
 さらに、本実施形態に係る半導体加工用シートは、半導体チップの間隔を比較的大きく離間させることが求められる用途への使用が好ましく、このような用途の例としては、ファンアウト型の半導体ウエハレベルパッケージ(FO-WLP)の製造方法が好ましく挙げられる。このようなFO-WLPの製造方法の例として、以下に説明する第1態様および第2態様が挙げられる。 Furthermore, the semiconductor processing sheet according to the present embodiment is preferably used for applications that require a relatively large gap between the semiconductor chips. Examples of such applications include fan-out type semiconductor wafer levels. A method for producing a package (FO-WLP) is preferred. Examples of such a method for producing FO-WLP include a first aspect and a second aspect described below.
(1)第1態様
 以下、本実施形態に係る半導体加工用シートを使用したFO-WLPの製造方法の第1態様を説明する。なお、この第1態様において、本実施形態に係る半導体加工用シートは、後述する第二の粘着シート20として使用される。
(1) First Aspect Hereinafter, a first aspect of a method for manufacturing FO-WLP using a semiconductor processing sheet according to the present embodiment will be described. In addition, in this 1st aspect, the sheet | seat for semiconductor processing which concerns on this embodiment is used as the 2nd adhesive sheet 20 mentioned later.
 図1(A)には、第一の粘着シート10に貼着された半導体ウエハWが示されている。半導体ウエハWは、回路面W1を有し、回路面W1には、回路W2が形成されている。第一の粘着シート10は、半導体ウエハWの回路面W1とは反対側の裏面W3に貼着されている。第一の粘着シート10は、第一の基材フィルム11と、第一の粘着剤層12とを有する。第一の粘着剤層12は、第一の基材フィルム11に積層されている。 FIG. 1A shows a semiconductor wafer W adhered to the first adhesive sheet 10. The semiconductor wafer W has a circuit surface W1, and a circuit W2 is formed on the circuit surface W1. The first adhesive sheet 10 is attached to the back surface W3 of the semiconductor wafer W opposite to the circuit surface W1. The first pressure-sensitive adhesive sheet 10 has a first base film 11 and a first pressure-sensitive adhesive layer 12. The first pressure-sensitive adhesive layer 12 is laminated on the first base film 11.
[ダイシング工程]
 図1(B)には、第一の粘着シート10に保持された複数の半導体チップCPが示されている。
[Dicing process]
FIG. 1B shows a plurality of semiconductor chips CP held on the first pressure-sensitive adhesive sheet 10.
 第一の粘着シート10に保持された半導体ウエハWは、ダイシングにより個片化され、複数の半導体チップCPが形成される。ダイシングには、ダイシングソーなどの切断手段が用いられる。ダイシングの際の切断深さは、半導体ウエハWの厚みと、第一の粘着剤層12との合計、並びにダイシングソーの磨耗分を加味した深さに設定する。ダイシングによって、第一の粘着剤層12も半導体チップCPと同じサイズに切断される。さらに、ダイシングによって第一の基材フィルム11にも切込みが形成される場合がある。 The semiconductor wafer W held on the first adhesive sheet 10 is divided into pieces by dicing, and a plurality of semiconductor chips CP are formed. A cutting means such as a dicing saw is used for dicing. The cutting depth at the time of dicing is set to a depth that takes into account the total thickness of the semiconductor wafer W, the first pressure-sensitive adhesive layer 12, and the wear of the dicing saw. The first pressure-sensitive adhesive layer 12 is also cut into the same size as the semiconductor chip CP by dicing. Furthermore, a cut may be formed in the first base film 11 by dicing.
 なお、ダイシングは、上述したダイシングソーなどの切断手段を用いる代わりに、半導体ウエハWに対してレーザ光を照射して行ってもよい。例えば、レーザ光の照射により、半導体ウエハWを完全に分断し、複数の半導体チップCPに個片化してもよい。あるいは、レーザ光の照射により半導体ウエハW内部に改質層を形成した後、後述する第一のエキスパンド工程において、第一の粘着シート10を引き延ばすことで、半導体ウエハWを改質層の位置で破断して、半導体チップCPに個片化してもよい(ステルスダイシング)。ステルスダイシングの場合、レーザ光の照射は、例えば、赤外域のレーザ光を、半導体ウエハWの内部に設定された焦点に集束されるように照射する。また、これらの方法においては、レーザ光の照射は、半導体ウエハWのいずれの側から行ってもよい。 Note that dicing may be performed by irradiating the semiconductor wafer W with laser light instead of using the above-described cutting means such as a dicing saw. For example, the semiconductor wafer W may be completely divided by laser light irradiation and separated into a plurality of semiconductor chips CP. Alternatively, after the modified layer is formed inside the semiconductor wafer W by laser light irradiation, the first adhesive sheet 10 is stretched in the first expanding step described later, so that the semiconductor wafer W is positioned at the modified layer position. It may be broken and separated into semiconductor chips CP (stealth dicing). In the case of stealth dicing, for example, laser light irradiation is performed such that infrared laser light is focused on a focal point set inside the semiconductor wafer W. In these methods, laser light irradiation may be performed from any side of the semiconductor wafer W.
[第一のエキスパンド工程]
 図1(C)には、複数の半導体チップCPを保持する第一の粘着シート10を引き延ばす工程(以下「第一のエキスパンド工程」という場合がある。)を説明する図が示されている。
[First expanding process]
FIG. 1C shows a diagram for explaining a process of extending the first pressure-sensitive adhesive sheet 10 that holds a plurality of semiconductor chips CP (hereinafter also referred to as “first expanding process”).
 ダイシングにより複数の半導体チップCPに個片化した後、第一の粘着シート10を引き延ばして、複数の半導体チップCP間の間隔を拡げる。また、ステルスダイシングを行う場合には、第一の粘着シート10を引き延ばすことで、半導体ウエハWを改質層の位置で破断し、複数の半導体チップCPに個片化するとともに、複数の半導体チップCP間の間隔を拡げる。第一のエキスパンド工程において第一の粘着シート10を引き延ばす方法は、特に限定されない。第一の粘着シート10を引き延ばす方法としては、例えば、環状または円状のエキスパンダを押し当てて第一の粘着シート10を引き延ばす方法や、把持部材などを用いて第二の粘着シートの外周部を掴んで引き延ばす方法などが挙げられる。 After dicing into a plurality of semiconductor chips CP by dicing, the first adhesive sheet 10 is stretched to widen the interval between the plurality of semiconductor chips CP. Further, when stealth dicing is performed, the first adhesive sheet 10 is stretched to break the semiconductor wafer W at the position of the modified layer and separate into a plurality of semiconductor chips CP. Increase the spacing between CPs. The method for extending the first pressure-sensitive adhesive sheet 10 in the first expanding step is not particularly limited. Examples of the method of stretching the first pressure-sensitive adhesive sheet 10 include a method of stretching the first pressure-sensitive adhesive sheet 10 by pressing an annular or circular expander, and an outer peripheral portion of the second pressure-sensitive adhesive sheet using a gripping member or the like. For example, a method of grabbing and stretching.
 第一の粘着シート10は、上述したダイシング工程に適すとともに、第一のエキスパンド工程にも適した引張弾性率を有することが好ましい。この観点から、第一の粘着シート10は、後述する第二の粘着シート20よりも引張弾性率が大きいことが好ましい。これにより、第一の粘着シート10は、ダイシング時における性能を損なうことなく、所定のエキスパンド性を発揮することができ、第二の粘着シート20は、さらに優れたエキスパンド性を発揮することができる。 The first pressure-sensitive adhesive sheet 10 preferably has a tensile elastic modulus suitable for the dicing process described above and also suitable for the first expanding process. From this viewpoint, the first pressure-sensitive adhesive sheet 10 preferably has a higher tensile elastic modulus than the second pressure-sensitive adhesive sheet 20 described later. Thereby, the 1st adhesive sheet 10 can exhibit predetermined expandability, without impairing the performance at the time of dicing, and the 2nd adhesive sheet 20 can exhibit the further excellent expandability. .
 なお、図1(C)に示されているように、半導体チップCP間の距離をD1とする。距離D1としては、例えば、15μm以上110μm以下とすることが好ましい。 Note that, as shown in FIG. 1C, the distance between the semiconductor chips CP is D1. The distance D1 is preferably 15 μm or more and 110 μm or less, for example.
[転写工程]
 図2(A)には、第一のエキスパンド工程の後に、複数の半導体チップCPを第二の粘着シート20に転写する工程(以下「転写工程」という場合がある。)を説明する図が示されている。第一の粘着シート10を引き延ばして複数の半導体チップCP間の距離D1を拡げた後、半導体チップCPの回路面W1に第二の粘着シート20を貼着する。ここで、当該第二の粘着シート20として、本実施形態に係る半導体加工用シートが使用される。
[Transfer process]
FIG. 2A is a diagram for explaining a step of transferring a plurality of semiconductor chips CP to the second pressure-sensitive adhesive sheet 20 (hereinafter sometimes referred to as “transfer step”) after the first expanding step. Has been. After extending the first adhesive sheet 10 to increase the distance D1 between the plurality of semiconductor chips CP, the second adhesive sheet 20 is adhered to the circuit surface W1 of the semiconductor chip CP. Here, the semiconductor processing sheet according to the present embodiment is used as the second pressure-sensitive adhesive sheet 20.
 第二の粘着シート20は、第二の基材フィルム21と、第二の粘着剤層22とを有する。第二の粘着シート20は、回路面W1を第二の粘着剤層22で覆うように貼着されることが好ましい。 The second pressure-sensitive adhesive sheet 20 has a second base film 21 and a second pressure-sensitive adhesive layer 22. It is preferable that the 2nd adhesive sheet 20 is stuck so that the circuit surface W1 may be covered with the 2nd adhesive layer 22. FIG.
 第二の粘着剤層22の粘着力は、第一の粘着剤層12の粘着力よりも大きいことが好ましい。第二の粘着剤層22の粘着力の方が大きければ、複数の半導体チップCPを第二の粘着シート20に転写した後に第一の粘着シート10を剥離し易くなる。 It is preferable that the adhesive force of the second adhesive layer 22 is larger than the adhesive force of the first adhesive layer 12. If the adhesive force of the second pressure-sensitive adhesive layer 22 is greater, the first pressure-sensitive adhesive sheet 10 can be easily peeled after the plurality of semiconductor chips CP are transferred to the second pressure-sensitive adhesive sheet 20.
 第二の粘着シート20は、複数の半導体チップCPとともに、第二のリングフレームに貼着されていてもよい。この場合、第二の粘着シート20の第二の粘着剤層22の上に、第二のリングフレームを載置し、これを軽く押圧し、固定する。その後、第二のリングフレームの環形状の内側にて露出する第二の粘着剤層22を半導体チップCPの回路面W1に押し当てて、第二の粘着シート20に複数の半導体チップCPを固定する。 The second adhesive sheet 20 may be adhered to the second ring frame together with the plurality of semiconductor chips CP. In this case, the second ring frame is placed on the second pressure-sensitive adhesive layer 22 of the second pressure-sensitive adhesive sheet 20, and this is lightly pressed and fixed. Thereafter, the second pressure-sensitive adhesive layer 22 exposed inside the ring shape of the second ring frame is pressed against the circuit surface W1 of the semiconductor chip CP to fix the plurality of semiconductor chips CP to the second pressure-sensitive adhesive sheet 20. To do.
 第二の粘着シート20を貼着した後、第一の粘着シート10を剥離すると、複数の半導体チップCPの裏面W3が露出する。第一の粘着シート10を剥離した後も、第一のエキスパンド工程において拡張させた複数の半導体チップCP間の距離D1が維持されていることが好ましい。 When the first pressure-sensitive adhesive sheet 10 is peeled after the second pressure-sensitive adhesive sheet 20 is adhered, the back surfaces W3 of the plurality of semiconductor chips CP are exposed. Even after the first pressure-sensitive adhesive sheet 10 is peeled, it is preferable that the distance D1 between the plurality of semiconductor chips CP expanded in the first expanding step is maintained.
[第二のエキスパンド工程]
 図2(B)には、複数の半導体チップCPを保持する第二の粘着シート20を引き延ばす工程(以下「第二のエキスパンド工程」という場合がある。)を説明する図が示されている。
[Second expanding process]
FIG. 2B shows a diagram for explaining a process of extending the second pressure-sensitive adhesive sheet 20 that holds a plurality of semiconductor chips CP (hereinafter also referred to as “second expanding process”).
 第二のエキスパンド工程では、複数の半導体チップCP間の間隔をさらに拡げる。第二のエキスパンド工程において第二の粘着シート20を引き延ばす方法は、特に限定されない。第二の粘着シート20を引き延ばす方法としては、例えば、環状または円状のエキスパンダを押し当てて第二の粘着シート20を引き延ばす方法や、把持部材などを用いて第二の粘着シートの外周部を掴んで引き延ばす方法などが挙げられる。後者の方法としては、例えば、前述した離間装置等を使用して2軸延伸する方法が挙げられる。これらの中でも、半導体チップCP間の間隔をより大きく拡げることが可能となるという観点から、2軸延伸する方法が好ましい。 In the second expanding step, the interval between the plurality of semiconductor chips CP is further expanded. The method of extending the second adhesive sheet 20 in the second expanding step is not particularly limited. Examples of the method for stretching the second pressure-sensitive adhesive sheet 20 include a method of stretching the second pressure-sensitive adhesive sheet 20 by pressing an annular or circular expander, and an outer peripheral portion of the second pressure-sensitive adhesive sheet using a gripping member or the like. For example, a method of grabbing and stretching. As the latter method, for example, a biaxial stretching method using the above-described separation device or the like can be mentioned. Among these, the method of biaxial stretching is preferable from the viewpoint that the interval between the semiconductor chips CP can be greatly increased.
 なお、図2(B)に示されているように、第二のエキスパンド工程後の半導体チップCP間の間隔をD2とする。距離D2は、距離D1よりも大きい。距離D2としては、例えば、200μm以上、6000μm以下とすることが好ましい。 Note that, as shown in FIG. 2B, the interval between the semiconductor chips CP after the second expanding step is D2. The distance D2 is larger than the distance D1. For example, the distance D2 is preferably 200 μm or more and 6000 μm or less.
[封止工程]
 図2(C)には、封止部材60を用いて複数の半導体チップCPを封止する工程(以下「封止工程」という場合がある。)を説明する図が示されている。
[Sealing process]
FIG. 2C shows a diagram illustrating a process of sealing a plurality of semiconductor chips CP using the sealing member 60 (hereinafter also referred to as “sealing process”).
 封止工程は、第二のエキスパンド工程の後に実施される。回路面W1を残して複数の半導体チップCPを封止部材60によって覆うことにより封止体3が形成される。複数の半導体チップCPの間にも封止部材60が充填されている。ここで、第二の粘着シート20により回路面W1および回路W2が覆われているので、封止部材60で回路面W1が覆われることを防止できる。 The sealing process is performed after the second expanding process. The sealing body 3 is formed by covering the plurality of semiconductor chips CP with the sealing member 60 while leaving the circuit surface W1. The sealing member 60 is also filled between the plurality of semiconductor chips CP. Here, since the circuit surface W1 and the circuit W2 are covered with the second adhesive sheet 20, it is possible to prevent the circuit surface W1 from being covered with the sealing member 60.
 封止工程により、所定距離ずつ離間した複数の半導体チップCPが封止部材60に埋め込まれた封止体3が得られる。封止工程においては、複数の半導体チップCPは、距離D2が維持された状態で、封止部材60により覆われることが好ましい。 By the sealing step, the sealing body 3 in which a plurality of semiconductor chips CP separated by a predetermined distance are embedded in the sealing member 60 is obtained. In the sealing step, the plurality of semiconductor chips CP are preferably covered with the sealing member 60 while the distance D2 is maintained.
 封止工程の後、第二の粘着シート20が剥離されると、半導体チップCPの回路面W1および封止体3の第二の粘着シート20と接触していた面3Aが露出する。 After the sealing step, when the second pressure-sensitive adhesive sheet 20 is peeled off, the surface 3A that has been in contact with the circuit surface W1 of the semiconductor chip CP and the second pressure-sensitive adhesive sheet 20 of the sealing body 3 is exposed.
[再配線層形成工程、および外部端子電極との接続工程]
 図3(A)には、第二の粘着シート20を剥離した後の封止体3の断面図が示されている。この封止体3に対して、再配線層を形成する再配線層形成工程と、形成された再配線層に対して外部端子電極を接続する工程とが順に行われる。なお、図3(A)には、図2(C)中に示される回路W2をより詳細に示したものとして、内部端子電極W4が示されている。
[Rewiring layer forming step and connecting step with external terminal electrode]
FIG. 3A shows a cross-sectional view of the sealing body 3 after the second pressure-sensitive adhesive sheet 20 is peeled off. A rewiring layer forming step for forming a rewiring layer and a step for connecting an external terminal electrode to the formed rewiring layer are sequentially performed on the sealing body 3. In FIG. 3A, the internal terminal electrode W4 is shown as the circuit W2 shown in FIG. 2C in more detail.
 再配線層形成工程および外部端子電極との接続工程によって、図3(B)に示されるように、内部端子電極W4に接続された再配線層5と、再配線層5に接続された外部端子電極6とが形成される。具体的には、次のように形成される。まず、半導体チップCPの回路面W1および封止体3の面3Aに第一の絶縁層4Aを形成する。続いて、再配線層5を、内部端子電極W4と電気的に接続するように形成する。さらに、再配線層5を覆う第二の絶縁層4Bを形成する。このとき、再配線層5は、外部電極パッド5Aを残して第二の絶縁層4Bにより覆われる。最後に、外部電極パッド5Aに、はんだボール等の外部端子電極6を載置し、はんだ接合などにより、外部端子電極6と外部電極パッド5Aとを電気的に接続する。 The rewiring layer 5 connected to the internal terminal electrode W4 and the external terminal connected to the rewiring layer 5 as shown in FIG. 3B by the rewiring layer forming step and the connecting step with the external terminal electrode. An electrode 6 is formed. Specifically, it is formed as follows. First, the first insulating layer 4A is formed on the circuit surface W1 of the semiconductor chip CP and the surface 3A of the sealing body 3. Subsequently, the rewiring layer 5 is formed so as to be electrically connected to the internal terminal electrode W4. Further, a second insulating layer 4B that covers the rewiring layer 5 is formed. At this time, the rewiring layer 5 is covered with the second insulating layer 4B leaving the external electrode pad 5A. Finally, the external terminal electrode 6 such as a solder ball is placed on the external electrode pad 5A, and the external terminal electrode 6 and the external electrode pad 5A are electrically connected by solder bonding or the like.
[第二のダイシング工程]
 図3(C)には、外部端子電極6が接続された封止体3を個片化させる工程(以下「第二のダイシング工程」という場合がある。)を説明する断面図が示されている。この第二のダイシング工程では、封止体3を半導体チップCP単位で個片化する。封止体3を個片化させる方法は、特に限定されない。例えば、前述の半導体ウエハWをダイシングした方法と同様の方法を採用して、封止体3を個片化することができる。封止体3を個片化させる工程は、封止体3をダイシングシート等の粘着シートに貼着させて実施してもよい。
[Second dicing process]
FIG. 3C shows a cross-sectional view for explaining a process of separating the sealing body 3 to which the external terminal electrode 6 is connected (hereinafter also referred to as “second dicing process”). Yes. In the second dicing process, the sealing body 3 is separated into individual semiconductor chips CP. The method for dividing the sealing body 3 into individual pieces is not particularly limited. For example, the sealing body 3 can be separated into pieces by adopting a method similar to the method of dicing the semiconductor wafer W described above. The step of dividing the sealing body 3 into pieces may be performed by sticking the sealing body 3 to an adhesive sheet such as a dicing sheet.
 封止体3を個片化することで、半導体チップCP単位の半導体パッケージ1が製造される。上述のように半導体チップCPの領域外にファンアウトさせた外部電極パッド5Aに外部端子電極6を接続させた半導体パッケージ1は、ファンアウト型のウエハレベルパッケージ(FO-WLP)として製造される。 The semiconductor package 1 of the semiconductor chip CP unit is manufactured by separating the sealing body 3 into pieces. As described above, the semiconductor package 1 in which the external terminal electrode 6 is connected to the external electrode pad 5A fanned out outside the region of the semiconductor chip CP is manufactured as a fan-out type wafer level package (FO-WLP).
[変形例]
 上述した第1態様に係るFO-WLPの製造方法は、一部の工程を変更したり、一部の工程を省略してもよい。
[Modification]
In the FO-WLP manufacturing method according to the first aspect described above, some processes may be changed or some processes may be omitted.
(2)第2態様
 以下、本実施形態に係る半導体加工用シートを使用したFO-WLPの製造方法の第2態様を説明する。なお、この第2態様においても、本実施形態に係る半導体加工用シートは、後述する第二の粘着シート20として使用される。
(2) Second Aspect Hereinafter, a second aspect of the FO-WLP manufacturing method using the semiconductor processing sheet according to the present embodiment will be described. Also in this second aspect, the semiconductor processing sheet according to the present embodiment is used as a second adhesive sheet 20 described later.
 図4(A)には、第三の粘着シートとしての保護シート30に貼着された半導体ウエハWが示されている。半導体ウエハWは、第一の面としての回路面W1を有し、回路面W1には、回路W2が形成されている。保護シート30は、半導体ウエハWの回路面W1に貼着されている。保護シート30は、回路面W1および回路W2を保護する。 FIG. 4A shows a semiconductor wafer W attached to a protective sheet 30 as a third adhesive sheet. The semiconductor wafer W has a circuit surface W1 as a first surface, and a circuit W2 is formed on the circuit surface W1. The protective sheet 30 is attached to the circuit surface W1 of the semiconductor wafer W. The protection sheet 30 protects the circuit surface W1 and the circuit W2.
 保護シート30は、第三の基材フィルム31と、第三の粘着剤層32とを有する。第三の粘着剤層32は、第三の基材フィルム31に積層されている。 The protective sheet 30 has a third base film 31 and a third pressure-sensitive adhesive layer 32. The third pressure-sensitive adhesive layer 32 is laminated on the third base film 31.
[溝形成工程]
 図4(B)には、半導体ウエハWの回路面W1側から所定深さの溝を形成する工程(以下「溝形成工程」という場合がある。)を説明する図が示されている。
[Groove formation process]
FIG. 4B shows a diagram for explaining a step of forming a groove having a predetermined depth from the circuit surface W1 side of the semiconductor wafer W (hereinafter also referred to as “groove forming step”).
 溝形成工程において、保護シート30側からダイシング装置のダイシングブレードなどを用いて半導体ウエハWに切込みを入れる。その際、保護シート30を完全に切断し、かつ、半導体ウエハWの回路面W1から、半導体ウエハWの厚さよりも浅い深さの切込みを入れて、溝W5を形成する。溝W5は、半導体ウエハWの回路面W1に形成された複数の回路W2を区画するように形成される。溝W5の深さは、目的とする半導体チップの厚みよりもやや深い程度であれば、特に限定はされない。溝W5の形成時には、半導体ウエハWからの切削屑が発生する。第2態様に係る製造方法では、回路面W1が保護シート30により保護された状態で、溝W5の形成を行っているため、切削屑による回路面W1や回路W2の汚染や破損を防止できる。 In the groove forming step, the semiconductor wafer W is cut from the protective sheet 30 side using a dicing blade of a dicing apparatus. At that time, the protective sheet 30 is completely cut, and a groove W5 is formed by making a cut with a depth shallower than the thickness of the semiconductor wafer W from the circuit surface W1 of the semiconductor wafer W. The groove W5 is formed so as to partition a plurality of circuits W2 formed on the circuit surface W1 of the semiconductor wafer W. The depth of the groove W5 is not particularly limited as long as it is a little deeper than the thickness of the target semiconductor chip. When the groove W5 is formed, cutting waste from the semiconductor wafer W is generated. In the manufacturing method according to the second aspect, since the groove W5 is formed in a state where the circuit surface W1 is protected by the protective sheet 30, it is possible to prevent contamination and breakage of the circuit surface W1 and the circuit W2 due to cutting waste.
[研削工程]
 図4(C)には、溝W5を形成した後、半導体ウエハWの第二の面としての裏面W6を研削する工程(以下「研削工程」という場合がある。)を説明する図が示されている。
[Grinding process]
FIG. 4C shows a diagram for explaining a process of grinding the back surface W6 as the second surface of the semiconductor wafer W (hereinafter sometimes referred to as “grinding process”) after forming the groove W5. ing.
 第2態様に係る製造方法では、研削する前に、保護シート30側に、第一の粘着シート10を貼着する。第一の粘着シート10を貼着した後、グラインダー50を用いて、裏面W6側から半導体ウエハWを研削する。研削により、半導体ウエハWの厚みが薄くなり、最終的に複数の半導体チップCPへ分割される。溝W5の底部が除去されるまで裏面W6側から研削を行い、半導体ウエハWを回路W2ごとに個片化する。その後、必要に応じてさらに裏面研削を行い、所定厚さの半導体チップCPを得ることができる。第2態様に係る製造方法では、第三の面としての裏面W3が露出するまで研削する。 In the manufacturing method according to the second aspect, the first pressure-sensitive adhesive sheet 10 is adhered to the protective sheet 30 side before grinding. After adhering the first adhesive sheet 10, the semiconductor wafer W is ground from the back surface W 6 side using the grinder 50. By grinding, the thickness of the semiconductor wafer W is reduced and finally divided into a plurality of semiconductor chips CP. Grinding is performed from the back surface W6 side until the bottom of the groove W5 is removed, and the semiconductor wafer W is separated into pieces for each circuit W2. Thereafter, back grinding is further performed as necessary to obtain a semiconductor chip CP having a predetermined thickness. In the manufacturing method according to the second aspect, grinding is performed until the back surface W3 as the third surface is exposed.
 図4(D)には、分割された複数の半導体チップCPが保護シート30および第一の粘着シート10に保持された状態が示されている。なお、本明細書においては、上述したように、先に溝W5を設けておき、その後裏面の研削を行うことで、半導体ウエハWを半導体チップCPに分割する方法を、「先ダイシング法」という場合がある。 FIG. 4D shows a state in which a plurality of divided semiconductor chips CP are held by the protective sheet 30 and the first adhesive sheet 10. In the present specification, as described above, the method of dividing the semiconductor wafer W into the semiconductor chips CP by providing the groove W5 in advance and then grinding the back surface is referred to as “front dicing method”. There is a case.
[貼付工程(第二の粘着シート)]
 図5(A)には、研削工程の後、第二の粘着シート20を、複数の半導体チップCPに貼付する工程(以下「貼付工程」という場合がある。)を説明する図が示されている。
[Attaching process (second adhesive sheet)]
FIG. 5A shows a diagram for explaining a step of sticking the second pressure-sensitive adhesive sheet 20 to a plurality of semiconductor chips CP (hereinafter also referred to as “sticking step”) after the grinding step. Yes.
 第二の粘着シート20は、半導体チップCPの裏面W3に貼着される。第二の粘着シート20は、第二の基材フィルム21と、第二の粘着剤層22とを有する。ここで、当該第二の粘着シート20として、本実施形態に係る半導体加工用シートが使用される。 The second adhesive sheet 20 is adhered to the back surface W3 of the semiconductor chip CP. The second pressure-sensitive adhesive sheet 20 has a second base film 21 and a second pressure-sensitive adhesive layer 22. Here, the semiconductor processing sheet according to the present embodiment is used as the second pressure-sensitive adhesive sheet 20.
 第二の粘着剤層22の半導体ウエハWに対する粘着力は、第三の粘着剤層32の半導体ウエハWに対する粘着力よりも大きいことが好ましい。第二の粘着剤層22の粘着力の方が大きければ、第一の粘着シート10および保護シート30を剥離し易くなる。 It is preferable that the adhesive force of the second adhesive layer 22 to the semiconductor wafer W is larger than the adhesive force of the third adhesive layer 32 to the semiconductor wafer W. If the adhesive force of the second pressure-sensitive adhesive layer 22 is greater, the first pressure-sensitive adhesive sheet 10 and the protective sheet 30 can be easily peeled off.
 第二の粘着シート20は、複数の半導体チップCPとともに、リングフレームに貼着されていてもよい。この場合、第二の粘着シート20の第二の粘着剤層22の上に、リングフレームを載置し、これを軽く押圧し、固定する。その後、リングフレームの環形状の内側にて露出する第二の粘着剤層22を半導体チップCPの回路面W1に押し当てて、第二の粘着シート20に複数の半導体チップCPを固定する。 The second adhesive sheet 20 may be attached to the ring frame together with the plurality of semiconductor chips CP. In this case, a ring frame is placed on the second pressure-sensitive adhesive layer 22 of the second pressure-sensitive adhesive sheet 20, and this is lightly pressed and fixed. Thereafter, the second adhesive layer 22 exposed inside the ring shape of the ring frame is pressed against the circuit surface W1 of the semiconductor chip CP to fix the plurality of semiconductor chips CP to the second adhesive sheet 20.
[剥離工程(第一の粘着シート)]
 図5(B)には、第二の粘着シート20を貼付した後に、第一の粘着シート10および保護シート30を剥離する工程(以下「剥離工程」という場合がある。)を説明する図が示されている。
[Peeling process (first adhesive sheet)]
FIG. 5B illustrates a step of peeling the first pressure-sensitive adhesive sheet 10 and the protective sheet 30 (hereinafter sometimes referred to as “peeling step”) after attaching the second pressure-sensitive adhesive sheet 20. It is shown.
 剥離工程おいて、第一の粘着シート10を剥離する際に、切断された保護シート30を同伴して剥離する。保護シート30を剥離すると、複数の半導体チップCPの回路面W1が露出する。ここで、図5(B)に示されているように、先ダイシング法によって分割された半導体チップCP間の距離をD1とする。距離D1としては、例えば、15μm以上、110μm以下とすることが好ましい。 In the peeling step, when the first pressure-sensitive adhesive sheet 10 is peeled off, the cut protective sheet 30 is accompanied and peeled off. When the protective sheet 30 is peeled off, the circuit surfaces W1 of the plurality of semiconductor chips CP are exposed. Here, as shown in FIG. 5B, the distance between the semiconductor chips CP divided by the previous dicing method is D1. For example, the distance D1 is preferably 15 μm or more and 110 μm or less.
[エキスパンド工程]
 図5(C)には、複数の半導体チップCPを保持する第二の粘着シート20を引き延ばす工程(以下「エキスパンド工程」という場合がある。)を説明する図が示されている。
[Expanding process]
FIG. 5C shows a diagram illustrating a process of extending the second pressure-sensitive adhesive sheet 20 that holds a plurality of semiconductor chips CP (hereinafter sometimes referred to as an “expanding process”).
 エキスパンド工程では、複数の半導体チップCP間の間隔をさらに拡げる。エキスパンド工程において第二の粘着シート20を引き延ばす方法は、特に限定されない。第二の粘着シート20を引き延ばす方法としては、例えば、環状または円状のエキスパンダを押し当てて第二の粘着シート20を引き延ばす方法や、把持部材などを用いて第二の粘着シートの外周部を掴んで引き延ばす方法などが挙げられる。後者の方法としては、例えば、前述した離間装置等を使用して2軸延伸する方法が挙げられる。これらの中でも、半導体チップCP間の間隔をより大きく拡げることが可能となるという観点から、2軸延伸する方法が好ましい。 In the expanding process, the interval between the plurality of semiconductor chips CP is further expanded. The method for extending the second pressure-sensitive adhesive sheet 20 in the expanding step is not particularly limited. Examples of the method of stretching the second pressure-sensitive adhesive sheet 20 include a method of stretching the second pressure-sensitive adhesive sheet 20 by pressing an annular or circular expander, and an outer peripheral portion of the second pressure-sensitive adhesive sheet using a gripping member or the like. For example, a method of grabbing and stretching. As the latter method, for example, a biaxial stretching method using the above-described separation device or the like can be mentioned. Among these, the method of biaxial stretching is preferable from the viewpoint that the interval between the semiconductor chips CP can be greatly increased.
 第2態様に係る製造方法では、図5(C)に示されているように、エキスパンド工程後の半導体チップCP間の距離をD2とする。距離D2は、距離D1よりも大きい。距離D2としては、例えば、200μm以上、6000μm以下とすることが好ましい。 In the manufacturing method according to the second aspect, as shown in FIG. 5C, the distance between the semiconductor chips CP after the expanding process is D2. The distance D2 is larger than the distance D1. For example, the distance D2 is preferably 200 μm or more and 6000 μm or less.
[封止工程]
 図6には、封止部材60を用いて複数の半導体チップCPを封止する工程(以下「封止工程」という場合がある。)を説明する図が示されている。
[Sealing process]
FIG. 6 is a diagram for explaining a process of sealing a plurality of semiconductor chips CP using the sealing member 60 (hereinafter also referred to as “sealing process”).
 図6(A)には、エキスパンド工程の後に、第四の粘着シートとしての表面保護シート40を複数の半導体チップCPに貼付する工程を説明する図が示されている。 FIG. 6 (A) shows a diagram illustrating a process of attaching a surface protection sheet 40 as a fourth pressure-sensitive adhesive sheet to a plurality of semiconductor chips CP after the expanding process.
 第二の粘着シート20を引き延ばして複数の半導体チップCP間の間隔を距離D2まで拡げた後、半導体チップCPの回路面W1に表面保護シート40を貼着する。表面保護シート40は、第四の基材フィルム41と、第四の粘着剤層42とを有する。表面保護シート40は、回路面W1を第四の粘着剤層42で覆うように貼着されることが好ましい。 After extending the second pressure-sensitive adhesive sheet 20 to increase the distance between the plurality of semiconductor chips CP to the distance D2, the surface protective sheet 40 is attached to the circuit surface W1 of the semiconductor chip CP. The surface protection sheet 40 includes a fourth base film 41 and a fourth pressure-sensitive adhesive layer 42. It is preferable that the surface protection sheet 40 is stuck so that the circuit surface W1 may be covered with the fourth pressure-sensitive adhesive layer 42.
 表面保護シート40を貼着した後、第二の粘着シート20を剥離すると、複数の半導体チップCPの裏面W3が露出する。第二の粘着シート20を剥離した後も、エキスパンド工程において拡張させた複数の半導体チップCP間の距離D2が維持されていることが好ましい。第二の粘着剤層22にエネルギー線重合性化合物が配合されている場合には、第二の粘着剤層22に第二の基材フィルム21側からエネルギー線を照射し、エネルギー線重合性化合物を硬化させてから第二の粘着シート20を剥離することが好ましい。 When the second pressure-sensitive adhesive sheet 20 is peeled off after the surface protective sheet 40 is adhered, the back surfaces W3 of the plurality of semiconductor chips CP are exposed. It is preferable that the distance D2 between the plurality of semiconductor chips CP expanded in the expanding process is maintained even after the second pressure-sensitive adhesive sheet 20 is peeled off. When the energy ray polymerizable compound is blended in the second pressure-sensitive adhesive layer 22, the second pressure-sensitive adhesive layer 22 is irradiated with energy rays from the second base film 21 side, and the energy ray polymerizable compound is irradiated. It is preferable to peel the second pressure-sensitive adhesive sheet 20 after curing.
 図6(B)には、表面保護シート40によって保持された複数の半導体チップCPを封止する工程を説明する図が示されている。 FIG. 6B shows a diagram for explaining a process of sealing a plurality of semiconductor chips CP held by the surface protection sheet 40.
 回路面W1を残して複数の半導体チップCPを、封止部材60によって覆うことにより封止体3が形成される。複数の半導体チップCPの間にも封止部材60が充填されている。ここにおいて、表面保護シート40により回路面W1および回路W2が覆われているので、封止部材60で回路面W1が覆われることを防止できる。 The sealing body 3 is formed by covering the plurality of semiconductor chips CP with the sealing member 60 while leaving the circuit surface W1. The sealing member 60 is also filled between the plurality of semiconductor chips CP. Here, since the circuit surface W1 and the circuit W2 are covered by the surface protection sheet 40, it is possible to prevent the circuit surface W1 from being covered by the sealing member 60.
 封止工程により、所定距離ずつ離間した複数の半導体チップCPが封止部材に埋め込まれた封止体3が得られる。封止工程においては、複数の半導体チップCPは、距離D2が維持された状態で、封止部材60により覆われることが好ましい。 By the sealing process, a sealing body 3 in which a plurality of semiconductor chips CP separated by a predetermined distance are embedded in a sealing member is obtained. In the sealing step, the plurality of semiconductor chips CP are preferably covered with the sealing member 60 while the distance D2 is maintained.
 封止工程の後、表面保護シート40が剥離されると、半導体チップCPの回路面W1および封止体3の表面保護シート40と接触していた面3Sが露出する(図3(A)参照)。 When the surface protection sheet 40 is peeled after the sealing step, the surface 3S that has been in contact with the circuit surface W1 of the semiconductor chip CP and the surface protection sheet 40 of the sealing body 3 is exposed (see FIG. 3A). ).
[再配線層形成工程、外部端子電極との接続工程および第二のダイシング工程]
 封止工程に続いて、再配線層形成工程、外部端子電極との接続工程および第二のダイシング工程が行われる。これらの工程は、第1態様に係る製造方法と同様に行うことができる(図3(B)および図3(C)参照)。これらの工程を経ることで、FO-WLPが得られる。
[Rewiring layer forming step, connecting step with external terminal electrode, and second dicing step]
Subsequent to the sealing step, a rewiring layer forming step, a connection step with an external terminal electrode, and a second dicing step are performed. These steps can be performed in the same manner as in the manufacturing method according to the first aspect (see FIGS. 3B and 3C). Through these steps, FO-WLP is obtained.
[変形例]
 上述した第2態様に係るFO-WLPの製造方法は、一部の工程を変更したり、一部の工程を省略してもよい。そのような変形例を以下に説明する。
[Modification]
In the FO-WLP manufacturing method according to the second aspect described above, some processes may be changed or some processes may be omitted. Such a modification will be described below.
 第2態様に係る製造方法の第1の変形例として、第二の粘着シート20の貼付工程に続いて、第一の粘着シート10だけを剥離する工程を行ってもよい。すなわち、前述した第2態様では、第一の粘着シート10を剥離する際に、切断された保護シート30を同伴して剥離したのに対し、本変形例では、保護シート30を半導体チップCPの回路面W1に残したまま第一の粘着シート10を剥離する。第一の粘着シート10の剥離により、図7(A)に示すように、切断された保護シート30が貼付された複数の半導体チップCPが、第二の粘着シート20上に積層された状態となる。 As a first modification of the manufacturing method according to the second aspect, a step of peeling only the first pressure-sensitive adhesive sheet 10 may be performed following the step of attaching the second pressure-sensitive adhesive sheet 20. That is, in the second embodiment described above, when the first pressure-sensitive adhesive sheet 10 is peeled off, the cut protective sheet 30 is accompanied and peeled, whereas in the present modification, the protective sheet 30 is attached to the semiconductor chip CP. The first adhesive sheet 10 is peeled off while remaining on the circuit surface W1. By peeling off the first pressure-sensitive adhesive sheet 10, as shown in FIG. 7A, a plurality of semiconductor chips CP to which the cut protective sheet 30 is attached are stacked on the second pressure-sensitive adhesive sheet 20. Become.
 続いて、図7(B)に示すように、前述したエキスパンド工程を行う。すなわち、半導体チップCPの回路面W1に切断された保護シート30が貼付された状態で、第二の粘着シート20を引き延ばして、複数の半導体チップCP間を距離D2まで拡げる。 Subsequently, as shown in FIG. 7B, the expanding process described above is performed. That is, the second adhesive sheet 20 is stretched in a state where the cut protective sheet 30 is attached to the circuit surface W1 of the semiconductor chip CP, and the space between the plurality of semiconductor chips CP is expanded to the distance D2.
 エキスパンド工程の後、図7(C)に示すように、複数の半導体チップCPを封止する工程を行う。前述した第2態様では、図6(B)に示すように、表面保護シート40上にて半導体チップCPを封止したのに対し、本変形例では、図7(C)に示すように、第二の粘着シート20上において、封止部材60を用いて半導体チップCPを封止する。ここで、回路面W1には保護シート30が貼着されているので、表面保護シート40を貼着しなくてもよく、半導体チップCPの裏面W3に第二の粘着シートが貼着されたたまま封止できる。回路面W1を残して複数の半導体チップCPを封止部材60によって覆うことにより封止体3が形成される。封止体3の面3Sと半導体チップCPの回路面W1とが同一面であることが好ましい。 After the expanding process, as shown in FIG. 7C, a process of sealing a plurality of semiconductor chips CP is performed. In the second aspect described above, the semiconductor chip CP is sealed on the surface protection sheet 40 as shown in FIG. 6B, whereas in this modification, as shown in FIG. On the second adhesive sheet 20, the semiconductor chip CP is sealed using the sealing member 60. Here, since the protective sheet 30 is adhered to the circuit surface W1, the surface protective sheet 40 may not be adhered, and the second adhesive sheet is adhered to the back surface W3 of the semiconductor chip CP. Can be sealed as it is. The sealing body 3 is formed by covering the plurality of semiconductor chips CP with the sealing member 60 while leaving the circuit surface W1. It is preferable that the surface 3S of the sealing body 3 and the circuit surface W1 of the semiconductor chip CP are the same surface.
 封止工程の後、保護シート30および第二の粘着シート20を剥離する。その後、前述した再配線層形成工程、外部端子電極との接続工程および第二のダイシング工程を行うことで、FO-WLPが得られる。 After the sealing step, the protective sheet 30 and the second adhesive sheet 20 are peeled off. Then, the FO-WLP is obtained by performing the above-described rewiring layer forming step, connecting step with the external terminal electrode, and second dicing step.
 本実施形態に係る半導体加工用シートは、大きく延伸することができるため、以上説明したような、半導体チップの間隔を大きく拡げる必要がある用途に好適に使用することができる。 Since the semiconductor processing sheet according to the present embodiment can be stretched greatly, it can be suitably used for applications where the interval between semiconductor chips needs to be greatly expanded as described above.
 以上説明した実施形態は、本発明の理解を容易にするために記載されたものであって、本発明を限定するために記載されたものではない。したがって、上記実施形態に開示された各要素は、本発明の技術的範囲に属する全ての設計変更や均等物をも含む趣旨である。 The embodiment described above is described for facilitating understanding of the present invention, and is not described for limiting the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention.
 例えば、半導体加工用シートが基材と粘着剤層とを備える構成である場合、基材と粘着剤層との間には、他の層が介在していてもよい。 For example, when the semiconductor processing sheet has a configuration including a base material and a pressure-sensitive adhesive layer, another layer may be interposed between the base material and the pressure-sensitive adhesive layer.
 以下、実施例等により本発明をさらに具体的に説明するが、本発明の範囲はこれらの実施例等に限定されるものではない。 Hereinafter, the present invention will be described more specifically with reference to examples and the like, but the scope of the present invention is not limited to these examples and the like.
〔実施例1〕
(1)粘着性組成物の調製
 ブチルアクリレート/2-ヒドロキシエチルアクリレート=85/15(質量比)を反応させて得られたアクリル系共重合体と、その2-ヒドロキシエチルアクリレートに対して80モル%のメタクリロイルオキシエチルイソシアネート(MOI)とを反応させて、エネルギー線硬化型重合体を得た。このエネルギー線硬化型重合体の重量平均分子量(Mw)は、60万であった。
[Example 1]
(1) Preparation of adhesive composition Acrylic copolymer obtained by reacting butyl acrylate / 2-hydroxyethyl acrylate = 85/15 (mass ratio), and 80 mol relative to 2-hydroxyethyl acrylate % Methacryloyloxyethyl isocyanate (MOI) was reacted to obtain an energy ray curable polymer. The energy ray curable polymer had a weight average molecular weight (Mw) of 600,000.
 得られたエネルギー線硬化型重合体100質量部と、光重合開始剤としての1-ヒドロキシシクロヘキシルフェニルケトン(BASF社製,製品名「イルガキュア184」)3質量部と、架橋剤としてのトリレンジイソシアネート系架橋剤(東ソー社製,製品名「コロネートL」)0.45質量部とを溶媒中で混合し、粘着性組成物を得た。 100 parts by mass of the obtained energy ray curable polymer, 3 parts by mass of 1-hydroxycyclohexyl phenyl ketone (product name “Irgacure 184”, manufactured by BASF) as a photopolymerization initiator, and tolylene diisocyanate as a crosslinking agent 0.45 parts by mass of a system cross-linking agent (manufactured by Tosoh Corporation, product name “Coronate L”) was mixed in a solvent to obtain an adhesive composition.
(2)半導体加工用シートの作製
 ポリエチレンテレフタレート(PET)フィルムの片面にシリコーン系の剥離剤層が形成されてなる剥離フィルム(リンテック社製,製品名「SP-PET3811」)の剥離面に対して、上記粘着性組成物を塗布し、加熱により乾燥させることで、剥離フィルム上に、厚さ10μmの粘着剤層を形成した。その後、この粘着剤層の露出面に、基材としてのポリエステル系ポリウレタンエラストマーシート(シーダム社製,製品名「ハイグレスDUS202」,厚さ50μm)の片面を貼り合せることで、粘着剤層に剥離フィルムが貼付された状態で半導体加工用シートを得た。
(2) Production of semiconductor processing sheet For the release surface of a release film (product name “SP-PET3811”, manufactured by Lintec Corporation) in which a silicone release agent layer is formed on one side of a polyethylene terephthalate (PET) film The pressure-sensitive adhesive composition was applied and dried by heating to form a pressure-sensitive adhesive layer having a thickness of 10 μm on the release film. After that, one side of a polyester polyurethane elastomer sheet (manufactured by Sea Dam Co., Ltd., product name “Higress DUS202”, thickness 50 μm) as a base material is bonded to the exposed surface of the pressure-sensitive adhesive layer. A sheet for semiconductor processing was obtained in a state where was stuck.
〔比較例1〕
 ポリ塩化ビニル樹脂(PVC,平均重合度:1050)100質量部と、アジピン酸系ポリエステル可塑剤42質量部と、少量の安定剤とを混練し、カレンダー装置を用いてフィルム状に成形することで得られた、厚さ80μmの塩化ビニルフィルムを基材として使用する以外、実施例1と同様にして半導体加工用シートを作製した。
[Comparative Example 1]
By kneading 100 parts by weight of polyvinyl chloride resin (PVC, average degree of polymerization: 1050), 42 parts by weight of adipic acid polyester plasticizer and a small amount of stabilizer, and molding into a film using a calendar device A semiconductor processing sheet was produced in the same manner as in Example 1 except that the obtained vinyl chloride film having a thickness of 80 μm was used as a base material.
〔比較例2〕
 厚さ80μmのポリプロピレンフィルム(PP,ダイヤプラスフィルム社製,製品名「LT01-06051」)を基材として使用する以外、実施例1と同様にして半導体加工用シートを作製した。
[Comparative Example 2]
A semiconductor processing sheet was produced in the same manner as in Example 1 except that a polypropylene film (PP, manufactured by Diaplus Film Co., Ltd., product name “LT01-06051”) having a thickness of 80 μm was used as a base material.
〔試験例1〕(引張試験)
 実施例および比較例において製造した半導体加工用シートを15mm×140mmに裁断し、剥離シートを剥離することで試験片とした。当該試験片について、JIS K7161:2014およびJIS K7127:1999に準拠して、23℃における破断伸度および引張弾性率を測定した。具体的には、上記試験片を、引張試験機(島津製作所製,製品名「オートグラフAG-IS 500N」)にて、チャック間距離100mmに設定した後、200mm/minの速度で引張試験を行い、破断伸度(%)および引張弾性率(MPa)を測定した。なお、測定は、基材の製造時の流れ方向(MD)およびこれに直角の方向(CD)の双方で行った。結果を表1に示す。
[Test Example 1] (Tensile test)
The semiconductor processing sheets produced in the examples and comparative examples were cut into 15 mm × 140 mm, and the release sheet was peeled off to obtain test pieces. About the said test piece, based on JISK7161: 2014 and JISK7127: 1999, the elongation at break and tensile elastic modulus in 23 degreeC were measured. Specifically, the test piece was set to a distance between chucks of 100 mm with a tensile tester (manufactured by Shimadzu Corporation, product name “Autograph AG-IS 500N”), and then subjected to a tensile test at a speed of 200 mm / min. The elongation at break (%) and the tensile modulus (MPa) were measured. The measurement was performed in both the flow direction (MD) during production of the substrate and the direction perpendicular to the flow direction (CD). The results are shown in Table 1.
〔試験例2〕(100%応力および復元率の測定)
 実施例または比較例で得た半導体加工用シートを、150mm×15mmに切断し、剥離シートを剥離することで試験片を得た。なお、半導体加工用シートの製造時における流れ方向(MD方向)が、試験片の長さ方向となるように切断した。その後、試験片の長さ方向の両端を、引張試験機(島図製作所社製,製品名「オートグラフAG-IS 50N」)のつかみ具で固定した。このとき、つかみ具間の長さが100mmとなるように、つかみ具で試験片を把持した。この長さを、初期つかみ具間の長さL0(mm)とした。そして、200mm/minの速度で長さ方向に100mm引張り、つかみ具間の長さを200mmとした。この長さから初期つかみ具間の長さL0(mm)(すなわち100mm)を引いた長さを拡張長さL1(mm)とした。この時の試験力を測定し、引張試験における100%強度(N)を求め、MD方向の100%強度(N)とした。そして、MD方向の100%強度(N)を、半導体加工シートの断面積で除算することで、MD方向の100%応力(MPa)を求めた。さらに、つかみ具間の長さが200mmとなった状態で1分間保持した後、つかみ具間の長さがL0(mm)となるまで200mm/minの速度でつかみ具を戻し、つかみ具間の長さがL0(mm)の状態で1分間保持した。その後、60mm/minの速度で長さ方向に引張り、引張力が0.1N/15mmを示した時点でのつかみ具間の長さを記録した。この長さから初期つかみ具間の長さL0(mm)を引いた値を、L2(mm)とした。
[Test Example 2] (Measurement of 100% stress and restoration rate)
The semiconductor processing sheet obtained in the example or comparative example was cut into 150 mm × 15 mm, and the release sheet was peeled off to obtain a test piece. In addition, it cut | disconnected so that the flow direction (MD direction) at the time of manufacture of the sheet | seat for semiconductor processing might become the length direction of a test piece. Thereafter, both ends in the length direction of the test piece were fixed with a gripping tool of a tensile tester (manufactured by Shimazu Seisakusho, product name “Autograph AG-IS 50N”). At this time, the test piece was gripped with the gripping tool so that the length between the gripping tools was 100 mm. This length was defined as the length L0 (mm) between the initial grippers. And it pulled 100 mm in the length direction at a speed | rate of 200 mm / min, and the length between grips was 200 mm. The length obtained by subtracting the length L0 (mm) (that is, 100 mm) between the initial grippers from this length was defined as the extended length L1 (mm). The test force at this time was measured, and the 100% strength (N) in the tensile test was determined to obtain the 100% strength (N) in the MD direction. And 100% strength (MPa) of MD direction was calculated | required by dividing 100% intensity | strength (N) of MD direction by the cross-sectional area of a semiconductor processed sheet. Furthermore, after holding for 1 minute in a state where the length between the grips is 200 mm, the grips are returned at a speed of 200 mm / min until the length between the grips reaches L0 (mm). The length was maintained for 1 minute in a state of L0 (mm). Then, it pulled in the length direction at the speed | rate of 60 mm / min, and recorded the length between the holding tools when the tensile force showed 0.1 N / 15mm. A value obtained by subtracting the length L0 (mm) between the initial grippers from this length was defined as L2 (mm).
 上記L1およびL2の値を下記式(I)にあてはめ、復元率(%)を算出した。その結果を表1に示す。
 復元率(%)={1-(L2÷L1)}×100 ・・・ (I)
The values of L1 and L2 were applied to the following formula (I), and the restoration rate (%) was calculated. The results are shown in Table 1.
Restoration rate (%) = {1− (L2 ÷ L1)} × 100 (I)
 また、実施例または比較例で得た半導体加工用シートを、その製造時における流れ方向に対して直交する方向(CD方向)が試験片の長さ方向となるように、150mm×15mmに切断し、剥離シートを剥離することで得た試験片についても、上記と同様に100%強度(N)および100%応力(MPa)の測定を行い、それぞれCD方向の100%強度(N)およびCD方向の100%応力(MPa)とした。それらの結果を表1に示す。さらに、CD方向の100%応力(MPa)に対する、MD方向の100%応力(MPa)の比を算出した。その結果も表1に示す。 Further, the semiconductor processing sheet obtained in the example or the comparative example was cut into 150 mm × 15 mm so that the direction (CD direction) perpendicular to the flow direction at the time of manufacture was the length direction of the test piece. The test piece obtained by peeling the release sheet was also measured for 100% strength (N) and 100% stress (MPa) in the same manner as described above, and 100% strength (N) and CD direction in the CD direction, respectively. 100% stress (MPa). The results are shown in Table 1. Furthermore, the ratio of 100% stress (MPa) in the MD direction to 100% stress (MPa) in the CD direction was calculated. The results are also shown in Table 1.
〔試験例3〕(エキスパンド試験)
 ダイシングテープ(リンテック社製,製品名「ADWILL D-675」)の剥離シートを剥離し、露出した粘着面を、リングフレームおよび6インチシリコンミラーウエハ(直径:150mm,厚さ:350μm,研削面#2000)の研削面に貼付した。次いで、ダイサー(ディスコ社製,製品名「DFD-651」)を使用して、以下の条件にてシリコンミラーウエハをフルカットでダイシングした。これにより、ダイシングテープ上に、個片化された複数のシリコンチップを得た。その後、ダイシングテープに対して、UV照射装置(リンテック社製,製品名「RAD-2000m/12」)を用いて、UV照射(照度:120mW/cm,光量:70mJ/cm)を行った。
・ダイシングブレード:ディスコ社製,製品名「NBC-ZH205O 27HECC」
・回転数:30,000rpm
・ハイト:0.06mm
・カット速度:60mm/sec
・チップサイズ:3mm×3mm
[Test Example 3] (Expand test)
The release sheet of dicing tape (product name “ADWILL D-675” manufactured by Lintec Corporation) is peeled off, and the exposed adhesive surface is divided into a ring frame and a 6-inch silicon mirror wafer (diameter: 150 mm, thickness: 350 μm, ground surface # 2000). Next, using a dicer (manufactured by Disco Corporation, product name “DFD-651”), the silicon mirror wafer was diced in a full cut under the following conditions. As a result, a plurality of individual silicon chips were obtained on the dicing tape. Thereafter, the dicing tape, using a UV irradiation device (manufactured by Lintec Corporation, product name "RAD-2000m / 12"), UV irradiation (illuminance: 120mW / cm 2, the amount of light: 70mJ / cm 2) was carried out .
・ Dicing blade: manufactured by Disco Corporation, product name “NBC-ZH205O 27HECC”
・ Rotation speed: 30,000 rpm
・ Height: 0.06mm
・ Cut speed: 60mm / sec
・ Chip size: 3mm × 3mm
 続いて、実施例または比較例で得た半導体加工用シートを、210mm×210mmの四角形のサイズに裁断した。このとき、裁断後のシートの各辺が、半導体加工用シートにおける基材のMD方向と平行または垂直となるように裁断した。次に、剥離シートを剥離し、露出した粘着面に、上記ダイシングで得られたシリコンチップすべてを転写した。このとき、シリコンチップの一群が、半導体加工用シートの中央部に位置するように転写した。また、シリコンウエハを個片化したときのダイシングラインが、半導体加工用シートの各辺と平行または垂直となるように転写した。 Subsequently, the semiconductor processing sheet obtained in the example or the comparative example was cut into a square size of 210 mm × 210 mm. At this time, each side of the cut sheet was cut so as to be parallel or perpendicular to the MD direction of the substrate in the semiconductor processing sheet. Next, the release sheet was peeled off, and all of the silicon chips obtained by the dicing were transferred to the exposed adhesive surface. At this time, transfer was performed so that a group of silicon chips were located in the center of the semiconductor processing sheet. Further, the dicing line when the silicon wafer was separated into pieces was transferred so as to be parallel or perpendicular to each side of the semiconductor processing sheet.
 次に、シリコンチップが転写された半導体加工用シートを、2軸延伸可能なエキスパンド装置(離間装置)に設置した。図8には、当該エキスパンド装置100を説明する平面図が示される。図8中、X軸およびY軸は、互いに直交する関係にあり、当該X軸の正の方向を+X軸方向、当該X軸の負の方向を-X軸方向、当該Y軸の正の方向を+Y軸方向、当該Y軸の負の方向を-Y軸方向とする。半導体加工用シート200は、各辺がX軸またはY軸と平行となるように、エキスパンド装置100に設置した。その結果、半導体加工用シート200における基材のMD方向は、X軸またはY軸と平行となる。なお、図8中、シリコンチップは省略されている。 Next, the semiconductor processing sheet on which the silicon chip was transferred was placed in an expanding apparatus (separating apparatus) capable of biaxial stretching. FIG. 8 shows a plan view for explaining the expanding apparatus 100. In FIG. 8, the X axis and the Y axis are orthogonal to each other. The positive direction of the X axis is the + X axis direction, the negative direction of the X axis is the −X axis direction, and the positive direction of the Y axis. Is the + Y axis direction, and the negative direction of the Y axis is the -Y axis direction. The semiconductor processing sheet 200 was installed in the expanding apparatus 100 so that each side was parallel to the X axis or the Y axis. As a result, the MD direction of the base material in the semiconductor processing sheet 200 is parallel to the X axis or the Y axis. In FIG. 8, the silicon chip is omitted.
 図8に示されるように、エキスパンド装置100は、+X軸方向、-X軸方向、+Y軸方向および-Y軸方向のそれぞれに5つの保持手段101(計20個の保持手段101)を備える。各方向における5つの保持手段100のうち、両端に位置するものを保持手段101Aとし、中央に位置するものを保持手段101Cとし、保持手段101Aと保持手段101Cとの間に位置するものを保持手段101Bとする。半導体加工用シート200の各辺を、これらの保持手段101によって把持させた。 As shown in FIG. 8, the expanding apparatus 100 includes five holding means 101 (20 holding means 101 in total) in each of the + X axis direction, the −X axis direction, the + Y axis direction, and the −Y axis direction. Of the five holding means 100 in each direction, the one located at both ends is the holding means 101A, the one located in the center is the holding means 101C, and the one located between the holding means 101A and the holding means 101C is the holding means. 101B. Each side of the semiconductor processing sheet 200 was held by these holding means 101.
 ここで、図8に示されるように、半導体加工用シート200の一辺は210mmである。また、各辺における保持手段101同士の間隔は40mmである。また、半導体加工用シート200の一辺における端部(シートの頂点)と、当該辺に存在し、当該端部に最も近い保持手段101Aとの間隔は25mmである。 Here, as shown in FIG. 8, one side of the semiconductor processing sheet 200 is 210 mm. The interval between the holding means 101 on each side is 40 mm. Further, the distance between the end portion (the apex of the sheet) on one side of the semiconductor processing sheet 200 and the holding means 101A closest to the end portion is 25 mm.
 続いて、保持手段101のそれぞれに対応する、図示されていない複数の張力付与手段を駆動させて、保持手段101をそれぞれ独立に移動させた。このとき、半導体加工用シート200における+X軸方向側の一辺を把持する5つの保持手段101については、+X軸方向に延伸速度:2.5mm/secで40秒間移動させた。それと同時に、これらの5つの保持手段101のうち、保持手段101Aおよび保持手段101Bを、保持手段101Cから遠ざける方向(すなわち、+Y軸方向または-Y軸方向)に移動させた。このとき、保持手段101Aは延伸速度:2.5mm/secの2/3の速度で移動させ、保持手段101Bは延伸速度:2.5mm/secの1/3の速度で移動させた。なお、保持手段101Cは、+Y軸方向および-Y軸方向へは移動させなかった。半導体加工用シート200における、+X軸方向以外の3方向側に位置する保持手段101についても、+X軸方向と同様に、各方向への移動と、保持手段101Aおよび保持手段101Bを保持手段101Cから遠ざける方向への移動とを行った。 Subsequently, a plurality of tension applying means (not shown) corresponding to each of the holding means 101 were driven to move the holding means 101 independently of each other. At this time, the five holding units 101 that grip one side of the semiconductor processing sheet 200 on the + X-axis direction side were moved in the + X-axis direction at a stretching speed of 2.5 mm / sec for 40 seconds. At the same time, among these five holding means 101, the holding means 101A and the holding means 101B were moved in the direction away from the holding means 101C (that is, the + Y axis direction or the −Y axis direction). At this time, the holding means 101A was moved at a stretching speed: 2/3 of 2.5 mm / sec, and the holding means 101B was moved at a stretching speed: 1/3 of 2.5 mm / sec. The holding means 101C was not moved in the + Y axis direction and the −Y axis direction. Regarding the holding means 101 located on the three directions other than the + X-axis direction in the semiconductor processing sheet 200, the movement in each direction and the holding means 101A and the holding means 101B are moved from the holding means 101C in the same manner as the + X-axis direction. Moved away.
 以上のように各保持手段101を移動させた結果、半導体加工用シート200は、+X軸方向および-X軸方向にそれぞれ100mmずつ延伸されるとともに、+Y軸方向および-Y軸方向にそれぞれ100mmずつ延伸された。すなわち、半導体加工用シート200は、各辺が200mmずつ延伸された。その結果、延伸後の半導体加工用シート200の各辺の長さは、410mmとなった。 As a result of moving each holding means 101 as described above, the semiconductor processing sheet 200 is stretched by 100 mm each in the + X-axis direction and the −X-axis direction, and 100 mm each in the + Y-axis direction and the −Y-axis direction. It was stretched. That is, the semiconductor processing sheet 200 was stretched by 200 mm on each side. As a result, the length of each side of the stretched semiconductor processing sheet 200 was 410 mm.
 上記のように延伸された状態の半導体加工用シート200について、以下の基準に基づいて、破断の有無を評価した。結果を表1に示す。
 ○:破断が生じることなく、良好に延伸された。
 ×:破断が生じた。
About the semiconductor processing sheet 200 in the stretched state as described above, the presence or absence of breakage was evaluated based on the following criteria. The results are shown in Table 1.
○: The film was stretched satisfactorily without causing breakage.
X: Breakage occurred.
 また、破断の有無の評価が「○」であった半導体加工用シート200については、半導体加工用シート200を延伸された状態において、複数のシリコンチップから構成される略円形の形状における外径(ダイシングおよび延伸を行う前のシリコンウエハの外径に対応する長さ)を、ウエハ外径対応長さ(mm)として測定した。結果を表1に示す。 Further, for the semiconductor processing sheet 200 in which the evaluation of the presence or absence of breakage was “◯”, the outer diameter of the substantially circular shape composed of a plurality of silicon chips in the stretched state of the semiconductor processing sheet 200 ( The length corresponding to the outer diameter of the silicon wafer before dicing and stretching) was measured as the length corresponding to the wafer outer diameter (mm). The results are shown in Table 1.
 さらに、測定したウエハ外径対応長さ(mm)を以下の計算式(II)にあてはめ、チップ間隔(mm)を算出した。結果を表1に示す。
   チップ間隔(mm)={ウエハ外径対応長さ(mm)-150mm(シリコンウエハ直径)}÷49(ダイシングライン数) ・・・ (II)
Further, the measured length (mm) corresponding to the wafer outer diameter was applied to the following calculation formula (II) to calculate the chip interval (mm). The results are shown in Table 1.
Chip interval (mm) = {length corresponding to wafer outer diameter (mm) −150 mm (silicon wafer diameter)} ÷ 49 (number of dicing lines) (II)
 なお、上記式(II)において、ダイシングライン数が49であることは、直径150mmのシリコンウエハを3mm×3mmのチップサイズにダイシングする場合、シリコンウエハは一方向および当該方向に直交する方向にそれぞれ3mm間隔でダイシングされ、各方向に最大で50等分されるが、そのときのダイシングライン数がそれぞれの方向において49個であることに基づく。 In the above formula (II), the number of dicing lines is 49. When a silicon wafer having a diameter of 150 mm is diced into a chip size of 3 mm × 3 mm, the silicon wafer is in one direction and in a direction perpendicular to the direction. Dicing is performed at intervals of 3 mm, and each direction is divided into a maximum of 50, based on the fact that the number of dicing lines at that time is 49 in each direction.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
 表1から明らかなように、実施例の半導体加工用シートは、破断することなく大きく延伸することができた。 As is clear from Table 1, the semiconductor processing sheets of the examples could be greatly stretched without breaking.
 本発明に係る半導体加工用シートは、例えばFO-WLPの製造に好適に用いられる。 The semiconductor processing sheet according to the present invention is suitably used for manufacturing, for example, FO-WLP.
W…半導体ウエハ
 W1…回路面
 W2…回路
 W3…裏面
 W4…内部端子電極
 W5…溝
 W6…裏面
CP…半導体チップ
1…半導体パッケージ
3…封止体
4A…第一の絶縁層
4B…第二の絶縁層
5…再配線層
 5A…外部電極パッド
6…外部端子電極
10…第一の粘着シート
 11…第一の基材フィルム
 12…第一の粘着剤層
20…第二の粘着シート
 21…第二の基材フィルム
 22…第二の粘着剤層
30…保護シート
40…表面保護シート
 41…第四の基材フィルム
 42…第四の粘着剤層
50…グラインダー
60…封止部材
100…エキスパンド装置
 101,101A,101B,101C…保持手段
200…半導体加工用シート
W ... Semiconductor wafer W1 ... Circuit surface W2 ... Circuit W3 ... Back surface W4 ... Internal terminal electrode W5 ... Groove W6 ... Back surface CP ... Semiconductor chip 1 ... Semiconductor package 3 ... Sealing body 4A ... First insulating layer 4B ... Second Insulating layer 5 ... Rewiring layer 5A ... External electrode pad 6 ... External terminal electrode 10 ... First adhesive sheet 11 ... First base film 12 ... First adhesive layer 20 ... Second adhesive sheet 21 ... First Second base film 22 ... second adhesive layer 30 ... protective sheet 40 ... surface protective sheet 41 ... fourth base film 42 ... fourth adhesive layer 50 ... grinder 60 ... sealing member 100 ... expanding device 101, 101A, 101B, 101C ... Holding means 200 ... Semiconductor processing sheet

Claims (10)

  1.  少なくとも基材を備える半導体加工用シートであって、
     前記半導体加工用シートの復元率が、70%以上、100%以下であり、
     前記復元率は、前記半導体加工用シートを150mm×15mmに切り出した試験片において、長さ方向の両端を、つかみ具間の長さが100mmとなるようにつかみ具でつかみ、その後、つかみ具間の長さが200mmとなるまで200mm/minの速度で引張り、つかみ具間の長さが200mmに拡張された状態で1分間保持し、その後、つかみ具間の長さが100mmとなるまで200mm/minの速度で長さ方向に戻し、つかみ具間の長さが100mmに戻された状態で1分間保持し、その後、60mm/minの速度で長さ方向に引張り、引張力の測定値が0.1N/15mmを示した時のつかみ具間の長さを測定し、当該長さから初期のつかみ具間の長さ100mmを引いた長さをL2(mm)とし、前記拡張された状態におけるつかみ具間の長さ200mmから初期のつかみ具間の長さ100mmを引いた長さをL1(mm)としたとき、次式(I)
     復元率(%)={1-(L2÷L1)}×100 ・・・ (I)
    から算出される値である
    ことを特徴とする半導体加工用シート。
    A semiconductor processing sheet comprising at least a base material,
    The restoration rate of the semiconductor processing sheet is 70% or more and 100% or less,
    In the test piece obtained by cutting the semiconductor processing sheet into 150 mm × 15 mm, the restoration rate is obtained by grasping both ends in the length direction with a gripping tool so that the length between the gripping tools is 100 mm, and then between the gripping tools. Is pulled at a speed of 200 mm / min until the length of the grip becomes 200 mm, held for 1 minute with the length between the grips extended to 200 mm, and then 200 mm / length until the length between the grips reaches 100 mm. Return to the length direction at a speed of min, hold for 1 minute with the length between the grippers returned to 100 mm, and then pull in the length direction at a speed of 60 mm / min. Measure the length between grips when showing 1N / 15mm, and subtract the length of 100mm between the initial grips from the length to make L2 (mm). When kicking the length obtained by subtracting the length of 100mm between the initial jaw from the length 200mm between jaws was L1 (mm), the following formula (I)
    Restoration rate (%) = {1− (L2 ÷ L1)} × 100 (I)
    A sheet for semiconductor processing, which is a value calculated from
  2.  少なくとも基材を備える半導体加工用シートであって、
     23℃において前記基材のCD方向に測定される前記半導体加工用シートの100%応力に対する、23℃において前記基材のMD方向に測定される前記半導体加工用シートの100%応力の比が、0.8以上、1.2以下であり、
     前記100%応力は、前記半導体加工用シートを150mm×15mmに切り出した試験片において、長さ方向の両端を、つかみ具間の長さが100mmとなるようにつかみ具でつかみ、その後、速度200mm/minで長さ方向に引張り、つかみ具間の長さが200mmとなったときの引張力の測定値を、半導体加工用シートの断面積で除算することで得られる値である
    ことを特徴とする半導体加工用シート。
    A semiconductor processing sheet comprising at least a base material,
    The ratio of the 100% stress of the semiconductor processing sheet measured in the MD direction of the substrate at 23 ° C. to the 100% stress of the semiconductor processing sheet measured in the CD direction of the substrate at 23 ° C. 0.8 or more and 1.2 or less,
    The 100% stress is obtained by gripping both ends in the length direction with a gripping tool so that the length between the gripping tools becomes 100 mm in a test piece obtained by cutting the semiconductor processing sheet into 150 mm × 15 mm, and thereafter speed of 200 mm. It is a value obtained by dividing the measured value of the tensile force when it is pulled in the length direction at / min and the length between the grips becomes 200 mm by the cross-sectional area of the semiconductor processing sheet. Sheet for semiconductor processing.
  3.  少なくとも基材を備える半導体加工用シートであって、
     23℃において前記基材のMD方向およびCD方向に測定される前記半導体加工用シートの引張弾性率が、それぞれ10MPa以上、350MPa以下であり、
     23℃において前記基材のMD方向およびCD方向に測定される前記半導体加工用シートの100%応力が、それぞれ3MPa以上、20MPa以下であり、
     前記100%応力は、前記半導体加工用シートを150mm×15mmに切り出した試験片において、長さ方向の両端を、つかみ具間の長さが100mmとなるようにつかみ具でつかみ、その後、速度200mm/minで長さ方向に引張り、つかみ具間の長さが200mmとなったときの引張力の測定値を、半導体加工用シートの断面積で除算することで得られる値であり、
     23℃において前記基材のMD方向およびCD方向に測定される前記半導体加工用シートの破断伸度が、それぞれ100%以上である
    ことを特徴とする半導体加工用シート。
    A semiconductor processing sheet comprising at least a base material,
    The tensile elastic modulus of the semiconductor processing sheet measured in the MD direction and the CD direction of the substrate at 23 ° C. is 10 MPa or more and 350 MPa or less,
    100% stress of the semiconductor processing sheet measured in the MD direction and CD direction of the substrate at 23 ° C. is 3 MPa or more and 20 MPa or less, respectively.
    The 100% stress is obtained by gripping both ends in the length direction with a gripping tool so that the length between the gripping tools becomes 100 mm in a test piece obtained by cutting the semiconductor processing sheet into 150 mm × 15 mm, and thereafter speed of 200 mm. It is a value obtained by dividing the measured value of the tensile force when the length between the grips becomes 200 mm by dividing the sectional area of the semiconductor processing sheet by pulling in the length direction at / min.
    The semiconductor processing sheet, wherein the breaking elongation of the semiconductor processing sheet measured in the MD direction and the CD direction of the substrate at 23 ° C. is 100% or more, respectively.
  4.  前記基材の少なくとも一方の面に積層された粘着剤層をさらに備えることを特徴とする請求項1~3のいずれか一項に記載の半導体加工用シート。 The semiconductor processing sheet according to any one of claims 1 to 3, further comprising an adhesive layer laminated on at least one surface of the substrate.
  5.  前記基材は、熱可塑性エラストマーを含有することを特徴とする請求項1~4のいずれか一項に記載の半導体加工用シート。 The semiconductor processing sheet according to any one of claims 1 to 4, wherein the base material contains a thermoplastic elastomer.
  6.  前記熱可塑性エラストマーは、ウレタン系エラストマーであることを特徴とする請求項5に記載の半導体加工用シート。 The semiconductor processing sheet according to claim 5, wherein the thermoplastic elastomer is a urethane-based elastomer.
  7.  前記半導体加工用シートの片面に積層された複数の半導体チップにおける隣り合う半導体チップの相互の間隔を、200μm以上、6000μm以下まで拡げるために使用されることを特徴とする請求項1~6のいずれか一項に記載の半導体加工用シート。 7. The semiconductor chip according to claim 1, wherein the semiconductor chip is used to increase a distance between adjacent semiconductor chips in a plurality of semiconductor chips stacked on one side of the semiconductor processing sheet to 200 μm or more and 6000 μm or less. The semiconductor processing sheet according to claim 1.
  8.  互いに直交するX軸およびY軸における+X軸方向、-X軸方向、+Y軸方向および-Y軸方向の4方向に張力を付与して半導体加工用シートを引き延ばすことにより、前記半導体加工用シートの片面に積層された複数の半導体チップの間隔を拡げるために使用されることを特徴とする請求項1~7のいずれか一項に記載の半導体加工用シート。 By stretching the semiconductor processing sheet by applying tension in the four directions of the X-axis direction, the -X-axis direction, the + Y-axis direction, and the -Y-axis direction on the X-axis and the Y-axis orthogonal to each other, The semiconductor processing sheet according to any one of claims 1 to 7, wherein the semiconductor processing sheet is used to increase a distance between a plurality of semiconductor chips laminated on one side.
  9.  粘着シートの片面に、個片化された複数の半導体チップを設ける工程と、
     前記粘着シートを引き延ばして、前記複数の半導体チップ同士の間隔を拡げる工程と
    を備える半導体装置の製造方法において、前記粘着シートとして使用されることを特徴とする請求項1~8のいずれか一項に記載の半導体加工用シート。
    Providing a plurality of individual semiconductor chips on one side of the adhesive sheet;
    9. The method according to claim 1, wherein the pressure-sensitive adhesive sheet is used as the pressure-sensitive adhesive sheet in a method of manufacturing a semiconductor device comprising a step of extending the pressure-sensitive adhesive sheet and widening the interval between the plurality of semiconductor chips. The semiconductor processing sheet according to 1.
  10.  ファンアウト型の半導体ウエハレベルパッケージを製造するために使用されることを特徴とする請求項1~9のいずれか一項に記載の半導体加工用シート。 10. The semiconductor processing sheet according to claim 1, wherein the semiconductor processing sheet is used for manufacturing a fan-out type semiconductor wafer level package.
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