TWI750171B - Plate for semiconductor processing and method for manufacturing semiconductor device - Google Patents

Abstract

The present invention relates to a sheet for semiconductor processing, which is a sheet for semiconductor processing including at least a base material, and the recovery rate is 70% or more and 100% or less; The ratio of the 100% stress of the sheet to the 100% stress of the above-mentioned sheet for semiconductor processing measured in the CD direction of the substrate at 23°C is 0.8 or more and 1.2 or less; or, at 23°C in the MD direction of the substrate The tensile modulus of elasticity of the sheet for semiconductor processing measured in the CD direction is 10 MPa or more and 350 MPa or less, respectively, and 100% of the sheet for semiconductor processing measured in the MD and CD directions of the substrate at 23°C The stress is 3 MPa or more and 20 MPa or less, respectively, and the breaking elongation of the sheet for semiconductor processing measured at 23° C. in the MD direction and the CD direction of the substrate is 100% or more, respectively. The sheet for semiconductor processing can be greatly extended, and the semiconductor wafers can be sufficiently separated from each other.

Description

Sheet for semiconductor processing and method for manufacturing semiconductor device

The present invention relates to a sheet for semiconductor processing, preferably a sheet for semiconductor processing used for widening the interval between a plurality of semiconductor wafers.

In recent years, miniaturization, weight reduction, and high functionality of electronic devices have continued to progress. Semiconductor devices mounted on electronic equipment are also required to be miniaturized, thinned, and high-density. Semiconductor wafers, which are housed in packages close to their size. Such a package is sometimes referred to as a Chip Scale Package (CSP). As one of the CSPs, a wafer level package (Wafer Level Package, WLP) can be cited. In WLP, before individualization by dicing, external electrodes and the like are formed on the wafer, and finally the wafer is diced and individualized. As the WLP, a fan-in (Fan-In) type and a fan-out (Fan-Out) type can be mentioned. In the fan-out WLP (hereinafter, sometimes abbreviated as "FO-WLP"), the semiconductor wafer is covered with a sealing member in a region larger than the wafer size to form a semiconductor wafer sealing body, not only the semiconductor wafer A rewiring layer or an external electrode is also formed on the surface area of the sealing member.

For example, Patent Document 1 describes that a plurality of semiconductor wafers are separated from semiconductor wafers, leaving their circuit forming surfaces, surrounding the periphery with a mold member to form an expanded wafer, and extending rewiring patterns in areas outside the semiconductor wafers A method of manufacturing a semiconductor package formed by existing. described in Patent Document 1 In the manufacturing method of the present invention, before the individualized plural semiconductor chips are surrounded by the mold member, they are replaced with wafer adhesive tapes for expansion, so that the wafer adhesive tapes are extended to increase the distance between the plural semiconductor chips.

[Prior Art Literature] [Patent Literature]

[Patent Document 1] International Publication No. 2010/058646

In the above-mentioned manufacturing method of FO-WLP, in order to form the above-mentioned rewiring pattern and the like in a region outside the semiconductor wafer, it is necessary to sufficiently separate the semiconductor wafers from each other.

The present invention has been accomplished in view of the above-mentioned actual conditions, and an object of the present invention is to provide a greatly extendable sheet for semiconductor processing suitable for applications in which semiconductor wafers are required to be sufficiently separated from each other.

In order to achieve the above object, first, the present invention provides a sheet for semiconductor processing, which is a sheet for semiconductor processing including at least a base material, wherein the recovery rate of the sheet for semiconductor processing is 70% or more, 100% or less, the above recovery rate is obtained by cutting out the test piece of 150mm×15mm from the above-mentioned sheet for semiconductor processing so that the length between the jigs becomes 100mm, and the both ends in the longitudinal direction are clamped by the jig, and then the two ends in the longitudinal direction are clamped by 200mm/ Stretch at a speed of min until the length between the clamps reaches 200 mm, and hold the state where the length between the clamps is expanded to 200 mm for 1 minute. In the longitudinal direction, the length between the clamps was restored to 100 mm, and the length between the clamps was restored to 100 mm for 1 minute. After that, it was stretched in the longitudinal direction at a speed of 60 mm/min. The measured value of the tensile force showed 0.1N. The length between the clamps at the time of /15mm is L2 (mm) by subtracting the length between the clamps at the initial stage of 100mm from the length, and the length between the clamps in the expanded state is 200mm minus the length between the clamps at the initial stage of 100mm. When the length (mm) of is L1 (mm), the value calculated by the following formula (I): recovery rate (%)={1-(L2÷L1)}×100...(I) (Invention 1).

According to the above-mentioned invention (Invention 1), by setting the recovery rate in the above-mentioned range, it can be greatly extended. Therefore, it can be suitably used for applications in which semiconductor wafers are required to be sufficiently separated from each other, such as manufacture of FO-WLP.

Second, the present invention provides a sheet for semiconductor processing, which is a sheet for semiconductor processing including at least a base material, wherein the sheet for semiconductor processing is measured at 23° C. in the MD direction of the base material. 100% stress, the ratio of the 100% stress to the 100% stress of the above-mentioned sheet for semiconductor processing measured in the CD direction of the above-mentioned substrate at 23° C. is 0.8 or more and 1.2 or less, and the above-mentioned 100% stress refers to the above-mentioned sheet for semiconductor processing. A test piece of 150 mm × 15 mm was cut out, and the two ends in the longitudinal direction were clamped by the clamps so that the length between the clamps was 100 mm, and then the test pieces were stretched along the longitudinal direction at a speed of 200 mm/min until the length between the clamps was 100 mm. The measured value of the tensile force when the length was 200 mm was calculated by dividing the quotient of the cross-sectional area of the sheet for semiconductor processing (Invention 2).

According to the above invention (Invention 2), by making the ratio of 100% stress within the above range, it is possible to greatly extend. Therefore, it can be suitably used for applications in which semiconductor wafers are sufficiently separated from each other, for example, in the production of FO-WLP.

Third, the present invention provides a sheet for semiconductor processing, which is a sheet for semiconductor processing including at least a base material, wherein the sheet for semiconductor processing is measured in the MD and CD directions of the base material at 23° C. The tensile modulus of elasticity of the sheet is 10 MPa or more and 350 MPa or less, respectively, and the 100% stress of the semiconductor processing sheet measured in the MD direction and CD direction of the substrate at 23°C is 3 MPa or more and 20 MPa, respectively. Hereinafter, the above-mentioned 100% stress is obtained by cutting out the test piece of 150 mm×15 mm from the above-mentioned sheet for semiconductor processing, and sandwiching both ends in the longitudinal direction with the jigs so that the length between the jigs becomes 100 mm. The measured value of the tensile force when the length between the jigs becomes 200 mm is obtained by dividing the cross-sectional area quotient of the semiconductor processing sheet in the longitudinal direction at a speed of min. The elongation at break of the above-mentioned sheet for semiconductor processing measured in the MD direction and the CD direction is 100% or more, respectively (Invention 3).

According to the above invention (Invention 3), by making the tensile modulus of elasticity and the elongation at break within the above-mentioned ranges, it is possible to greatly extend. Therefore, it can be suitably used for applications in which semiconductor wafers are required to be sufficiently separated from each other, such as manufacture of FO-WLP.

In the above inventions (Inventions 1 to 3), it is preferable to further include an adhesive layer laminated on at least one surface of the base material (Invention 4).

In the above inventions (Inventions 1 to 4), the substrate preferably contains a thermoplastic elastomer (Invention 5).

In the above invention (Invention 5), the thermoplastic elastomer is preferably a urethane-based elastomer (Invention 6).

In the above-mentioned inventions (Inventions 1 to 6), the adjacent semiconductor wafers are used for the plurality of semiconductor wafers stacked on one surface of the above-mentioned semiconductor processing sheet. The distance between the sheets is preferably expanded to 200 μm or more and 6000 μm or less (Invention 7).

In the above inventions (Inventions 1 to 7), tension is applied in four directions: +X-axis direction, -X-axis direction, +Y-axis direction, and -Y-axis direction of the X-axis and Y-axis which are orthogonal to each other. It is preferable to stretch the sheet for semiconductor processing, and to expand the interval of the plurality of semiconductor wafers stacked on one side of the sheet for semiconductor processing (Invention 8).

In the above-mentioned inventions (Inventions 1 to 8), there is provided a step of disposing a plurality of individual semiconductor wafers on one side of an adhesive sheet; The manufacturing method of a semiconductor device according to the steps is preferable as the above-mentioned adhesive sheet (Invention 9).

In the above inventions (Inventions 1 to 9), it is preferable to use them for manufacturing a fan-out semiconductor wafer level package (Invention 10).

The sheet piece for semiconductor processing of the present invention can be greatly extended, and the semiconductor wafers can be sufficiently separated from each other.

W‧‧‧Semiconductor Wafer

W1‧‧‧circuit surface

W2‧‧‧circuit

W3‧‧‧Back

W4‧‧‧Internal terminal electrode

W5‧‧‧ditch

W6‧‧‧Back

CP‧‧‧Semiconductor Chip

1‧‧‧Semiconductor Packaging

3‧‧‧Sealing body

4A‧‧‧First insulating layer

4B‧‧‧Second insulating layer

5‧‧‧Rewiring layer

5A‧‧‧External electrode pad

6‧‧‧External terminal electrode

10‧‧‧First adhesive plate

11‧‧‧First substrate film

12‧‧‧First Adhesive Layer

20‧‧‧Second adhesive plate

21‧‧‧Second substrate film

22‧‧‧Second adhesive layer

30‧‧‧Protection plate

40‧‧‧Surface protection sheet

41‧‧‧Fourth substrate film

42‧‧‧The fourth adhesive layer

50‧‧‧grinding machine

60‧‧‧Sealing components

100‧‧‧Extensions

101, 101A, 101B, 101C‧‧‧Maintaining means

200‧‧‧Semiconductor processing sheet

FIG. 1 is a cross-sectional view illustrating a first aspect of a method of using a sheet for semiconductor processing according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a first aspect of the method of using the sheet for semiconductor processing according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a first aspect of the method of using the sheet for semiconductor processing according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a second aspect of the method of using the sheet for semiconductor processing according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a second aspect of the method of using the sheet for semiconductor processing according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a second aspect of the method of using the sheet for semiconductor processing according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a second aspect of the method of using the sheet for semiconductor processing according to the embodiment of the present invention.

Fig. 8 is a plan view illustrating the 2-axis extension device used in the embodiment.

Embodiments of the present invention will be described below.

The sheet for semiconductor processing according to the present embodiment is configured to include at least a base material.

The recovery rate of the sheet for semiconductor processing according to the present embodiment is preferably 70% or more and 100% or less.

In this specification, the so-called recovery rate is calculated as follows. First, the sheet piece for semiconductor processing was cut out to 150 mm×15 mm to obtain a test piece. This cutting out was performed in the MD direction of the base material of the sheet|seat for semiconductor processing, which matched the longitudinal direction of a test piece. Next, both ends in the longitudinal direction of the test piece were clamped with jigs so that the length between the jigs was 100 mm. Let the length between the jigs at this time be the length L0 (mm) between the initial jigs. Next, the space between the clamps was stretched in the longitudinal direction at a speed of 200 mm/min, and the state where the space between the clamps was 200 mm was maintained for 1 minute. The length between the clamps after expansion to 200mm is subtracted from the length between the initial clamps The length of L0 (mm) (that is, 100 mm) is set as the expansion length L1 (mm) (=100 mm). After holding for 1 minute, the length between the jigs was recovered at a speed of 200 mm/min, and the length between the jigs was kept at 100 mm (ie, L0 (mm)) for 1 minute. After that, the length between the jigs was drawn at a speed of 60 mm/min in the longitudinal direction, and the measured value of the recorded tensile force showed the length between the jigs at 0.1 N/15 mm. The value obtained by subtracting the initial length L0 (mm) between the jigs from this length is set to L2 (mm). By inserting the values of L1 and L2 obtained above, the recovery rate (%) is obtained

Recovery rate (%)={1-(L2÷L1)}×100...(I)

In addition, in this tensile test, the thickness of the test piece is not particularly limited, and may be the same as the thickness of the test piece for semiconductor processing. In addition, the specific measurement method is shown in the test example mentioned later.

In addition, regarding the sheet for semiconductor processing of the present embodiment, the 100% stress of the sheet for semiconductor processing measured at 23° C. in the MD direction of the base material is compared to the 100% stress measured at 23° C. in the CD direction of the base material. The 100% stress ratio of the sheet for semiconductor processing is preferably 0.8 or more and 1.2 or less. Here, the MD direction refers to the flow direction at the time of manufacture of the base material, and the CD direction refers to the direction perpendicular to the MD direction.

In this specification, the so-called 100% stress is calculated as follows. Cut out a test piece of 150 mm × 15 mm from the above-mentioned sheet for semiconductor processing, clamp both ends in the longitudinal direction with clamps, make the length between the clamps 100 mm, and stretch at a speed of 200 mm/min in the longitudinal direction until the clamps The 100% strength shown by the tensile strength (measured value of tensile force) when the length of the gap is 200 mm is calculated by dividing the 100% stress (MPa) obtained by dividing the cross-sectional area quotient of the sheet for semiconductor processing. The cutting out is based on the flow method during the manufacture of the sheet for semiconductor processing. The direction (MD direction) or the direction orthogonal to the MD direction (CD direction) is carried out in accordance with the longitudinal direction of the test piece. In addition, in this tensile test, the thickness of the test piece is not particularly limited, and may be the same as the thickness of the test piece for semiconductor processing. In addition, the specific measurement method is shown in the test example mentioned later.

In addition, in the sheet for semiconductor processing according to the present embodiment, it is preferable that the tensile modulus of elasticity of the sheet for semiconductor processing measured in the MD direction and CD direction of the base material at 23° C. is 10 MPa or more and 350 MPa, respectively. Hereinafter, the 100% stress of the sheet for semiconductor processing measured in the MD and CD directions of the substrate at 23°C is 3 MPa or more and 20 MPa or less, respectively, and the 100% stress measured in the MD and CD directions of the substrate at 23°C The elongation at break of the semiconductor processing sheet is more than 100%, respectively.

Since the sheet for semiconductor processing of the present embodiment has the above-mentioned physical properties, it can be easily stretched without breaking, and as a result, it can be greatly stretched.

In particular, when the above-mentioned recovery rate is in the above-mentioned range, it means that recovery is easy after the sheet for semiconductor processing is largely stretched. In general, when a plate having a yield point is extended beyond the yield point, the plate undergoes plastic deformation, and the plastically deformed portion, that is, the extremely extended portion, is in a state of uneven distribution. When the sheet piece in such a state is further stretched, a break occurs from the portion extending from the above-mentioned extreme extent, and even if the break does not occur, the spread becomes uneven. In addition, in a stress-strain diagram that plots strain on the x-axis and elongation on the y-axis, even the slope dx/dy does not obtain a stress value that changes from a positive value to a 0 or a negative value, and does not Plates exhibiting a well-defined yield point will still undergo plastic deformation as the amount of stretch increases, and likewise fracture, or spread unevenly. On the other hand, when not plastic deformation occurs, but elastic deformation occurs, By removing the stress, the pattern is easily restored to its original shape. Therefore, the recovery rate is an index representing the degree of recovery after 100% elongation with a sufficiently large stretching amount. By setting the recovery rate in the above-mentioned range, when the sheet for semiconductor processing is greatly stretched, the film can be The plastic deformation is suppressed to a minimum, fracture is not easy to occur, and it can be expanded uniformly.

In addition, when the ratio of 100% stress is in the above range, and when the tensile modulus, 100% stress and elongation at break are in the above range, when the sheet for semiconductor processing is extended in the MD and CD directions of the base material (Hereinafter, such stretching may be referred to as "biaxial stretching".) It is unlikely to be broken and can be greatly stretched.

In the above-mentioned sheet for semiconductor processing, specifically, the mutual distance between the semiconductor wafers can be separated by a distance of 200 μm or more. Such a sheet for semiconductor processing can be suitably used for a manufacturing method of a semiconductor device in which the distance between semiconductor wafers is sufficiently widened, such as a manufacturing method of FO-WLP.

1. Physical properties of wafers for semiconductor processing

In the sheet for semiconductor processing according to the present embodiment, the recovery rate is preferably 70% or more, particularly 80% or more, and more preferably 85% or more. In addition, the recovery rate is preferably 100% or less. By setting the recovery rate in the above-mentioned range, as described above, the sheet for semiconductor processing can be greatly stretched.

Regarding the sheet for semiconductor processing of the present embodiment, the 100% stress of the sheet for semiconductor processing measured in the MD direction of the substrate at 23° C. is measured in the CD direction of the substrate at 23° C. The ratio of the 100% stress of the plate is preferably above 0.8, especially preferably above 0.83. More preferably, it is 0.85 or more. In addition, the ratio is preferably 1.2 or less, particularly preferably 1.17 or less, and more preferably 1.15 or less. By setting the 100% stress ratio in the above range, even when stress is easily applied only in a specific direction when the sheet for semiconductor processing is extended biaxially, the sheet for semiconductor processing can be suppressed from breaking. As a result, the sheet for semiconductor processing can be extended larger.

Regarding the sheet for semiconductor processing of the present embodiment, the elongation at break of the sheet for semiconductor processing measured at 23° C. in the CD direction of the substrate is preferably 100% or more, particularly preferably 150% or more. Further more preferably 200% or more. In addition, the elongation at break is preferably 1200% or less, especially 1000% or less. By making this breaking elongation into the said range, the sheet|seat for semiconductor processing can be extended largely in the CD direction of a base material. In addition, the measuring method of the breaking elongation in CD direction is as shown in the test example mentioned later.

Regarding the sheet for semiconductor processing of the present embodiment, the elongation at break of the sheet for semiconductor processing measured in the MD direction of the substrate at 23° C. is preferably 100% or more, particularly preferably 150% or more. Further more preferably 200% or more. In addition, the elongation at break is preferably 1200% or less, especially 1000% or less. By setting the elongation at break in the above-mentioned range, the sheet for semiconductor processing can be greatly extended in the MD direction of the base material. In addition, the measuring method of the elongation at break in the MD direction is as shown in the test example described later.

Regarding the sheet for semiconductor processing of the present embodiment, the tensile modulus of elasticity of the sheet for semiconductor processing measured at 23° C. in the CD direction of the substrate is preferably 10 MPa or more, particularly preferably 20 MPa or more. More preferably, it is 25 MPa or more. In addition, the tensile modulus of elasticity is preferably 350 MPa or less, particularly 300 MPa or less, and more preferably 250 MPa or less. good. When the said tensile elastic modulus is 10 MPa or more, when a semiconductor wafer etc. are laminated|stacked on the sheet|seat for semiconductor processing, the said semiconductor wafer etc. can be supported favorably. Moreover, by making the said tensile elastic modulus 350 MPa or less, the sheet|seat for semiconductor processing can have suitable flexibility, and the sheet|seat for semiconductor processing can be extended more easily. In addition, the measuring method of the said tensile elastic modulus is shown in the test example mentioned later.

Regarding the sheet for semiconductor processing of the present embodiment, the tensile modulus of elasticity of the sheet for semiconductor processing measured in the MD direction of the substrate at 23° C. is preferably 10 MPa or more, particularly preferably 20 MPa or more. More preferably, it is 25 MPa or more. The tensile modulus of elasticity is preferably 350 MPa or less, particularly 300 MPa or less, and more preferably 250 MPa or less. When the said tensile elastic modulus is 10 MPa or more, when a semiconductor wafer etc. are laminated|stacked on the sheet|seat for semiconductor processing, the said semiconductor wafer etc. can be supported favorably. Moreover, by making the said tensile elastic modulus 350 MPa or less, the sheet|seat for semiconductor processing can have suitable flexibility, and the sheet|seat for semiconductor processing can be extended more easily. In addition, the measuring method of the said tensile elastic modulus is shown in the test example mentioned later.

Regarding the sheet for semiconductor processing of the present embodiment, the 100% stress of the sheet for semiconductor processing measured in the CD direction of the substrate at 23° C. is preferably 3 MPa or more, particularly preferably 5 MPa or more, and further Better than 6MPa. By making the 100% stress 3 MPa or more, even if the thickness of the substrate is reduced by greatly extending the sheet for semiconductor processing, the force required to support the separated wafer can be maintained. In addition, the 100% stress is preferably 20 MPa or less, particularly preferably 18 MPa or less, and more preferably 16 MPa or less. By setting the 100% stress to 20 MPa or less, the sheet for semiconductor processing can be greatly extended without applying an excessive load to the expansion device, and even if the device is continuously used for a long time, it can be expected to prevent the failure of the device. In addition, the measuring method of the 100% stress in CD direction is as shown in the test example mentioned later.

Regarding the sheet for semiconductor processing of the present embodiment, the 100% stress of the sheet for semiconductor processing measured in the MD direction of the substrate at 23° C. is preferably 3 MPa or more, particularly preferably 5 MPa or more, and further Better than 6MPa. By making the 100% stress 3MPa or more, even if the thickness of the substrate is reduced by greatly extending the sheet for semiconductor processing, the force required to support the separated wafer can be maintained, and the sheet for semiconductor processing can be moved along the The CD direction of the base material is greatly extended. In addition, the 100% stress is preferably 20 MPa or less, particularly preferably 18 MPa or less, and more preferably 16 MPa or less. By setting the 100% stress to 20 MPa or less, the sheet for semiconductor processing can be greatly extended without applying an excessive load to the expansion device, and even if the device is continuously used for a long time, it can be expected to prevent the failure of the device. In addition, the measuring method of the 100% stress in MD direction is as shown in the test example mentioned later.

It is preferable that at least one surface of the sheet for semiconductor processing of the present embodiment has adhesiveness. Thereby, a semiconductor chip etc. can be attached and fixed to this surface. In addition, in this specification, the surface which has adhesiveness to the sheet|seat for semiconductor processing, and adheres a semiconductor wafer etc. may be called "adhesion surface." The adhesive force of the semiconductor processing sheet of the present embodiment is preferably 300 mN/25 mm or more, particularly 800 mN/25 mm or more, and more preferably 1000 mN/25 mm or more. In addition, the adhesive force is preferably 30000mN/25mm or less, especially 15000mN/25mm or less, and further 10000mN/25mm or less better. By making this adhesive force 300mN/25mm or more, a semiconductor chip etc. can be adhered and fixed favorably. In addition, by setting the adhesive force to be 30,000 mN/25mm or less, it is possible to satisfactorily carry out exchanging semiconductor wafers and the like from the sheet for semiconductor processing related to this embodiment to another adhesive sheet; The sheet for semiconductor processing according to the embodiment is transferred to a holding member capable of adsorbing and holding semiconductor wafers and the like, and the semiconductor wafers and the like are picked up from the sheet for semiconductor processing according to the present embodiment. In addition, the adhesive force in this specification refers to the adhesive force (mN/25mm) measured according to the 180° peeling method of JIS Z0237:2009 using a silicon mirror wafer as a substrate. In addition, when the sheet for semiconductor processing of the present embodiment is formed from only the base material, the adhesive force is measured on one side of the base material; for the sheet for semiconductor processing of the present embodiment, the adhesive force is measured from the base material When the adhesive layer described later is formed, the adhesive force is measured on the surface of the adhesive layer on the opposite side to the substrate.

The sheet for semiconductor processing according to the present embodiment preferably has heat resistance. When a wafer level package is manufactured using the sheet for semiconductor processing according to the present embodiment, the semiconductor wafer may be sealed with a sealing member on the sheet for semiconductor processing according to the present embodiment. Generally, a thermosetting material is used as the sealing member, and the material is heated during sealing. By making the sheet for semiconductor processing heat resistant, deformation of the sheet for semiconductor processing due to heating can be suppressed.

The thickness of the sheet for semiconductor processing according to the present embodiment is preferably 30 μm or more, and particularly preferably 50 μm or more. In addition, the thickness is preferably 300 μm or less, and particularly preferably 250 μm or less for sealing.

2. Substrate

The base material of the sheet for semiconductor processing of the present embodiment is not particularly limited as long as the sheet for semiconductor processing can achieve the above-mentioned physical properties, and its constituent material is not particularly limited, but is usually formed of a film mainly composed of a resin-based material. In particular, it is preferable to use a thermoplastic elastomer or a rubber-based material as the material of the base material from the viewpoint that the above-mentioned physical properties can be easily achieved, and among these, the use of a thermoplastic elastomer is particularly useful from the viewpoint that the above-mentioned physical properties can be easily achieved. good. In addition, from the viewpoint of easily attaining the above-mentioned physical properties, it is preferable to use a resin having a relatively low glass transition temperature (Tg) as a constituent material of the base material. In particular, the glass transition temperature (Tg) of such a resin is 90° C. The temperature is preferably below, particularly preferably 80°C or lower, and more preferably 70°C or lower.

Examples of the thermoplastic elastomer include urethane-based elastomers, olefin-based elastomers, vinyl chloride-based elastomers, polyester-based elastomers, styrene-based elastomers, acrylic-based elastomers, amide-based elastomers, and the like. Among these, it is preferable to use a urethane-based elastomer from the viewpoint of achieving the above-mentioned physical properties more easily.

Urethane-based elastomers are generally obtained by reacting long-chain polyols, chain extenders, and diisocyanates, and are composed of soft segments having structural units derived from long-chain polyols, chain extenders, and diisocyanates. It is composed of hard segments of the polyurethane structure obtained by the reaction.

Urethane-based elastomers can be classified into polyester-based polyurethane elastomers and polyether-based polyurethanes according to the type of long-chain polyol used as a soft segment component. Elastomers, polycarbonate-based polyurethane elastomers, etc. Among the sheets for semiconductor processing according to the present embodiment, polyether-based polyurethanes are used from the viewpoint of being easy to achieve the above-mentioned physical properties. Ethyl ester elastomers are preferred.

Examples of the above-mentioned long-chain polyols include polyester polyols such as lactone-based polyester polyols and adipate-based polyester polyols; polypropylene (ethylene) polyols, polytetramethylene ether diols Polyether polyols of alcohols, etc.; polycarbonate polyols, etc. Among these, it is preferable to use an adipate-based polyester polyol from the viewpoint of achieving the above-mentioned physical properties more easily.

As an example of the said diisocyanate, 2, 4- toluene diisocyanate, 2, 6- toluene diisocyanate, 4, 4'- diphenylmethane diisocyanate, hexamethylene diisocyanate, etc. are mentioned. Among these, it is preferable to use hexamethylene diisocyanate from the viewpoint of achieving the above-mentioned physical properties more easily.

As said chain extension agent, 1, 4- butanediol, the low molecular weight polyol of 1, 6- hexanediol, and aromatic diamine are mentioned. Among these, it is preferable to use 1,6-hexanediol from the viewpoint of easily attaining the above-mentioned physical properties.

Examples of the olefin-based elastomer include copolymers selected from the group consisting of ethylene·α-olefin copolymers, propylene·α-olefin copolymers, butene·α-olefin copolymers, ethylene·propylene·α-olefin copolymers, ethylene·butene ‧Alpha-olefin copolymer, propylene‧butene‧alpha-olefin copolymer, ethylene‧propylene‧butene‧alpha-olefin copolymer, styrene‧isoprene copolymer and styrene‧ethylene‧butene copolymer At least one resin of the group consisting of.

^{The density of the olefin-based elastomer is not particularly limited, but it is 0.860 g/cm 3} or more, not less than 0.860 g/cm 3 , from the viewpoint of more stably obtaining a substrate that is excellent in conformability to irregularities when a semiconductor wafer is attached to a sheet for semiconductor processing. full 0.905g / cm ³ preferably to 0.862g / cm ³ or more and less than 0.900g / cm ³ is more preferred to 0.864g / cm ³ or more, less than 0.895g / cm ³ or less is particularly preferred.

In the olefin-based elastomer, the mass ratio of the monomer composed of the olefin-based compound among all the monomers used to form the elastomer (in this specification, it is also referred to as "the olefin content ratio".) is 50 to 100. Mass % is better. When the olefin content is too low, it becomes difficult to exhibit the properties of an elastomer including a structural unit derived from an olefin, and it becomes difficult to exhibit flexibility or rubber elasticity. From the viewpoint of stably obtaining this effect, the olefin content is preferably 50 mass % or more, more preferably 60 mass % or more.

As a styrene-type elastomer, a styrene-conjugated diene copolymer, a styrene-olefin copolymer, etc. are mentioned. Specific examples of styrene-conjugated diene copolymers include styrene-butadiene copolymers, styrene-butadiene-styrene copolymers (SBS), styrene-butadiene-butene- Unhydrogenated styrene copolymers, styrene-isoprene copolymers, styrene-isoprene-styrene copolymers (SIS), styrene-ethylene-isoprene-styrene copolymers, etc. Styrene-conjugated diene copolymer; styrene-ethylene/propylene-styrene copolymer (SEPS, hydrogenated product of styrene-isoprene-styrene copolymer), styrene-ethylene-butylene- Hydrogenated styrene-conjugated diene copolymers such as styrene copolymers (SEBS, hydrogenated products of styrene-butadiene copolymers) and the like. In addition, industrially, Tufprene (manufactured by Asahi Kasei Co., Ltd.), Kraton (manufactured by Kraton Polymer Japan Co., Ltd.), Sumitomo TPE-SB (manufactured by Sumitomo Chemical Co., Ltd.), Epo Friend (manufactured by Daicel Chemical Industry Co., Ltd.), Rabalon (manufactured by Mitsubishi Chemical Corporation) ), Septon (manufactured by Kuraray Corporation), tuftec (manufactured by Asahi Kasei Corporation), etc. The styrene-based elastomer may be a hydrogenated product or an unhydrogenated product.

Examples of rubber-based materials include natural rubber, synthetic isoprene rubber (IR), butadiene rubber (BR), styrene-butadiene rubber (SBR), chloroprene rubber (CR), Acrylonitrile-butadiene copolymer rubber (NBR), Butyl rubber (IIR), halogenated butyl rubber, acrylic rubber, urethane rubber, polysulfide rubber, etc., may be used alone or in combination of two or more.

As the base material, a thin film formed by laminating a plurality of layers of the above-mentioned materials can be used. Moreover, the base material which laminated|stacked the thin film formed by the above-mentioned material and another thin film can also be used.

When a plurality of layers of thin films are laminated, in order to achieve the above-mentioned physical properties, a thin film with a high contribution rate can be arranged in the center with a relatively thick thickness, and the thin film with a low contribution rate and a relatively thin thickness can be sandwiched by the above-mentioned thin film. film. In addition, it is preferable to use a resin with a relatively low glass transition temperature (Tg) to achieve the above-mentioned physical properties. However, since such a resin has high adhesiveness, when such a resin is provided on the surface of the semiconductor processing sheet, the There is a possibility that the handling may be difficult at the time of manufacture or use of the sheet for semiconductor processing. Therefore, the resin film with a relatively low glass transition temperature (Tg) can be sandwiched with a resin film with a relatively high glass transition temperature (Tg), or the resin film layer with a relatively low glass transition temperature (Tg) can be sandwiched By depositing a resin film with a relatively high glass transition temperature (Tg), the achievement of the above-mentioned physical properties and workability are coexisted.

When the sheet for semiconductor processing according to the present embodiment is composed of only a base material, it is preferable that the base material has adhesiveness. The adhesiveness can be used as a base material under normal conditions, and it is better to use a self-adhesive one.

In addition, the sheet for semiconductor processing according to the present embodiment is composed of only the base material, and when the base material is formed by laminating plural thin films, among the plural thin films to be laminated, only the thin film located in the outermost layer may be or only one of those parties is adhesive. For example, by laminating a resin having a relatively high glass transition temperature (Tg) on one side of a resin film having a relatively low glass transition temperature (Tg) The film can exhibit adhesiveness only in this aspect. In addition, in the outermost layer of the sheet|seat for semiconductor processing of this specification, the thing which will be removed at the time of use, such as a peeling sheet|seat, is not included.

The substrate of the present embodiment may contain various additives such as pigments, dyes, flame retardants, plasticizers, antistatic agents, lubricants, and fillers in the film mainly composed of the above-mentioned resin-based material. As a pigment, titanium dioxide, carbon black, etc. are mentioned, for example. Moreover, as a filler, organic materials, such as melamine resin, inorganic materials, such as fumed silica, and metal materials, such as nickel particles, can be illustrated. The content of such additives is not particularly limited, but it is preferable to maintain the content within the range in which the substrate can exhibit the desired function.

When the sheet for semiconductor processing has an adhesive layer described later, the base material may be subjected to an oxidation method or unevenness on one side or both sides, as desired, for the purpose of improving the adhesiveness with the adhesive layer laminated on the surface. Surface treatment by method, etc., or a primer layer treatment for forming a primer layer. The above-mentioned oxidation method includes, for example, corona discharge treatment, plasma discharge treatment, chromium oxidation treatment (wet type), flame treatment, hot air treatment, ozone, ultraviolet irradiation treatment, etc. In addition, the concavo-convex method includes, for example, Sandblasting, thermal spraying, etc.

In addition, when the adhesive layer contains an energy ray curable adhesive, the substrate preferably has permeability to energy rays. In particular, when ultraviolet rays are used as energy rays, the substrate preferably has penetrability to ultraviolet rays; when electron rays are used as energy rays, the substrate preferably has penetrability to electron rays.

There is no particular limitation on the method for producing the substrate for semiconductor processing according to the present embodiment, and for example, a melt extrusion method such as a casting method (melt casting method), a T-die method, or an expansion method can be used. any method. Among them, it is preferable to use the casting method to manufacture the base material from the viewpoint of easy control of the thickness error. In this case, it is preferable to cast a liquid mixture (resin before hardening, a solution of resin, etc.) of the material used as the base material on the engineering sheet to form a thin film, and then harden the coating film to form a thin film, to manufacture the base material.

The thickness of the base material is not limited as long as the sheet for semiconductor processing can function appropriately in a desired step. The thickness of the base material is preferably 20 μm or more, particularly 40 μm or more. In addition, the thickness is preferably 250 μm or less, particularly preferably 200 μm or less.

Further, when the thickness is measured at intervals of 2 cm, the standard deviation of the thickness of the base material is preferably 2 μm or less, particularly 1.5 μm or less, and more preferably 1 μm or less. By making this standard deviation 2 μm or less, the thickness of the sheet for semiconductor processing can be obtained with high precision, and the sheet for semiconductor processing can be uniformly stretched.

3. Adhesive layer

It is preferable that the sheet|seat for semiconductor processing of this embodiment further includes the adhesive bond layer laminated|stacked on at least one surface of a base material. Thereby, the sheet|seat for semiconductor processing can exhibit the desired adhesiveness easily on the surface on the side of this adhesive agent layer, and can adhere a semiconductor wafer etc. to this surface satisfactorily.

The adhesive layer is not particularly limited as long as the physical properties described above can be achieved in the sheet for semiconductor processing. The adhesive layer may be composed of a non-energy ray curable adhesive or an energy ray curable adhesive. As a non-energy ray-curable adhesive, those having desired adhesive force and releasability are preferred, and for example, acrylic adhesives, rubber-based adhesives, silicone-based adhesives, urethane-based adhesives can be used. Adhesives, polyester-based adhesives, polyvinyl ether-based adhesives, etc. Among these, an acrylic adhesive is preferable because it can effectively suppress the detachment of a semiconductor wafer or the like when extending a sheet for semiconductor processing.

On the other hand, the energy ray-curable adhesive reduces the adhesive force by curing by energy ray irradiation. Therefore, when the semiconductor wafer and the sheet for semiconductor processing are to be separated, they can be easily separated by irradiating the energy ray. .

The energy ray curable adhesive constituting the adhesive layer may be mainly composed of a polymer with energy ray curability; it may also be composed of a non-energy ray curable polymer (a polymer without energy ray curability) and A mixture of monomers and/or oligomers having at least one energy ray-curable group as a main component. In addition, it may be a mixture of a polymer having energy ray curability and a non-energy ray curable polymer; it may also be a polymer having energy ray curability, a monomer having at least one energy ray curable group, and /or a mixture of oligomers; also a mixture of these 3 kinds.

First, the case where the energy ray-curable adhesive is mainly composed of a polymer having energy ray-curability will be described below.

(Meth)acrylate (co)polymer (A) (hereinafter, sometimes referred to as energy-ray-curable polymer) having an energy-ray-curable functional group (energy-ray-curable group) introduced into its side chain "Energy ray curable polymer (A)") is preferred. The energy ray-curable polymer (A) is preferably an acrylic copolymer (a1) having a functional group-containing monomer unit, and an unsaturated group-containing compound (a2) having a functional group that can be bonded to the functional group. Recipients of the reaction. In addition, in this specification, (meth)acrylate means both acrylate and methacrylate. The same applies to other similar terms.

Acrylic copolymer (a1), preferably comprising a functional group-containing monomer A derived structural unit, and a structural unit derived from a (meth)acrylate monomer or a derivative thereof.

The functional group-containing monomer, which is a structural unit of the acrylic copolymer (a1), has a functional group such as a hydroxyl group, a carboxyl group, an amino group, a substituted amino group, an epoxy group, etc., which can be bonded to a polymerizable double bond in the molecule monomer is better.

Examples of the hydroxyl group-containing monomer include 2-hydroxyethyl (meth)acrylate, 2-hydroxypropyl (meth)acrylate, 3-hydroxypropyl (meth)acrylate, 2-hydroxypropyl (meth)acrylate, and 2-hydroxypropyl (meth)acrylate. -Hydroxybutyl ester, 3-hydroxybutyl (meth)acrylate, 4-hydroxybutyl (meth)acrylate, etc., these can be used individually or in combination of 2 or more types.

As the carboxyl group-containing monomer, for example, ethylenically unsaturated carboxylic acids such as acrylic acid, methacrylic acid, crotonic acid, maleic acid, itaconic acid, and citraconic acid can be used. These may be used alone or in combination of two or more.

Examples of the amino group-containing monomer or the substituted amino group-containing monomer include aminoethyl (meth)acrylate, n-butylaminoethyl (meth)acrylate, and the like. These may be used alone or in combination of two or more.

As the (meth)acrylate monomer constituting the acrylic copolymer (a1), other than the alkyl (meth)acrylate having 1 to 20 carbon atoms in the alkyl group, for example, in the molecular A monomer with an alicyclic structure inside (a monomer containing an alicyclic structure).

As the alkyl (meth)acrylate, especially the alkyl (meth)acrylate having 1 to 18 carbon atoms in the alkyl group, for example, methyl (meth)acrylate, (methyl) Ethyl acrylate, propyl (meth)acrylate, n-butyl (meth)acrylate, 2-ethylhexyl (meth)acrylate, and the like. These may be used individually by 1 type, and may be used in combination of 2 or more types.

As the alicyclic structure-containing monomer, for example, cyclohexyl (meth)acrylate, dicyclopentyl (meth)acrylate, adamantyl (meth)acrylate, isobornyl (meth)acrylate, Dicyclopentenyl (meth)acrylate, dicyclopentenyloxyethyl (meth)acrylate, and the like. These may be used individually by 1 type, and may be used in combination of 2 or more types.

The ratio of the acrylic copolymer (a1) containing the structural unit derived from the functional group-containing monomer is preferably 1% by mass or more, particularly preferably 5% by mass or more, and more preferably 10% by mass or more . In addition, the acrylic copolymer (a1) contains a ratio of structural units derived from the functional group-containing monomers, preferably 35% by mass or less, particularly preferably 30% by mass or less, and more preferably 25% by mass or less better.

Furthermore, the ratio of the acrylic copolymer (a1) containing the structural unit derived from the (meth)acrylate monomer or its derivative is preferably 50% by mass or more, particularly preferably 60% by mass or more , more preferably 70% by mass or more. In addition, the ratio of the acrylic copolymer (a1) containing the structural unit derived from the (meth)acrylate monomer or its derivative is preferably 99% by mass or less, particularly preferably 95% by mass or less, More preferably, it is 90 mass % or less.

Acrylic copolymer (a1) is obtained by copolymerizing the above-mentioned functional group-containing monomer with a (meth)acrylate monomer or its derivative by a conventional method, and other than these monomers , can also be copolymerized with dimethyl acrylamide, vinyl formate, vinyl acetate, styrene, etc.

By combining the acrylic copolymer (a1) having the above-mentioned functional group-containing monomer unit with an unsaturated group-containing functional group having a functional group bonded to the functional group The substance (a2) is reacted to obtain an energy ray-curable polymer (A).

The functional group which the unsaturated group-containing compound (a2) has can be appropriately selected according to the kind of the functional group of the functional group-containing monomer unit which the acrylic copolymer (a1) has. For example, when the functional group of the acrylic copolymer (a1) is a hydroxyl group, an amino group or a substituted amino group, the functional group of the unsaturated group-containing compound (a2) is preferably an isocyanate group or an epoxy group, and an acrylic acid group is preferred. When the functional group contained in the copolymer (a1) is an epoxy group, the functional group contained in the unsaturated group-containing compound (a2) is preferably an amino group, a carboxyl group, or an aziridine group.

唑啉、2-異丙烯基-2-

唑啉等。 Further, the unsaturated group-containing compound (a2) contains at least one energy ray polymerizable carbon-carbon double bond in the molecule, preferably 1 to 6, and more preferably 1 to 4. Specific examples of such an unsaturated group-containing compound (a2) include, for example, 2-methacryloyloxyethyl isocyanate, m-isopropenyl-α,α-dimethylbenzyl isocyanate, methyl Acryloyl isocyanate, allyl isocyanate, 1,1-(bisacrylooxymethyl)ethyl isocyanate; obtained by reaction of diisocyanate compound or polyisocyanate compound with hydroxyethyl (meth)acrylate Acryloyl monoisocyanate compound; Acryloyl monoisocyanate compound obtained by reaction of diisocyanate compound or polyisocyanate compound, polyol compound, and hydroxyethyl (meth)acrylate; Glycidyl (meth)acrylate ; (meth)acrylic acid, 2-(1-aziridinyl)ethyl (meth)acrylate, 2-vinyl-2-

oxazoline, 2-isopropenyl-2-

oxazoline etc.

Relative to the molar number of the functional group-containing monomer of the above-mentioned acrylic copolymer (a1), the ratio of the above-mentioned unsaturated group-containing compound (a2) used is preferably 50 mol % or more, especially 60 mol % or more. good, further to 70 mol% Above is better. In addition, with respect to the molar number of the functional group-containing monomer of the above-mentioned acrylic copolymer (a1), the proportion of the above-mentioned unsaturated group-containing compound (a2) used is preferably 95 mol % or less, especially 93 mol % The following is more preferable, and more preferably 90 mol% or less.

The reaction between the acrylic copolymer (a1) and the unsaturated group-containing compound (a2) may be based on the functional group of the acrylic copolymer (a1) and the functional group of the unsaturated group-containing compound (a2). In combination, the temperature, pressure, solvent, and time of the reaction, the presence or absence of a catalyst, and the type of catalyst are appropriately selected. Thereby, the functional group present in the acrylic copolymer (a1) reacts with the functional group present in the unsaturated group-containing compound (a2), and the unsaturated group is introduced into the side chain in the acrylic copolymer (a1). , and the energy ray hardening type polymer (A) was obtained.

The weight-average molecular weight (Mw) of the energy ray-curable polymer (A) thus obtained is preferably at least 10,000, particularly preferably at least 150,000, and more preferably at least 200,000. Further, the weight average molecular weight (Mw) is preferably 1.5 million or less, particularly preferably 1 million or less. In addition, the weight average molecular weight (Mw) in this specification is the value in terms of standard polystyrene measured by gel permeation chromatography (GPC method).

Even when the energy ray curable adhesive is mainly composed of a polymer such as an energy ray curable polymer (A) having energy ray curability, the energy ray curable adhesive may further contain energy ray curable of monomers and/or oligomers (B).

As the energy ray-curable monomer and/or oligomer (B), for example, esters of polyhydric alcohol and (meth)acrylic acid, etc. can be used.

Examples of the energy ray curable monomer and/or oligomer (B) include For example, monofunctional acrylates such as cyclohexyl (meth)acrylate, isobornyl (meth)acrylate, trimethylolpropane tri(meth)acrylate, neopentaerythritol tri(meth)acrylate, etc. base) acrylate, neopentaerythritol tetra(meth)acrylate, dipeotaerythritol hexa(meth)acrylate, 1,4-butanediol di(meth)acrylate, 1,6-hexane Polyfunctional acrylates such as glycol di(meth)acrylate, polyethylene glycol di(meth)acrylate, dimethyloltricyclodecane di(meth)acrylate, polyester oligomers (meth)acrylate, polyurethane oligo(meth)acrylate, and the like.

Energy ray curable monomer and/or oligomer in energy ray curable adhesive when energy ray curable monomer and/or oligomer (B) are formulated into energy ray curable polymer (A) The content of the substance (B) is preferably more than 0 parts by mass, particularly preferably 60 parts by mass or more, relative to 100 parts by mass of the energy ray-curable polymer (A). In addition, the content is preferably 250 parts by mass or less, particularly preferably 200 parts by mass or less, relative to 100 parts by mass of the energy ray-curable polymer (A).

Here, when using ultraviolet rays as an energy ray for curing the energy ray-curable adhesive, it is preferable to add a photopolymerization initiator (C). By using the photopolymerization initiator (C), the polymerization curing time can be reduced and light exposure.

Specific examples of the photopolymerization initiator (C) include benzophenone, acetophenone, benzoin, benzoin methyl ether, benzoin ethyl ether, benzoin isopropyl ether, benzoin isobutyl ether, benzoin benzoic acid, and benzoin benzoic acid methyl Esters, Benzoin dimethyl ketal, 2,4-diethylthioxanthone, 1-hydroxycyclohexyl phenyl ketone, benzyl diphenyl sulfide, tetramethylamine thiocarboxylate monosulfide, azobis Isobutyronitrile, benzyl, bibenzyl, diacetyl, β-chloroanthraquinone, (2,4,6-trimethylbenzyldiphenyl)phosphine oxide, 2-benzothiazole-N,N-di Ethyl dithiocarbamate, oligo{2-hydroxy-2-methyl yl-1-[4-(1-propenyl)phenyl]acetone}, 2,2-dimethoxy-1,2-diphenylethan-1-one. These may be used alone or in combination of two or more.

The usage amount of the photopolymerization initiator (C) refers to the energy ray curable copolymer (A) (when the energy ray curable monomer and/or oligomer (B) is prepared, the energy ray curable copolymer The total amount of the substance (A) and the energy ray-curable monomer and/or oligomer (B) is 100 parts by mass) 100 parts by mass, preferably 0.1 part by mass or more, particularly 0,5 part by mass or more. In addition, the usage-amount of the photopolymerization initiator (C) refers to the energy ray hardening type copolymer (A) (when the energy ray hardening monomer and/or oligomer (B) is prepared) The total amount of the type copolymer (A) and the energy ray-curable monomer and/or oligomer (B) is 100 parts by mass) 100 parts by mass, preferably 10 parts by mass or less, particularly preferably 6 parts by mass or less.

In the energy ray-curable adhesive, other components may be appropriately blended in addition to the above-mentioned components. As other components, a non-energy ray curable polymer component, an oligomer component (D), a bridge|crosslinking agent (E), etc. are mentioned, for example.

Examples of the non-energy ray-curable polymer component or oligomer component (D) include polyacrylates, polyesters, polyurethanes, polycarbonates, polyolefins, and the like. The weight average molecular weight (Mw) A polymer or oligomer of 30 million to 2.5 million is preferred. By blending the component (D) in the energy ray-curable adhesive, the adhesiveness and peelability before curing, the strength after curing, adhesion to other layers, storage stability, and the like can be improved. The compounding quantity of this component (D) is not specifically limited, It can be determined suitably in the range exceeding 0 mass part and 50 mass parts or less with respect to 100 mass parts of energy-beam curable copolymer (A).

唑啉化合物、金屬烷氧化合物、金屬螯合物化合物、金屬鹽、銨鹽、反應性酚樹脂等。 As a bridge|crosslinking agent (E), the polyfunctional compound which has reactivity with the functional group which an energy ray hardening-type copolymer (A) etc. have can be used can be used. Examples of such polyfunctional compounds include isocyanate compounds, epoxy compounds, amine compounds, melamine compounds, aziridine compounds, hydrazine compounds, aldehyde compounds,

oxazoline compounds, metal alkoxy compounds, metal chelate compounds, metal salts, ammonium salts, reactive phenol resins, and the like.

The blending amount of the bridging agent (E) is preferably 0.01 part by mass or more, particularly preferably 0.03 part by mass or more, more preferably 0.04 part by mass or more, relative to 100 parts by mass of the energy ray-curable copolymer (A). . In addition, the compounding amount of the bridging agent (E) is preferably 8 parts by mass or less, particularly preferably 5 parts by mass or less, and further preferably 3.5 parts by mass or less with respect to 100 parts by mass of the energy ray-curable copolymer (A). better.

Next, the case where the energy ray-curable adhesive is mainly composed of a mixture of a non-energy ray-curable polymer component and a monomer and/or oligomer having at least one energy ray-curable group will be explained as follows .

As the non-energy ray-curable polymer component, for example, the same components as those of the above-mentioned acrylic copolymer (a1) can be used.

The monomer and/or oligomer having at least one or more energy ray-curable groups can be selected from those similar to those of the above-mentioned component (B). The blending ratio of the non-energy ray-curable polymer component to the monomer and/or oligomer having at least one energy ray-curable group has at least 100 parts by mass of the non-energy ray-curable polymer component. The monomer and/or oligomer of one or more energy ray-curable groups is preferably 1 part by mass or more, particularly preferably 60 parts by mass or more. In addition, the mixing ratio is preferably 200 parts by mass or less of monomers and/or oligomers having at least one energy ray-curable group relative to 100 parts by mass of the non-energy ray-curable polymer component, especially It is preferably 160 parts by mass or less.

In this case, the photopolymerization initiator (C) and the bridging agent (E) can be appropriately prepared in the same manner as described above.

The thickness of the adhesive layer is not particularly limited, but for example, it is preferably 3 μm or more, and particularly preferably 5 μm or more. In addition, the thickness is preferably 50 μm or less, particularly 40 μm or less.

4. Peel off the plate

With regard to the sheet for semiconductor processing of the present embodiment, a release sheet may be laminated on the surface for the purpose of protecting the adhesive surface until the adhesive surface is attached to a substrate such as a semiconductor wafer. The structure of the peeling sheet is arbitrary, and a plastic film subjected to peeling treatment with a peeling agent or the like can be exemplified. Specific examples of plastic films include polyester films such as polyethylene terephthalate, polybutylene terephthalate, and polyethylene naphthalate, and polypropylene or polyethylene films. Polyolefin film. As a release agent, a silicone type, a fluorine type, a long-chain alkyl type, etc. can be used, and among these, a silicone type which can obtain stable performance at low cost is preferable. Although there is no restriction|limiting in particular about the thickness of a peeling sheet, Usually, it is about 20-250 micrometers.

5. Manufacturing method of sheet for semiconductor processing

The sheet for semiconductor processing of the present embodiment can be manufactured in the same manner as the sheet for conventional semiconductor processing. In particular, as a method for producing a sheet for semiconductor processing formed from a substrate and an adhesive layer, as long as the adhesive layer formed of the above-mentioned adhesive composition is laminated on one surface of the substrate, the details The method is not particularly limited. As an example, a coating liquid containing an adhesive composition constituting an adhesive layer and, if desired, further containing a solvent or a dispersing agent can be prepared, and a die coater or curtain coating can be used on one side of the substrate. The coating liquid is applied by cloth machine, spray coater, slit coater, knife coater, etc. to form a coating film, and the The coating film dries, thereby forming an adhesive layer. The properties of the coating liquid are not particularly limited as long as it can be applied, and when it contains a component for forming an adhesive layer as a solute, it may be contained as a dispersoid.

In addition, as another example of the manufacturing method of the sheet for semiconductor processing, the coating liquid is applied to the peeling surface of the peeling sheet to form a coating film, which is dried to form an adhesive layer and a peeling sheet. The laminated body is bonded to the base material on the surface of the laminated body on the opposite side to the surface on the release sheet side of the adhesive layer to obtain a laminated body of the sheet for semiconductor processing and the release sheet. The peeling sheet of the laminate can be peeled off as a process material, so that the adhesive layer can be protected until a semiconductor wafer, a semiconductor wafer, or the like to be attached.

When the coating liquid contains a bridging agent, the non-energy ray-curable acrylic adhesive (N) or the energy ray-curable adhesive in the coating film can be cured by changing the above-mentioned drying conditions (temperature, time, etc.) or setting heat treatment separately. The adhesive (A) may undergo a bridging reaction with the bridging agent to form a bridging structure at a desired density in the adhesive layer. In order to make this bridging reaction sufficiently proceed, after laminating the adhesive layer on the base material by the above-mentioned method or the like, the obtained sheet for semiconductor processing may be allowed to stand, for example, in an environment of 23° C. and 50% relative humidity for several days. to mature.

6. How to use the sheet for semiconductor processing

The sheet for semiconductor processing according to the present embodiment can be used, for example, to widen the interval between a plurality of semiconductor wafers stacked on one surface of the sheet for semiconductor processing.

In particular, it is preferable to widen the mutual interval between adjacent semiconductor wafers between a plurality of semiconductor wafers stacked on one surface of the semiconductor processing sheet to 200 μm or more. Furthermore, the upper limit of the interval is not particularly limited, It can be, for example, 6000 μm.

In addition, the sheet for semiconductor processing according to the present embodiment can be used when extending at least two axes to widen the interval between a plurality of semiconductor wafers stacked on one surface of the sheet for semiconductor processing. At this time, the sheet for semiconductor processing is stretched, for example, by applying tension in four directions of the X axis and the Y axis that are orthogonal to each other: the +X axis direction, the -X axis direction, the +Y axis direction, and the -Y axis direction. More specifically, it stretches along the MD direction and CD direction of the base material, respectively.

The biaxial stretching as described above can be performed, for example, using a separation device that applies tension in the X-axis direction and the Y-axis direction. Here, the X axis and the Y axis are orthogonal, one of the directions parallel to the X axis is the +X axis direction, the direction opposite to the +X axis direction is the -X axis direction, and one of the directions parallel to the Y axis is the -X axis direction. One of them is the +Y-axis direction, and the direction opposite to the +Y-axis direction is the -Y-axis direction.

The above-mentioned separation device preferably applies tension to four directions of +X-axis direction, -X-axis direction, +Y-axis direction, and -Y-axis direction to the sheet for semiconductor processing, and each of the four directions has a plurality of holding means, and the means for applying the corresponding plural tensions. In each direction, the number of the holding means and the tension applying means can be determined according to the size of the sheet for semiconductor processing, and may be, for example, about 3 or more and 10 or less.

Here, for example, in a group including a plurality of holding means and a plurality of tensioning means provided for applying tension in the +X axis direction, each holding means is preferably provided with a holding member for holding a semiconductor processing sheet, and each holding member is preferably provided. The tension applying means moves the holding member corresponding to the tension applying means in the +X-axis direction to apply tension to the sheet for semiconductor processing. Then, a plurality of tension applying means are preferably used to move the holding means in the +X-axis direction independently of each other. mode setting. In addition, it is preferable that three groups including plural holding means and plural tension applying means are provided for applying tension in the -X axis direction, +Y axis direction, and -Y axis direction, respectively, and have the same configuration. As a result, the above-described separation device can apply different magnitudes of tension to the semiconductor processing sheet for each region in the direction orthogonal to each direction.

In general, when four holding members are used to hold the sheet for semiconductor processing from four directions of the +X axis direction, the -X axis direction, the +Y axis direction, and the -Y axis direction, respectively, and extend in the four directions, For the sheet for semiconductor processing, in addition to these four directions, the combined directions of these (for example, the combined direction of the +X-axis direction and the +Y-axis direction, the combined direction of the +Y-axis direction and the -X-axis direction, Tension is also applied in the combined direction of the -X axis direction and the -Y axis direction, and the combined direction of the -Y axis direction and the +X axis direction). As a result, the interval between the semiconductor wafers on the inner side of the sheet for semiconductor processing and the interval between the semiconductor wafers on the outer side may be different.

However, in the above separation device, since the plurality of tension applying means can apply tension to the semiconductor processing plate independently in each of the +X axis direction, the -X axis direction, the +Y axis direction, and the -Y axis direction. The sheet piece for semiconductor processing can be extended so that the difference of the space|interval of the inner side and the outer side of the sheet piece for semiconductor processing as mentioned above may be eliminated. As a result, the spacing of the semiconductor wafers can be adjusted correctly.

It is preferable that the above-mentioned separation apparatus further includes a measuring means for measuring the mutual distance between the semiconductor wafers. Here, the tension applying means is preferably provided so that the plurality of holding members can be moved individually based on the measurement results of the measurement means. Thereby, the interval can be further adjusted based on the measurement result of the interval between the semiconductor wafers by the above-mentioned measuring means, and as a result, the half can be adjusted more accurately. spacing of conductor wafers.

Furthermore, in the above-mentioned separation device, the holding means may be a mechanical chuck, a chuck means such as a clamping cylinder, a pressure reducing means such as a decompression pump or a vacuum aspirator, or may be a bonding agent, Magnetic force etc. support the structure of the sheet for semiconductor processing. In addition, it can also be used as a holding member in the chuck means. For example, there is a structure including a lower support member that supports the semiconductor processing plate from the bottom, a drive device supported by the following support member, and a drive device. The output shaft supports an upper support member that can be driven by a driving machine to press the semiconductor processing plate from above. Examples of the driving device include electric devices such as rotary motors, translation motors, linear motors, uniaxial robots, and articulated robots, and actuators such as air cylinders, hydraulic cylinders, rodless cylinders, and rotary cylinders.

Moreover, in the said separation apparatus, the tension|tensile_strength applying means may be provided with a drive apparatus, and the holding member may be moved by this drive apparatus. As the driving device, the above-mentioned ones can be used. For example, the tension applying means may include a translation motor as a driving device, and an output shaft interposed between the translation motor and the holding member, and the driven translation motor may move the holding member via the output shaft.

When the space between the semiconductor wafers is widened by using the sheet for semiconductor processing according to the present embodiment, the space between the semiconductor wafers can be enlarged from a state in which the semiconductor wafers are in contact with each other, or a state in which the space between the semiconductor wafers is hardly enlarged, or the space between the semiconductor wafers can be enlarged. The distance between each other has been expanded to the predetermined distance, and the distance is further expanded.

From a state in which the semiconductor wafers are in contact with each other, or a state in which the gap between the semiconductor wafers is hardly widened, when the gap is widened, for example, by cutting After dividing the semiconductor wafer on the dicing sheet to obtain a plurality of semiconductor wafers, the plurality of semiconductor wafers are transferred from the dicing sheet to the sheet for semiconductor processing according to the present embodiment, and then the intervals between the semiconductor wafers are enlarged. Alternatively, after dividing a semiconductor wafer on the sheet for semiconductor processing according to the present embodiment to obtain a plurality of semiconductor wafers, the interval between the semiconductor wafers may be widened.

From the state where the gap between the semiconductor wafers has been widened to a predetermined gap, when the gap is further widened, another sheet for semiconductor processing is used, and it is preferable to use another sheet for semiconductor processing in the present embodiment. After the interval between the two is expanded to a predetermined interval, the semiconductor wafer is transferred from the sheet to the sheet for semiconductor processing according to the present embodiment, and then, by extending the sheet for semiconductor processing according to the present embodiment, it is possible to further Increase the spacing of semiconductor wafers. In addition, such transfer of a semiconductor wafer and extension of the sheet|seat for semiconductor processing can be repeated several times until the space|interval of a semiconductor wafer becomes a desired distance.

Furthermore, the sheet for semiconductor processing according to the present embodiment is preferably used for an application requiring relatively large separation of semiconductor wafers, and as an example of such an application, a fan-out type semiconductor wafer is preferably used. A manufacturing method of packaging-in-level (FO-WLP). As an example of the manufacturing method of such a FO-WLP, the 1st aspect and the 2nd aspect demonstrated below are mentioned.

(1) The first aspect

Hereinafter, the first aspect of the manufacturing method of the FO-WLP of the sheet for semiconductor processing according to the present embodiment will be described. In addition, in this 1st aspect, the sheet for semiconductor processing of this embodiment is used as the 2nd adhesive sheet 20 mentioned later.

In FIG. 1(A), the semiconductor wafer W attached to the first adhesive sheet 10 is shown. The semiconductor wafer W has a circuit surface W1, and a circuit W2 is formed on the circuit surface W1. The first adhesive sheet 10 is attached to the back surface W3 on the opposite side to the circuit surface W1 of the semiconductor wafer W. As shown in FIG. The first adhesive sheet 10 has a first base film 11 and a first adhesive layer 12 . The first adhesive layer 12 is laminated on the first base film 11 .

[cutting step]

FIG. 1(B) shows a plurality of semiconductor wafers CP held by the first adhesive sheet 10 .

The semiconductor wafers W held on the first adhesive sheet 10 are individualized by dicing to form a plurality of semiconductor wafers CP. To cut, use a cutting means such as a dicing saw. The cutting depth at the time of dicing is set as the sum of the thickness of the semiconductor wafer W and the first adhesive layer 12 , and the depth of the worn portion of the dicing saw. By dicing, the first adhesive layer 12 is also cut into the same size as the semiconductor wafer CP. In addition, there is a case where a slit is formed in the first base film 11 by dicing.

In addition, the dicing may be performed by irradiating the semiconductor wafer W with a laser, instead of the cutting means such as the dicing saw used above. For example, by irradiating a laser, the semiconductor wafer W can be completely cut, and individualized into a plurality of semiconductor wafers CP. Alternatively, after the modification layer is formed inside the semiconductor wafer W by irradiation of laser light, the semiconductor wafer W may be modified by stretching the first adhesive sheet 10 in the first expansion step described later. The position of the layer is broken, and the semiconductor wafer CP is individually sliced (stealth dicing). In the case of stealth dicing, it is the irradiation of laser light, for example, the laser light in the infrared light domain is focused on the surface of the semiconductor wafer W. It is irradiated at the focal point set inside. In addition, in these methods, the irradiation of the laser light can be performed from either side of the semiconductor wafer W. As shown in FIG.

[First expansion step]

In FIG. 1(C), the figure explaining the process of extending|stretching the 1st adhesive sheet 10 holding the plurality of semiconductor wafers CP (Hereinafter, it may be referred to as "the 1st expansion process.") is shown.

After the plurality of semiconductor wafers CP are separated into pieces by dicing, the first adhesive sheet 10 is stretched to widen the interval between the plurality of semiconductor wafers CP. In addition, when the stealth dicing is performed, by stretching the first adhesive sheet 10, the semiconductor wafer W is broken at the position of the modified layer, and the plurality of semiconductor wafers CP are separated into pieces, and the gap between the plurality of semiconductor wafers CP is enlarged at the same time. interval. In the first expansion step, the stretching method of the first adhesive sheet 10 is not particularly limited. As a method of stretching the first adhesive sheet 10, for example, a method of stretching the first adhesive sheet 10 by pressing an annular or circular dilator; A method of grasping and stretching the outer peripheral portion of the sheet, etc.

The first adhesive sheet 10 preferably has a tensile modulus of elasticity suitable for the above-mentioned cutting step and also suitable for the first expanding step. From this point of view, the tensile modulus of elasticity of the first adhesive sheet 10 is preferably larger than that of the second adhesive sheet 20 to be described later. In this way, the first adhesive sheet 10 can exhibit a predetermined expansibility without impairing the performance during cutting, and the second adhesive sheet 20 can exhibit better expansibility.

Furthermore, as shown in FIG. 1(C), the distance between the semiconductor wafers CP is set to D1. The distance D1 is preferably, for example, 15 μm or more and 110 μm or less.

[transfer step]

FIG. 2(A) shows a diagram explaining the step of transferring the plurality of semiconductor wafers CP to the second adhesive sheet 20 after the first spreading step (hereinafter, sometimes referred to as a “transfer step”). After the first adhesive sheet 10 is stretched to widen the distance D1 between the plurality of semiconductor wafers CP, the second adhesive sheet 20 is attached to the circuit surface W1 of the semiconductor wafer CP. Here, the sheet for semiconductor processing according to the present embodiment is used as the second adhesive sheet 20 .

The second adhesive sheet 20 has a second base film 21 and a second adhesive layer 22 . The second adhesive sheet 20 is preferably pasted in such a way that the second adhesive layer 22 covers the circuit surface W1.

The adhesive force of the second adhesive layer 22 is preferably greater than the adhesive force of the first adhesive layer 12 . If the adhesive force of the second adhesive layer 22 is large, the first adhesive sheet 10 can be easily peeled off after transferring the plurality of semiconductor wafers CP to the second adhesive sheet 20 .

The second adhesive plate 20 can be attached to the second annular frame together with the plurality of semiconductor chips CP. At this time, the second annular frame is placed on the second adhesive layer 22 of the second adhesive sheet 20, and is lightly pressed and fixed. After that, the second adhesive layer 22 exposed inside the ring shape of the second annular frame is pressed against the circuit surface W1 of the semiconductor wafer CP, and the plurality of semiconductor wafers CP are fixed to the second adhesive sheet 20 .

After the second adhesive sheet 20 is pasted, the first adhesive sheet 10 is peeled off to expose the back surfaces W3 of the plurality of semiconductor chips CP. After the first adhesive sheet 10 is peeled off, the distance D1 between the plurality of semiconductor wafers CP expanded in the first expansion step is preferably maintained.

[Second expansion step]

FIG. 2(B) is a diagram illustrating a drawing step (hereinafter, sometimes referred to as a “second expansion step”) of the second adhesive sheet 20 holding the plurality of semiconductor wafers CP.

In the second expanding step, the intervals between the plurality of semiconductor wafers CP are further expanded. In the second expansion step, the method for stretching the second adhesive sheet 20 is not particularly limited. As a method of stretching the second adhesive sheet 20, for example, a method of stretching the second adhesive sheet 20 by pressing an annular or circular dilator; A method in which the outer peripheral part of the sheet is grasped and stretched. As the latter method, for example, a biaxial stretching method using the above-mentioned separation apparatus or the like can be mentioned. Among these, from the viewpoint that the interval between the semiconductor wafers CP can be further expanded, the method of biaxial extension is preferable.

Furthermore, as shown in FIG. 2(B), the interval between the semiconductor wafers CP after the second expansion step is set to D2. The distance D2 is larger than the distance D1. The distance D2 is preferably, for example, 200 μm or more and 6000 μm or less.

[Sealing step]

FIG. 2(C) is a diagram illustrating a step (hereinafter, sometimes referred to as a “sealing step”) of sealing the plurality of semiconductor wafers CP using the sealing member 60 .

The sealing step is performed after the second expansion step. The sealing body 3 is formed by covering the plurality of semiconductor wafers CP with the sealing member 60 while leaving the circuit surface W1. The sealing member 60 is also filled between the plurality of semiconductor wafers CP. Here, since the circuit surface W1 and the circuit W2 are covered by the second adhesive sheet 20 , the circuit surface W1 can be prevented from being covered by the sealing member 60 .

Through the sealing step, plural numbers are obtained that separate each by a predetermined distance The semiconductor wafer CP is embedded in the sealing body 3 of the sealing member 60 . In the sealing step, preferably a plurality of semiconductor wafers CP are covered by the sealing member 60 in a state where the distance D2 is maintained.

After the sealing step, the second adhesive sheet 20 is peeled off to expose the circuit surface W1 of the semiconductor wafer CP and the surface 3A of the sealing body 3 which is in contact with the second adhesive sheet 20 .

[Rewiring Forming Step and External Terminal Electrode Connection Step]

FIG. 3(A) shows a cross-sectional view of the sealing body 3 after peeling off the second adhesive sheet 20 . The sealing body 3 is sequentially performed: a rewiring layer forming step of forming a rewiring layer; and a step of connecting an external terminal electrode to the formed rewiring layer. In addition, in Fig. 3(A), the internal terminal electrode W4 of the circuit W2 shown in Fig. 2(C) is shown in more detail.

Through the rewiring layer forming step and the connecting step with the external terminal electrodes, as shown in FIG. 3(B), the rewiring layer 5 connected to the internal terminal electrode W4 and the external terminal electrode connected to the rewiring layer 5 are formed 6. Specifically, it is formed as follows. First, the first insulating layer 4A is formed on the circuit surface W1 of the semiconductor wafer CP and the surface 3A of the sealing body 3 . Next, the rewiring layer 5 is formed so as to be electrically connected to the internal terminal electrode W4. Furthermore, the second insulating layer 4B covering the rewiring layer 5 is formed. At this time, the rewiring layer 5 is covered with the second insulating layer 4B, leaving the external electrode pad 5A. Finally, the external terminal electrodes 6 such as solder balls are placed on the external electrode pads 5A, and the external terminal electrodes 6 and the external electrode pads 5A are electrically connected by soldering or the like.

[Second cutting step]

In Fig. 3(C), the sealing body 3 to which the external terminal electrodes 6 are to be connected is shown and explained A cross-sectional view of the step of individualization (hereinafter, sometimes referred to as a "second dicing step"). In the second dicing step, the encapsulated body 3 is individualized in units of the semiconductor wafer CP. The method of forming the three sealed bodies into pieces is not particularly limited. For example, the sealing body can be divided into three pieces by the same method as the method of dicing the semiconductor wafer W described above. The step of forming the sealing body into three pieces can be carried out by sticking the sealing body on an adhesive sheet such as a dicing sheet.

By dividing the sealing body into three pieces, the semiconductor package 1 of the semiconductor wafer CP unit is manufactured. The semiconductor package 1 in which the external electrode pads 5A fan-out outside the area of the semiconductor wafer CP as described above are connected to the external terminal electrodes 6 is manufactured as a fan-out wafer level package (FO-WLP).

[Variation]

About the manufacturing method of the FO-WLP of the said 1st aspect, you may change a part of steps, or may abbreviate|omit a part of steps.

(2) The second aspect

Next, the second aspect of the manufacturing method of the FO-WLP of the sheet for semiconductor processing according to the present embodiment will be described. In addition, in the 2nd aspect, the sheet for semiconductor processing of this embodiment is used as the 2nd adhesive sheet 20 mentioned later.

In FIG. 4(A), the semiconductor wafer W attached to the protective sheet 30 as the third adhesive sheet is shown. The semiconductor wafer W has a circuit surface W1 as a first surface, and a circuit W2 is formed on the circuit surface W1. The protective sheet 30 is attached to the circuit surface W1 of the semiconductor wafer W. As shown in FIG. The protection plate 30 protects the circuit surface W1 and the circuit W2.

The protective sheet 30 has a third base film 31 and a third adhesive Layer 32. The third adhesive layer 32 is laminated on the third base film 31 .

[Groove formation step]

FIG. 4(B) is a diagram illustrating a step of forming a groove of a predetermined depth from the circuit surface W1 side of the semiconductor wafer W (hereinafter, sometimes referred to as a “groove forming step”).

In the groove forming step, a notch is cut into the semiconductor wafer W from the side of the protective sheet 30 using a dicing blade of a dicing device or the like. At this time, the protective sheet 30 is completely cut, and a groove W5 is formed from the circuit surface W1 of the semiconductor wafer W to a depth shallower than the thickness of the semiconductor wafer W. The grooves W5 are formed so as to divide the plurality of circuits W2 formed on the circuit surface W1 of the semiconductor wafer W. As shown in FIG. The depth of the groove W5 is not particularly limited as long as it is slightly deeper than the thickness of the intended semiconductor wafer. When the grooves W5 are formed, chips from the semiconductor wafer W are generated. In the manufacturing method of the second aspect, since the grooves W5 are formed in a state where the circuit surface W1 is protected by the protective sheet 30 , contamination or damage of the circuit surface W1 and the circuit W2 due to chips can be prevented.

[grinding step]

FIG. 4(C) is a diagram illustrating a step (hereinafter, sometimes referred to as a “grinding step”) of grinding the back surface W6 as the second surface of the semiconductor wafer W after the trench W5 is formed.

In the manufacturing method of the second aspect, before grinding, the first adhesive sheet 10 is pasted on the protective sheet 30 side. After the first adhesive sheet 10 is pasted, the semiconductor wafer W is ground from the back surface W6 side using the grinder 50 . The thickness of the semiconductor wafer W is reduced by grinding, and finally divided into a plurality of semiconductor wafers CP. Grinding is performed from the back surface W6 side until the bottom of the groove W5 is removed, The semiconductor wafer W is diced into each circuit W2. After that, back surface grinding is further performed as necessary to obtain a semiconductor wafer CP having a predetermined thickness. In the manufacturing method of the second aspect, grinding is performed until the back surface W3, which is the third surface, is exposed.

FIG. 4(D) shows a state in which the divided plural semiconductor wafers CP are held by the protective sheet 30 and the first adhesive sheet 10 . In this specification, as described above, the method of first forming the grooves W5 and then performing backside grinding to divide the semiconductor wafer W into the semiconductor wafers CP is sometimes referred to as the "first dicing method".

[Paste Step (Second Adhesive Sheet)]

FIG. 5(A) is a diagram illustrating a step of pasting the second adhesive sheet 20 on the plurality of semiconductor wafers CP after the grinding step (hereinafter, sometimes referred to as a “sticking step”).

The second adhesive sheet 20 is attached to the back surface W3 of the semiconductor chip CP. The second adhesive sheet 20 has a second base film 21 and a second adhesive layer 22 . Here, the sheet for semiconductor processing according to the present embodiment is used as the second adhesive sheet 20 .

The adhesion force of the second adhesive layer 22 to the semiconductor wafer W is better than the adhesion force of the third adhesive layer 32 to the semiconductor wafer W. If the adhesive force of the second adhesive layer 22 is large, the first adhesive sheet 10 and the protective sheet 30 can be easily peeled off.

The second adhesive plate 20 can be attached to the annular frame together with the plurality of semiconductor chips CP. At this time, an annular frame is placed on the second adhesive layer 22 of the second adhesive sheet 20, and is lightly pressed and fixed. After that, the second adhesive layer 22 exposed on the inner side of the ring shape of the ring frame is pressed against the semiconductor crystal The circuit surface W1 of the chip CP fixes the plurality of semiconductor chips CP on the second adhesive sheet 20 .

[Peeling Step (First Adhesive Sheet)]

FIG. 5(B) shows a diagram explaining a step of peeling off the first adhesive sheet 10 and the protective sheet 30 after the second adhesive sheet 20 is pasted (hereinafter, sometimes referred to as a “peeling step”.) .

In the peeling step, when the first adhesive sheet 10 is peeled off, the cut protective sheet 30 is peeled off together. The protective sheet 30 is peeled off to expose the circuit surfaces W1 of the plurality of semiconductor wafers CP. Here, as shown in FIG. 5(B), the distance between the semiconductor wafers CP divided by the pre-dicing method is set to D1. The distance D1 is preferably, for example, 15 μm or more and 110 μm or less.

[Extended step]

In FIG. 5(C), the figure explaining the process of extending|stretching the 2nd adhesive sheet 20 holding the plurality of semiconductor wafers CP (it may be called "expanding process" hereafter) is shown.

In the expanding step, the intervals between the plurality of semiconductor wafers CP are further expanded. In the expansion step, the method of stretching the second adhesive sheet 20 is not particularly limited. As a method of stretching the second adhesive sheet 20, for example, a method of stretching the second adhesive sheet 20 by pressing an annular or circular dilator; The method of grasping and stretching the outer peripheral part of the As the latter method, for example, a method of biaxially extending using the above-mentioned separation device or the like can be mentioned. Among these, from the viewpoint that the interval between the semiconductor wafers CP can be further expanded, the method of biaxial extension is preferable.

In the manufacturing method of the second aspect, as shown in FIG. 5(C), the distance between the semiconductor wafers CP after the expansion step is set to D2. Distance D2 It is larger than the distance D1. The distance D2 is preferably, for example, 200 μm or more and 6000 μm or less.

[Sealing step]

FIG. 6 is a diagram illustrating a step of sealing the plurality of semiconductor wafers CP using the sealing member 60 (hereinafter, sometimes referred to as a “sealing step”).

FIG. 6(A) shows a diagram explaining the step of adhering the surface protection sheet 40 as the fourth adhesive sheet to the plurality of semiconductor wafers CP after the expansion step.

After the second adhesive sheet 20 is stretched to expand the interval between the plurality of semiconductor chips CP to a distance D2, the surface protection sheet 40 is attached to the circuit surface W1 of the semiconductor chips CP. The surface protection sheet 40 has a fourth base film 41 and a fourth adhesive layer 42 . The surface protection plate 40 is preferably pasted in such a way that the fourth adhesive layer 42 covers the circuit surface W1.

After the surface protection sheet 40 is pasted, the second adhesive sheet 20 is peeled off to expose the back surfaces W3 of the plurality of semiconductor wafers CP. After peeling off the second adhesive sheet 20, it is preferable to maintain the distance D2 between the plurality of semiconductor wafers CP expanded in the expanding step. When preparing the energy ray polymerizable compound in the second adhesive layer 22 , it is preferable to irradiate the second adhesive layer 22 with energy rays from the side of the second base film 21 to harden the energy ray polymerizable compound, and then the second adhesive layer 22 is irradiated with energy rays The adhesive sheet 20 is peeled off.

FIG. 6(B) is a diagram illustrating a procedure of sealing the plurality of semiconductor wafers CP held by the surface protection sheet 40 .

The sealing body 3 is formed by covering the plurality of semiconductor wafers CP with the sealing member 60 while leaving the circuit surface W1. between the plurality of semiconductor wafers CP Filled with sealing member 60 . Here, since the circuit surface W1 and the circuit W2 are covered with the surface protection sheet 40 , the circuit surface W1 can be prevented from being covered by the sealing member 60 .

Through the sealing step, the sealing body 3 in which the plurality of semiconductor wafers CP separated from each other by a predetermined distance is embedded in the sealing member is obtained. In the sealing step, a plurality of semiconductor wafers CP are preferably covered by the sealing member 60 while maintaining the distance D2.

After the sealing step, the surface protection sheet 40 is peeled off to expose the circuit surface W1 of the semiconductor wafer CP and the surface 3S of the sealing body 3 in contact with the surface protection sheet 40 (see FIG. 3(A) ).

[Rewiring layer formation step, connection step with external terminal electrodes, and second dicing step]

After the sealing step, a rewiring layer forming step, a connection step with an external terminal electrode, and a second dicing step are performed. These steps can be performed in the same manner as in the manufacturing method of the first aspect (see Fig. 3(B) and Fig. 3(C) ). Through these steps, FO-WLP can be obtained.

[Variation]

About the manufacturing method of the FO-WLP of the said 2nd aspect, a part of steps may be changed or a part of steps may be omitted. Such a modified example will be described below.

As a 1st modification of the manufacturing method concerning the 2nd aspect, after the sticking process of the 2nd adhesive sheet 20, the process of peeling only the 1st adhesive sheet 10 may be performed. That is, in the above-mentioned second aspect, when the first adhesive sheet 10 is peeled off, it is peeled off together with the cut protection sheet 30; on the other hand, in this modification, the protection sheet 30 is left on the semiconductor wafer The circuit surface W1 of CP, Then, the first adhesive sheet 10 is peeled off. By peeling off the first adhesive sheet 10 , as shown in FIG. 7(A) , the plurality of semiconductor wafers CP to which the protective sheet 30 has been cut and pasted are in a state of being stacked on the second adhesive sheet 20 . .

Next, as shown in FIG. 7(B), the above-mentioned expansion step is performed. That is, in a state where the protective sheet 30 is adhered to the circuit surface W1 of the cut semiconductor wafer CP, the second adhesive sheet 20 is stretched to spread the distance D2 between the plurality of semiconductor wafers CP.

After the expansion step, as shown in FIG. 7(C), a step of sealing the plurality of semiconductor wafers CP is performed. In the above-mentioned second aspect, as shown in FIG. 6(B), the semiconductor wafer CP is sealed on the surface protection sheet 40; on the other hand, in this modification, as shown in FIG. 7(C), On the second adhesive sheet 20 , the semiconductor wafer CP is sealed using the sealing member 60 . Here, since the protection sheet 30 is attached to the circuit surface W1, the surface protection sheet 40 is not attached, and the second adhesive sheet can be directly sealed with the second adhesive sheet attached to the back surface W3 of the semiconductor wafer CP. The sealing body 3 is formed by covering the plurality of semiconductor wafers CP with the sealing member 60 while leaving the circuit surface W1. The surface 3S of the sealing body 3 is preferably the same surface as the circuit surface W1 of the semiconductor wafer CP.

After the sealing step, the protective sheet 30 and the second adhesive sheet 20 are peeled off. Then, by performing the above-mentioned rewiring layer forming step, external terminal electrode connecting step, and second dicing step, FO-WLP is obtained.

Since the sheet|seat for semiconductor processing of this embodiment can be extended greatly, as demonstrated above, it can apply suitably to the application which needs to enlarge the space|interval of a semiconductor wafer.

The above-described embodiments are intended to facilitate understanding of the present invention. The description is not intended to limit the present invention. Therefore, each element disclosed in the above-described embodiment is intended to include all design changes and equivalents that belong to the technical scope of the present invention.

For example, when the sheet|seat for semiconductor processing has a structure of a base material and an adhesive bond layer, another layer may be interposed between the base material and the adhesive bond layer.

[Example]

Hereinafter, the present invention will be described more specifically with reference to examples and the like, but the scope of the present invention is not limited to these examples and the like.

[Example 1]

(1) Preparation of adhesive composition

Acrylic copolymer obtained by reacting butyl acrylate/2-hydroxyethyl acrylate = 85/15 (mass ratio), and 80 mol% of methacryloyloxyethyl isocyanate relative to its 2-hydroxyethyl ester (MOI) reaction to obtain an energy ray hardening type polymer. The weight-average molecular weight (Mw) of this energy ray-curable polymer was 600,000.

100 parts by mass of the obtained energy ray-curable polymer, 3 parts by mass of 1-hydroxycyclohexyl phenyl ketone (manufactured by BASF, product name "IRGACURE 184") as a photopolymerization initiator, and 0.45 parts by mass as a bridge A toluene diisocyanate-based bridging agent (manufactured by TOSOH, product name "CORONATE L") was mixed in a solvent to obtain an adhesive composition.

(2) Production of sheets for semiconductor processing

A release surface of a release film (manufactured by LINTEC, product name "SP-PET3811") obtained by forming a silicone-based release layer on one side of a polyethylene terephthalate (PET) film was coated with the above-mentioned adhesive properties composition by adding After thermal drying, an adhesive layer with a thickness of 10 μm was formed on the release film. Then, one side of a polyester-based polyethylene formate elastomer sheet (manufactured by Sheedom Corporation, product name "Higress DUS202", thickness 50 μm) as a base material was adhered to the exposed surface of the adhesive layer to prevent the adhesive A sheet for semiconductor processing was obtained in the state where the release film was adhered to the layers.

[Comparative Example 1]

100 parts by mass of polyvinyl chloride resin (PVC, average degree of polymerization: 1050), 42 parts by mass of adipic acid-based polyester plasticizer, and a small amount of stabilizer were kneaded, and formed into a film using a curtain coater. A sheet for semiconductor processing was produced in the same manner as in Example 1, except that the vinyl chloride film having a thickness of 80 μm was used as a base material.

[Comparative Example 2]

A sheet for semiconductor processing was produced in the same manner as in Example 1, except that a polypropylene film (PP, manufactured by DiaPlus Film Co., Ltd., product name "LT01-06051") having a thickness of 80 μm was used as a base material.

[Test Example 1] (tensile test)

The sheet piece for semiconductor processing manufactured in the Example and the comparative example was cut into 15 mm x 140 mm, the peeling sheet piece was peeled, and it was set as a test piece. About this test piece, the elongation at break and the tensile modulus of elasticity at 23°C were measured in accordance with JIS K7161:2014 and JIS K7127:1999. Specifically, the above-mentioned test piece was subjected to a tensile test at a speed of 200 mm/min using a tensile tester (manufactured by Shimadzu Corporation, product name "Autograph AG-IS 500N"), and the distance between the clamps was set to 100 mm. The elongation at break (%) and the tensile modulus of elasticity (MPa) were measured. In addition, the measurement is carried out in both the flow direction (MD) and the direction (CD) at right angles to the flow direction at the time of manufacture of the base material. Row. The results are shown in Table 1.

[Test Example 2] (Measurement of 100% stress and recovery rate)

The sheets for semiconductor processing manufactured in the examples and comparative examples were cut into 150 mm×15 mm, and the peeling sheets were peeled off as test pieces. In addition, it cut|disconnected so that the flow direction (MD direction) of the sheet piece for semiconductor processing at the time of manufacture might become the longitudinal direction of a test piece. After that, both ends in the longitudinal direction of the test piece were fixed with jigs of a tensile testing machine (manufactured by Shimadzu Corporation, product name "Autograph AG-IS 50N"). At this time, the test piece was held by the jig so that the length between the jigs was 100 mm. Let this length be the length L0 (mm) between the initial jigs. Then, it stretched by 100 mm in the longitudinal direction at a speed of 200 mm/min so that the length between the jigs was 200 mm. The length obtained by subtracting the length L0 (mm) (that is, 100 mm) between the initial clips from this length is defined as the expansion length L1 (mm). The test force at this time was measured, and the 100% strength (N) of the tensile test was obtained as the 100% strength (N) in the MD direction. Then, the 100% stress (MPa) in the MD direction is obtained by dividing the 100% strength (N) in the MD direction by the quotient of the cross-sectional area of the sheet for semiconductor processing. In addition, after maintaining the state where the length between the clamps is expanded to 200 mm for 1 minute, the clamp is returned to the state where the length between the clamps is L0 (mm) and the length between the clamps is L0 (mm) at a speed of 200 mm/min. Hold for 1 minute. After that, it was stretched in the longitudinal direction at a speed of 60 mm/min, and the measured value of the recorded tensile force showed the length between the jigs at 0.1 N/15 mm. The value obtained by subtracting the initial length L0 (mm) between the jigs from this length is set to L2 (mm).

The recovery rate (%) was calculated by fitting the values of L1 and L2 into the following formula (I). The results are shown in Table 1.

Recovery rate (%)={1-(L2÷L1)}×100...(I)

In addition, the sheet pieces for semiconductor processing manufactured in the examples and comparative examples were cut into 150 mm × 150 mm so that the direction (CD direction) perpendicular to the flow direction at the time of manufacture was used as the longitudinal direction of the test piece. 15mm, peel off the peeled sheet and use it as a test piece, perform the measurement of 100% strength (N) and 100% stress (MPa) in the same manner as above, and use it as the 100% strength (N) in the CD direction and 100% in the CD direction. % stress (MPa). The results are shown in Table 1. Furthermore, the ratio of the 100% stress (MPa) in the MD direction to the 100% stress (MPa) in the CD direction was calculated. The results are also shown in Table 1.

[Test Example 3] (Extended Test)

Peel off the release sheet of dicing tape (manufactured by LINTEC, product name "ADWILL D-675"), and stick the exposed adhesive surface to the ring frame and 6-inch silicon mirror wafer (diameter: 150mm, thickness: 350μm, Ground surface #2000). Next, using a dicing machine (manufactured by DISCO, product name "DFD-651"), the silicon mirror wafer was diced by full dicing under the following conditions. Thereby, on the dicing tape, a plurality of pieces of silicon wafers are obtained. ^{Then, the dicing tape was irradiated with UV (illuminance: 120 mW/cm 2} , light intensity: 70 mJ/cm ² ) using a UV irradiation device (manufactured by LINTEC, product name “RAD-2000m/12”).

‧Cutting blade: manufactured by DISCO, product name "NBC-ZH205O 27HECC"

‧Rotation speed: 30,000rpm

‧Height: 0.06mm

‧Cutting speed: 60mm/sec

‧Chip size: 3mm×3mm

Next, the sheet piece for semiconductor processing obtained in the Example and the comparative example was cut into the size of the square of 210 mm x 210 mm. At this time, each side of the cut sheet is cut in parallel or perpendicular to the MD direction of the base material of the sheet for semiconductor processing. Next, the release sheet is peeled off, and all the silicon wafers obtained by the above dicing are transferred to the exposed adhesive surface. At this time, it transfers so that a group of silicon wafers may be located in the center part of the sheet|seat for semiconductor processing. Moreover, it transfers so that the dicing line at the time of individualizing a silicon wafer may be parallel or perpendicular to each side of the sheet|seat for semiconductor processing.

Next, the wafer for semiconductor processing on which the silicon wafer was transferred is set in an expansion device (separation device) capable of extending in two axes. In FIG. 8, a plan view illustrating the expansion device 100 is shown. In Fig. 8, the X-axis and the Y-axis are orthogonal to each other, so that the positive direction of the X-axis is the +X-axis direction, and the negative direction of the X-axis is the -X-axis direction, so that the Y-axis The positive direction is the +Y-axis direction, and the negative direction of the Y-axis is the -Y-axis direction. The wafer 200 for semiconductor processing is installed on the expansion device 100 so that each side is parallel to the X-axis or the Y-axis. As a result, the MD direction of the base material of the sheet 200 for semiconductor processing is parallel to the X axis or the Y axis. In addition, in Fig. 8, the silicon wafer is omitted.

As shown in FIG. 8 , the expansion device 100 includes five holding means 101 (20 holding means 101 in total) in the +X-axis direction, the -X-axis direction, the +Y-axis direction, and the -Y-axis direction, respectively. Among the five holding means 100 in each direction, those located at both ends are designated as holding means 101A, those at the center are designated as holding means 101C, and those located between holding means 101A and 101C are designated as holding means 101B. Each side of the sheet 200 for semiconductor processing is held by the holding means 101 .

Here, as shown in FIG. 8, one side of the sheet 200 for semiconductor processing is 210 mm. In addition, the interval between the holding means 101 on each side was 40 mm. In addition, the space|interval between the edge part (the vertex of the board piece) of one side of the sheet|seat 200 for semiconductor processing and the holding means 101A closest to this edge part which exists in this side is 25 mm.

Next, a plurality of tension applying means, not shown, respectively corresponding to the holding means 101 are driven to move the holding means 101 independently. At this time, the five holding means 101 holding one side of the sheet 200 for semiconductor processing on the +X axis direction side were moved in the +X axis direction for 40 seconds at an extension speed: 2.5 mm/sec. At the same time, among these five holding means 101, holding means 101A and holding means 101B are moved in a direction away from holding means 101C (ie, the +Y-axis direction or the -Y-axis direction). At this time, the holding means 101A is moved at a speed of 2/3 of the extension speed: 2.5 mm/sec, and the holding means 101B is moved at a speed of 1/3 of the extension speed: 2.5 mm/sec. In addition, the holding means 101C does not move in the +Y-axis direction and the -Y-axis direction. In the sheet 200 for semiconductor processing, the holding means 101 located on the three-direction sides other than the +X-axis direction are also moved in various directions in the same manner as in the +X-axis direction, and the holding means 101A and the holding means 101B are moved toward each other. Move in the direction away from the holding means 101C.

As a result of moving the holding means 101 as described above, the semiconductor processing plate 200 extends 100 mm each in the +X-axis direction and the -X-axis direction, and simultaneously extends 100 mm each in the +Y-axis direction and the -Y-axis direction. . That is, each side of the sheet 200 for semiconductor processing extends by 200 mm. As a result, the length of each side of the stretched sheet 200 for semiconductor processing was 410 mm.

The sheet for semiconductor processing in the state extended as described above 200, the presence or absence of breakage was evaluated based on the following criteria. The results are shown in Table 1.

◯: No fracture occurred, and it stretched well.

×: Breakage occurred.

In addition, with respect to the semiconductor processing sheet 200 which was evaluated as "○" for the presence or absence of fracture, the outer diameter of the substantially circular shape composed of a plurality of silicon wafers (corresponding to the state of the extended semiconductor processing sheet 200) was measured. The length of the outer diameter of the silicon wafer before dicing and extension) is used as the length (mm) corresponding to the outer diameter of the wafer. The results are shown in Table 1.

Furthermore, the measured wafer outer diameter corresponding length (mm) was fitted into the following calculation formula (II), and the wafer interval (mm) was calculated. The results are shown in Table 1.

Chip spacing (mm)={Length corresponding to the outer diameter of the wafer (mm)-150mm (Si wafer diameter)}÷49(Number of cutting lines)...(II)

Furthermore, in the above formula (II), the number of cutting lines is 49, which is based on the fact that when a silicon wafer with a diameter of 150 mm is cut into a wafer size of 3 mm × 3 mm, the silicon wafer is in one direction and the direction orthogonal to the direction. Separately, cut at 3mm intervals, and make up to 50 equal parts in each direction. At this time, the number of cutting lines is 49 in each direction.

As can be seen from Table 1, the sheet for semiconductor processing of the examples can be greatly extended without breaking.

【Industrial Profitability】

The sheet for semiconductor processing of the present invention can be favorably used, for example, in the production of FO-WLP.

W‧‧‧Semiconductor Wafer

W1‧‧‧circuit surface

W2‧‧‧circuit

W3‧‧‧Back

CP‧‧‧Semiconductor Chip

10‧‧‧First adhesive plate

11‧‧‧First substrate film

12‧‧‧First Adhesive Layer

Claims (10)

A sheet for semiconductor processing, which is a sheet for semiconductor processing having at least a base material, wherein the recovery rate of the sheet for semiconductor processing is 70% or more and 100% or less, and the recovery rate is the above-mentioned recovery rate. A test piece of 150 mm × 15 mm was cut out of the sheet for semiconductor processing, and the two ends in the longitudinal direction were clamped by the clamps so that the length between the clamps was 100 mm. When the length is 200mm, the length between the clamps is expanded to 200mm and held for 1 minute. After that, the length between the clamps is restored to 100mm in the longitudinal direction at a speed of 200mm/min, and the length between the clamps is restored to 100mm. After 1 minute, it was stretched in the longitudinal direction at a speed of 60 mm/min, and the measured value of the tensile force showed the length between the clamps at 0.1 N/15 mm, and the initial length between the clamps 100 mm was subtracted from the length. The length is L2 (mm), and when the length between the clamps in the expanded state is 200 mm minus the length of 100 mm between the initial clamps as L1 (mm), the value calculated by the following formula (I): Recovery rate ( %)={1-(L2÷L1)}×100...(I), and the above-mentioned base material is formed of a urethane-based elastomer. A sheet for semiconductor processing, which is a sheet for semiconductor processing including at least a base material, wherein 100% stress of the sheet for semiconductor processing measured in the MD direction of the base material at 23° C. The ratio of 100% stress of the above-mentioned sheet for semiconductor processing measured in the CD direction of the above-mentioned base material at 23° C. is 0.8 or more and 1.2 or less, The above-mentioned 100% stress is obtained by cutting the above-mentioned sheet for semiconductor processing into a test piece of 150 mm × 15 mm, and clamping both ends in the longitudinal direction with the clamps so that the length between the clamps is 100 mm, and then at 200 mm/min. The speed is stretched in the longitudinal direction, and the value calculated by dividing the measured value of the tensile force when the length between the jigs becomes 200 mm by the cross-sectional area of the sheet for semiconductor processing when the plane perpendicular to the longitudinal direction is cut, The said base material is formed of the urethane type elastomer. A sheet for semiconductor processing, which is a sheet for semiconductor processing comprising at least a base material, wherein the tensile elasticity of the sheet for semiconductor processing is measured in the MD and CD directions of the base material at 23° C. The modulus is 10 MPa or more and 350 MPa or less, respectively, and the 100% stress of the semiconductor processing sheet measured in the MD and CD directions of the substrate at 23°C is 3 MPa or more and 20 MPa or less, respectively. The above 100% stress , the above-mentioned semiconductor processing sheet is cut out of a test piece of 150 mm × 15 mm, and the two ends in the longitudinal direction are clamped by the clamps so that the length between the clamps is 100 mm, and then the length is 200 mm/min. Directional stretching, the value calculated by dividing the measured value of the tensile force when the length between the jigs is 200 mm by the cross-sectional area of the sheet for semiconductor processing when the plane perpendicular to the longitudinal direction is cut, at 23°C. The elongation at break of the sheet for semiconductor processing measured in the MD direction and the CD direction of the base material is 100% or more, respectively, and the base material is formed of a urethane-based elastomer. The sheet for semiconductor processing according to any one of claims 1 to 3, further comprising an adhesive layer laminated on at least one surface of the base material. The sheet for semiconductor processing according to any one of claims 1 to 3 of the scope of application, which is used for mutual communication between adjacent semiconductor wafers among a plurality of semiconductor wafers stacked on one surface of the sheet for semiconductor processing. The interval is expanded to 200 μm or more and 6000 μm or less. The sheet for semiconductor processing according to any one of claims 1 to 3, which is used in the +X-axis direction, -X-axis direction, +X-axis direction, -X-axis direction, + Tension is applied in four directions of the Y-axis direction and the -Y-axis direction, and the semiconductor processing sheet is stretched to widen the interval between the plurality of semiconductor wafers stacked on one surface of the semiconductor processing sheet. The sheet for semiconductor processing according to any one of claims 1 to 3, which is used in a method for manufacturing a semiconductor device, wherein the manufacturing method includes: providing individual sheets on one side of the sheet for semiconductor processing. the step of extending the plurality of semiconductor wafers; and the step of extending the above-mentioned sheet for semiconductor processing to widen the distance between the plurality of semiconductor wafers. The wafer for semiconductor processing according to any one of claims 1 to 3 of the patent application scope is used for manufacturing a fan-out semiconductor wafer-level package. A method of manufacturing a semiconductor device, comprising: dividing a semiconductor wafer on a dicing plate to obtain a plurality of semiconductor wafers; A step of transferring the plurality of semiconductor wafers from the dicing sheet to the sheet for semiconductor processing according to any one of claims 1 to 3; and stretching the sheet for semiconductor processing to expand the plurality of The step of spacing the semiconductor wafers from each other. A method of manufacturing a semiconductor device, comprising: a step of dividing a semiconductor wafer on a dicing sheet to obtain a plurality of semiconductor wafers; a step of transferring the plurality of semiconductor wafers from the dicing sheet to a first semiconductor processing sheet; The steps of extending the first sheet for semiconductor processing to widen the distance between the plurality of semiconductor wafers; the step of transferring the plurality of semiconductor wafers from the first sheet for semiconductor processing to the second sheet for semiconductor processing; and drawing The step of extending the above-mentioned second sheet for semiconductor processing and further expanding the distance between the plurality of semiconductor wafers, wherein the above-mentioned first sheet for semiconductor processing and the above-mentioned second sheet for semiconductor processing are as described in the first to third of the scope of the patent application, respectively. The sheet for semiconductor processing according to any one of the clauses.

Images