TW201803042A - Semiconductor processing sheet - Google Patents

Abstract

A semiconductor processing sheet comprising at least a base material, wherein: the semiconductor processing sheet has a recovery rate of not less than 70% and not more than 100%; or the ratio of a 100% stress measured in an MD direction of the base material at 23 DEG C to the 100% stress measured in a CD direction of the base material at 23 DEG C is not less than 0.8 and not more than 1.2; or the tensile elasticity measured in the MD direction and the CD direction of the base material at 23 DEG C is in each case not less than 10 MPa and not more than 350 MPa, the 100% stress measured in the MD direction and the CD direction of the base material at 23 DEG C is in each case not less than 3 MPa and not more than 20 MPa, and the rupture elongation measured in the MD direction and the CD direction of the base material at 23 DEG C is in each case not less than 100%. The semiconductor processing sheet can be greatly stretched, allowing semiconductor chips to be moved apart from each other sufficiently.

Description

Semiconductor processing plate

The present invention relates to a sheet for semiconductor processing, and more preferably to a sheet for semiconductor processing used to increase the interval between a plurality of semiconductor wafers.

In recent years, miniaturization, weight reduction, and high-performance of electronic devices have continued to progress. Semiconductor devices mounted on electronic devices are also required to be reduced in size, thickness, and density. Semiconductor wafers are packaged in packages close to their size. Such a package is sometimes referred to as a Chip Scale Package (CSP). One of the CSPs is a wafer level package (Wafer Level Package, WLP). In WLP, an external electrode or the like is formed on a wafer before dicing and dicing, and the wafer is finally diced and diced. Examples of the WLP include a fan-in type and a fan-out type. In a fan-out type WLP (hereinafter, sometimes referred to simply as "FO-WLP"), a semiconductor wafer is covered with a sealing member so as to have a larger area than the wafer size, thereby forming a semiconductor wafer sealing body, not just a semiconductor wafer. A redistribution layer or an external electrode is also formed on the circuit surface of the sealing member.

For example, in Patent Document 1, it is described that a plurality of semiconductor wafers singulated from a semiconductor wafer are left with circuit formation surfaces, and an expansion wafer is formed by surrounding the periphery with a mold member, and a rewiring pattern is extended in a region outside the semiconductor wafer. There is a method for manufacturing a semiconductor package. Described in Patent Document 1 In the manufacturing method of the present invention, before singulating the plurality of semiconductor wafers into a mold member, the wafers are replaced with an expansion wafer adhesive tape, and the wafer adhesive tape is extended to increase the distance between the plurality of semiconductor wafers.

[Prior technical literature] [Patent Literature]

[Patent Document 1] International Publication No. 2010/058646

In the manufacturing method of the FO-WLP described above, in order to form the rewiring pattern and the like in a region outside the semiconductor wafer, it is necessary to sufficiently separate the semiconductor wafers from each other.

The present invention has been made in view of the solid state as described above, and has as its object to provide a sheet for semiconductor processing that is suitable for applications in which semiconductor wafers need to be sufficiently separated from each other and that can be greatly extended.

In order to achieve the above object, firstly, the present invention provides a sheet for semiconductor processing, which is a sheet for semiconductor processing having at least a base material, wherein the recovery rate of the sheet for semiconductor processing is 70% or more, 100% or less, the recovery rate is that the test piece for semiconductor processing is cut out of a test piece of 150 mm × 15 mm so that the length between the clamps becomes 100 mm. Stretch at a speed of min until the length between the clamps becomes 200 mm, and keep the length between the clamps extended to 200 mm for 1 minute, and then move along at a speed of 200 mm / min. The length between the clamps was restored to 100 mm in the longitudinal direction, and the length between the clamps was restored to 100 mm. The state was maintained for 1 minute, and then the specimen was stretched in the longitudinal direction at a speed of 60 mm / min. The length between the clamps at / 15mm is L2 (mm), which is the length minus the initial length between the clamps of 100mm. The length between the clamps in the expanded state is 200mm minus the initial length between the clamps. When the length (mm) is set to L1 (mm), the value calculated by the following formula (I): Recovery rate (%) = {1- (L2 ÷ L1)} × 100 ... (I) (Invention 1).

According to the above-mentioned invention (Invention 1), the recovery rate can be greatly extended by setting the recovery rate to the above range. Therefore, it can be used suitably, for example, in applications, such as manufacture of FO-WLP, which require semiconductor wafers to be sufficiently separated from each other.

Secondly, the present invention provides a sheet for semiconductor processing, which is a sheet for semiconductor processing having at least a base material, characterized in that the thickness of the sheet for semiconductor processing is measured at 23 ° C. in the MD direction of the base material. The ratio of 100% stress to the 100% stress of the semiconductor processing plate measured at 23 ° C in the CD direction of the substrate is 0.8 or more and 1.2 or less. The 100% stress refers to the semiconductor processing plate. A 150 mm × 15 mm test piece was cut out, and the two ends of the longitudinal direction were clamped by the clamp so that the length between the clamps became 100 mm. Then, the test piece was stretched in the length direction at a speed of 200 mm / min until the The measured value of the tensile force when the length was 200 mm was calculated by dividing the cross-sectional area of the semiconductor processing plate (invention 2).

According to the above-mentioned invention (Invention 2), the 100% stress ratio can be greatly extended by setting the ratio of 100% stress to the above-mentioned range. Therefore, it can be suitably used, for example, in the manufacture of FO-WLP, etc. which needs to fully isolate | separate a semiconductor wafer from each other.

Third, the present invention provides a sheet for semiconductor processing, which is a sheet for semiconductor processing including at least a substrate, characterized in that the semiconductor processing sheet is measured at 23 ° C in the MD direction and the CD direction of the substrate. The tensile elastic modulus of the plate is 10 MPa or more and 350 MPa or less. The 100% stress of the semiconductor processing plate measured at 23 ° C in the MD direction and CD direction of the substrate is 3 MPa or more and 20 MPa, respectively. Hereinafter, the above-mentioned 100% stress is obtained by cutting out a test piece of 150 mm × 15 mm from the above-mentioned semiconductor processing plate, and clamping both ends in the longitudinal direction with a jig so that the length between the jigs becomes 100 mm. The speed of min is stretched along the length direction until the length between the clamps is 200 mm. The measured value of the tensile force is calculated by dividing the cross-sectional area of the semiconductor processing plate. The breaking elongation of the above-mentioned semiconductor processing sheet measured in the MD direction and the CD direction was 100% or more (Invention 3).

According to the above-mentioned invention (Invention 3), the tensile elastic modulus and the breaking elongation can be greatly extended by setting the tensile elastic modulus and the elongation at break to the above ranges. Therefore, it can be used suitably, for example, in applications, such as manufacture of FO-WLP, which require semiconductor wafers to be sufficiently separated from each other.

In the above inventions (Inventions 1 to 3), it is preferable to further include an adhesive layer laminated on at least one surface of the substrate (Invention 4).

In the above inventions (Inventions 1 to 4), the base material preferably contains a thermoplastic elastomer (Invention 5).

In the above invention (Invention 5), the thermoplastic elastomer is preferably a urethane-based elastomer (Invention 6).

In the above inventions (Inventions 1 to 6), adjacent semiconductor crystals for a plurality of semiconductor wafers laminated on one surface of the semiconductor processing plate are used. The interval between the sheets is preferably expanded to 200 μm or more and 6000 μm or less (Invention 7).

In the above inventions (Inventions 1 to 7), tension is applied in four directions by + X-axis direction, -X-axis direction, + Y-axis direction, and -Y-axis direction in mutually orthogonal X-axis and Y-axis. The semiconductor processing sheet is stretched, and the interval between the plurality of semiconductor wafers laminated on one side of the semiconductor processing sheet is preferably extended (Invention 8).

In the above invention (Inventions 1 to 8), it is used to include a step of: providing a plurality of semiconductor wafers on one side of the adhesive sheet; and stretching the adhesive sheet to increase a distance between the plurality of semiconductor wafers. The method for manufacturing a semiconductor device in this step is preferred as the above-mentioned adhesive sheet (Invention 9).

In the above inventions (Inventions 1 to 9), it is preferable to use it for manufacturing a fan-out-type semiconductor wafer-level package (Invention 10).

The semiconductor processing sheet of the present invention can be greatly extended, and the semiconductor wafers can be sufficiently separated from each other.

W‧‧‧Semiconductor wafer

W1‧‧‧Circuit Surface

W2‧‧‧Circuit

W3‧‧‧ back

W4‧‧‧Internal terminal electrode

W5‧‧‧ trench

W6‧‧‧Back

CP‧‧‧Semiconductor wafer

1‧‧‧Semiconductor Package

3‧‧‧Sealed body

4A‧‧‧First insulation layer

4B‧‧‧Second insulation layer

5‧‧‧ redistribution layer

5A‧‧‧External electrode pad

6‧‧‧External terminal electrode

10‧‧‧The first adhesive plate

11‧‧‧ the first substrate film

12‧‧‧ the first adhesive layer

20‧‧‧Second Adhesive Plate

21‧‧‧Second substrate film

22‧‧‧Second adhesive layer

30‧‧‧protection plate

40‧‧‧Surface protection sheet

41‧‧‧ Fourth substrate film

42‧‧‧ fourth adhesive layer

50‧‧‧Grinding machine

60‧‧‧Sealing member

100‧‧‧Expansion device

101, 101A, 101B, 101C

200‧‧‧Semiconductor processing plate

FIG. 1 is a cross-sectional view illustrating a first aspect of a method of using a semiconductor processing plate according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a first aspect of a method of using a semiconductor processing plate according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a first aspect of a method of using a semiconductor processing plate according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a second aspect of a method of using a semiconductor processing plate according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a second aspect of a method of using a semiconductor processing plate according to an embodiment of the present invention.

Fig. 6 is a cross-sectional view illustrating a second aspect of a method of using a semiconductor processing plate according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a second aspect of a method of using a semiconductor processing plate according to an embodiment of the present invention.

Fig. 8 is a plan view illustrating a two-axis extension and expansion device used in the embodiment.

Embodiments of the present invention will be described below.

The semiconductor processing sheet of this embodiment is configured to include at least a base material.

The recovery rate of the semiconductor processing sheet of this embodiment is preferably 70% or more and 100% or less.

In this specification, the recovery rate is calculated as follows. First, 150 mm × 15 mm was cut out of a plate for semiconductor processing to obtain a test piece. This cutting out was performed in the MD direction of the base material of the semiconductor processing plate, and in accordance with the longitudinal direction of the test piece. Next, the both ends of the test piece in the longitudinal direction were clamped with a jig so that the length between the jigs became 100 mm. The length between the clamps at this time is set to the length L0 (mm) between the initial clamps. Next, the jigs were stretched in the longitudinal direction at a speed of 200 mm / min, and the state of the jigs was maintained at 200 mm for 1 minute. The length between the clamps after the expansion to 200 mm is subtracted from the length between the initial clamps The length of L0 (mm) (that is, 100 mm) is set to the expanded length L1 (mm) (= 100 mm). After holding for 1 minute, the length between the clamps was restored at a speed of 200 mm / min, and the length between the clamps was set to 100 mm (that is, L0 (mm)) and held for 1 minute. Thereafter, the jigs were stretched in the longitudinal direction at a speed of 60 mm / min, and the measured value of the recorded tensile force showed the length between the jigs at 0.1 N / 15 mm. A value obtained by subtracting the length L0 (mm) between the initial jigs from this length is set to L2 (mm). By inserting the values of L1 and L2 obtained above, the recovery rate (%) is obtained.

Recovery rate (%) = (1- (L2 ÷ L1)) × 100 ... (I)

In this tensile test, the thickness of the test piece is not particularly limited, and may be the same as the thickness of the semiconductor processing plate to be tested. In addition, the specific measurement method is as shown in the test example mentioned later.

In addition, regarding the semiconductor processing sheet of this embodiment, the 100% stress of the semiconductor processing sheet measured at 23 ° C in the MD direction of the substrate was measured with respect to the CD direction of the substrate measured at 23 ° C. The 100% stress ratio of the semiconductor processing plate is preferably 0.8 or more and 1.2 or less. Here, the MD direction refers to the flow direction during the manufacture of the substrate, and the CD direction refers to a direction perpendicular to the MD direction.

In this specification, the so-called 100% stress is calculated as follows. A 150 mm × 15 mm test piece was cut out of the above-mentioned semiconductor processing plate, and the two ends in the length direction were clamped by a jig so that the length between the jigs was 100 mm, and the length was extended at a speed of 200 mm / min until the jig The length of time is 100% of the strength shown by the tensile strength (measured value of the tensile force) when the length is 200 mm, and the 100% stress (MPa) is calculated by dividing the cross-sectional area of the semiconductor processing sheet. This cut-out is based on the flow method used in the manufacture of semiconductor processing plates. The direction (MD direction) or the direction orthogonal to the MD direction (CD direction) was performed in accordance with the longitudinal direction of the test piece. In this tensile test, the thickness of the test piece is not particularly limited, and may be the same as the thickness of the semiconductor processing plate to be tested. In addition, the specific measurement method is as shown in the test example mentioned later.

In addition, regarding the semiconductor processing sheet of this embodiment, the tensile elastic modulus of the semiconductor processing sheet measured at 23 ° C in the MD direction and the CD direction of the substrate is preferably 10 MPa or more and 350 MPa, respectively. Hereinafter, the 100% stress of the semiconductor processing sheet measured at 23 ° C in the MD direction and the CD direction of the substrate is 3 MPa or more and 20 MPa or less, respectively, and measured at 23 ° C in the MD direction and the CD direction of the substrate. The elongation at break of the semiconductor processing plates is 100% or more.

With regard to the sheet for semiconductor processing of this embodiment, the above-mentioned physical properties can be easily extended without breaking, and as a result, it can be significantly extended.

In particular, when the recovery rate is within the above range, it means that it is easy to recover after the semiconductor processing sheet is greatly extended. Generally speaking, if a plate having an undulation point is extended above the undulation point, the plate is plastically deformed, and the portion where the plastic deformation occurs, that is, the extremely extended portion, is in a state of uneven distribution. When the sheet in such a state is further extended, a fracture occurs from the extreme extending portion, and even if the fracture does not occur, the extension becomes uneven. In addition, in the stress-strain diagrams where the strain is plotted on the x-axis and the elongation is plotted on the y-axis, even if the slope dx / dy does not get a stress value that changes from a positive value to 0 or a negative value, instead of As the sheet shows a clear drop point, as the amount of stretching becomes larger, the sheet still undergoes plastic deformation, breaks likewise, or spreads unevenly. On the other hand, instead of plastic deformation, but elastic deformation, By removing stress, the plate is easily restored to its original shape. Therefore, the recovery rate is an index representing the degree of recovery after 100% elongation with a sufficiently large stretch amount. By setting the recovery rate within the above range, the film can be stretched when the sheet for semiconductor processing is greatly extended The plastic deformation is suppressed to a minimum, it is not easy to break, and it can spread uniformly.

In addition, when the ratio of 100% stress is in the above range, and when the tensile elastic modulus, 100% stress, and elongation at break are in the above ranges, the semiconductor processing sheet is extended in the MD direction and CD direction of the substrate. (Hereinafter, such an extension is sometimes referred to as "biaxial extension.") It is not easy to break and can be extended significantly.

In the above-mentioned semiconductor processing sheet, specifically, the interval between the semiconductor wafers can be separated to a distance of 200 μm or more. Such a sheet for semiconductor processing can be suitably used for a method of manufacturing a semiconductor device that requires a sufficiently large interval between semiconductor wafers, such as a method of manufacturing FO-WLP.

Physical properties of plate for semiconductor processing

Regarding the sheet for semiconductor processing of this embodiment, the recovery rate is preferably 70% or more, particularly preferably 80% or more, and further preferably 85% or more. The recovery rate is preferably 100% or less. By setting the recovery ratio to the above range, as described above, the sheet for semiconductor processing can be significantly extended.

With regard to the semiconductor processing sheet of this embodiment, 100% stress of the semiconductor processing sheet measured at 23 ° C in the MD direction of the substrate, and for semiconductor processing measured at 23 ° C in the CD direction of the substrate The 100% stress ratio of the plate is preferably 0.8 or more, especially 0.83 or more. It is more preferably 0.85 or more. The ratio is preferably 1.2 or less, particularly preferably 1.17 or less, and further preferably 1.15 or less. By setting the ratio of 100% stress in the above range, it is possible to suppress the occurrence of breakage in the semiconductor processing plate even when the stress is applied only in a specific direction when the semiconductor processing plate is biaxially extended. As a result, the sheet for semiconductor processing can be extended further.

Regarding the sheet for semiconductor processing of this embodiment, the elongation at break of the sheet for semiconductor processing measured at 23 ° C in the CD direction of the substrate is preferably 100% or more, particularly 150% or more. It is more preferably 200% or more. The elongation at break is preferably 1200% or less, and particularly preferably 1000% or less. By making this fracture elongation into the said range, the sheet for semiconductor processing can be extended in the CD direction of a base material significantly. The method for measuring the elongation at break in the CD direction is shown in the test example described later.

Regarding the sheet for semiconductor processing of this embodiment, the breaking elongation of the sheet for semiconductor processing measured at 23 ° C. in the MD direction of the substrate is preferably 100% or more, particularly 150% or more. It is more preferably 200% or more. The elongation at break is preferably 1200% or less, and particularly preferably 1000% or less. By making this fracture elongation into the said range, the sheet for semiconductor processing can be extended in the MD direction of a base material significantly. The method for measuring the elongation at break in the MD direction is shown in the test example described later.

Regarding the sheet for semiconductor processing of this embodiment, the tensile elastic modulus of the sheet for semiconductor processing measured at 23 ° C in the CD direction of the substrate is preferably 10 MPa or more, and particularly preferably 20 MPa or more. It is more preferably 25 MPa or more. The tensile elastic modulus is preferably 350 MPa or less, particularly preferably 300 MPa or less, and further preferably 250 MPa or less. good. When the above-mentioned tensile elastic modulus is 10 MPa or more, when a semiconductor wafer or the like is laminated on a sheet for semiconductor processing, the semiconductor wafer or the like can be favorably supported. In addition, by setting the above-mentioned tensile elastic modulus to 350 MPa or less, the sheet for semiconductor processing can have appropriate flexibility, and the sheet for semiconductor processing can be more easily extended. The method for measuring the tensile elastic modulus is as shown in the test example described later.

Regarding the sheet for semiconductor processing of this embodiment, the tensile elastic modulus of the sheet for semiconductor processing measured at 23 ° C. in the MD direction of the substrate is preferably 10 MPa or more, particularly preferably 20 MPa or more. It is more preferably 25 MPa or more. The tensile elastic modulus is preferably 350 MPa or less, particularly 300 MPa or less, and further preferably 250 MPa or less. When the above-mentioned tensile elastic modulus is 10 MPa or more, when a semiconductor wafer or the like is laminated on a sheet for semiconductor processing, the semiconductor wafer or the like can be favorably supported. In addition, by setting the above-mentioned tensile elastic modulus to 350 MPa or less, the sheet for semiconductor processing can have appropriate flexibility, and the sheet for semiconductor processing can be more easily extended. The method for measuring the tensile elastic modulus is as shown in the test example described later.

Regarding the sheet for semiconductor processing of this embodiment, the 100% stress of the sheet for semiconductor processing measured at 23 ° C in the CD direction of the substrate is preferably 3 MPa or more, particularly 5 MPa or more, and further preferably Above 6 MPa is preferred. By making the 100% stress be 3 MPa or more, even if the semiconductor processing sheet is greatly extended to reduce the thickness of the substrate, the force required to support the wafer in a separated state can be maintained. The 100% stress is preferably 20 MPa or less, particularly 18 MPa or less, and further preferably 16 MPa or less. By setting the fracture elongation to 20 MPa or less, the semiconductor processing sheet can be largely extended without applying an excessive load to the expansion device, and even if the device is continuously used for a long period of time, it is possible to prevent the failure of the device. The method for measuring the 100% stress in the CD direction is shown in the test example described later.

Regarding the sheet for semiconductor processing of this embodiment, the 100% stress of the sheet for semiconductor processing measured at 23 ° C. in the MD direction of the substrate is preferably 3 MPa or more, particularly 5 MPa or more, and further preferably Above 6 MPa is preferred. By making the 100% stress be 3 MPa or more, even if the semiconductor processing sheet is greatly extended and the thickness of the substrate is reduced, the force required to support the wafer in a separated state can be maintained, and the semiconductor processing sheet can be moved along The CD direction of the substrate is greatly extended. The 100% stress is preferably 20 MPa or less, particularly 18 MPa or less, and further preferably 16 MPa or less. By setting the fracture elongation to 20 MPa or less, the semiconductor processing sheet can be largely extended without applying an excessive load to the expansion device, and even if the device is continuously used for a long period of time, it is possible to prevent the failure of the device. The method for measuring the 100% stress in the MD direction is shown in the test example described later.

As for the sheet for semiconductor processing of this embodiment, it is preferable that at least one surface has adhesiveness. Thereby, a semiconductor wafer, etc. can be stuck and fixed on this surface. In addition, in this specification, the surface which has adhesiveness on the board for semiconductor processing, and a semiconductor wafer etc. are adhered may be called "adhesive surface." Regarding the adhesive force of the plate for semiconductor processing of this embodiment, 300 mN / 25 mm or more is preferable, 800 mN / 25 mm or more is preferable, and 1000 mN / 25 mm or more is more preferable. In addition, the adhesion is preferably 30,000 mN / 25mm or less, particularly preferably 15,000 mN / 25 mm or less, and further preferably 10,000 mN / 25 mm or less. Better. By setting the adhesive force to be 300 mN / 25 mm or more, a semiconductor wafer or the like can be adhered and fixed well. In addition, by making the adhesive force 30,000 mN / 25 mm or less, it is possible to perform well, and change the semiconductor wafer or the like from the semiconductor processing plate of the present embodiment to another adhesive plate; The semiconductor processing plate of the embodiment is transferred to a holding member capable of holding and holding a semiconductor wafer or the like; the semiconductor wafer or the like is picked up from the semiconductor processing plate of the present embodiment. In addition, the adhesive force in this specification refers to the adhesive force (mN / 25mm) measured using a mirror wafer made of silicon as an adherend and conforming to the 180 ° peeling method of JIS Z0237: 2009. In addition, regarding the sheet for semiconductor processing of this embodiment, when the sheet is formed of only a base material, the adhesion force is measured on one side of the base material; and for the sheet for semiconductor processing of this embodiment, the base material is made of a base material. When it forms with the adhesive layer mentioned later, an adhesive force is measured on the surface of this adhesive layer on the side opposite to a base material.

It is preferable that the plate for semiconductor processing of this embodiment has heat resistance. When a wafer-level package is manufactured using the semiconductor processing sheet according to this embodiment, the semiconductor wafer may be sealed with a sealing member on the semiconductor processing sheet according to this embodiment. Generally, a thermosetting material is used as a sealing member, and the material is heated during sealing. By making the sheet for semiconductor processing heat-resistant, deformation of the sheet for semiconductor processing due to heating can be suppressed.

The thickness of the sheet for semiconductor processing of this embodiment is preferably 30 μm or more, and particularly preferably 50 μm or more. The thickness is preferably 300 μm or less, and particularly preferably 250 μm or less for sealing.

Substrate

Regarding the base material of the sheet for semiconductor processing of this embodiment, as long as the sheet for semiconductor processing can achieve the above-mentioned physical properties, the constituent material is not particularly limited, and it is usually formed of a thin film using a resin-based material as a main material. In particular, from the viewpoint of easily achieving the above-mentioned physical properties, it is preferable to use a thermoplastic elastomer or a rubber-based material as the material of the base material. Among these, from the viewpoint of achieving the above-mentioned physical properties more easily, the use of a thermoplastic elastomer is particularly preferred good. In addition, from the viewpoint of easily achieving the above-mentioned physical properties, it is preferable to use a resin having a relatively low glass transition temperature (Tg) as a constituent material of the substrate. In particular, the glass transition temperature (Tg) of such a resin is 90 ° C The temperature is preferably below, particularly preferably below 80 ° C, and more preferably below 70 ° C.

Examples of the thermoplastic elastomer include a urethane-based elastomer, an olefin-based elastomer, a vinyl chloride-based elastomer, a polyester-based elastomer, a styrene-based elastomer, an acrylic-based elastomer, and a fluorene-based elastomer. Among these, it is preferable to use a urethane-based elastomer from the viewpoint that the above-mentioned physical properties are more easily achieved.

Urethane-based elastomers are generally obtained by reacting a long-chain polyol, a chain extender, and a diisocyanate. The urethane-based elastomer is composed of a soft segment having a constituent unit derived from a long-chain polyol, and a chain extender and a diisocyanate The reaction results in a hard segment of polyurethane structure.

The urethane-based elastomers can be classified into polyester-based polyurethane elastomers and polyether-based polyurethanes according to the type of the long-chain polyol used as the soft segment component. Elastomers, polycarbonate-based polyurethane elastomers, and the like. Regarding the sheet for semiconductor processing of this embodiment, among these, from the viewpoint of easily achieving the above-mentioned physical properties, polyether-based polyurethane is used. Ethyl elastomer is preferred.

Examples of the long-chain polyols include polyester polyols such as internal polyester polyols and adipate polyester polyols; polypropylene (ethylene) polyols, and polytetramethylene ether diols. Polyether polyols such as alcohols; polycarbonate polyols and the like. Among these, from the viewpoint of making it easier to achieve the above-mentioned physical properties, it is preferable to use an adipate-based polyester polyol.

Examples of the diisocyanate include 2,4-toluene diisocyanate, 2,6-toluene diisocyanate, 4,4'-diphenylmethane diisocyanate, and hexamethylene diisocyanate. Among these, hexamethylene diisocyanate is preferably used because it is easier to achieve the above-mentioned physical properties.

Examples of the chain extender include 1,4-butanediol, a low-molecular-weight polyol of 1,6-hexanediol, and an aromatic diamine. Among these, it is preferable to use 1,6-hexanediol from the viewpoint of easily achieving the above-mentioned physical properties.

Examples of the olefin-based elastomer include those selected from the group consisting of ethylene‧α-olefin copolymer, propylene‧α-olefin copolymer, butene‧α-olefin copolymer, ethylene‧propylene‧α-olefin copolymer, and ethylene‧butene. ‧Α-olefin copolymer, propylene‧butene-α‧olefin copolymer, ethylene‧propylene‧butene-α‧olefin copolymer, styrene‧isoprene copolymer and styrene‧ethylene‧butene copolymer Resin of at least one type of composition.

The density of the olefin-based elastomer is not particularly limited. From the viewpoint of more stable obtaining of a substrate having excellent unevenness followability when a semiconductor wafer is adhered to a semiconductor processing plate, the density is 0.860 g / cm ³ or more. full 0.905g / cm ³ preferably to 0.862g / cm ³ or more and less than 0.900g / cm ³ is more preferred to 0.864g / cm ³ or more, less than 0.895g / cm ³ or less is particularly preferred.

The olefin-based elastomer has a mass ratio of a monomer composed of an olefin-based compound among all the monomers used to form the elastomer (also referred to as "olefin content rate" in this specification), and ranges from 50 to 100. Mass% is preferred. When the olefin content is too low, it is difficult to express the properties of an elastomer containing a structural unit derived from an olefin, and it is difficult to exhibit flexibility or rubber elasticity. From the viewpoint of stably obtaining this effect, the olefin content is preferably 50% by mass or more, and more preferably 60% by mass or more.

Examples of the styrene-based elastomer include a styrene-conjugated diene copolymer and a styrene-olefin copolymer. Specific examples of the styrene-conjugated diene copolymer include a styrene-butadiene copolymer, a styrene-butadiene-styrene copolymer (SBS), and a styrene-butadiene-butene- Unhydrogenated styrene copolymer, styrene-isoprene copolymer, styrene-isoprene-styrene copolymer (SIS), styrene-ethylene-isoprene-styrene copolymer, etc. Styrene-conjugated diene copolymer; styrene-ethylene / propylene-styrene copolymer (SEPS, hydrogenated product of styrene-isoprene-styrene copolymer), styrene-ethylene-butene- Hydrogenated styrene-conjugated diene copolymers such as styrene copolymers (SEBS, hydrogenated products of styrene-butadiene copolymers) and the like. Industrially, Tufprene (manufactured by Asahi Kasei Corporation), Kraton (manufactured by Kraton Polymer Japan), Sumitomo TPE-SB (manufactured by Sumitomo Chemical Co., Ltd.), Epo Friend (manufactured by Daicel Chemical Industry Co., Ltd.), and Rabalon (manufactured by Mitsubishi Chemical Corporation) ), Septon (manufactured by Kuraray), tuftec (manufactured by Asahi Kasei), and the like. The styrene-based elastomer may be a hydrogenated substance or an unhydrogenated substance.

Examples of the rubber-based material include natural rubber, synthetic isoprene rubber (IR), butadiene rubber (BR), styrene-butadiene rubber (SBR), chloroprene rubber (CR), Acrylonitrile-butadiene copolymer rubber (NBR), Butyl rubber (IIR), halogenated butyl rubber, acrylic rubber, urethane rubber, polysulfide rubber, etc. These can be used alone or in combination of two or more.

As the substrate, a thin film formed by laminating a plurality of layers as described above can be used. In addition, a substrate in which a thin film formed of the above-mentioned material and another thin film are laminated may be used.

When a plurality of layers of films are laminated, in order to achieve the above-mentioned physical properties, the structure can arrange a film with a high contribution rate in the center with a relatively thick thickness, and sandwich the other film with a relatively low thickness and a relatively thin thickness. film. In addition, the use of a resin with a relatively low glass transition temperature (Tg) is better in achieving the above-mentioned physical properties, but because such a resin has high adhesiveness, when such a resin is provided on the surface of a semiconductor processing plate, When manufacturing or using a semiconductor processing sheet, there is a possibility that the operation may be difficult. Therefore, a resin film having a relatively low glass transition temperature (Tg) can be sandwiched between a resin film having a relatively high glass transition temperature (Tg), or a resin film layer having a relatively low glass transition temperature (Tg). A resin film having a relatively high glass transition temperature (Tg) allows the achievement of the above-mentioned physical properties to coexist with operability.

Regarding the sheet for semiconductor processing of this embodiment, when the substrate is composed of only a base material, it is preferable that the base material has adhesiveness. This adhesiveness can be used as a base material in a normal state, and it is preferable to use a self-adhesive material.

In addition, as for the sheet for semiconductor processing of this embodiment, only the base material is used, and when the base material is formed by laminating a plurality of thin films, only the outermost thin film may be included among the plurality of laminated thin films. Or only one of them is an adhesive person. For example, a resin having a relatively high glass transition temperature (Tg) is laminated to a resin film having a relatively low glass transition temperature (Tg). The film can exhibit adhesiveness only on one side. In addition, the outermost layer of the semiconductor processing sheet in this specification does not include a peeling sheet and the like which are removed during use.

The base material of this embodiment may contain various additives such as pigments, dyes, flame retardants, plasticizers, antistatic agents, lubricants, and fillers in the film using the resin-based material as a main material. Examples of the pigment include titanium dioxide and carbon black. Examples of the filler include organic materials such as melamine resin, inorganic materials such as fumed silica, and metal materials such as nickel particles. The content of such additives is not particularly limited, and it is preferable to maintain the range in which the substrate can exhibit a desired function.

When the sheet for semiconductor processing has an adhesive layer to be described later, the substrate may be oxidized or roughened on one or both sides for the purpose of improving the adhesion of the adhesive layer laminated on the surface. Surface treatment such as coating or primer layer treatment to form a primer layer. Examples of the oxidation method include, for example, corona discharge treatment, plasma discharge treatment, chromium oxidation treatment (wet), flame treatment, hot air treatment, ozone, ultraviolet irradiation treatment, and the like. Examples of the unevenness method include, for example, Sand blasting method, spray processing method, etc.

In addition, when the adhesive layer contains an energy ray-curable adhesive, it is preferable that the base material has a permeability to energy rays. In particular, when ultraviolet rays are used as energy rays, the substrate is preferably transparent to ultraviolet rays; when electron rays are used as energy rays, the substrate is preferably transparent to electron rays.

The method for manufacturing the semiconductor processing sheet and the substrate according to this embodiment is not particularly limited, and for example, a melt extrusion method such as a casting method (melt casting method), a T-die method, or an expansion method, Any method method. Among them, from the viewpoint of making it easy to control the thickness error, it is preferable to manufacture the base material by a casting method. In this case, it is preferable that the liquid mixture (resin before curing, resin solution, etc.) as the material of the base material is cast on the engineering sheet to form a thin film, and then the coating film is hardened to form a thin film. And manufacture the substrate.

The thickness of the substrate is not limited as long as the plate for semiconductor processing can function properly in a desired step. The thickness of the substrate is preferably 20 μm or more, and particularly preferably 40 μm or more. The thickness is preferably 250 μm or less, and particularly preferably 200 μm or less.

When measuring the thickness at 2 cm intervals, the standard deviation of the thickness of the substrate is preferably 2 μm or less, particularly preferably 1.5 μm or less, and further preferably 1 μm or less. By setting the standard deviation to 2 μm or less, the thickness of the sheet for semiconductor processing can be made high-precision, and the sheet for semiconductor processing can be uniformly extended.

3. Adhesive layer

It is preferable that the sheet for semiconductor processing of this embodiment further includes an adhesive layer laminated on at least one surface of the substrate. Thereby, the sheet for semiconductor processing can easily exhibit desired adhesiveness on the surface on the side of the adhesive layer, and a semiconductor wafer or the like can be satisfactorily adhered to the surface.

The adhesive layer is not particularly limited as long as the above-mentioned physical properties can be achieved in the sheet for semiconductor processing. The adhesive layer may be composed of a non-energy-ray-curable adhesive or an energy-ray-curable adhesive. As the non-energy ray hardening adhesive, it is preferable to have a desired adhesive force and re-peelability. For example, acrylic adhesive, rubber-based adhesive, silicone-based adhesive, urethane-based adhesive can be used. Adhesives, polyester-based adhesives, polyvinyl ether-based adhesives, and the like. Among these, an acrylic adhesive is preferable because it can effectively suppress the peeling of a semiconductor wafer or the like when extending a sheet for semiconductor processing.

On the other hand, energy-ray-curable adhesives are hardened by irradiation with energy rays, which reduces the adhesive force. Therefore, when a semiconductor wafer and a semiconductor processing plate are to be separated, they can be easily separated by irradiating energy rays. .

The energy ray-curable adhesive constituting the adhesive layer may be composed of a polymer having energy ray curability as a main component, or a non-energy ray-curable polymer (a polymer having no energy ray-curable) and A mixture of monomers and / or oligomers having at least one energy ray-curable group is used as a main component. In addition, it may be a mixture of an energy ray-curable polymer and a non-energy ray-curable polymer; it may also be a polymer having energy ray-curable properties and a monomer having at least one or more energy ray-curable groups and A mixture of oligomers; or a mixture of these three.

First, a case where the energy ray-curable adhesive is based on a polymer having energy ray-curability as a main component will be described below.

(Meth) acrylate (co) polymer (A) (hereinafter, sometimes referred to as a polymer having energy ray-curable polymer) "Energy ray hardening polymer (A)".) The energy ray-curable polymer (A) is preferably an acrylic copolymer (a1) having a functional group-containing monomer unit and an unsaturated group-containing compound (a2) having a functional group capable of bonding to the functional group. Receiver of the response. In addition, in this specification, (meth) acrylate means both an acrylate and a methacrylate. Other similar terms are the same.

The acrylic copolymer (a1) preferably contains a functional group-containing monomer Derived constituent units and constituent units derived from a (meth) acrylate monomer or a derivative thereof.

The functional group-containing monomer as a constituent unit of the acrylic copolymer (a1) has a functional group such as a hydroxyl group, a carboxyl group, an amine group, a substituted amine group, or an epoxy group that can be bonded to a polymerizable double bond in the molecule. Monomers are preferred.

Examples of the hydroxyl-containing monomer include 2-hydroxyethyl (meth) acrylate, 2-hydroxypropyl (meth) acrylate, 3-hydroxypropyl (meth) acrylate, and (meth) acrylic acid 2 -Hydroxybutyl ester, 3-hydroxybutyl (meth) acrylate, 4-hydroxybutyl (meth) acrylate, etc. These can be used alone or in combination of two or more.

As the carboxyl group-containing monomer, for example, ethylenically unsaturated carboxylic acids such as acrylic acid, methacrylic acid, crotonic acid, maleic acid, itaconic acid, and citraconic acid can be used. These may be used alone or in combination of two or more.

Examples of the amine-containing monomer or substituted amine-containing monomer include, for example, aminoethyl (meth) acrylate, n-butylaminoethyl (meth) acrylate, and the like. These may be used alone or in combination of two or more.

As the (meth) acrylic acid ester monomer constituting the acrylic copolymer (a1), in addition to (meth) acrylic acid alkyl esters having 1 to 20 carbon atoms in the alkyl group, it can be suitably used. A monomer having an alicyclic structure (alicyclic structure-containing monomer).

As the (meth) acrylic acid alkyl ester, in particular, the (meth) acrylic acid alkyl ester having 1 to 18 carbon atoms can be suitably used. For example, (meth) acrylic acid methyl ester, (meth) Ethyl acrylate, propyl (meth) acrylate, n-butyl (meth) acrylate, 2-ethylhexyl (meth) acrylate, and the like. These may be used individually by 1 type, and may be used in combination of 2 or more type.

Examples of the alicyclic structure-containing monomer include cyclohexyl (meth) acrylate, dicyclopentyl (meth) acrylate, adamantyl (meth) acrylate, isoamyl (meth) acrylate, Dicyclopentenyl (meth) acrylate, dicyclopentenyloxy (meth) acrylate, and the like. These may be used individually by 1 type, and may be used in combination of 2 or more type.

The proportion of the acrylic copolymer (a1) containing a constituent unit derived from the functional group-containing monomer is preferably 1% by mass or more, particularly preferably 5% by mass or more, and further preferably 10% by mass or more. . In addition, the proportion of the acrylic copolymer (a1) containing a constituent unit derived from the functional group-containing monomer is preferably 35% by mass or less, particularly preferably 30% by mass or less, and further 25% by mass or less. Better.

The proportion of the acrylic copolymer (a1) containing a (meth) acrylic acid ester monomer or a derivative thereof derived from the constituent unit is preferably 50% by mass or more, and particularly preferably 60% by mass or more. More preferably, it is more than 70% by mass. The proportion of the acrylic copolymer (a1) containing a (meth) acrylic acid ester monomer or a derivative thereof is preferably 99% by mass or less, particularly 95% by mass or less. It is more preferably 90% by mass or less.

The acrylic copolymer (a1) is obtained by copolymerizing a functional group-containing monomer with a (meth) acrylic acid ester monomer or a derivative thereof by a conventional method. It can also be copolymerized with methacrylamide, vinyl formate, vinyl acetate, styrene, etc.

The acrylic copolymer (a1) having the functional group-containing monomer unit is combined with an unsaturated group-containing group having a functional group bonded to the functional group. The substance (a2) is reacted to obtain an energy ray-curable polymer (A).

The functional group of the unsaturated group-containing compound (a2) can be appropriately selected according to the type of the functional group of the functional group-containing monomer unit of the acrylic copolymer (a1). For example, when the functional group of the acrylic copolymer (a1) is a hydroxyl group, an amine group, or a substituted amine group, the functional group of the unsaturated group-containing compound (a2) is preferably an isocyanate group or an epoxy group. Acrylic acid When the functional group of the copolymer (a1) is an epoxy group, the functional group of the unsaturated group-containing compound (a2) is preferably an amine group, a carboxyl group, or an aziridinyl group.

唑啉、2-異丙烯基-2-

唑啉等。 In addition, the unsaturated group-containing compound (a2) contains at least one energy ray polymerizable carbon-carbon double bond in the molecule, preferably 1 to 6 carbon atoms, and further preferably 1 to 4 carbon atoms. Specific examples of such an unsaturated group-containing compound (a2) include, for example, 2-methacryloxyethyl isocyanate, m-isopropenyl-α, α-dimethylbenzyl isocyanate, and methyl group. Propylene isocyanate, allyl isocyanate, 1,1- (bispropenyloxymethyl) ethyl isocyanate; obtained by reacting a diisocyanate compound or a polyisocyanate compound with hydroxyethyl (meth) acrylate Acrylic fluorenyl monoisocyanate compound; Acrylic fluorenyl monoisocyanate compound obtained by reaction of a diisocyanate compound or polyisocyanate compound, a polyol compound, and hydroxyethyl (meth) acrylate; glycidyl (meth) acrylate ; (Meth) acrylic acid, 2- (1-aziridinyl) ethyl (meth) acrylate, 2-vinyl-2-

Oxazoline, 2-isopropenyl-2-

Oxazoline and so on.

Relative to the number of moles of the functional group-containing monomer of the acrylic copolymer (a1), the proportion of the unsaturated group-containing compound (a2) used is preferably 50 mol% or more, particularly 60 mol% or more Better, further to 70 mol% Better. In addition, for the molar number of the functional group-containing monomer of the acrylic copolymer (a1), the proportion of the unsaturated group-containing compound (a2) used is preferably 95 mol% or less, and particularly 93 mol%. The following is preferable, and more preferably 90 mol% or less.

The reaction between the acrylic copolymer (a1) and the unsaturated group-containing compound (a2) can be based on the functional group of the acrylic copolymer (a1) and the functional group of the unsaturated group-containing compound (a2). The combination is suitable to select the reaction temperature, pressure, solvent, time, presence or absence of catalyst, and type of catalyst. Thereby, the functional group existing in the acrylic copolymer (a1) reacts with the functional group existing in the unsaturated group-containing compound (a2), and an unsaturated group is introduced into the side chain in the acrylic copolymer (a1). To obtain an energy ray-curable polymer (A).

The weight-average molecular weight (Mw) of the energy ray-curable polymer (A) thus obtained is preferably 10,000 or more, particularly preferably 150,000 or more, and more preferably 200,000 or more. The weight average molecular weight (Mw) is preferably 1.5 million or less, and particularly preferably 1 million or less. In addition, the weight average molecular weight (Mw) in this specification is a standard polystyrene conversion value measured by the gel permeation chromatography method (GPC method).

Even if the energy ray curable adhesive is based on a polymer such as an energy ray curable polymer (A) having energy ray curability as the main component, the energy ray curable adhesive may further contain energy ray curability. Monomer and / or oligomer (B).

As the energy ray-curable monomer and / or oligomer (B), for example, an ester of a polyhydric alcohol and (meth) acrylic acid can be used.

As the energy ray-curable monomer and / or oligomer (B), there are listed For example, monofunctional acrylates such as cyclohexyl (meth) acrylate, isoamyl (meth) acrylate, trimethylolpropane tri (meth) acrylate, neopentaerythritol tris (methyl) Base) acrylate, neopentaerythritol tetra (meth) acrylate, dinepentaerythritol hexa (meth) acrylate, 1,4-butanediol di (meth) acrylate, 1,6-hexane Polyfunctional acrylates and polyester oligomers such as glycol di (meth) acrylate, polyethylene glycol di (meth) acrylate, dimethylol tricyclodecane di (meth) acrylate, etc. (Meth) acrylate, polyurethane oligo (meth) acrylate, and the like.

When an energy ray-curable monomer and / or oligomer (B) is blended with the energy ray-curable polymer (A), the energy ray-curable monomer and / or oligomer in the energy ray-curable adhesive is used. The content of the substance (B) is preferably more than 0 parts by mass, and more preferably 60 parts by mass or more, based on 100 parts by mass of the energy ray-curable polymer (A). The content is preferably 250 parts by mass or less, and particularly preferably 200 parts by mass or less, based on 100 parts by mass of the energy ray-curable polymer (A).

Here, when ultraviolet rays are used as the energy rays for curing the energy-ray-curable adhesive, it is preferable to add a photopolymerization initiator (C). By using the photopolymerization initiator (C), the polymerization curing time can be reduced. And light exposure.

Specific examples of the photopolymerization initiator (C) include benzophenone, acetophenone, benzoin, benzoin methyl ether, benzoin ether, benzoin isopropyl ether, benzoin isobutyl ether, benzoin benzoic acid, and benzoin benzoic acid methyl ester. Ester, benzoin dimethyl ketal, 2,4-diethylthioxanthone, 1-hydroxycyclohexylphenyl ketone, benzyl diphenyl sulfide, tetramethylamine thiomethanyl monosulfide, azobis Isobutyronitrile, benzyl, bibenzyl, biacetamidine, β-chloroanthraquinone, (2,4,6-trimethylbenzyldiphenyl) phosphine oxide, 2-benzothiazole-N, N-di Ethyl dithiocarbamate, oligomeric {2-hydroxy-2-methyl Phenyl-1- [4- (1-propenyl) phenyl] acetone}, 2,2-dimethoxy-1,2-diphenylethane-1-one. These can be used alone or in combination of two or more.

The amount of the photopolymerization initiator (C) used refers to the energy ray-curable copolymer relative to the energy ray-curable copolymer (A) (when the energy ray-curable monomer and / or oligomer (B) is blended). The total amount of the substance (A) and the energy ray-curable monomer and / or oligomer (B) is 100 parts by mass), preferably 0.1 part by mass or more, and particularly preferably 0.5 part by mass or more. In addition, the usage amount of the photopolymerization initiator (C) refers to energy ray curing when compared to the energy ray-curable copolymer (A) (the energy ray-curable monomer and / or oligomer (B) is formulated). The total amount of the copolymer (A) and the energy ray-curable monomer and / or oligomer (B) is 100 parts by mass), preferably 10 parts by mass or less, and particularly preferably 6 parts by mass or less.

In addition to the above-mentioned components, the energy ray-curable adhesive may be appropriately blended with other components. Examples of other components include, for example, a non-energy-ray-curable polymer component or an oligomer component (D), a bridging agent (E), and the like.

Examples of the non-energy-ray-curable polymer component or oligomer component (D) include, for example, polyacrylate, polyester, polyurethane, polycarbonate, polyolefin, and the like, and the weight average molecular weight (Mw) A polymer or oligomer of 30 to 2.5 million is preferred. By blending this component (D) in an energy ray-curable adhesive, it is possible to improve the adhesiveness and peelability before curing, the strength after curing, adhesion to other layers, storage stability, and the like. The blending amount of the component (D) is not particularly limited, and can be appropriately determined in a range of more than 0 parts by mass and 50 parts by mass or less with respect to 100 parts by mass of the energy ray-curable copolymer (A).

唑啉化合物、金屬烷氧化合物、金屬螯合物化合物、金屬鹽、銨鹽、反應性酚樹脂等。 As the bridging agent (E), a polyfunctional compound having a reactivity with a functional group possessed by the energy ray-curable copolymer (A) and the like can be used. Examples of such polyfunctional compounds include isocyanate compounds, epoxy compounds, amine compounds, melamine compounds, aziridine compounds, hydrazine compounds, aldehyde compounds,

An oxazoline compound, a metal alkoxy compound, a metal chelate compound, a metal salt, an ammonium salt, a reactive phenol resin, and the like.

The blending amount of the bridging agent (E) is preferably 0.01 parts by mass or more relative to 100 parts by mass of the energy ray-curable copolymer (A), particularly preferably 0.03 parts by mass or more, and more preferably 0.04 parts by mass or more . The blending amount of the bridging agent (E) is preferably 8 parts by mass or less, more preferably 5 parts by mass or less, and further 3.5 parts by mass or less based on 100 parts by mass of the energy ray-curable copolymer (A). Better.

Next, the case where the energy ray-curable adhesive is based on a mixture of a non-energy ray-curable polymer component and a monomer and / or oligomer having at least one energy ray-curable group as a main component is described below. .

As the non-energy-ray-curable polymer component, for example, the same component as the above-mentioned acrylic copolymer (a1) can be used.

As the monomer and / or oligomer having at least one energy ray-curable group, the same as the component (B) can be selected. The blending ratio of the non-energy-ray-curable polymer component to a monomer and / or oligomer having at least one or more energy-ray-curable polymer components is at least 100 parts by mass of the non-energy-ray-curable polymer component. The monomer and / or oligomer having one or more energy ray-curable groups is preferably 1 part by mass or more, and particularly preferably 60 parts by mass or more. In addition, the blending ratio is preferably 200 parts by mass or less with respect to 100 parts by mass of the non-energy ray-curable polymer component, and a monomer and / or oligomer having at least one energy ray-curable group, particularly It is preferably 160 parts by mass or less.

In this case, similarly to the above, a photopolymerization initiator (C) and a bridging agent (E) can be appropriately blended.

The thickness of the adhesive layer is not particularly limited, and for example, it is preferably 3 μm or more, and particularly preferably 5 μm or more. The thickness is preferably 50 μm or less, and particularly preferably 40 μm or less.

4. Peel off the sheet

Regarding the sheet for semiconductor processing of this embodiment, the sheet can be laminated on the surface for the purpose of protecting the adhesive surface until the adhesive surface is adhered to an adherend such as a semiconductor wafer. The configuration of the release sheet is arbitrary, and examples thereof include a plastic film subjected to a release treatment with a release agent or the like. Specific examples of the plastic film include polyester films such as polyethylene terephthalate, polybutylene terephthalate, polyethylene naphthalate, and polypropylene or polyethylene. Polyolefin film. As the release agent, a silicone-based, fluorine-based, long-chain alkyl-based, or the like can be used. Among these, a silicone-based one which is inexpensive and can obtain stable performance is preferred. The thickness of the release sheet is not particularly limited, but is usually about 20 to 250 μm.

5. Manufacturing method of semiconductor processing plate

The plate for semiconductor processing of this embodiment can be manufactured similarly to the plate for conventional semiconductor processing. In particular, as a method for manufacturing a semiconductor processing plate formed of a base material and an adhesive layer, as long as an adhesive layer formed of the above-mentioned adhesive composition is laminated on one surface of the base material, the details thereof The method is not particularly limited. As an example, an adhesive composition containing an adhesive layer, and a coating liquid containing a solvent or a dispersant, if desired, may be prepared. On one side of the substrate, a die coater or shower curtain coating may be applied. A coating machine, a spray coater, a slit coater, a doctor blade coater, etc. apply the coating solution to form a coating film. The coating film is dried, thereby forming an adhesive layer. The properties of the coating liquid are not particularly limited as long as the coating liquid can be applied. The coating liquid may contain a component for forming an adhesive layer as a solute or may be contained as a dispersant.

In addition, as another example of a method for manufacturing a sheet for semiconductor processing, a coating liquid is formed on the peeling surface of the peeling sheet to form a coating film, and the sheet is dried to form an adhesive layer and the peeling sheet. The laminated body is obtained by pasting the surface of the laminated body on the side of the adhesive layer opposite to the side of the release sheet to the base material to obtain a laminated body of the sheet for semiconductor processing and the release sheet. The release sheet of the laminated body can be peeled as an engineering material so as to protect the adhesive layer until the adherend such as a semiconductor wafer or a semiconductor wafer is adhered.

When the coating solution contains a bridging agent, the non-energy ray-curable acrylic adhesive (N) or energy ray in the coating film can be hardened by changing the above-mentioned drying conditions (temperature, time, etc.), or by separately setting a heat treatment. The cross-linking reaction between the adhesive (A) and the bridging agent may be performed, and a bridging structure may be formed in the adhesive layer at a desired existence density. In order to make the bridging reaction fully proceed, after laminating the adhesive layer on the base material by the method described above, the obtained semiconductor processing sheet may be left in an environment of 23 ° C. and a relative humidity of 50% for several days. And mature.

6. How to use the plate for semiconductor processing

The semiconductor processing sheet of this embodiment can be used, for example, to increase the interval between a plurality of semiconductor wafers laminated on one surface of the semiconductor processing sheet.

In particular, the interval between adjacent semiconductor wafers of a plurality of semiconductor wafers laminated on one surface of a semiconductor processing plate is preferably increased to 200 μm or more. Moreover, the upper limit of the interval is not particularly limited. It may be, for example, 6000 μm.

In addition, the semiconductor processing sheet of this embodiment can be used in a case where it extends at least in two axes to increase the interval between a plurality of semiconductor wafers laminated on one surface of the semiconductor processing sheet. At this time, the sheet for semiconductor processing is stretched by applying tension in four directions of + X axis direction, -X axis direction, + Y axis direction, and -Y axis direction, which are orthogonal to each other in the X and Y axes, More specifically, they are stretched in the MD direction and the CD direction of the substrate, respectively.

The two-axis extension described above can be performed using, for example, a separating device that applies tension in the X-axis direction and the Y-axis direction. Here, the X-axis and the Y-axis are orthogonal, and one of the directions parallel to the X-axis is the + X-axis direction, and the direction opposite to the + X-axis direction is the -X-axis direction, which is a direction parallel to the Y-axis. One of them is the + Y axis direction, and the direction opposite to the + Y axis direction is the -Y axis direction.

The separating device preferably applies tension to four directions of the + X-axis direction, the -X-axis direction, the + Y-axis direction, and the -Y-axis direction on the semiconductor processing plate, and each of the four directions has a plurality of holding means, And plural tension applying means corresponding to these. The number of holding means and tension applying means in each direction may be determined depending on the size of the semiconductor processing sheet, and may be, for example, about 3 or more and 10 or less.

Here, for example, in the group including a plurality of holding means and a plurality of tension applying means provided for applying tension in the + X-axis direction, it is preferable that each holding means includes a holding member for holding a semiconductor processing plate, and each The tension applying means moves the holding member corresponding to the tension applying means in the + X axis direction to apply tension to the semiconductor processing sheet. Then, it is preferable to use a plurality of tension applying means to independently move the holding means in the + X axis direction. Way setting. In addition, it is preferable that three groups including a plural holding means and a plural tension applying means, which are provided to apply tension to the -X axis direction, the + Y axis direction, and the -Y axis direction, have the same configuration. Thereby, the above-mentioned separating device can apply a tension of different magnitude to each of the regions of the direction orthogonal to each direction to the plate for semiconductor processing.

Generally, four holding members are used to hold a semiconductor processing plate from four directions of + X-axis direction, -X-axis direction, + Y-axis direction, and -Y-axis direction, and when extending in these four directions, For semiconductor processing plates, in addition to the four directions, the combined directions (for example, the combined direction of + X-axis direction and + Y-axis direction, the combined direction of + Y-axis direction and -X-axis direction, The combined direction of the -X axis direction and the -Y axis direction, and the combined direction of the -Y axis direction and the + X axis direction) are also applied with tension. As a result, the interval between the semiconductor wafer on the inner side of the semiconductor processing plate and the interval between the semiconductor wafer on the outer side may be different.

However, in the above-mentioned separating device, since the plural tension applying means can independently apply tension to the semiconductor processing plate in each of the + X-axis direction, -X-axis direction, + Y-axis direction, and -Y-axis direction, The semiconductor processing plate can be extended so that the difference in the space | interval of the inside and outside of the semiconductor processing plate mentioned above may be eliminated. As a result, the interval between semiconductor wafers can be adjusted accurately.

It is preferable that the separation device further includes a measuring means for measuring a distance between semiconductor wafers. Here, it is preferable that the tension applying means is provided so that the plurality of holding members can be individually moved based on the measurement result of the measuring means. Thereby, based on the measurement result of the interval of the semiconductor wafer by the above-mentioned measuring means, the interval can be further adjusted, and as a result, the half can be adjusted more accurately. Space between conductor wafers.

Furthermore, in the separation device, the holding means may be a chuck means such as a mechanical chuck or a clamping cylinder, a pressure reducing means such as a pressure reducing pump or a vacuum aspirator, or a bonding agent, The magnetic force and the like support the structure of the semiconductor processing plate. In addition, it can also be used as a holding member in the chuck means. For example, it has a structure including a lower supporting member that supports a semiconductor processing plate from below, a driving device that supports the following supporting member, and a driving device that supports the device. The output shaft supports an upper support member that can drive the semiconductor processing plate from above by driving the driving machine. Examples of the driving device include electric machines such as rotary motors, translational motors, linear motors, single-axis robots, and articulated robots, actuators such as cylinders, hydraulic cylinders, rodless cylinders, and rotary cylinders.

Moreover, in the said separation apparatus, the tension | tensile_strength application means may be equipped with the drive apparatus, and the holding member is moved by this drive apparatus. As the driving device, those described above can be used. For example, the tension applying means may have a configuration including a translation motor as a driving device and an output shaft interposed between the translation motor and the holding member, and the driven translation motor moves the holding member via the output shaft.

When the interval between semiconductor wafers is increased by using the semiconductor processing sheet according to this embodiment, the interval can be increased from a state where the semiconductor wafers are in contact with each other, or a state where the interval between the semiconductor wafers is hardly enlarged, or from a semiconductor wafer The interval between them has been expanded to a predetermined interval, and the interval is further expanded.

From the state where the semiconductor wafers are in contact with each other, or the state where the interval between the semiconductor wafers is hardly widened, when the interval is enlarged, for example, by cutting After the semiconductor wafer is divided on the dicing sheet to obtain a plurality of semiconductor wafers, the plurality of semiconductor wafers are transferred from the dicing sheet to the semiconductor processing sheet according to this embodiment, and then the interval between the semiconductor wafers is increased. Alternatively, after a semiconductor wafer is divided on the semiconductor processing plate according to this embodiment to obtain a plurality of semiconductor wafers, the interval between the semiconductor wafers may be increased.

When the interval between the semiconductor wafers has been expanded to a predetermined interval, when further increasing the interval, another semiconductor processing plate is used. It is preferable that the semiconductor processing plates of this embodiment are used to separate the semiconductor wafers from each other. After extending the interval to a predetermined interval, the semiconductor wafer is transferred from the plate to the semiconductor processing plate according to this embodiment, and the semiconductor processing plate according to this embodiment can be further extended by extending the semiconductor processing plate according to this embodiment. Increase the interval between semiconductor wafers. Furthermore, the transfer of the semiconductor wafer and the extension of the semiconductor processing sheet can be repeated several times until the interval between the semiconductor wafers becomes a desired distance.

In addition, the semiconductor processing sheet of the present embodiment is preferably used for applications requiring relatively large separation of semiconductor wafers. As an example of such applications, fan-out semiconductor wafers are preferred. Manufacturing Method for FO-WLP. Examples of the method for manufacturing such a FO-WLP include the first aspect and the second aspect described below.

(1) The first aspect

A first aspect of the FO-WLP manufacturing method for the semiconductor processing sheet of this embodiment will be described below. In addition, in this first aspect, the semiconductor processing sheet of the present embodiment is used as a second adhesive sheet 20 to be described later.

FIG. 1 (A) shows a semiconductor wafer W adhered to the first adhesive plate 10. The semiconductor wafer W has a circuit surface W1, and a circuit W2 is formed on the circuit surface W1. The first adhesive plate 10 is adhered to the back surface W3 opposite to the circuit surface W1 of the semiconductor wafer W. The first adhesive plate 10 has a first base film 11 and a first adhesive layer 12. The first adhesive layer 12 is laminated on the first base film 11.

[Cutting steps]

FIG. 1 (B) shows a plurality of semiconductor wafers CP held on the first adhesive plate 10.

The semiconductor wafer W held on the first adhesive plate 10 is singulated to form a plurality of semiconductor wafers CP. For cutting, use a cutting means such as a dicing saw. The cutting depth during dicing is set to the total of the thickness of the semiconductor wafer W and the first adhesive layer 12 and the depth of the abrasion part added to the dicing saw. By the dicing, the first adhesive layer 12 is also cut into the same size as the semiconductor wafer CP. Furthermore, a cut may be formed in the first base film 11 by cutting.

The dicing may be performed by irradiating the semiconductor wafer W with a laser instead of the cutting means such as the dicing saw used above. For example, by irradiating a laser, the semiconductor wafer W can be completely cut off, and the individual wafers can be divided into a plurality of semiconductor wafers CP. Alternatively, after the modified layer is formed inside the semiconductor wafer W by the irradiation of laser light, the semiconductor wafer W is modified by stretching the first adhesive plate 10 in a first expansion step described later. The position of the layer is broken, and the semiconductor wafer CP is fragmented (stealth dicing). In the case of stealth dicing, it is the irradiation of laser light, for example, the laser light in the infrared light field is focused on the semiconductor wafer W It irradiates with the focus set inside. In these methods, the irradiation of laser light can be performed from either side of the semiconductor wafer W.

[First expansion step]

FIG. 1 (C) is a diagram illustrating a step (hereinafter, sometimes referred to as a “first expansion step”) of stretching the first adhesive sheet 10 holding the plurality of semiconductor wafers CP.

After the plurality of semiconductor wafers CP are singulated by dicing, the first adhesive plate 10 is stretched to increase the interval between the plurality of semiconductor wafers CP. In addition, during the stealth dicing, the semiconductor wafer W is broken at the position of the reforming layer by stretching the first adhesive plate 10, and the plurality of semiconductor wafers CP are singulated, and the distance between the plurality of semiconductor wafers CP is enlarged. interval. In the first expansion step, the stretching method of the first adhesive sheet 10 is not particularly limited. Examples of the method of stretching the first adhesive sheet 10 include, for example, a method of stretching the first adhesive sheet 10 against a ring-shaped or circular dilator; or a second adhesive sheet using a holding member or the like. A method of stretching the outer periphery of the sheet by grasping it.

The first adhesive sheet 10 preferably has a tensile elastic modulus suitable for the cutting step and at the same time suitable for the first expansion step. From this point of view, it is preferable that the first adhesive sheet 10 has a larger tensile elastic modulus than the second adhesive sheet 20 described later. Thereby, the first adhesive plate 10 can exhibit a predetermined expandability without impairing the performance at the time of cutting, and the second adhesive plate 20 can exhibit more excellent expandability.

In addition, as shown in FIG. 1 (C), the distance between the semiconductor wafers CP is D1. The distance D1 is, for example, preferably 15 μm or more and 110 μm or less.

[Transfer step]

FIG. 2 (A) is a diagram illustrating a step (hereinafter, sometimes referred to as a “transfer step”) of transferring the plurality of semiconductor wafers CP to the second adhesive sheet 20 after the first expansion step. After the first adhesive plate 10 is stretched to extend the distance D1 between the plurality of semiconductor wafers CP, the second adhesive plate 20 is adhered to the circuit surface W1 of the semiconductor wafer CP. Here, as the second adhesive plate 20, a semiconductor processing plate according to this embodiment is used.

The second adhesive plate 20 includes a second base film 21 and a second adhesive layer 22. The second adhesive plate 20 is preferably adhered in such a manner that the second adhesive layer 22 covers the circuit surface W1.

The adhesive force of the second adhesive layer 22 is better than that of the first adhesive layer 12. If the adhesive force of the second adhesive layer 22 is large, after the plurality of semiconductor wafers CP are transferred to the second adhesive plate 20, the first adhesive plate 10 is easily peeled off.

The second adhesive plate 20 can be adhered to the second ring frame together with the plurality of semiconductor wafers CP. At this time, a second ring frame is placed on the second adhesive layer 22 of the second adhesive plate 20, and it is pressed and fixed gently. Thereafter, the second adhesive layer 22 exposed on the inner side of the ring shape of the second ring frame is pressed against the circuit surface W1 of the semiconductor wafer CP, and the plurality of semiconductor wafers CP are fixed to the second adhesive plate 20.

After the second adhesive sheet 20 is adhered, the first adhesive sheet 10 is peeled off to expose the back surface W3 of the plurality of semiconductor wafers CP. After the first adhesive sheet 10 is peeled off, the distance D1 between the plurality of semiconductor wafers CP expanded in the first expansion step is preferably maintained.

[Second expansion step]

FIG. 2 (B) is a diagram illustrating a drawing step (hereinafter, sometimes referred to as a “second expansion step”) of the second adhesive sheet 20 holding the plurality of semiconductor wafers CP.

In the second expansion step, the interval between the plurality of semiconductor wafers CP is further expanded. In the second expanding step, the method of stretching the second adhesive plate 20 is not particularly limited. Examples of the method for stretching the second adhesive sheet 20 include, for example, a method of stretching the second adhesive sheet 20 against a ring-shaped or circular dilator; or using a holding member or the like to stretch the second adhesive sheet. A method in which the outer periphery of the sheet is grasped and stretched. As the latter method, for example, a biaxial stretching method using the above-mentioned separation device or the like is mentioned. Among these, a two-axis extension method is preferable from the viewpoint that the interval between the semiconductor wafers CP can be greatly increased.

In addition, as shown in FIG. 2 (B), the interval between the semiconductor wafers CP after the second expansion step is D2. The distance D2 is greater than the distance D1. The distance D2 is preferably, for example, 200 μm or more and 6000 μm or less.

[Sealing step]

FIG. 2 (C) is a diagram illustrating a step (hereinafter, sometimes referred to as a “sealing step”) of sealing the plurality of semiconductor wafers CP using the sealing member 60.

The sealing step is performed after the second expansion step. The circuit surface W1 is left, and the plurality of semiconductor wafers CP are covered with the sealing member 60 to form the sealing body 3. A sealing member 60 is also filled between the plurality of semiconductor wafers CP. Here, since the circuit surface W1 and the circuit W2 are covered by the second adhesive plate 20, the circuit surface W1 can be prevented from being covered by the sealing member 60.

By the sealing step, a plural number is obtained which separates each from a predetermined distance. The semiconductor wafer CP is embedded in the sealing body 3 of the sealing member 60. In the sealing step, it is preferable that the plurality of semiconductor wafers CP are covered with the sealing member 60 while maintaining the distance D2.

After the sealing step, the second adhesive plate 20 is peeled off to expose the circuit surface W1 of the semiconductor wafer CP and the surface 3A of the sealing body 3 that is in contact with the second adhesive plate 20.

[Rewiring formation step and connection step of external terminal electrode]

FIG. 3 (A) shows a cross-sectional view of the sealing body 3 after the second adhesive plate 20 is peeled off. The sealing body 3 is sequentially subjected to: a rewiring layer forming step of forming a rewiring layer; and a step of connecting an external terminal electrode to the formed rewiring layer. In addition, in FIG. 3 (A), the internal terminal electrode W4 of the circuit W2 shown in FIG. 2 (C) is shown in more detail.

Through the rewiring layer forming step and the connection step with the external terminal electrode, as shown in FIG. 3 (B), a rewiring layer 5 connected to the internal terminal electrode W4 and an external terminal electrode connected to the rewiring layer 5 are formed. 6. Specifically, it is formed as follows. First, a first insulating layer 4A is formed on the circuit surface W1 of the semiconductor wafer CP and the surface 3A of the sealing body 3. Next, the redistribution layer 5 is formed so as to be electrically connected to the internal terminal electrode W4. Furthermore, a second insulating layer 4B is formed so as to cover the redistribution layer 5. At this time, the wiring layer 5 is rewired, leaving the external electrode pad 5A and covered with the second insulating layer 4B. Finally, an external terminal electrode 6 such as a solder ball is placed on the external electrode pad 5A, and the external terminal electrode 6 and the external electrode pad 5A are electrically connected by soldering or the like.

[Second cutting step]

In FIG. 3 (C), the sealing body 3 to be connected to the external terminal electrode 6 is shown. A cross-sectional view of a step of slicing (hereinafter, sometimes referred to as a "second cutting step"). In the second dicing step, the sealing bodies 3 are formed into pieces in units of the semiconductor wafer CP. The method of forming the sealing body into three pieces is not particularly limited. For example, the sealing body can be formed into three pieces by the same method as the method of dicing the semiconductor wafer W described above. The three steps of forming the sealing body can be performed by sticking the sealing body to an adhesive plate such as a cutting board.

By singulating the sealing body into three pieces, a semiconductor package 1 of a semiconductor wafer CP unit is manufactured. As described above, the external electrode pad 5A fanned out of the region of the semiconductor wafer CP is connected to the semiconductor package 1 of the external terminal electrode 6, and is manufactured as a fan-out wafer-level package (FO-WLP).

[Modification]

Regarding the manufacturing method of the FO-WLP according to the first aspect described above, a part of the steps may be changed or a part of the steps may be omitted.

(2) The second aspect

The second aspect of the FO-WLP manufacturing method for the semiconductor processing sheet of the present embodiment will be described below. In addition, in the second aspect, the semiconductor processing sheet of the present embodiment is used as a second adhesive sheet 20 described later.

FIG. 4 (A) shows a semiconductor wafer W adhered to a protective plate 30 as a third adhesive plate. The semiconductor wafer W has a circuit surface W1 as a first surface, and a circuit W2 is formed on the circuit surface W1. The protective plate 30 is adhered to the circuit surface W1 of the semiconductor wafer W. The protective plate 30 protects the circuit surface W1 and the circuit W2.

The protective sheet 30 has a third base film 31 and a third adhesive Layer 32. The third adhesive layer 32 is laminated on the third base film 31.

[Ditch formation step]

FIG. 4 (B) is a diagram illustrating a step (hereinafter, sometimes referred to as a “trench forming step”) of forming a trench of a predetermined depth from the circuit surface W1 side of the semiconductor wafer W.

In the trench formation step, the semiconductor wafer W is cut into a cut from the protective plate 30 side using a dicing blade of a dicing device or the like. At this time, the protective plate 30 is completely cut off, and a notch having a depth shallower than the thickness of the semiconductor wafer W is cut from the circuit surface W1 of the semiconductor wafer W to form a groove W5. The trench W5 is formed so as to divide a plurality of circuits W2 formed on the circuit surface W1 of the semiconductor wafer W. The depth of the groove W5 is not particularly limited as long as it is slightly deeper than the thickness of the intended semiconductor wafer. When the groove W5 is formed, chips from the semiconductor wafer W occur. In the manufacturing method of the second aspect, the groove W5 is formed in a state where the circuit surface W1 is protected by the protective plate 30, so that it is possible to prevent the circuit surface W1 and the circuit W2 from being contaminated or damaged due to cutting chips.

[Grinding steps]

FIG. 4 (C) is a diagram illustrating a step (hereinafter, sometimes referred to as a “grinding step”) of grinding the back surface W6 that is the second surface of the semiconductor wafer W after the groove W5 is formed.

In the manufacturing method of the second aspect, the first adhesive plate 10 is adhered to the protective plate 30 side before grinding. After the first adhesive plate 10 is adhered, the semiconductor wafer W is ground from the back surface W6 side using a grinder 50. The thickness of the semiconductor wafer W is reduced by grinding, and the semiconductor wafer W is finally divided into a plurality of semiconductor wafers CP. Grind from the back W6 side until the bottom of the groove W5 is removed, The W wafers are divided into circuits W2. Thereafter, if necessary, further back grinding is performed to obtain a semiconductor wafer CP of a predetermined thickness. In the manufacturing method of the 2nd aspect, it grinds until the back surface W3 which is a 3rd surface is exposed.

FIG. 4 (D) shows a state where the divided plurality of semiconductor wafers CP are held by the protective plate 30 and the first adhesive plate 10. In addition, in this specification, as described above, a method in which the groove W5 is provided first, and then the back surface grinding is performed to divide the semiconductor wafer W into the semiconductor wafer CP is sometimes referred to as a "first cut method".

[Adhesive step (second adhesive sheet)]

FIG. 5 (A) is a diagram illustrating a step (hereinafter, sometimes referred to as “adhesion step”) of attaching the second adhesive plate 20 to the plurality of semiconductor wafers CP after the grinding step.

The second adhesive plate 20 is adhered to the back surface W3 of the semiconductor wafer CP. The second adhesive plate 20 includes a second base film 21 and a second adhesive layer 22. Here, as the second adhesive plate 20, a semiconductor processing plate according to this embodiment is used.

The adhesion force of the second adhesive layer 22 to the semiconductor wafer W is better than the adhesion force of the third adhesive layer 32 to the semiconductor wafer W. If the adhesive force of the second adhesive layer 22 is large, it is easy to peel off the first adhesive sheet 10 and the protective sheet 30.

The second adhesive plate 20 may be adhered to the ring frame together with the plurality of semiconductor wafers CP. At this time, a ring frame is placed on the second adhesive layer 22 of the second adhesive plate 20, and it is pressed and fixed gently. Thereafter, the second adhesive layer 22 exposed on the inner side of the ring shape of the ring frame is pressed against the semiconductor crystal. The circuit surface W1 of the chip CP fixes the plurality of semiconductor wafers CP to the second adhesive plate 20.

[Peeling step (first adhesive sheet)]

FIG. 5 (B) is a diagram illustrating a step (hereinafter, sometimes referred to as a “peeling step”) of peeling the first adhesive sheet 10 and the protective sheet 30 after the second adhesive sheet 20 is adhered. .

In the peeling step, when the first adhesive sheet 10 is peeled off, the cut protective sheet 30 is peeled together. The protective sheet 30 is peeled off to expose the circuit surface W1 of the plurality of semiconductor wafers CP. Here, as shown in FIG. 5 (B), the distance between the semiconductor wafers CP divided by the pre-cut method is D1. The distance D1 is, for example, preferably 15 μm or more and 110 μm or less.

[Expansion steps]

FIG. 5 (C) is a diagram illustrating a step (hereinafter, sometimes referred to as “expanding step”) of stretching the second adhesive sheet 20 holding the plurality of semiconductor wafers CP.

In the expanding step, the interval between the plurality of semiconductor wafers CP is further enlarged. In the expanding step, the method of stretching the second adhesive sheet 20 is not particularly limited. Examples of the method of stretching the second adhesive sheet 20 include, for example, a method of stretching the second adhesive sheet 20 by abutting a ring-shaped or circular dilator; and using a holding member or the like to stretch the second adhesive sheet. The outer peripheral part is grasped and stretched. As the latter method, for example, a method of biaxial stretching using the above-mentioned separation device or the like can be mentioned. Among these, a two-axis extension method is preferable from the viewpoint that the interval between the semiconductor wafers CP can be greatly increased.

In the manufacturing method of the second aspect, as shown in FIG. 5 (C), the distance between the semiconductor wafers CP after the expansion step is D2. Distance D2 Greater than distance D1. The distance D2 is preferably, for example, 200 μm or more and 6000 μm or less.

[Sealing step]

FIG. 6 is a diagram illustrating a step (hereinafter, sometimes referred to as a “sealing step”) of sealing the plurality of semiconductor wafers CP using the sealing member 60.

FIG. 6 (A) is a diagram illustrating a step of pasting the surface protection plate 40 as the fourth adhesive plate to the plurality of semiconductor wafers CP after the expansion step.

After the second adhesive plate 20 is stretched to extend the interval between the plurality of semiconductor wafers CP to a distance D2, the surface protection plate 40 is adhered to the circuit surface W1 of the semiconductor wafer CP. The surface protection sheet 40 includes a fourth base film 41 and a fourth adhesive layer 42. The surface protection plate 40 is preferably adhered in such a manner that the fourth adhesive layer 42 covers the circuit surface W1.

After the surface protection plate 40 is adhered, the second adhesive plate 20 is peeled off to expose the back surface W3 of the plurality of semiconductor wafers CP. After the second adhesive plate 20 is peeled off, it is preferable to maintain a distance D2 between the plurality of semiconductor wafers CP expanded in the expanding step. When the second adhesive layer 22 is formulated with an energy ray polymerizable compound, it is preferable to irradiate the second adhesive layer 22 with energy rays from the second base film 21 side to harden the energy ray polymerizable compound, and then The adhesive sheet 20 is peeled.

FIG. 6 (B) is a diagram illustrating a step of sealing the plurality of semiconductor wafers CP held by the surface protection plate 40.

The circuit surface W1 is left, and the plurality of semiconductor wafers CP are covered with the sealing member 60 to form the sealing body 3. Also among plural semiconductor wafers CP Filled with a sealing member 60. Here, since the circuit surface W1 and the circuit W2 are covered with the surface protection plate 40, the circuit surface W1 can be prevented from being covered by the sealing member 60.

By the sealing step, a sealing body 3 is obtained in which a plurality of semiconductor wafers CP separated by a predetermined distance are embedded in a sealing member. In the sealing step, it is preferable that the plurality of semiconductor wafers CP are covered with the sealing member 60 while maintaining the distance D2.

After the sealing step, the surface protection plate 40 is peeled off to expose the circuit surface W1 of the semiconductor wafer CP and the surface 3S of the sealing body 3 in contact with the surface protection plate 40 (see FIG. 3 (A)).

[Rewiring layer forming step, connection step with external terminal electrode, and second cutting step]

After the sealing step, a rewiring layer forming step, a connection step with an external terminal electrode, and a second cutting step are performed. These steps can be performed in the same manner as the manufacturing method of the first aspect (refer to FIGS. 3 (B) and 3 (C)). Through these steps, FO-WLP can be obtained.

[Modification]

Regarding the manufacturing method of the FO-WLP according to the second aspect described above, a part of the steps may be changed and a part of the steps may be omitted. Such a modification will be described below.

As a first modification of the manufacturing method of the second aspect, after the step of sticking the second adhesive sheet 20, a step of peeling off only the first adhesive sheet 10 may be performed. That is, in the second aspect, when the first adhesive sheet 10 is peeled off, it is peeled off together with the cut protective sheet 30. In contrast, in this modification, the protective sheet 30 is left on the semiconductor wafer. Circuit surface W1 of CP, The first adhesive sheet 10 is peeled. By peeling off the first adhesive sheet 10, as shown in FIG. 7 (A), the plurality of semiconductor wafers CP to which the protective sheet 30 has been cut and pasted are in a state of being laminated on the second adhesive sheet 20. .

Next, as shown in FIG. 7 (B), the above-mentioned expansion step is performed. That is, the second adhesive plate 20 is stretched in a state in which the protective plate 30 is adhered to the circuit surface W1 of the cut semiconductor wafer CP to extend the distance D2 between the plurality of semiconductor wafers CP.

After the expansion step, a step of sealing the plurality of semiconductor wafers CP is performed as shown in FIG. 7 (C). In the second aspect, as shown in FIG. 6 (B), the semiconductor wafer CP is sealed on the surface protection plate 40. In contrast, in this modification, as shown in FIG. 7 (C), The semiconductor wafer CP is sealed on the second adhesive plate 20 using a sealing member 60. Here, since the protective plate 30 is adhered to the circuit surface W1, the surface protective plate 40 can be adhered without being adhered, and the second adhesive plate can be directly adhered to the back surface W3 of the semiconductor wafer CP. The circuit surface W1 is left, and the plurality of semiconductor wafers CP are covered with the sealing member 60 to form the sealing body 3. The surface 3S of the sealing body 3 is preferably the same surface as the circuit surface W1 of the semiconductor wafer CP.

After the sealing step, the protective sheet 30 and the second adhesive sheet 20 are peeled off. After that, the FO-WLP is obtained by performing the above-mentioned redistribution layer forming step, the external terminal electrode connection step, and the second cutting step.

Since the sheet for semiconductor processing of this embodiment can be greatly extended, as described above, it can be suitably used for applications that require a larger interval between semiconductor wafers.

The embodiments described above are for easy understanding of the present invention. The description is not intended to limit the present invention. Therefore, each element disclosed in the said embodiment is the summary including all the design changes or an equivalent thing which belongs to the technical scope of this invention.

For example, when the plate for semiconductor processing has a structure of a base material and an adhesive layer, another layer may be interposed between the base material and the adhesive layer.

[Example]

Hereinafter, the present invention will be described more specifically with examples and the like, but the scope of the present invention is not limited to these examples and the like.

[Example 1]

(1) Preparation of adhesive composition

Acrylic copolymer obtained by reacting butyl acrylate / 2-hydroxyethyl acrylate = 85/15 (mass ratio) with 80 mol% of methacrylic acid oxyethyl isocyanate with respect to 2-hydroxyethyl ester (MOI) reaction to obtain an energy ray-curable polymer. The weight-average molecular weight (Mw) of this energy ray-curable polymer was 600,000.

100 parts by mass of the obtained energy ray-curable polymer, 3 parts by mass of 1-hydroxycyclohexylphenyl ketone (manufactured by BASF, product name "IRGACURE184") as a photopolymerization initiator, and 0.45 parts by mass as a bridge The toluene diisocyanate-based bridging agent (manufactured by TOSOH Corporation, product name "CORONATE L") was mixed in a solvent to obtain an adhesive composition.

(2) Fabrication of plates for semiconductor processing

The release surface of a release film (manufactured by LINTEC, product name "SP-PET3811") was formed on one side of a polyethylene terephthalate (PET) film by forming a silicone-based release layer, and the above-mentioned adhesion was applied Composition by adding Heat-dried to form an adhesive layer with a thickness of 10 μm on the release film. Then, one side of a polyester-based polyurethane elastomer sheet (manufactured by Sheedom Co., Ltd., product name "Higress DUS202", thickness 50 µm) was adhered to the exposed surface of the adhesive layer to make the adhesive The state of the peeling film was adhered layer by layer to obtain a sheet for semiconductor processing.

[Comparative Example 1]

100 parts by mass of a polyvinyl chloride resin (PVC, average degree of polymerization: 1050), 42 parts by mass of an adipic acid-based polyester plasticizer, and a small amount of a stabilizer are kneaded, and formed into a film shape using a shower coating device A sheet for semiconductor processing was produced in the same manner as in Example 1 except that the vinyl chloride film having a thickness of 80 μm was used as a substrate.

[Comparative Example 2]

A sheet for semiconductor processing was produced in the same manner as in Example 1 except that a polypropylene film (PP, manufactured by DiaPlus Film Co., Ltd., product name "LT01-06051") was used as the substrate.

[Test Example 1] (tensile test)

The semiconductor processing plates produced in the examples and comparative examples were cut into 15 mm × 140 mm, and the plates were peeled and peeled as test pieces. About this test piece, the elongation at break and the tensile elastic modulus at 23 ° C. were measured in accordance with JIS K7161: 2014 and JIS K7127: 1999. Specifically, the above test piece was subjected to a tensile test at a speed of 200 mm / min using a tensile tester (manufactured by Shimadzu Corporation, product name "Autograph AG-IS 500N") with a distance between the clamps of 100 mm The elongation at break (%) and the modulus of tensile elasticity (MPa) were measured. In addition, the measurement is carried out in both the flow direction (MD) and the direction (CD) at a right angle to this during the manufacture of the substrate. Row. The results are shown in Table 1.

[Test Example 2] (Measurement of 100% stress and recovery rate)

The sheet for semiconductor processing manufactured in the examples and comparative examples was cut into 150 mm × 15 mm, and the sheet was peeled off and used as a test piece. In addition, it cut out so that the flow direction (MD direction) at the time of manufacture of the board for semiconductor processing might become the longitudinal direction of a test piece. Then, both ends of the test piece in the longitudinal direction were fixed with a jig of a tensile tester (manufactured by Shimadzu Corporation, product name "Autograph AG-IS 50N"). At this time, the test piece was held with a jig so that the length between the jigs was 100 mm. This length is defined as the length L0 (mm) between the initial jigs. Then, it stretched 100 mm in the longitudinal direction at a speed of 200 mm / min, so that the length between the clamps became 200 mm. A length obtained by subtracting the length L0 (mm) (that is, 100 mm) between the initial jigs from this length is referred to as an expanded length L1 (mm). The test force at this time was measured, and the 100% strength (N) in the tensile test was determined as the 100% strength (N) in the MD direction. Then, by dividing the 100% strength (N) in the MD direction by the quotient of the cross-sectional area of the semiconductor processing sheet, the 100% stress (MPa) in the MD direction was obtained. Furthermore, after maintaining the state where the length between the clamps is 200 mm for 1 minute, the clamp is restored to a state where the length between the clamps is L0 (mm) and the length between the clamps is L0 (mm) at a rate of 200 mm / min Hold for 1 minute. After that, it was stretched in the longitudinal direction at a speed of 60 mm / min, and the measured value of the recorded tensile force showed the length between the clamps at 0.1 N / 15 mm. A value obtained by subtracting the length L0 (mm) between the initial jigs from this length is set to L2 (mm).

The values of the above-mentioned L1 and L2 were incorporated into the following formula (I), and the recovery rate (%) was calculated. The results are shown in Table 1.

Recovery rate (%) = (1- (L2 ÷ L1)) × 100 ... (I)

In addition, the semiconductor processing plates manufactured in the examples and comparative examples were cut to a length of the test piece so that the direction (CD direction) orthogonal to the flow direction at the time of manufacturing was 150 mm × 15 mm, peeling the peeled sheet as a test piece, and measuring the 100% strength (N) and 100% stress (MPa) in the same manner as described above, and the respective 100% strength (N) in the CD direction and 100 in the CD direction were measured. % Stress (MPa). The results are shown in Table 1. Furthermore, the ratio of 100% stress (MPa) in the MD direction to 100% stress (MPa) in the CD direction was calculated. The results are also shown in Table 1.

[Test Example 3] (Extended Test)

Peel off the release sheet of dicing tape (product name: "ADWILL D-675" manufactured by LINTEC), and stick the exposed adhesive surface to the ring frame and 6-inch silicon mirror wafer (diameter: 150mm, thickness: 350μm, Grinding surface of Grinding surface # 2000). Next, using a dicing machine (manufactured by DISCO, product name "DFD-651"), the silicon mirror wafer was diced in a full dicing manner in accordance with the following conditions. Thereby, a plurality of pieces of silicon wafers were obtained on the dicing tape. Thereafter, the dicing tape was subjected to UV irradiation (illuminance: 120 mW / cm ² , light amount: 70 mJ / cm ² ) using a UV irradiation device (manufactured by LINTEC, product name "RAD-2000m / 12").

‧Cutting blade: made by DISCO Corporation, product name "NBC-ZH205O 27HECC"

‧Revolutions: 30,000rpm

‧Height: 0.06mm

‧Cutting speed: 60mm / sec

‧Chip size: 3mm × 3mm

Next, the semiconductor processing plates obtained in the examples and comparative examples were cut into a rectangular shape of 210 mm × 210 mm. At this time, the sides of the cut sheet are cut in such a manner that the sides of the cut sheet are parallel or perpendicular to the MD direction of the base material of the semiconductor processing sheet. Next, the release sheet was peeled off, and all the silicon wafers obtained by the dicing were transferred to the exposed adhesive surface. At this time, a group of silicon wafers is transferred so that they are located at the center of the semiconductor processing sheet. In addition, the dicing lines during the singulation of the silicon wafer are transferred so that they are parallel or perpendicular to the sides of the semiconductor processing sheet.

Next, a semiconductor processing plate to which a silicon wafer is transferred is set in an expansion device (separation device) that can be extended in two axes. FIG. 8 is a plan view illustrating the expansion device 100. In FIG. 8, the X axis and the Y axis are orthogonal to each other. The positive direction of the X axis is + X axis direction, and the negative direction of the X axis is -X axis direction. The positive direction is the + Y axis direction, and the negative direction of the Y axis is the -Y axis direction. The semiconductor processing sheet 200 is installed in the expansion device 100 such that each side is parallel to the X-axis or the Y-axis. As a result, the MD direction of the substrate of the semiconductor processing sheet 200 is parallel to the X-axis or Y-axis. In addition, in FIG. 8, the silicon wafer system is omitted.

As shown in FIG. 8, the expansion device 100 includes five holding means 101 (a total of 20 holding means 101) in the + X-axis direction, the -X-axis direction, the + Y-axis direction, and the -Y-axis direction, respectively. Among the five holding means 100 in each direction, the holding means 101A is located at both ends, the holding means 101C is located at the center, and the holding means 101B is located between the holding means 101A and 101C. Each side of the semiconductor processing sheet 200 is held by these holding means 101.

Here, as shown in FIG. 8, one side of the semiconductor processing sheet 200 is 210 mm. The distance between the holding means 101 on each side is 40 mm. In addition, the distance between the end portion (the vertex of the plate) of one side of the semiconductor processing sheet 200 and the holding means 101A closest to the end portion on the side is 25 mm.

Next, a plurality of tension applying means (not shown) corresponding to the holding means 101 are driven, and the holding means 101 are moved independently. At this time, the five holding means 101 holding one side of the + X-axis direction side of the semiconductor processing sheet 200 are moved in the + X-axis direction at an extension speed: 2.5 mm / sec for 40 seconds. At the same time, among the five holding means 101, the holding means 101A and the holding means 101B are moved away from the holding means 101C (that is, the + Y-axis direction or the -Y-axis direction). At this time, the holding means 101A is moved at a speed of 2/3 of the extension speed: 2.5 mm / sec, and the holding means 101B is moved at a speed of 1/3 of the extension speed: 2.5 mm / sec. In addition, the holding means 101C does not move in the + Y-axis direction and the -Y-axis direction. In the semiconductor processing board 200, the holding means 101 located on three sides other than the + X axis direction is moved in the same direction as the + X axis direction, and the holding means 101A and the holding means 101B are moved to Move away from the holding means 101C.

As a result of moving the holding means 101 as described above, the semiconductor processing sheet 200 extends 100 mm in the + X-axis direction and the -X-axis direction, respectively, and extends 100 mm in the + Y-axis direction and the -Y-axis direction, respectively. . That is, the semiconductor processing sheet 200 extends 200 mm on each side. As a result, the length of each side of the extended semiconductor processing sheet 200 becomes 410 mm.

To the sheet for semiconductor processing in the state extended as described above 200, the presence or absence of breakage was evaluated based on the following criteria. The results are shown in Table 1.

○: No breakage occurred, and it extended well.

×: Fracture occurred.

In addition, for the semiconductor processing sheet 200 having an evaluation of the presence or absence of cracking, the outer diameter of the approximately circular shape (corresponding to a plurality of silicon wafers) corresponding to the extended semiconductor processing sheet 200 was measured (corresponding to The length of the outer diameter of the silicon wafer before dicing and extension is used as the corresponding length (mm) of the wafer outer diameter. The results are shown in Table 1.

In addition, the measured wafer outer diameter corresponding length (mm) was fitted into the following calculation formula (II) to calculate a wafer interval (mm). The results are shown in Table 1.

Wafer interval (mm) = (corresponding length of wafer outer diameter (mm)-150mm (silicon wafer diameter)) ÷ 49 (number of cutting lines) ... (II)

Furthermore, in the above formula (II), the number of cutting lines is 49, which is based on a silicon wafer with a diameter of 150 mm and a wafer size of 3 mm × 3 mm. The silicon wafer is in one direction and a direction orthogonal to the direction. Cut at 3mm intervals, and make 50 equal parts in each direction. At this time, the number of cutting lines is 49 in each direction.

As can be seen from Table 1, the semiconductor processing sheet of the example can be largely extended without breaking.

[Industrial profitability]

The sheet for semiconductor processing of the present invention can be favorably used in, for example, the production of FO-WLP.

W‧‧‧Semiconductor wafer

W1‧‧‧Circuit Surface

W2‧‧‧Circuit

W3‧‧‧ back

CP‧‧‧Semiconductor wafer

10‧‧‧The first adhesive plate

11‧‧‧ the first substrate film

12‧‧‧ the first adhesive layer

Claims (10)

A semiconductor processing plate is a semiconductor processing plate having at least a base material, characterized in that the recovery rate of the semiconductor processing plate is 70% or more and 100% or less, and the recovery rate is the above A 150 mm × 15 mm test piece was cut out of the semiconductor processing plate, and the two ends in the longitudinal direction were clamped by the clamp so that the length between the clamps became 100 mm. Then, the test piece was stretched at a speed of 200 mm / min. The length becomes 200mm, and the length between the clamps is expanded to 200mm and maintained for 1 minute, and then the length between the clamps is restored to 100mm along the length direction at a speed of 200mm / min. After 1 minute, it was stretched in the longitudinal direction at a speed of 60 mm / min, and the measured value of the tensile force showed the length between the clamps at 0.1 N / 15 mm. This length was subtracted from the initial clamp length of 100 mm. When the length is L2 (mm), and the length (mm) of the length between the clamps in the expanded state 200 mm minus the length between the initial clamps 100 mm is set to L1 (mm), the value calculated by the following formula (I): Recovery rate (%) = (1- (L2 ÷ L 1)} × 100 ... (I). A semiconductor processing plate is a semiconductor processing plate having at least a base material, characterized in that 100% stress of the semiconductor processing plate is measured at 23 ° C. in the MD direction of the base material. The ratio of the 100% stress of the semiconductor processing plate measured at 23 ° C in the CD direction of the substrate is 0.8 or more and 1.2 or less. The 100% stress is obtained by cutting out the semiconductor processing plate. The test piece of 150mm × 15mm was clamped at both ends in the longitudinal direction so that the length between the clamps became 100mm, and then stretched in the length direction at a speed of 200mm / min until the length between the clamps became 200mm. The measured value of the tensile force at this time is a value calculated by dividing the cross-sectional area of the plate for semiconductor processing. A sheet for semiconductor processing, which is a sheet for semiconductor processing having at least a base material, characterized in that the tensile elasticity of the sheet for semiconductor processing is measured at 23 ° C. in the MD direction and the CD direction of the base material. The modulus is 100 MPa or more and 350 MPa or less. The 100% stress of the semiconductor processing plate measured at 23 ° C in the MD direction and the CD direction of the substrate is 3 MPa or more and 20 MPa or less, respectively. The test piece of 150 mm × 15 mm was cut out from the above-mentioned semiconductor processing plate, and the two ends in the length direction were clamped by the clamp so that the length between the clamps became 100 mm. Then, the length was 200 mm / min along the length. The measured value of the tensile force when the length between the clamps reaches 200 mm is calculated by quoting the cross-sectional area of the semiconductor processing plate. It is the MD direction and CD direction of the substrate at 23 ° C. The measured breaking elongations of the above-mentioned semiconductor processing plates were 100% or more. The sheet for semiconductor processing according to any one of claims 1 to 3, further comprising an adhesive layer laminated on at least one surface of the base material. The sheet for semiconductor processing according to any one of claims 1 to 3, wherein the substrate includes a thermoplastic elastomer. The sheet for semiconductor processing according to item 5 of the scope of patent application, wherein the thermoplastic elastomer is a urethane-based elastomer. The semiconductor processing plate according to any one of claims 1 to 3, which is used for the mutual interconnection of adjacent semiconductor wafers of a plurality of semiconductor wafers laminated on one surface of the semiconductor processing plate. The interval is expanded to 200 μm or more and 6000 μm or less. The sheet for semiconductor processing according to any one of claims 1 to 3, which is used for + X-axis direction, -X-axis direction, + X-axis direction, A tension is applied in four directions of the Y-axis direction and the -Y-axis direction, the semiconductor processing plate is stretched, and the interval of the plurality of semiconductor wafers laminated on one surface of the semiconductor processing plate is extended. The sheet for semiconductor processing according to any one of claims 1 to 3, comprising: a step of providing a plurality of semiconductor wafers on one side of the adhesive sheet; and stretching the adhesive sheet. In the method for manufacturing a semiconductor device in the step of increasing the distance between the plurality of semiconductor wafers, the sheet is used as the adhesive sheet. The sheet for semiconductor processing according to any one of claims 1 to 3, which is used for manufacturing a fan-out type semiconductor wafer-level package.