WO2018000484A1 - 绝缘层的制造方法、阵列的制造方法及阵列基板 - Google Patents

绝缘层的制造方法、阵列的制造方法及阵列基板 Download PDF

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Publication number
WO2018000484A1
WO2018000484A1 PCT/CN2016/090652 CN2016090652W WO2018000484A1 WO 2018000484 A1 WO2018000484 A1 WO 2018000484A1 CN 2016090652 W CN2016090652 W CN 2016090652W WO 2018000484 A1 WO2018000484 A1 WO 2018000484A1
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Prior art keywords
insulating layer
opening
array substrate
depositing
manufacturing
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English (en)
French (fr)
Inventor
范德勇
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/116,497 priority Critical patent/US10147598B2/en
Publication of WO2018000484A1 publication Critical patent/WO2018000484A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2922—Materials being non-crystalline insulating materials, e.g. glass or polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6536—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light
    • H10P14/6538—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light by exposure to UV light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/095—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by irradiating with electromagnetic or particle radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/097—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by thermally treating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of panel manufacturing, and in particular to a method for fabricating an insulating layer, a method for fabricating an array substrate, and an array substrate.
  • liquid crystal panels As a mainstream display panel, liquid crystal panels have been widely used in people's daily life and work. Liquid crystal panels are usually controlled by an array substrate to realize display. An organic insulating layer is generally used in the array substrate, which can reduce the parasitic capacitance between the metal electrodes to reduce the power consumption of the panel, and can also be used to flatten each film layer, thereby improving the dark state of the panel display and improving The contrast displayed.
  • the manufacture of the organic insulating layer is basically an indispensable process in the array substrate, and in the existing manufacturing process, the opening formed on the insulating layer usually has severe deformation, which easily causes the opening to be blocked, and the resolution of the insulating layer The problem of falling.
  • the present invention provides a method of manufacturing an insulating layer, the manufacturing method comprising the steps of: depositing an insulating layer on a substrate; performing an exposure and development process on the insulating layer to obtain an insulating layer having an opening; The insulating layer having the opening is subjected to a photocuring treatment; and the insulating layer having the opening which is subjected to the photocuring treatment is subjected to a high temperature annealing treatment.
  • the step of photocuring the insulating layer having the opening comprises: performing an ultraviolet curing treatment on the insulating layer having the opening.
  • the step of depositing an insulating layer on the substrate comprises: placing the substrate having the insulating layer in a vacuum for a period of time.
  • the step of depositing an insulating layer includes: baking the insulating layer.
  • the step of depositing an insulating layer comprises: obtaining an insulating layer using chemical vapor deposition.
  • the present invention also provides a method of fabricating an array substrate, wherein a step of forming an insulating layer is included between the steps of forming a data line and forming a common electrode line, and the step of forming the insulating layer includes: depositing a The insulating layer is subjected to exposure and development treatment to obtain an insulating layer having an opening; the insulating layer having an opening is photocured; and the insulating layer having an opening subjected to photocuring is subjected to a high temperature annealing treatment.
  • the step of photocuring the insulating layer having the opening comprises: performing an ultraviolet curing treatment on the insulating layer having the opening.
  • the step of depositing an insulating layer comprises: placing the array substrate after depositing an insulating layer in a vacuum for a period of time.
  • the step of depositing an insulating layer includes: baking the insulating layer.
  • the step of depositing an insulating layer comprises: obtaining an insulating layer using chemical vapor deposition.
  • the present invention also provides an array substrate, which is fabricated by a manufacturing method including the steps of forming an insulating layer between the steps of forming a data line and forming a common electrode line,
  • the step of forming an insulating layer includes: depositing an insulating layer; performing an exposure and development process on the insulating layer to obtain an insulating layer having an opening; performing photocuring treatment on the insulating layer having an opening; and insulating the opening having a photocuring process
  • the layer is subjected to a high temperature annealing treatment.
  • the step of photocuring the insulating layer having the opening comprises: performing an ultraviolet curing treatment on the insulating layer having the opening.
  • the step of depositing an insulating layer comprises: placing the array substrate after depositing an insulating layer in a vacuum for a period of time.
  • the step of depositing an insulating layer includes: baking the insulating layer.
  • the step of depositing an insulating layer comprises: obtaining an insulating layer using chemical vapor deposition.
  • the manufacturing method of the insulating layer of the present invention comprises the steps of: depositing an insulating layer on the substrate, exposing and developing the insulating layer to obtain an insulating layer having an opening; performing photocuring treatment on the insulating layer having the opening; The insulating layer having an opening is subjected to a high temperature annealing treatment. After the insulating layer is exposed by exposure and development, the insulating layer is further photocured to crosslink the insulating layer, and the degree of crosslinking of the insulating layer is higher, and the flow deformation is less likely to occur at high temperature annealing, thus avoiding There is a problem that the flow occurs at the time of high temperature annealing and the opening is blocked.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for manufacturing an insulating layer of the present invention
  • FIG. 2 is a schematic structural view of an insulating layer in an embodiment of a method for manufacturing the insulating layer shown in FIG. 1;
  • FIG. 3 is a schematic flow chart of an embodiment of a method for fabricating an array substrate of the present invention
  • FIG. 4 is a schematic structural view of an array substrate in an embodiment of a method for fabricating the array substrate shown in FIG. 3;
  • FIG. 5 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating an insulating layer of the present invention
  • FIG. 2 is a schematic structural view of an insulating layer in an embodiment of a method for fabricating the insulating layer of FIG.
  • the method for producing an insulating layer of the present embodiment includes the following steps.
  • S101 depositing an insulating layer on the substrate.
  • the manufacturing of the insulating layer 20 of the present embodiment is one process in the fabrication of the array substrate.
  • the substrate 10 does not refer to a single layer in the array substrate, but refers to a broad concept including a glass substrate, a metal layer, and the like.
  • the insulating layer 20 is formed on the substrate 10 by chemical vapor deposition.
  • the substrate 10 on which the insulating layer 20 is deposited is placed in a vacuum for a period of time to accelerate the evaporation of the solvent.
  • the insulating layer 20 can be further subjected to a baking treatment.
  • S102 performing an exposure and development treatment on the insulating layer to obtain an insulating layer having an opening.
  • the insulating layer 20 is subjected to exposure and development treatment using a photomask to obtain an insulating layer 20 having an opening 21.
  • the insulating layer 20 is of a negative type, that is, exposure is developed by using a mask that covers the opening 21, and the unexposed opening 21 is etched, and other portions that are irradiated can undergo a slight crosslinking reaction.
  • the insulating layer 20 is photocured by ultraviolet rays, that is, the insulating layer 20 having the opening 21 is further subjected to a crosslinking reaction, and the insulating layer 20 can be further cured without being easily deformed.
  • S104 performing high temperature annealing treatment on the insulating layer having an opening for completing the photocuring treatment.
  • the high temperature annealing treatment in the step S104 can sufficiently crosslink the insulating layer 20, and since the insulating layer 20 has been solidified in the step S103, the high temperature in the step S104 has less influence on the insulating layer 20, so that The deformation of the insulating layer material at the opening 21 is slightly reversed, thereby reducing the problem of clogging of the opening 21.
  • the manufacturing method of the insulating layer of the present invention comprises the steps of: depositing an insulating layer on the substrate, exposing and developing the insulating layer to obtain an insulating layer having an opening; performing photocuring treatment on the insulating layer having the opening; The insulating layer having an opening is subjected to a high temperature annealing treatment. After the insulating layer is exposed by exposure and development, the insulating layer is further photocured to crosslink the insulating layer, and the degree of crosslinking of the insulating layer is higher, and the flow deformation is less likely to occur at high temperature annealing, thus avoiding There is a problem that the flow occurs at the time of high temperature annealing and the opening is blocked.
  • FIG. 3 is a schematic flow chart of an embodiment of a method for fabricating an array substrate of the present invention
  • FIG. 4 is a schematic structural view of an array substrate according to an embodiment of the method for fabricating the array substrate of FIG.
  • the method of manufacturing the array substrate of the present embodiment includes the following steps.
  • S301 Form a data line on a substrate.
  • the insulating layer 42 is formed between the data line 41 and the common electrode line 43.
  • the order of the formation of the data line 41, that is, the common electrode line 43 is not limited, that is, the steps in this embodiment. S301 and S303 can be swapped, the common electrode line 43 is formed first, then the insulating layer 42 is formed, and finally the data line 41 is formed. Which method is specifically determined according to the structure of the array substrate.
  • a passivation layer 44 made of silicon nitride (SiNx) is further formed between the data line and the insulating layer.
  • the step S301 further includes the step of forming the gate layer 46 and the gate insulating layer 47 on the glass substrate 45 before forming the data line.
  • Step S302 is to form the insulating layer 42, specifically comprising the steps of: 1) depositing an insulating layer, and placing the array substrate after depositing an insulating layer in a vacuum for a period of time, and baking the insulating layer; 2) insulating the layer The layer is subjected to an exposure and development process to obtain an insulating layer 42 having an opening 421; 3) an ultraviolet light curing treatment is performed on the insulating layer 42 having the opening 421; and 4) a high temperature annealing treatment is performed on the insulating layer 42 having the opening 421 which is subjected to the photocuring treatment. .
  • This step S302 is similar to the method for manufacturing the insulating layer of the above embodiment, and details are not described herein again.
  • the insulating layer is subjected to exposure and development to obtain an opening, and then subjected to photocuring treatment before high-temperature annealing to reduce the degree of deformation by high-temperature action during high-temperature annealing.
  • the quality of the openings in the array substrate is high, and the quality of the corresponding array substrate is also high.
  • FIG. 5 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • the array substrate 500 of the present embodiment is produced by the method of manufacturing the array substrate of the above embodiment.
  • the array substrate 500 of the present embodiment includes a glass substrate 51, and a gate layer 52, a gate insulating layer 53, a data line 54, a passivation layer 55, an insulating layer 56, and a common electrode 57 are sequentially formed on the glass substrate 51.
  • the insulating layer 56 is further subjected to photocuring treatment after exposure and development to obtain an opening 561, and then subjected to high temperature annealing.
  • the positional relationship of the gate layer 52, the data line 54 and the common electrode 57 may be determined according to the type of the array substrate 500.
  • the gate layer 52 is disposed in the same layer as the common electrode 57. Therefore, the positional relationship of the gate layer 52, the data line 54, and the common electrode 57 is not limited in the present invention.

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Abstract

一种绝缘层的制造方法、阵列基板的制造方法及阵列基板，其中绝缘层的制造方法包括步骤：（S101）在基板（10）上沉积一绝缘层（20）；（S102）对绝缘层（20）进行曝光显影处理，得到具有开口（21）的绝缘层（20）；（S103）对具有开口（21）的绝缘层（20）进行光固化处理；（S104）对完成光固化处理的具有开口（21）的绝缘层（20）进行高温退火处理。绝缘层制造方法能够减少绝缘层开口发生变形的情况。

Description

绝缘层的制造方法、阵列的制造方法及阵列基板
【技术领域】
本发明涉及面板制造领域，特别是涉及一种绝缘层的制造方法、阵列基板的制造方法及阵列基板。
【背景技术】
液晶面板作为主流显示面板已广泛应用到人们日常生活和工作中，液晶面板通常由阵列基板进行电路控制，以实现显示。阵列基板中通常会使用到有机绝缘层，其能够降低金属电极之间的寄生电容，以降低面板的功耗，还可用于使各个膜层更为平坦化，从而改善面板显示的暗态，提高显示的对比度。
有机绝缘层的制造基本算是阵列基板中必不可少的工艺，而现有的制造工艺中，绝缘层上所形成的开口通常会出现的严重的变形，容易导致开口被堵住，绝缘层解析度下降的问题。
【发明内容】
本发明的目的在于提供一种绝缘层的制造方法、阵列基板的制造方法及阵列基板，以解决现有的制造工艺中绝缘层开口容易出现变形的情况。
为解决上述问题，本发明提出一种绝缘层的制造方法，所述制造方法包括以下步骤：在基板上沉积一绝缘层；对所述绝缘层进行曝光显影处理，得到具有开口的绝缘层；对具有开口的绝缘层进行光固化处理；对完成光固化处理的具有开口的绝缘层进行高温退火处理。
其中，所述对具有开口的绝缘层进行光固化处理的步骤包括：对具有开口的绝缘层进行紫外线固化处理。
其中，所述在基板上沉积一绝缘层的步骤之后包括：将具有绝缘层的基板在真空中放置一段时间。
其中，所述沉积一绝缘层后的步骤包括：对所述绝缘层进行烘烤处理。
其中，所述沉积一绝缘层的步骤包括：使用化学气相沉积得到一绝缘层。
为解决上述问题，本发明还提供一种阵列基板的制造方法，其中，在形成数据线和形成公共电极线的步骤之间包括形成绝缘层的步骤，所述形成绝缘层的步骤包括：沉积一绝缘层；对所述绝缘层进行曝光显影处理，得到具有开口的绝缘层；对具有开口的绝缘层进行光固化处理；对完成光固化处理的具有开口的绝缘层进行高温退火处理。
其中，所述对具有开口的绝缘层进行光固化处理的步骤包括：对具有开口的绝缘层进行紫外线固化处理。
其中，所述沉积一绝缘层的步骤之后包括：将沉积一绝缘层后的阵列基板在真空中放置一段时间。
其中，所述沉积一绝缘层后的步骤包括：对所述绝缘层进行烘烤处理。
其中，所述沉积一绝缘层的步骤包括：使用化学气相沉积得到一绝缘层。
为解决上述问题，本发明还提供一种阵列基板，该阵列基板由一制造方法制得，该制造方法包括在形成数据线和形成公共电极线的步骤之间包括形成绝缘层的步骤，所述形成绝缘层的步骤包括：沉积一绝缘层；对所述绝缘层进行曝光显影处理，得到具有开口的绝缘层；对具有开口的绝缘层进行光固化处理；对完成光固化处理的具有开口的绝缘层进行高温退火处理。
其中，所述对具有开口的绝缘层进行光固化处理的步骤包括：对具有开口的绝缘层进行紫外线固化处理。
其中，所述沉积一绝缘层的步骤之后包括：将沉积一绝缘层后的阵列基板在真空中放置一段时间。
其中，所述沉积一绝缘层后的步骤包括：对所述绝缘层进行烘烤处理。
其中，所述沉积一绝缘层的步骤包括：使用化学气相沉积得到一绝缘层。
本发明绝缘层的制造方法包括步骤：在基板上沉积一绝缘层，对绝缘层进行曝光显影处理，得到具有开口的绝缘层；对具有开口的绝缘层进行光固化处理；对完成光固化处理的具有开口的绝缘层进行高温退火处理。绝缘层在曝光显影得到开口后，对绝缘层进行进一步的光固化处理，使绝缘层发生交联反应，绝缘层的交联程度越高，在高温退火时就越不容易出现流动变形，因此避免了高温退火时出现流动而导致开口堵塞的问题。
【附图说明】
图1是本发明绝缘层的制造方法一实施方式的流程示意图；
图2是图1所示绝缘层的制造方法一实施方式中绝缘层的结构示意图；
图3是本发明阵列基板的制造方法一实施方式的流程示意图；
图4是图3所示阵列基板的制造方法一实施方式中阵列基板的结构示意图；
图5是本发明阵列基板一实施方式的结构示意图。
【具体实施方式】
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对发明所提供的一种绝缘层的制造方法、阵列基板的制造方法及阵列基板做进一步详细描述。
参阅图1和图2，图1是本发明绝缘层的制造方法一实施方式的流程示意图，图2是图1所示绝缘层的制造方法一实施方式中绝缘层的结构示意图。
本实施方式绝缘层的制造方法包括以下步骤。
S101：在基板上沉积一绝缘层。
本实施方式绝缘层20的制造是阵列基板制造中的一个工艺，本步骤中基板10不是指阵列基板中单一的某一层，而是指包括玻璃基板、金属层等的广义概念。本步骤中绝缘层20由化学气相沉积形成在基板10上。
化学气相沉积中一般有溶剂的挥发步骤，本实施方式中将沉积了绝缘层20的基板10于真空中放置一段时间，以加快溶剂的挥发。还可进一步的对绝缘层20进行烘烤处理。
S102：对绝缘层进行曝光显影处理，得到具有开口的绝缘层。
利用光罩对绝缘层20进行曝光显影处理，得到具有开口21的绝缘层20。本实施方式中绝缘层20为负型，即采用遮住开口21的光罩实现曝光显影，未被光照到的开口21被刻蚀，而被光照到的其他部分能够发生轻微的交联反应。
S103：对具有开口的绝缘层进行光固化处理。
本步骤S103中采用紫外线对绝缘层20进行光固化处理，即使得具有开口21的绝缘层20进一步的发生交联反应，绝缘层20能够进一步的被固化，而不容易发生变形流动。
S104：对完成光固化处理的具有开口的绝缘层进行高温退火处理。
本步骤S104中的高温退火处理能够使绝缘层20充分交联，并且由于步骤S103中已经对绝缘层20做了一定的固化，因此本步骤S104中的高温对绝缘层20的影响较小，使开口21处的绝缘层材料变形回流变得轻微，从而减少开口21堵塞等问题。
本发明绝缘层的制造方法包括步骤：在基板上沉积一绝缘层，对绝缘层进行曝光显影处理，得到具有开口的绝缘层；对具有开口的绝缘层进行光固化处理；对完成光固化处理的具有开口的绝缘层进行高温退火处理。绝缘层在曝光显影得到开口后，对绝缘层进行进一步的光固化处理，使绝缘层发生交联反应，绝缘层的交联程度越高，在高温退火时就越不容易出现流动变形，因此避免了高温退火时出现流动而导致开口堵塞的问题。
请参阅图3和图4，图3是本发明阵列基板的制造方法一实施方式的流程示意图，图4是图3所示阵列基板的制造方法一实施方式中阵列基板的结构示意图。
本实施方式阵列基板的制造方法包括以下步骤。
S301：在一基板上形成数据线。
S302：在数据线上形成绝缘层。
S303：在绝缘层上形成公共电极线。
本实施方式得到的阵列基板400中绝缘层42形成在数据线41与公共电极线43之间，而数据线41即公共电极线43的形成的先后顺序并不做限定，即本实施方式中步骤S301及S303可以对换，先形成公共电极线43，然后形成绝缘层42，最后形成数据线41，具体采用哪种方式需根据阵列基板的结构确定。
本实施方式中数据线与绝缘层之间还形成有材料为氮化硅（SiNx）的钝化层44。步骤S301形成数据线之前进一步包括步骤：在玻璃基板45上形成栅极层46以及栅极绝缘层47。
其中步骤S302为形成绝缘层42，具体包括步骤：1）沉积一绝缘层，并将沉积一绝缘层后的阵列基板在真空中放置一段时间，且对绝缘层进行烘烤处理；2）对绝缘层进行曝光显影处理，得到具有开口421的绝缘层42；3）对具有开口421的绝缘层42进行紫外线光固化处理；4）对完成光固化处理的具有开口421的绝缘层42进行高温退火处理。本步骤S302与上述实施方式绝缘层的制造方法类似，具体不再赘述。
通过本发明阵列基板的制造方法所得到的阵列基板中绝缘层在曝光显影得到开口后，进行高温退火之前对其实施光固化处理，使其在高温退火时受到高温作用发生变形的程度变小。阵列基板中开口的质量较高，相应的阵列基板的质量也较高。
请参阅图5，图5是本发明阵列基板一实施方式的结构示意图。
本实施方式阵列基板500由上述实施方式阵列基板的制造方法制得。
具体来说，本实施方式阵列基板500包括玻璃基板51，在玻璃基板51上依次形成的栅极层52、栅极绝缘层53、数据线54、钝化层55、绝缘层56以及公共电极57。其中绝缘层56在曝光显影得到开口561后，进一步进行光固化处理，然后进行高温退火。
在其他实施方式中，栅极层52、数据线54以及公共电极57的位置关系可以根据阵列基板500的类型确定，例如在某些阵列基板中，栅极层52与公共电极57同层设置，因此本发明中对于栅极层52、数据线54以及公共电极57的位置关系不做限制。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种绝缘层的制造方法，其中，所述制造方法包括以下步骤：
    在基板上沉积一绝缘层；
    对所述绝缘层进行曝光显影处理，得到具有开口的绝缘层；
    对具有开口的绝缘层进行光固化处理；
    对完成光固化处理的具有开口的绝缘层进行高温退火处理。
  2. 根据权利要求1所述的制造方法，其中，所述对具有开口的绝缘层进行光固化处理的步骤包括：
    对具有开口的绝缘层进行紫外线固化处理。
  3. 根据权利要求1所述的制造方法，其中，所述在基板上沉积一绝缘层的步骤之后包括：
    将具有绝缘层的基板在真空中放置一段时间。
  4. 根据权利要求1所述的制造方法，其中，所述沉积一绝缘层后的步骤包括：
    对所述绝缘层进行烘烤处理。
  5. 根据权利要求1所述的制造方法，其中，所述沉积一绝缘层的步骤包括：
    使用化学气相沉积得到一绝缘层。
  6. 一种阵列基板的制造方法，其中，在形成数据线和形成公共电极线的步骤之间包括形成绝缘层的步骤，
    所述形成绝缘层的步骤包括：
    沉积一绝缘层；
    对所述绝缘层进行曝光显影处理，得到具有开口的绝缘层；
    对具有开口的绝缘层进行光固化处理；
    对完成光固化处理的具有开口的绝缘层进行高温退火处理。
  7. 根据权利要求6所述的制造方法，其中，所述对具有开口的绝缘层进行光固化处理的步骤包括：
    对具有开口的绝缘层进行紫外线固化处理。
  8. 根据权利要求6所述的制造方法，其中，所述沉积一绝缘层的步骤之后包括：
    将沉积一绝缘层后的阵列基板在真空中放置一段时间。
  9. 根据权利要求6所述的制造方法，其中，所述沉积一绝缘层后的步骤包括：
    对所述绝缘层进行烘烤处理。
  10. 根据权利要求6所述的制造方法，其中，所述沉积一绝缘层的步骤包括：
    使用化学气相沉积得到一绝缘层。
  11. 一种阵列基板，其中，所述阵列基板由一制造方法制得，所述制造方法包括：在形成数据线和形成公共电极线的步骤之间包括形成绝缘层的步骤，
    所述形成绝缘层的步骤包括：
    沉积一绝缘层；
    对所述绝缘层进行曝光显影处理，得到具有开口的绝缘层；
    对具有开口的绝缘层进行光固化处理；
    对完成光固化处理的具有开口的绝缘层进行高温退火处理。
  12. 根据权利要求11所述的阵列基板，其中，所述对具有开口的绝缘层进行光固化处理的步骤包括：
    对具有开口的绝缘层进行紫外线固化处理。
  13. 根据权利要求11所述的阵列基板，其中，所述沉积一绝缘层的步骤之后包括：
    将沉积一绝缘层后的阵列基板在真空中放置一段时间。
  14. 根据权利要求11所述的阵列基板，其中，所述沉积一绝缘层后的步骤包括：
    对所述绝缘层进行烘烤处理。
  15. 根据权利要求11所述的阵列基板，其中，所述沉积一绝缘层的步骤包括：
    使用化学气相沉积得到一绝缘层。
PCT/CN2016/090652 2016-07-01 2016-07-20 绝缘层的制造方法、阵列的制造方法及阵列基板 Ceased WO2018000484A1 (zh)

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