WO2018000478A1 - 薄膜晶体管的制造方法及阵列基板的制造方法 - Google Patents

薄膜晶体管的制造方法及阵列基板的制造方法 Download PDF

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WO2018000478A1
WO2018000478A1 PCT/CN2016/090591 CN2016090591W WO2018000478A1 WO 2018000478 A1 WO2018000478 A1 WO 2018000478A1 CN 2016090591 W CN2016090591 W CN 2016090591W WO 2018000478 A1 WO2018000478 A1 WO 2018000478A1
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contact region
pattern
forming
layer
amorphous silicon
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French (fr)
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张卜芳
李松杉
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Definitions

  • Embodiments of the present invention relate to the field of liquid crystal display technologies, and in particular, to a method for fabricating a thin film transistor and a method for fabricating an array substrate.
  • the ion implanter performs doping treatment on the entire surface of the deposited amorphous silicon (abbreviated as a-Si), and then doping the doping.
  • the ionized amorphous silicon is subjected to a thermal annealing (RTA) crystallization treatment to obtain an active layer of the TFT.
  • RTA thermal annealing
  • This crystallization method essentially crystallizes the whole-surface properties of amorphous silicon after implanting doping ions.
  • the crystal orientation of amorphous silicon particles is random, and the crystallization efficiency and crystal uniformity are low, and it is easy to appear more.
  • the grain boundary thereby reducing the electron mobility of the TFT and affecting the electrical characteristics of the TFT.
  • the present invention provides a method for fabricating a thin film transistor and a method for fabricating an array substrate, which can crystallize as much as possible, improve crystallization efficiency and crystal uniformity, reduce the influence of grain boundaries on the electron mobility and leakage current of the TFT, and improve the TFT. Electrical characteristics.
  • a method for fabricating a thin film transistor includes: providing a substrate; sequentially forming an amorphous silicon layer and a photoresist layer on the substrate, and patterning the photoresist layer by using a photomask to form spaced light a resist pattern; doping treatment of the amorphous silicon layer not covered by the photoresist pattern, the doped ions of the doping treatment include boron ions; stripping the photoresist pattern, and performing thermal annealing crystallization treatment on the amorphous silicon layer Forming a source contact region and a drain contact region in the doped region of the amorphous silicon layer, forming a channel region in a region covered by the photoresist pattern; forming a gate on the amorphous silicon layer subjected to thermal annealing crystallization treatment a gate insulating layer; a gate pattern is formed on the gate insulating layer, and the gate pattern is located between the source contact region and the drain contact region and correspondingly above
  • the manufacturing method further includes: forming an interlayer dielectric layer on the gate pattern; forming a contact hole penetrating the interlayer dielectric layer and the gate insulating layer above the source contact region and the drain contact region; Forming an upper portion of the interlayer dielectric layer corresponding to the source contact region and the drain contact region
  • the source pattern and the drain pattern are formed such that the source pattern and the drain pattern are electrically connected to the source contact region and the drain contact region through the contact holes, respectively.
  • a method for fabricating a thin film transistor includes: providing a substrate; sequentially forming an amorphous silicon layer and a photoresist layer on the substrate, and patterning the photoresist layer by using a photomask to form spaced light a resist pattern; doping the amorphous silicon layer not covered by the photoresist pattern; stripping the photoresist pattern, and performing thermal annealing crystallization treatment on the amorphous silicon layer to make the doped region of the amorphous silicon layer A source contact region and a drain contact region are formed, and a region covered by the photoresist pattern forms a channel region.
  • the manufacturing method further comprises: forming a gate insulating layer on the amorphous silicon layer subjected to thermal annealing crystallization treatment; forming a gate pattern on the gate insulating layer, and the gate pattern is located at the source contact region and the drain The contact regions are located between and correspondingly above the channel region.
  • the manufacturing method further includes: forming an interlayer dielectric layer on the gate pattern; forming a contact hole penetrating the interlayer dielectric layer and the gate insulating layer above the source contact region and the drain contact region; Forming a source pattern and a drain pattern respectively above the source contact region and the drain contact region of the interlayer dielectric layer such that the source pattern and the drain pattern are respectively contactable with the source contact region through the contact hole
  • the drain contact region is electrically connected.
  • the step of sequentially forming an amorphous silicon layer and a photoresist layer on the substrate includes sequentially forming a gate pattern and a gate insulating layer on the substrate; and sequentially forming an amorphous silicon layer and a photoresist layer on the gate insulating layer.
  • the manufacturing method further comprises: forming an interlayer dielectric layer on the amorphous silicon layer subjected to thermal annealing crystallization; forming an inter-layer dielectric layer above the source contact region and the drain contact region; a contact hole; a source pattern and a drain pattern are respectively formed above the source contact region and the drain contact region of the interlayer dielectric layer, so that the source pattern and the drain pattern are respectively in contact with the source through the contact hole The region and the drain contact region are electrically connected.
  • the doping-treated dopant ions comprise boron ions.
  • a method for manufacturing an array substrate includes: providing a substrate; sequentially forming an amorphous silicon layer and a photoresist layer on the substrate, and patterning the photoresist layer by using a photomask to form spaced light a resist pattern; doping the amorphous silicon layer not covered by the photoresist pattern; stripping the photoresist pattern, and performing thermal annealing crystallization treatment on the amorphous silicon layer to dope the amorphous silicon layer
  • the region forms a source contact region and a drain contact region, and is covered by the photoresist pattern Forming a channel region; forming an interlayer dielectric layer on the amorphous silicon layer subjected to thermal annealing crystallization; forming a layer penetrating the interlayer dielectric layer above the source contact region and the drain contact region a contact hole; a source pattern and a drain pattern are respectively formed above the source contact region and the drain contact region of the interlayer dielectric layer, such that the source pattern and
  • the step of forming an interlayer dielectric layer on the amorphous silicon layer subjected to the thermal annealing crystallization treatment comprises: forming a gate insulating layer on the amorphous silicon layer subjected to thermal annealing crystallization treatment; on the gate insulating layer Forming a gate pattern, and the gate pattern is located between the source contact region and the drain contact region and correspondingly above the channel region; forming an interlayer dielectric layer on the gate pattern; the corresponding to the source contact
  • the step of forming a first contact hole penetrating the interlayer dielectric layer over the region and the drain contact region includes: forming a through interlayer dielectric layer and a gate insulating layer over the source contact region and the drain contact region The first contact hole.
  • the step of sequentially forming an amorphous silicon layer and a photoresist layer on the substrate includes sequentially forming a gate pattern and a gate insulating layer on the substrate; and sequentially forming an amorphous silicon layer and a photoresist layer on the gate insulating layer.
  • the doping-treated dopant ions comprise boron ions.
  • a method for fabricating a thin film transistor and a method for fabricating an array substrate according to an embodiment of the present invention wherein a region to be doped by an amorphous silicon layer is defined by a photoresist pattern, that is, an amorphous region corresponding only to a source contact region and a drain contact region is defined.
  • the silicon layer is doped to cause crystallization to occur in the source contact region and the drain contact region, and the crystal direction is from the source contact region and the drain contact region toward the channel region, thereby achieving directional crystallization as much as possible, improving crystallization efficiency and crystallization. Uniformity reduces the influence of grain boundaries on the electron mobility and leakage current of the TFT and improves the electrical characteristics of the TFT.
  • FIG. 1 is a flow chart showing a method of manufacturing a thin film transistor according to an embodiment of the present invention
  • FIG. 2 is a schematic view showing a scenario based on a method of manufacturing the thin film transistor shown in FIG. 1;
  • FIG. 3 is a schematic flow chart of a method of manufacturing a thin film transistor according to another embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method of manufacturing an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing the structure of an array substrate produced based on the manufacturing method shown in FIG. 4;
  • FIG. 6 is a schematic flow chart of a method of manufacturing an array substrate according to another embodiment of the present invention.
  • the purpose of the embodiment of the present invention is to use a photoresist pattern to define a region to be doped by the amorphous silicon layer, that is, to do only the source contact region and the drain contact region, so that crystallization occurs in the source contact region and the drain.
  • the crystal direction is from the source contact region and the drain contact region toward the channel region, thereby achieving directional crystallization as much as possible, improving crystallization efficiency and crystal uniformity, and reducing the influence of grain boundaries on the electron mobility and leakage current of the TFT.
  • FIG. 1 illustrates a method of fabricating a thin film transistor according to an embodiment of the present invention.
  • the method of manufacturing the thin film transistor may include steps S11 to S19.
  • the substrate of the embodiment of the present invention may be a transparent substrate such as a glass substrate, a transparent plastic substrate, or a flexible substrate.
  • the substrate may also be provided with a passivation protective layer.
  • the substrate 21 includes a substrate substrate 211 and a buffer layer 212 formed on the substrate substrate 211.
  • the substrate substrate 211 may be a transparent substrate such as a glass substrate, a transparent plastic substrate, or a flexible substrate.
  • the buffer layer 212 serves as a passivation protective layer, and its material includes, but not limited to, a silicon nitride compound such as Si 3 N 4 (tetrazinc silicon nitride, abbreviated as silicon nitride).
  • S12 forming an amorphous silicon layer and a photoresist layer on the substrate in sequence, and patterning the photoresist layer with a photomask to form a photoresist pattern arranged at intervals.
  • the amorphous silicon layer 22 may be formed on the substrate 21 by a method such as vacuum evaporation, sputtering, coating, chemical vapor deposition (CVD) or the like.
  • the photoresist layer 23 is preferably formed on the amorphous silicon layer 22 by a coating process.
  • the material of the photoresist layer 23 is preferably a positive photoresist.
  • the embodiment of the patterning process may be such that when the photoresist layer 23 is irradiated with light by the photomask 20, the portion irradiated with the light may be removed by the developing solution by the developing process, and the portion not irradiated with the light is subjected to the development process. It is retained so that spacer films 231 (only one shown in the drawing) are formed on the amorphous silicon layer 22.
  • spacer films 231 (only one shown in the drawing) are formed on the amorphous silicon layer 22.
  • the region Z 1 of the amorphous silicon layer 22 not covered by the photoresist pattern 231 is used to form the source contact region and the drain contact region of the TFT, and the region Z 2 of the amorphous silicon layer 22 covered by the photoresist pattern 231 A channel region for forming a TFT.
  • the doped dopant ions include, but are not limited to, boron (Boron) ions.
  • S14 stripping the photoresist pattern and performing thermal annealing crystallization treatment on the amorphous silicon layer, so that the doped region of the amorphous silicon layer forms a source contact region and a drain contact region, and the region covered by the photoresist pattern A channel region is formed.
  • the thermal annealing treatment causes the amorphous silicon layer 22 to crystallize to form a polycrystalline silicon (poly-Si) semiconductor layer 24 of the TFT.
  • the region Z 1 subjected to the doping treatment forms a source contact region Z S and a drain contact region Z D , and a region Z 2 covered by the photoresist pattern forms a channel region Z G of the TFT.
  • the crystal direction is from the source contact region Z S and the drain contact region Z D toward the channel region Z G .
  • Such oriented crystallization can improve crystallization efficiency and crystal uniformity, reduce the influence of grain boundaries on the electron mobility and leakage current of the TFT, and improve the electrical characteristics of the TFT. Further, after the crystallization is completed, the doping ions in the channel region Z G are small, and the electron mobility is low, so that the leakage current of the TFT can be reduced.
  • the source contact region Z S and the drain contact region Z D have more dopant ions and higher electron mobility, so that the contact impedance with the subsequently formed source and drain can be reduced.
  • a Gate Insulation Layer (GI) 25 is formed by coating, evaporation, or sputtering.
  • the gate insulating layer 25 may include a silicon oxide compound layer and a silicon nitride compound, such as SiO 2 (silica, abbreviated as silicon oxide) and Si 3 N 4 , which are sequentially formed on the polysilicon semiconductor layer 24, thereby The wear resistance and insulation properties of the gate insulating layer 25 can be further improved.
  • the gate pattern G having a predetermined pattern may be formed by patterning treatment of exposure, development, and etching.
  • An interlayer dielectric layer (IDL, also referred to as a dielectric layer) 26 covers the gate pattern G and the gate insulating layer 25.
  • the two contact holes Z O can be formed by etching.
  • the two contact holes Z O expose the upper surfaces of the source contact region Z S and the drain contact region Z D such that the subsequently formed source pattern and drain pattern can respectively contact the source contact region Z through the contact hole Z O S and the drain contact region Z D are electrically connected.
  • the material of the source pattern S and the drain pattern D may be the same as or different from the material of the gate pattern G, and is, for example, molybdenum (Molybdenum, chemical formula: Mo).
  • the manufacturing method of the present embodiment only performs doping treatment on the amorphous silicon layer 22 not covered by the photoresist pattern 231, and corresponds to the amorphous silicon layer 22 when the amorphous silicon layer 22 is crystallized to form the polycrystalline silicon semiconductor layer. Partial crystallization is performed, and the crystal orientation is an undoped region from the doped region toward both sides, thereby improving crystallization efficiency and crystal uniformity, reducing the influence of grain boundaries on the electron mobility and leakage current of the TFT, and improving the electrical properties of the TFT. characteristic.
  • the TFT of this embodiment can be regarded as a top gate type structure. Based on the foregoing object, the embodiment of the present invention is also applicable to a TFT of a bottom gate type structure.
  • the method of manufacturing the thin film transistor may include the following steps S31 to S39.
  • S33 forming an amorphous silicon layer and a photoresist layer sequentially on the gate insulating layer, and patterning the photoresist layer by using a photomask to form a spacer pattern disposed at intervals.
  • S35 stripping the photoresist pattern, and performing thermal annealing crystallization treatment on the amorphous silicon layer, so that the doped region of the amorphous silicon layer forms a source contact region and a drain contact region, and the region covered by the photoresist pattern A channel region is formed.
  • the present embodiment places the gate pattern and the gate insulating layer under the amorphous silicon layer, and the contact hole penetrates only the interlayer dielectric layer, and Does not penetrate the gate insulating layer. Since the non-silicon crystal layer of the present embodiment can also perform directional crystallization, the TFT obtained in the present embodiment also has the aforementioned advantageous effects.
  • FIG. 4 illustrates a method of fabricating an array substrate according to an embodiment of the invention.
  • the method of manufacturing the array substrate may include steps S41 to S51.
  • S42 forming an amorphous silicon layer and a photoresist layer on the substrate in sequence, and patterning the photoresist layer by using a photomask to form a photoresist pattern arranged at intervals.
  • S44 stripping the photoresist pattern, and performing thermal annealing crystallization treatment on the amorphous silicon layer, so that the doped region of the amorphous silicon layer forms a source contact region and a drain contact region, and is covered by the photoresist pattern.
  • the area forms a channel region.
  • S49 forming a source pattern and a drain pattern respectively corresponding to the source contact region and the drain contact region of the interlayer dielectric layer, such that the source pattern and the drain pattern respectively pass through the first contact hole and the source
  • the contact region and the drain contact region are electrically connected.
  • the first contact hole of this embodiment can be regarded as the contact hole Z O of the embodiment described in FIG. 2 described above.
  • steps S41 to S49 are the same as steps S11 to S48 of the embodiment shown in Fig. 1.
  • the two embodiments use the same reference numerals.
  • the second contact hole Z O2 prepared in steps S50 and S51 is used to electrically connect the pixel electrode 27 and the drain contact region Z S .
  • the array substrate of the present embodiment can be regarded as a TFT having a top gate structure.
  • the embodiment of the present invention can also be applied to an array substrate having a bottom gate type TFT.
  • the manufacturing method of the array substrate may include the following steps S61 to S70.
  • S62 sequentially forming a gate pattern and a gate insulating layer on the substrate.
  • S63 forming an amorphous silicon layer and a photoresist layer sequentially on the gate insulating layer, and patterning the photoresist layer by using a photomask to form a photoresist pattern arranged at intervals.
  • S65 stripping the photoresist pattern, and performing thermal annealing crystallization treatment on the amorphous silicon layer, so that the doped region of the amorphous silicon layer forms a source contact region and a drain contact region, and the region covered by the photoresist pattern A channel region is formed.
  • S68 forming a source pattern and a drain pattern respectively corresponding to the source contact region and the drain contact region of the interlayer dielectric layer, such that the source pattern and the drain pattern respectively pass through the first contact hole and the source The contact region and the drain contact region are electrically connected.
  • the first contact hole of this embodiment can be regarded as the contact hole of the embodiment described above in FIG. Among them, steps S61 to S68 are the same as steps S31 to S38 of the embodiment described in FIG.
  • the second contact holes prepared in steps S69 and S70 of the embodiment are used to electrically connect the pixel electrodes and the drain contact regions.
  • the array substrate prepared in the embodiments of FIGS. 4-6 can also achieve directional junction.
  • the crystal, the material of each structural element, and the shape to be formed can be referred to the foregoing, and thus have the same advantageous effects as the manufacturing method of the foregoing thin film transistor.

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  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管的制造方法及阵列基板的制造方法，利用光阻限定非晶硅层（22）所要掺杂的区域，使得结晶发生在源极接触区和漏极接触区，结晶方向为从源极接触区和漏极接触区朝向沟道区，从而尽量实现定向结晶，提高结晶效率和结晶均一性，减少晶界对TFT的电子迁移率和漏电流的影响，改善TFT的电学特性。

Description

薄膜晶体管的制造方法及阵列基板的制造方法 【技术领域】
本发明实施例涉及液晶显示技术领域，具体而言涉及一种薄膜晶体管的制造方法及阵列基板的制造方法。
【背景技术】
在当前的TFT(Thin Film Transistor，薄膜晶体管)制造工艺中，离子植入机对沉积的非晶硅(amorphous silicon，简称a-Si)整面的进行掺杂处理，而后对掺杂有掺杂离子的非晶硅进行热退火(Rapid Thermal Anneal，RTA)结晶处理，从而得到TFT的有源层。这种结晶方法实质上是在植入掺杂离子后对非晶硅整面性的进行结晶，非晶硅颗粒的结晶方向是随机的，结晶效率和结晶均一性较低，容易出现较多的晶界，从而降低TFT的电子迁移率，影响TFT的电学特性。
【发明内容】
鉴于此，本发明提供一种薄膜晶体管的制造方法及阵列基板的制造方法，能够尽量定向结晶，提高结晶效率和结晶均一性，减少晶界对TFT的电子迁移率和漏电流的影响，改善TFT的电学特性。
本发明一实施例的薄膜晶体管的制造方法，包括：提供一基板；在基板上依次形成非晶硅层和光阻层，并利用光罩对光阻层进行图案化处理，以形成间隔设置的光阻图案；对未被光阻图案覆盖的非晶硅层进行掺杂处理，所述掺杂处理的掺杂离子包括硼离子；剥除光阻图案，并对非晶硅层进行热退火结晶处理，使得非晶硅层的经过掺杂处理的区域形成源极接触区和漏极接触区，被光阻图案覆盖的区域形成沟道区；在经过热退火结晶处理的非晶硅层上形成栅极绝缘层；在栅极绝缘层上形成栅极图案，且栅极图案位于源极接触区和漏极接触区之间且对应位于沟道区的上方。
其中，所述制造方法进一步包括：在栅极图案上形成层间介电层；在对应于源极接触区和漏极接触区的上方形成贯穿层间介电层和栅极绝缘层的接触孔；在层间介电层的对应于源极接触区和漏极接触区的上方分别形 成源极图案和漏极图案，使得源极图案和漏极图案可通过接触孔分别与源极接触区和漏极接触区电性连接。
本发明一实施例的薄膜晶体管的制造方法，包括：提供一基板；在基板上依次形成非晶硅层和光阻层，并利用光罩对光阻层进行图案化处理，以形成间隔设置的光阻图案；对未被光阻图案覆盖的非晶硅层进行掺杂处理；剥除光阻图案，并对非晶硅层进行热退火结晶处理，使得非晶硅层的经过掺杂处理的区域形成源极接触区和漏极接触区，被光阻图案覆盖的区域形成沟道区。
其中，所述制造方法还包括：在经过热退火结晶处理的非晶硅层上形成栅极绝缘层；在栅极绝缘层上形成栅极图案，且栅极图案位于源极接触区和漏极接触区之间且对应位于沟道区的上方。
其中，所述制造方法进一步包括：在栅极图案上形成层间介电层；在对应于源极接触区和漏极接触区的上方形成贯穿层间介电层和栅极绝缘层的接触孔；在层间介电层的对应于源极接触区和漏极接触区的上方分别形成源极图案和漏极图案，使得源极图案和漏极图案可通过接触孔分别与源极接触区和漏极接触区电性连接。
其中，所述在基板上依次形成非晶硅层和光阻层的步骤包括：在基板上依次形成栅极图案和栅极绝缘层；在栅极绝缘层上依次形成非晶硅层和光阻层。
其中，所述制造方法进一步包括：在经过热退火结晶处理的非晶硅层上形成层间介电层；在对应于源极接触区和漏极接触区的上方形成贯穿层间介电层的接触孔；在层间介电层的对应于源极接触区和漏极接触区的上方分别形成源极图案和漏极图案，使得源极图案和漏极图案可通过接触孔分别与源极接触区和漏极接触区电性连接。
其中，所述掺杂处理的掺杂离子包括硼离子。
本发明一实施例的阵列基板的制造方法，包括：提供一基板；在基板上依次形成非晶硅层和光阻层，并利用光罩对光阻层进行图案化处理，以形成间隔设置的光阻图案；对未被光阻图案覆盖的非晶硅层进行掺杂处理；剥除所述光阻图案，并对非晶硅层进行热退火结晶处理，使得非晶硅层的经过掺杂处理的区域形成源极接触区和漏极接触区，被光阻图案覆盖的区 域形成沟道区；在经过热退火结晶处理的非晶硅层上形成层间介电层；在对应于源极接触区和漏极接触区的上方形成贯穿所述层间介电层的第一接触孔；在层间介电层的对应于源极接触区和漏极接触区的上方分别形成源极图案和漏极图案，使得源极图案和漏极图案可通过第一接触孔分别与源极接触区和漏极接触区电性连接；在对应于漏极接触区的上方形成暴露漏极接触区的第二接触孔；在层间介电层上形成像素电极，使得像素电极可通过第二接触孔与漏极接触区电性连接。
其中，所述在经过热退火结晶处理的非晶硅层上形成层间介电层的步骤包括：在经过热退火结晶处理的非晶硅层上形成栅极绝缘层；在栅极绝缘层上形成栅极图案，且栅极图案位于源极接触区和漏极接触区之间且对应位于沟道区的上方；在栅极图案上形成层间介电层；所述在对应于源极接触区和漏极接触区的上方形成贯穿层间介电层的第一接触孔的步骤包括：在对应于源极接触区和漏极接触区的上方形成贯穿层间介电层和栅极绝缘层的第一接触孔。
其中，所述在基板上依次形成非晶硅层和光阻层的步骤包括：在基板上依次形成栅极图案和栅极绝缘层；在栅极绝缘层上依次形成非晶硅层和光阻层。
其中，所述掺杂处理的掺杂离子包括硼离子。
本发明实施例的薄膜晶体管的制造方法及阵列基板的制造方法，利用光阻图案限定非晶硅层所要掺杂的区域，即限定了仅对源极接触区和漏极接触区对应的非晶硅层进行掺杂处理，使得结晶发生在源极接触区和漏极接触区，结晶方向为从源极接触区和漏极接触区朝向沟道区，从而尽量实现定向结晶，提高结晶效率和结晶均一性，减少晶界对TFT的电子迁移率和漏电流的影响，改善TFT的电学特性。
【附图说明】
图1是本发明一实施例的薄膜晶体管的制造方法的流程示意图；
图2是基于图1所示的薄膜晶体管的制造方法的场景示意图；
图3是本发明另一实施例的薄膜晶体管的制造方法的流程示意图；
图4是本发明一实施例的阵列基板的制造方法的流程示意图；
图5是基于图4所示的制造方法所制得的阵列基板的结构剖视图；
图6是本发明另一实施例的阵列基板的制造方法的流程示意图。
【具体实施方式】
本发明实施例的目的是利用光阻图案限定非晶硅层所要掺杂的区域，即仅对源极接触区和漏极接触区进行掺杂处理，使得结晶发生在源极接触区和漏极接触区，结晶方向为从源极接触区和漏极接触区朝向沟道区，从而尽量实现定向结晶，提高结晶效率和结晶均一性，减少晶界对TFT的电子迁移率和漏电流的影响，改善TFT的电学特性。
下面结合本发明实施例中的附图，对本发明所提供的示例性的实施例的技术方案进行清楚、完整地描述。在不冲突的情况下，下述的实施例及实施例中的技术特征可以相互组合。
请参阅图1，为本发明一实施例的薄膜晶体管的制造方法。所述薄膜晶体管的制造方法可以包括步骤S11～S19。
S11：提供一基板。
本发明实施例的基板可以为玻璃基材、透明塑料基材、可挠式基材等透明基材。当然，所述基板也可以设置有钝化保护层，如图2所示，基板21包括衬底基材211和形成于衬底基材211上的缓冲层212。衬底基材211可以为玻璃基材、透明塑料基材、可挠式基材等透明基材。缓冲层212作为钝化保护层，其材料包括但不限于硅氮化合物，例如Si3N4(四氮化三硅，简称氮化硅)。
S12：在基板上依次形成非晶硅层和光阻层，并利用光罩对光阻层进行图案化处理，以形成间隔设置的光阻图案。
本发明实施例可以采用例如真空蒸镀、溅射、涂覆、化学气相沉积(Chemical vapor deposition，CVD)等方法在基板21上形成非晶硅层22。进一步，本实施例优选采用涂覆工艺在非晶硅层22上形成光阻层23。所述光阻层23的材料优选为正性光阻。
图案化处理的实施方式可以为：在利用光罩20对光阻层23进行光照射时，被光照射的部分可以经过显影处理被显影液去除，而未被光照射的部分经过显影处理后仍然保留，从而在非晶硅层22上形成间隔设置的光阻 图案231(图中仅示出一个)。其中，非晶硅层22的未被光阻图案231覆盖的区域Z1用于形成TFT的源极接触区和漏极接触区，非晶硅层22的被光阻图案231覆盖的区域Z2用于形成TFT的沟道区。
S13：对未被光阻图案覆盖的非晶硅层进行掺杂处理。
结合图2所示，即为对区域Z1的非晶硅层22进行掺杂处理。所述掺杂处理的掺杂离子包括但不限于硼(Boron)离子。
S14：剥除光阻图案，并对非晶硅层进行热退火结晶处理，使得非晶硅层的经过掺杂处理的区域形成源极接触区和漏极接触区，被光阻图案覆盖的区域形成沟道区。
热退火处理使得非晶硅层22结晶形成TFT的多晶硅(poly-Si)半导体层24。其中，进行掺杂处理的区域Z1形成源极接触区ZS和漏极接触区ZD，被光阻图案覆盖的区域Z2形成TFT的沟道区ZG。
由于进行掺杂处理的区域Z1的掺杂离子较多，因此结晶方向为从源极接触区ZS和漏极接触区ZD朝向沟道区ZG。这种定向结晶能够提高结晶效率和结晶均一性，减少晶界对TFT的电子迁移率和漏电流的影响，改善TFT的电学特性。另外，结晶完成后，沟道区ZG中的掺杂离子较少，电子迁移率较低，从而能够减少TFT的漏电流。而源极接触区ZS和漏极接触区ZD中的掺杂离子较多，电子迁移率较高，从而能够降低与后续形成的源极和漏极的接触阻抗。
S15：在经过热退火结晶处理的非晶硅层上形成栅极绝缘层。
优选采用涂覆或蒸镀、溅射方式形成栅极绝缘层(Gate Insulation Layer，GI)25。进一步优选地，所述栅极绝缘层25可以包括依次形成于多晶硅半导体层24上的硅氧化合物层和硅氮化合物，例如SiO2(二氧化硅，简称氧化硅)和Si3N4，从而能够进一步提高栅极绝缘层25的耐磨损能力和绝缘性能。
S16：在栅极绝缘层上形成栅极图案，且栅极图案位于源极接触区和漏极接触区之间且对应位于沟道区的上方。
本发明实施例可以采用曝光、显影、刻蚀的图案化处理形成具有预定图案的栅极图案G。
S17：在栅极图案上形成层间介电层。
层间介电层(Interlayer Dielectric Layer，简称IDL，又称介电层)26覆盖栅极图案G以及栅极绝缘层25。
S18：在对应于源极接触区和漏极接触区的上方形成贯穿层间介电层和栅极绝缘层的接触孔。
请继续参阅图2，本实施例可以通过刻蚀方式形成所述两个接触孔ZO。所述两个接触孔ZO暴露源极接触区ZS和漏极接触区ZD的上表面，使得后续形成的源极图案和漏极图案可通过接触孔ZO分别与源极接触区ZS和漏极接触区ZD电性连接。
S19：在对应于源极接触区和漏极接触区的上方分别形成源极图案和漏极图案，使得源极图案和漏极图案可通过接触孔分别与源极接触区和漏极接触区电性连接。
源极图案S和漏极图案D的材质与栅极图案G的材质可以相同也可以不相同，例如为钼(Molybdenum，化学式为Mo)。
由上述可知，本实施例的制造方法仅对未被光阻图案231覆盖的非晶硅层22进行掺杂处理，在非晶硅层22结晶形成多晶硅半导体层时相当于对非晶硅层22进行局部结晶，并且结晶方向为从掺杂区域朝向两侧的未掺杂区域，从而能够提高结晶效率和结晶均一性，减少晶界对TFT的电子迁移率和漏电流的影响，改善TFT的电学特性。
请继续参阅图2，鉴于栅极图案G形成于沟道区ZG的上方，因此该实施例的TFT可视为顶栅型结构。基于前述发明目的，本发明实施例还适用于底栅型结构的TFT。如图3所示，所述薄膜晶体管的制造方法可以包括以下步骤S31～S39。
S31：提供一基板。
S32：在基板上依次形成栅极图案和栅极绝缘层。
S33：在栅极绝缘层上依次形成非晶硅层和光阻层，并利用光罩对光阻层进行图案化处理，以形成间隔设置的光阻图案。
S34：对未被光阻图案覆盖的非晶硅层进行掺杂处理。
S35：剥除光阻图案，并对非晶硅层进行热退火结晶处理，使得非晶硅层的经过掺杂处理的区域形成源极接触区和漏极接触区，被光阻图案覆盖的区域形成沟道区。
S36：在经过热退火结晶处理的非晶硅层上形成层间介电层。
S37：在对应于源极接触区和漏极接触区的上方形成贯穿层间介电层的接触孔。
S38：在层间介电层的对应于源极接触区和漏极接触区的上方分别形成源极图案和漏极图案，使得源极图案和漏极图案可通过接触孔分别与源极接触区和漏极接触区电性连接。
在图2所述实施例的描述基础上但与其不同的是，本实施例将栅极图案和栅极绝缘层设置于非晶硅层的下方，并且接触孔仅贯穿层间介电层，而未贯穿栅极绝缘层。由于本实施例的非硅晶层也可以进行定向结晶，因此本实施例所制得的TFT也具有前述有益效果。
请参阅图4，为本发明一实施例的阵列基板的制造方法。所述阵列基板的制造方法可以包括步骤S41～S51。
S41：提供一基板。
S42：在基板上依次形成非晶硅层和光阻层，并利用光罩对光阻层进行图案化处理，以形成间隔设置的光阻图案。
S43：对未被光阻图案覆盖的非晶硅层进行掺杂处理。
S44：剥除所述光阻图案，并对非晶硅层进行热退火结晶处理，使得非晶硅层的经过掺杂处理的区域形成源极接触区和漏极接触区，被光阻图案覆盖的区域形成沟道区。
S45：在经过热退火结晶处理的非晶硅层上形成栅极绝缘层。
S46：在栅极绝缘层上形成栅极图案，且栅极图案位于源极接触区和漏极接触区之间且对应位于沟道区的上方。
S47：在栅极图案上形成层间介电层。
S48：在对应于源极接触区和漏极接触区的上方形成贯穿层间介电层和栅极绝缘层的第一接触孔。
S49：在层间介电层的对应于源极接触区和漏极接触区的上方分别形成源极图案和漏极图案，使得源极图案和漏极图案可通过第一接触孔分别与源极接触区和漏极接触区电性连接。
S50：在对应于漏极接触区的上方形成暴露漏极接触区的第二接触孔。
S51：在层间介电层上形成像素电极，使得像素电极可通过第二接触孔 与漏极接触区电性连接。
本实施例的第一接触孔可视为前述图2所述实施例的接触孔ZO。其中，步骤S41～S49与图1所述实施例的步骤S11～S48相同。对于相同结构元件，两实施例采用相同的标号。结合图5所示，步骤S50和S51所制得的第二接触孔ZO2用于电性连接像素电极27和漏极接触区ZS。
鉴于栅极图案G形成于沟道区ZG的上方，因此本实施例的阵列基板可视为具有顶栅型结构的TFT。当然，本发明实施例还可以适用于具有底栅型结构TFT的阵列基板。请参阅图6，所述阵列基板的制造方法可以包括以下步骤S61～S70。
S61：提供一基板。
S62：在基板上依次形成栅极图案和栅极绝缘层。
S63：在栅极绝缘层上依次形成非晶硅层和光阻层，并利用光罩对光阻层进行图案化处理，以形成间隔设置的光阻图案。
S64：对未被光阻图案覆盖的非晶硅层进行掺杂处理。
S65：剥除光阻图案，并对非晶硅层进行热退火结晶处理，使得非晶硅层的经过掺杂处理的区域形成源极接触区和漏极接触区，被光阻图案覆盖的区域形成沟道区。
S66：在经过热退火结晶处理的非晶硅层上形成层间介电层。
S67：在对应于源极接触区和漏极接触区的上方形成贯穿层间介电层的第一接触孔。
S68：在层间介电层的对应于源极接触区和漏极接触区的上方分别形成源极图案和漏极图案，使得源极图案和漏极图案可通过第一接触孔分别与源极接触区和漏极接触区电性连接。
S69：在对应于漏极接触区的上方形成暴露漏极接触区的第二接触孔。
S70：在层间介电层上形成像素电极，使得像素电极可通过第二接触孔与漏极接触区电性连接。
本实施例的第一接触孔可视为前述图3所述实施例的接触孔。其中，步骤S61～S68与图3所述实施例的步骤S31～S38相同。而本实施例的步骤S69和S70所制得的第二接触孔用于电性连接像素电极和漏极接触区。
综上所述，图4～图6所述实施例制得的阵列基板，也可以实现定向结 晶，各个结构元件的材质以及所要形成的形状可参阅前述，因此具有与前述薄膜晶体管的制造方法相同的有益效果。
应理解，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种薄膜晶体管的制造方法，其中，所述制造方法包括：
    提供一基板；
    在所述基板上依次形成非晶硅层和光阻层，并利用光罩对所述光阻层进行图案化处理，以形成间隔设置的光阻图案；
    对未被所述光阻图案覆盖的非晶硅层进行掺杂处理，所述掺杂处理的掺杂离子包括硼离子；
    剥除所述光阻图案，并对所述非晶硅层进行热退火结晶处理，使得所述非晶硅层的经过所述掺杂处理的区域形成源极接触区和漏极接触区，被所述光阻图案覆盖的区域形成沟道区；
    在经过所述热退火结晶处理的非晶硅层上形成栅极绝缘层；
    在所述栅极绝缘层上形成栅极图案，且所述栅极图案位于所述源极接触区和所述漏极接触区之间且对应位于所述沟道区的上方。
  2. 根据权利要求1所述的制造方法，其中，所述制造方法进一步包括：
    在所述栅极图案上形成层间介电层；
    在对应于所述源极接触区和所述漏极接触区的上方形成贯穿所述层间介电层和所述栅极绝缘层的接触孔；
    在所述层间介电层的对应于所述源极接触区和所述漏极接触区的上方分别形成源极图案和漏极图案，使得所述源极图案和所述漏极图案可通过所述接触孔分别与所述源极接触区和所述漏极接触区电性连接。
  3. 一种薄膜晶体管的制造方法，其中，所述制造方法包括：
    提供一基板；
    在所述基板上依次形成非晶硅层和光阻层，并利用光罩对所述光阻层进行图案化处理，以形成间隔设置的光阻图案；
    对未被所述光阻图案覆盖的非晶硅层进行掺杂处理；
    剥除所述光阻图案，并对所述非晶硅层进行热退火结晶处理，使得所述非晶硅层的经过所述掺杂处理的区域形成源极接触区和漏极接触区，被所述光阻图案覆盖的区域形成沟道区。
  4. 根据权利要求3所述的制造方法，其中，所述制造方法还包括：
    在经过所述热退火结晶处理的非晶硅层上形成栅极绝缘层；
    在所述栅极绝缘层上形成栅极图案，且所述栅极图案位于所述源极接触区和所述漏极接触区之间且对应位于所述沟道区的上方。
  5. 根据权利要求4所述的制造方法，其中，所述制造方法进一步包括：
    在所述栅极图案上形成层间介电层；
    在对应于所述源极接触区和所述漏极接触区的上方形成贯穿所述层间介电层和所述栅极绝缘层的接触孔；
    在所述层间介电层的对应于所述源极接触区和所述漏极接触区的上方分别形成源极图案和漏极图案，使得所述源极图案和所述漏极图案可通过所述接触孔分别与所述源极接触区和所述漏极接触区电性连接。
  6. 根据权利要求3所述的制造方法，其中，所述在所述基板上依次形成非晶硅层和光阻层的步骤包括：
    在所述基板上依次形成栅极图案和栅极绝缘层；
    在所述栅极绝缘层上依次形成非晶硅层和光阻层。
  7. 根据权利要求6所述的制造方法，其中，所述制造方法进一步包括：
    在经过所述热退火结晶处理的非晶硅层上形成层间介电层；
    在对应于所述源极接触区和所述漏极接触区的上方形成贯穿所述层间介电层的接触孔；
    在所述层间介电层的对应于所述源极接触区和所述漏极接触区的上方分别形成源极图案和漏极图案，使得所述源极图案和所述漏极图案可通过所述接触孔分别与所述源极接触区和所述漏极接触区电性连接。
  8. 根据权利要求3所述的制造方法，其中，所述掺杂处理的掺杂离子包括硼离子。
  9. 一种阵列基板的制造方法，其中，所述制造方法包括：
    提供一基板；
    在所述基板上依次形成非晶硅层和光阻层，并利用光罩对所述光阻层进行图案化处理，以形成间隔设置的光阻图案；
    对未被所述光阻图案覆盖的非晶硅层进行掺杂处理；
    剥除所述光阻图案，并对所述非晶硅层进行热退火结晶处理，使得所述非晶硅层的经过所述掺杂处理的区域形成源极接触区和漏极接触区，被 所述光阻图案覆盖的区域形成沟道区；
    在经过所述热退火结晶处理的非晶硅层上形成层间介电层；
    在对应于所述源极接触区和所述漏极接触区的上方形成贯穿所述层间介电层的第一接触孔；
    在所述层间介电层的对应于所述源极接触区和所述漏极接触区的上方分别形成源极图案和漏极图案，使得所述源极图案和所述漏极图案可通过所述第一接触孔分别与所述源极接触区和所述漏极接触区电性连接；
    在对应于所述漏极接触区的上方形成暴露所述漏极接触区的第二接触孔；
    在所述层间介电层上形成像素电极，使得所述像素电极可通过所述第二接触孔与所述漏极接触区电性连接。
  10. 根据权利要求9所述的制造方法，其中，
    所述在经过所述热退火结晶处理的非晶硅层上形成层间介电层的步骤包括：
    在经过所述热退火结晶处理的非晶硅层上形成栅极绝缘层；
    在所述栅极绝缘层上形成栅极图案，且所述栅极图案位于所述源极接触区和所述漏极接触区之间且对应位于所述沟道区的上方；
    在所述栅极图案上形成层间介电层；
    所述在对应于所述源极接触区和所述漏极接触区的上方形成贯穿所述层间介电层的第一接触孔的步骤包括：
    在对应于所述源极接触区和所述漏极接触区的上方形成贯穿所述层间介电层和所述栅极绝缘层的第一接触孔。
  11. 根据权利要求9所述的制造方法，其中，所述在所述基板上依次形成非晶硅层和光阻层的步骤包括：
    在所述基板上依次形成栅极图案和栅极绝缘层；
    在所述栅极绝缘层上依次形成非晶硅层和光阻层。
  12. 根据权利要求9所述的制造方法，其中，所述掺杂处理的掺杂离子包括硼离子。
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