WO2017187856A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2017187856A1
WO2017187856A1 PCT/JP2017/011701 JP2017011701W WO2017187856A1 WO 2017187856 A1 WO2017187856 A1 WO 2017187856A1 JP 2017011701 W JP2017011701 W JP 2017011701W WO 2017187856 A1 WO2017187856 A1 WO 2017187856A1
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region
semiconductor device
drift layer
pillar
type pillar
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PCT/JP2017/011701
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English (en)
Japanese (ja)
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洪平 海老原
壮之 古橋
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三菱電機株式会社
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Priority to JP2017544974A priority Critical patent/JPWO2017187856A1/ja
Publication of WO2017187856A1 publication Critical patent/WO2017187856A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device having a structure called a super junction structure.
  • the electrical resistance of a vertical semiconductor device greatly depends on the electrical resistance of a conductive layer portion called “drift layer”.
  • the electrical resistance of the drift layer is determined by its impurity concentration. If the impurity concentration is increased, the on-resistance can be lowered. However, the impurity concentration of the drift layer cannot be increased beyond the limit determined by the breakdown voltage required for the semiconductor device. That is, there is a trade-off relationship between the electrical resistance and the breakdown voltage of the semiconductor device.
  • a structure in which a p-type pillar layer and an n-type pillar layer having a strip-shaped cross section are alternately formed on a drift layer is known.
  • Such a structure of the drift layer is called a “super junction structure”.
  • a semiconductor device having a conventional drift layer made of a single conductivity type layer maintains a high voltage by spreading a depletion layer in the vertical direction from the surface of the drift layer during reverse bias.
  • a semiconductor device having a super junction structure maintains a high voltage by spreading a depletion layer laterally from a pn junction between a p-type pillar layer and an n-type pillar layer.
  • the impurity amounts in the p-type pillar layer and the n-type pillar layer are made similar, high breakdown voltage performance is maintained even if the impurity concentration in the drift layer is very high. be able to.
  • a current can flow through the n-type pillar layer having a very high impurity concentration, a low on-resistance exceeding the material limit can be realized.
  • Patent Document 1 discloses a structure in which a termination region in which frame-shaped p-type pillar layers and n-type pillar layers surrounding four sides of an active region are alternately arranged is provided in a semiconductor device having a super junction structure. Has been.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to suppress local electric field concentration in a termination region in a semiconductor device having a super junction structure.
  • the semiconductor device includes a semiconductor substrate, a first conductivity type drift layer formed on the semiconductor substrate, a plurality of second conductivity type pillar regions formed in the drift layer, and the plurality of the plurality of pillar regions.
  • the corner portion is curved in the bending direction of the corner portion, and among the plurality of pillar regions, the pillar region provided in the termination region surrounding the active region is directed from the inner periphery side to the outer periphery side of the termination region. It extends in the direction, and is arranged radially at the corner portion of the termination region so as to spread from the inner periphery side to the outer periphery side of the termination region.
  • the semiconductor device of the present invention local electric field concentration in the termination region of the semiconductor device can be suppressed, and the resistance can be lowered while maintaining a high breakdown voltage.
  • FIG. 3 is a schematic plan view of a drift layer of the SBD according to Embodiment 1.
  • FIG. 3 is a schematic plan view in which a vicinity of a corner portion of the drift layer of the SBD according to Embodiment 1 is enlarged.
  • FIG. 2 is a schematic cross-sectional view of an SBD according to Embodiment 1.
  • FIG. 6 is a schematic plan view showing a modification of the SBD according to Embodiment 1.
  • FIG. 6 is a schematic plan view showing a modification of the SBD according to Embodiment 1.
  • FIG. 6 is a schematic plan view showing a modification of the SBD according to Embodiment 1.
  • FIG. 9 is a schematic cross-sectional view showing a modified example of the SBD according to the first embodiment.
  • FIG. 9 is a schematic cross-sectional view showing a modified example of the SBD according to the first embodiment.
  • FIG. 9 is a schematic cross-sectional view showing a modified example of the SBD according to the first embodiment.
  • FIG. 9 is a schematic cross-sectional view showing a modified example of the SBD according to the first embodiment.
  • FIG. 9 is a schematic cross-sectional view showing a modified example of the SBD according to the first embodiment.
  • FIG. 9 is a schematic cross-sectional view showing a modified example of the SBD according to the first embodiment.
  • FIG. 9 is a schematic cross-sectional view showing a modified example of the SBD according to the first embodiment.
  • 6 is a schematic cross-sectional view showing an example of a method for manufacturing the SBD according to Embodiment 1.
  • FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the SBD according to Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view showing an example of a method for manufacturing the SBD according to Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view showing an example of a method for manufacturing the SBD according to Embodiment 1.
  • FIG. It is a figure for demonstrating the problem of the termination
  • FIG. It is a figure which shows the pressure
  • FIG. 6 is a schematic plan view of a MOSFET according to a second embodiment.
  • FIG. 6 is a schematic plan view of a MOSFET according to a second embodiment.
  • FIG. 6 is a schematic plan view of a drift layer of a MOSFET according to Embodiment 2.
  • FIG. FIG. 6 is a schematic plan view in which a vicinity of a corner portion of a drift layer of a MOSFET according to a second embodiment is enlarged.
  • 6 is a schematic cross-sectional view of a MOSFET according to a second embodiment.
  • FIG. 6 is a schematic cross-sectional view of a unit cell of a MOSFET according to Embodiment 2.
  • FIG. 10 is a schematic plan view showing a modification of the MOSFET according to the second embodiment.
  • each element constituting the invention is a conceptual unit, and one element may be composed of a plurality of structures, or one element may constitute a part of the structure. Each element may have a different structure or shape as long as it exhibits the same function.
  • a vertical structure silicon carbide (SiC) semiconductor device is shown as an example of a semiconductor device having a super junction structure.
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • FIGS. 1 to 3 are schematic diagrams showing the configuration of an SBD (Schottky Barrier Diode) that is the semiconductor device 100 according to the first embodiment.
  • 1 is a plan view showing the surface structure of the drift layer 1 of the semiconductor device 100
  • FIG. 2 is an enlarged plan view of the vicinity of the corner of the drift layer 1 shown in FIG. 1
  • FIG. 3 is an A1-A2 diagram in FIG. FIG.
  • the diode to which the present invention is applied is not limited to the SBD, and the present invention can be applied to, for example, a PN junction diode or a JBS (Junction Barrier Schottky) diode.
  • the semiconductor device 100 is formed using a semiconductor substrate 4 made of n-type SiC.
  • a semiconductor substrate 4 made of n-type SiC On the semiconductor substrate 4, an n-type drift layer 1 is formed by epitaxial growth.
  • each p-type pillar region 2 has a line shape extending in a certain direction in plan view. That is, the plurality of p-type pillar regions 2 extend in parallel to each other and are provided in a stripe shape.
  • the p-type pillar region 2 provided in the active region 11 is formed to extend in the vertical direction of FIG.
  • the p-type pillar region 2 is curved toward the bending direction of the corner portion.
  • the corner portion of the active region 11 is bent in a curved manner, and the p-type pillar region 2 is curved in accordance with the curvature of the corner portion of the active region 11. That is, the curved portion of the p-type pillar region 2 is parallel to the outer periphery of the corner portion of the active region 11.
  • the p-type pillar region 2 extends in the direction from the inner periphery side to the outer periphery side of the termination region. That is, in FIG. 1, the p-type pillar region 2 extends in the vertical direction in the termination regions of the upper side and the lower side of the semiconductor device 100, and the p-type pillar region 2 is formed in the termination regions of the right side and the left side. It extends in the left-right direction. Furthermore, the p-type pillar regions 2 are arranged radially at the corners of the termination region so as to spread from the inner periphery side to the outer periphery side of the termination region. Therefore, the p-type pillar regions 2 provided in the termination region are arranged almost radially in the entire termination region.
  • the p-type pillar regions 2 provided in the termination region those extending in the same direction as the p-type pillar region 2 provided in the active region 11 are the same as the p-type pillar region 2 provided in the active region 11. It is formed to be connected. That is, in FIG. 1, the p-type pillar region 2 provided in the termination region of the upper side and the lower side of the semiconductor device 100 is connected to the p-type pillar region 2 provided in the active region 11.
  • the p-type pillar regions 2 having different extending directions are separated from each other. That is, in FIG. 1, the p-type pillar region 2 provided in the termination region of the right side and the left side of the semiconductor device 100 is not connected to the p-type pillar region 2 provided in the active region 11 (FIG. 1). Region B in 2). In addition, the p-type pillar regions 2 are also spaced apart from each other at the tip portion (region C shown in FIG. 2) of the p-type pillar region 2 curved at the corner portion of the active region 11.
  • the distance between the p-type pillar regions 2 having different extending directions is set to be equal to or less than half of the distance between the same p-type pillar regions 2 having the same extending direction, and the distance between the p-type pillar regions 2 having different extending directions is the same as the extending direction.
  • the difference from the half of the interval between the pillar regions 2 is preferably 1 ⁇ m or less. That is, the interval between the p-type pillar regions 2 having different extending directions is equal to or more than the value obtained by subtracting 1 ⁇ m from the half of the interval between the same p-type pillar regions 2 having the same extending direction. It is desirable to be within a range equal to or less than half of the value.
  • a surface electrode 5 as an anode electrode of SBD is formed on the drift layer 1 including the p-type pillar region 2 in the active region 11. Further, a back electrode 6 as a cathode electrode of SBD is formed on the lower surface of the semiconductor substrate 4.
  • the front electrode 5 is in Schottky connection with the drift layer 1 and the p-type pillar region 2, and the back electrode 6 is in ohmic connection with the semiconductor substrate 4.
  • the p-type pillar regions 2 arranged radially at the corners of the termination region may have a shape that increases in width from the inner periphery side to the outer periphery side of the termination region as shown in FIG. Thereby, it is possible to prevent the density of the p-type pillar region 2 from being lowered at the corner portion of the termination region.
  • the p-type pillar regions 2 are arranged radially, so that the interval between the p-type pillar regions 2 is widened to another p-type pillar region 2.
  • the p-type pillar region 2 having a shorter length may be provided locally. This method also prevents the density of the p-type pillar region 2 from being lowered at the corner portion of the termination region.
  • a resurf region 3 made of a p-type semiconductor region may be provided in the surface layer portion of the drift layer 1 including the p-type pillar region 2 in the termination region (FIG. 6 is a diagram). 7 shows a cross section along line A1-A2.
  • the RESURF region 3 is formed in a frame shape surrounding the surface electrode 5.
  • the p-type pillar region 2 provided in the termination region extends to the outside of the RESURF region 3. Further, it is preferable that a part of the RESURF region 3 is formed so as to overlap a part of the surface electrode 5 in plan view.
  • the RESURF region 3 is formed in contact with the end portion of the surface electrode 5.
  • the RESURF region 3 is in contact with the surface of the drift layer 1 including the p-type pillar region 2, but may be configured not to contact the surface of the drift layer 1.
  • the RESURF region 3 may be divided into a plurality of portions in the direction from the inner periphery side to the outer periphery side as shown in FIG. In other words, a plurality of frame-shaped RESURF regions 3 surrounding the active region 11 may be provided.
  • the resurf region 3 may include a plurality of regions having different impurity concentrations so that the impurity concentration of the resurf region 3 decreases from the inner peripheral side toward the outer peripheral side.
  • the RESURF region 3 is composed of three regions 31 to 33, the region 31 having the highest impurity concentration, the region 31 having the second highest impurity concentration, and the region 33 having the lowest impurity concentration. It may be arranged in this order from the circumferential side.
  • a high-concentration p region 7 having an impurity concentration higher than that of the p-type pillar region 2 is provided at a position including a portion overlapping the surface electrode 5 in the surface layer portion of the drift layer 1 including the p-type pillar region 2. Also good.
  • the high concentration p region 7 is provided in contact with the end of the surface electrode 5.
  • the high-concentration p region 7 is in contact with the surface of the drift layer 1 including the p-type pillar region 2, but may be configured not to contact the surface of the drift layer 1.
  • the high concentration p region 7 and the RESURF region 3 shown in FIGS. 7 to 9 may be combined. In that case, the high-concentration p region 7 is formed in the surface layer portion of the RESURF region 3, and the impurity concentration is higher than that of the RESURF region 3.
  • a field insulating film 8 may be formed on the drift layer 1 including the p-type pillar region 2 so as to be in contact with and surround the surface electrode 5. Further, as shown in FIG. 12, the surface electrode 5 may have a two-layer structure including the conductive films 51 and 52.
  • the bottom of the p-type pillar region 2 reaches the bottom of the drift layer 1, but the bottom of the p-type pillar region 2 may be separated from the bottom of the drift layer 1 as shown in FIG. 13. That is, the depth of the p-type pillar region 2 may be smaller than the thickness of the drift layer 1.
  • the first method is a method in which a trench is formed on the surface of the drift layer 1 and a p-type pillar region 2 is buried therein.
  • 14 and 15 are process diagrams showing a method of forming the drift layer 1 and the p-type pillar region 2 using the first method. These process diagrams are cross-sectional views of FIG. 3, that is, A1- This corresponds to the cross section along A2.
  • a semiconductor substrate 4 made of n-type SiC is prepared, and an n-type drift layer 1 is epitaxially grown on the surface of the semiconductor substrate 4 by a CVD (Chemical Vapor Deposition) method.
  • the thickness of the drift layer 1 is in the range of 2 ⁇ m to 150 ⁇ m.
  • the n-type dopant to be introduced into the drift layer 1, can be nitrogen (N) or the like is used, the impurity concentration of the drift layer 1, and in the range of 1 ⁇ 10 15 cm -3 ⁇ 1 ⁇ 10 18 cm -3 To do.
  • a silicon oxide film is formed on the surface of the drift layer 1 by a CVD method or the like, and the silicon oxide film is patterned by using a photolithography technique, so that an etching mask in which a formation region of the p-type pillar region 2 is opened is formed.
  • the drift layer 1 is selectively etched by RIE (ReactivechingIon ⁇ ⁇ Etching), and the etching mask is removed by hydrofluoric acid treatment or the like.
  • RIE ReactivechingIon ⁇ ⁇ Etching
  • a p-type semiconductor to be the p-type pillar region 2 is epitaxially grown by CVD so as to fill the trench 9 of the drift layer 1.
  • a dopant introduced into the p-type semiconductor that is, the p-type pillar region 2
  • aluminum (Al), boron (B), or the like can be used, and the impurity concentration is set within the same range as the impurity concentration of the drift layer 1.
  • the surface of the drift layer 1 is planarized by CMP (Chemical Mechanical Polishing), thereby forming a p-type pillar region 2 in the trench 9 as shown in FIG. Thereby, a super junction structure in which the linear p-type pillar region 2 is formed in the drift layer 1 is obtained.
  • CMP Chemical Mechanical Polishing
  • the second method of forming the super junction structure is a method of repeating the epitaxial growth of the drift layer 1 and the ion implantation for forming the p-type pillar region 2.
  • FIG. 16 is a process diagram showing a method of forming the drift layer 1 and the p-type pillar region 2 using the second method. This process diagram is also taken along the cross section of FIG. 3, that is, along A1-A2 of FIG. Corresponds to the cross section.
  • a semiconductor substrate 4 made of n-type SiC is prepared, and an n-type drift layer 1 having a thickness of 0.5 to 2 ⁇ m is epitaxially grown on the surface of the semiconductor substrate 4 by a CVD method.
  • nitrogen (N) or the like can be used as the n-type dopant introduced into the drift layer 1, and the impurity concentration of the drift layer 1 is 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3.
  • a photoresist 10 in which the formation region of the p-type pillar region 2 is opened is formed by photolithography, and ion implantation using the photoresist 10 as a mask is performed in the drift layer 1. Then, the p-type pillar region 2 is formed.
  • the dopant introduced into the p-type pillar region 2 Al, B, or the like can be used, and the impurity concentration is in the same range as the impurity concentration of the drift layer 1.
  • the photoresist 10 is removed with an organic solvent, a super junction structure including a thin drift layer 1 and a p-type pillar region 2 is formed.
  • the resurf region 3 shown in FIGS. 6 to 9, the high-concentration p region 7 shown in FIG. 10, or the like may be formed by repeating mask formation and ion implantation using a photolithography technique. .
  • Al, B, or the like can also be used as ion species implanted into the RESURF region 3 and the high concentration p region 7.
  • the impurity concentration of the RESURF region 3 and the high concentration p region 7 is set higher than the impurity concentration of the drift layer 1.
  • the impurity concentration of the high concentration p region 7 is set higher than the impurity concentration of the RESURF region 3.
  • annealing is performed for 30 seconds to 1 hour in an inert gas atmosphere (1300 ° C. to 1900 ° C.) such as argon (Ar) gas using a heat treatment apparatus.
  • an inert gas atmosphere (1300 ° C. to 1900 ° C.) such as argon (Ar) gas
  • a heat treatment apparatus By this annealing, the ions implanted in the above process are electrically activated.
  • a silicon oxide film is formed on the surface of the drift layer 1 including the p-type pillar region 2 by a CVD method or the like, and the silicon oxide film is patterned by selective etching using a photolithography technique.
  • the field insulating film 8 shown in FIG. 12 may be formed.
  • the surface electrode 5 is formed on the upper surface of the drift layer 1 including the p-type pillar region 2 and the back electrode 6 is formed on the lower surface of the semiconductor substrate 4 by sputtering or vapor deposition, as shown in FIG.
  • the semiconductor device 100 having the configuration is completed.
  • the material of the front surface electrode 5 one or more of metals such as titanium (Ti), molybdenum (Mo), tungsten (W), and Al can be used.
  • the material of the back surface electrode 6 for example, nickel ( One or more of metals such as Ni) and gold (Au) can be used.
  • the semiconductor device 100 having the super junction structure almost no current flows in the p-type pillar region 2 having a large Schottky barrier with the surface electrode 5, but the drift layer 1 has a very high impurity concentration and a low electrical resistance.
  • the power consumption can be greatly reduced compared to the one without a super junction structure.
  • the depletion layer extends in the drift layer 1 and the p-type pillar region 2, thereby interrupting the current between the front electrode 5 and the back electrode 6.
  • a depletion layer extends in the lateral direction from the pn junction between the drift layer 1 and the p-type pillar region 2, so that a sufficient breakdown voltage can be secured even if the impurity concentration of the drift layer 1 is very large. it can.
  • the breakdown voltage in the thickness direction of the drift layer 1 can be increased also in the termination region.
  • the configuration of the termination region is p in the direction from the inner peripheral side to the outer peripheral side as shown in FIG.
  • the type pillar regions 2 and the drift layers 1 are alternately arranged.
  • the p-type pillar region 2 of the termination region is shaped to extend from the inner peripheral side to the outer peripheral side of the termination region.
  • a depletion layer widely spreads from the outer peripheral side to the inner peripheral side in the p-type pillar region 2, and a potential gradient is generated in the region where the depletion layer has spread. Lateral electric field concentration is reduced. That is, the problem shown in FIG. 17 can be prevented from occurring, and the semiconductor device 100 with high withstand voltage performance can be obtained.
  • the balance between the density of the drift layer 1 and the density of the p-type pillar region 2 is lost.
  • the depletion layer does not effectively spread from the pn junction to both the drift layer 1 and the p-type pillar region 2, and the breakdown voltage may be reduced.
  • FIG. 18 is a plan view of a region where the extending direction of the p-type pillar region 2 transitions, and the simulation shows that the region shown in FIG. 18 is a unit, the width Wp of the p-type pillar region 2 and the p-type extending in the same direction.
  • the interval Wn between the pillar regions 2 and the interval x between the p-type pillar regions 2 extending in different directions were used as parameters.
  • the thickness of the drift layer 1 and the depth of the p-type pillar region 2 are both 10 ⁇ m.
  • FIG. 19 shows the simulation results when the impurity concentrations of the drift layer 1 and the p-type pillar region 2 are both 3 ⁇ 10 16 cm ⁇ 3 and Wn and Wp are both 2 ⁇ m. ing. As can be seen from FIG. 19, a high breakdown voltage is obtained when x is 1 ⁇ m or less.
  • FIG. 20 shows simulation results when the impurity concentration of the drift layer 1 is 3 ⁇ 10 16 cm ⁇ 3 , the impurity concentration of the p-type pillar region 2 is 9 ⁇ 10 16 cm ⁇ 3 , Wn is 6 ⁇ m, and Wp is 2 ⁇ m. is there.
  • high breakdown voltage is obtained in the range of x from 2 ⁇ m to 3 ⁇ m, which is half of Wn.
  • the interval between the p-type pillar regions 2 having different extending directions is a value obtained by subtracting 1 ⁇ m from the interval between the p-type pillar regions 2 having the same extending direction. To the same value as the half of the interval between the same p-type pillar regions 2.
  • the density of the p-type pillar regions 2 decreases on the outer peripheral side of the termination region, and the depletion layer extends from the pn junction to the drift layer 1. May become difficult to spread, and the pressure resistance may decrease.
  • the width of the radially arranged p-type pillar regions 2 is widened on the outer peripheral side, or between the radially arranged p-type pillar regions 2 as shown in FIG. The problem can be avoided by providing the p-type pillar region 2a so that the density of the p-type pillar region 2 does not decrease on the outer peripheral side.
  • the p-type pillar region 2 disposed in the termination region is preferably extended to the outside of the RESURF region 3.
  • the region where the RESURF region 3 and the p-type pillar region 2 overlap is the p-type region having the highest impurity concentration, and the electric field concentration is most likely to occur at the end thereof.
  • the RESURF region 3 When the RESURF region 3 is provided in the termination region, there is a possibility that the electric field concentrates on the end portion of the depletion layer spreading inside the RESURF region 3. As shown in FIG. 8, when the RESURF region 3 is divided into a plurality of portions, the portions where the electric field concentrates can be dispersed, and a higher breakdown voltage can be obtained.
  • the withstand voltage of the termination region where the RESURF region 3 is provided depends on how much the depletion layer spreads inside the RESURF region 3. As shown in FIG. 9, when the impurity concentration of the RESURF region 3 is decreased from the inner peripheral side toward the outer peripheral side, the probability that an appropriate impurity concentration of the RESURF region 3 is obtained in order to obtain a withstand voltage is increased and higher. A breakdown voltage can be obtained.
  • the number of response carriers in the high concentration p region 7 can be increased even in a transient state where a high voltage is applied to the semiconductor device 100. Sufficiently maintained, local electric field concentration at the end of the surface electrode 5 can be suppressed, and higher breakdown voltage can be obtained.
  • the drift layer 1 is compared with the case where the field insulating film 8 is not formed.
  • the amount of fixed charge introduced to the surface can be reduced, and a high breakdown voltage semiconductor device can be obtained without interfering with the role of the p-type pillar 2 and the breakdown voltage holding structure 3.
  • Embodiment 1 shows an example in which the present invention is applied to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the present invention can be applied to JFET (Junction FET), IGBT (Insulated Gate Bipolar Transistor), and the like in addition to MOSFET.
  • FIG. 21 to 25 are schematic diagrams showing the configuration of a MOSFET that is the semiconductor device 200 according to the second embodiment.
  • FIG. 21 is a plan view of the semiconductor device 200
  • FIG. 22 is a plan view showing the surface structure of the drift layer 1.
  • 23 is an enlarged plan view of the vicinity of the corner portion of the drift layer 1 shown in FIG. 22, and
  • FIG. 24 is a cross-sectional view taken along A1-A2 of FIG.
  • FIG. 25 is a cross-sectional view showing the configuration of a plurality of MOSFET unit cells (hereinafter referred to as “MOSFET cells”) provided in the semiconductor device 200.
  • MOSFET cells MOSFET unit cells
  • a surface electrode 5 functioning as a source pad of a MOSFET, a gate pad 15a formed away from the surface electrode 5, and a surface electrode connected to the gate pad 15a. 5 is formed so as to surround 5.
  • the drift layer 1 of the semiconductor device 200 has a super junction structure in which a plurality of p-type pillar regions 2 are arranged in the same manner as in the first embodiment. That is, in the active region 11 where the MOSFET is formed, each of the p-type pillar regions 2 has a line shape extending in a certain direction in plan view, but at the corner portion of the active region 11, the p-type pillar region 2 is Curved toward the bending direction of the corner. Further, in the termination region, the p-type pillar region 2 extends in a direction from the inner peripheral side to the outer peripheral side of the termination region. In particular, in the corner portion of the termination region, the p-type pillar regions 2 are radially arranged so as to spread from the inner peripheral side to the outer peripheral side of the termination region.
  • the active region 11 of the semiconductor device 200 is a cell region in which a plurality of MOSFET unit cells are formed. Further, on the outer peripheral portion of the active region 11, a p-type outer peripheral well region 12 a is formed in the surface layer portion of the drift layer 1 including the p-type pillar region 2. The outer peripheral well region 12a has a frame shape surrounding the active region 11 while being in contact with the p-type pillar region 2 provided in the termination region.
  • the MOSFET cell includes a p-type well region 12 formed in the surface layer portion of the drift layer 1 including the p-type pillar region 2.
  • the p-type well region 12 is formed with a width wider than that of the p-type pillar region 2 so as to reach the drift layer 1 on both sides of the p-type pillar region 2.
  • an n-type source region 13 is formed in the surface layer portion of the p-type well region 12. A portion sandwiched between the n-type source region 13 and the drift layer 1 in the surface layer portion of the p-type well region 12 becomes a channel region of the MOSFET.
  • a high-concentration p region 7 is further formed, and the n-type source region 13 is formed in the high-concentration p region 7 so that channel regions are formed on both sides of the p-type well region 12. It is formed so as to sandwich.
  • a gate insulating film 14 is formed so as to straddle the surfaces of the drift layer 1, the p-type well region 12, and the n-type source region 13, and a gate electrode 15 is formed thereon. That is, the gate electrode 15 extends on the channel region via the gate insulating film 14.
  • An interlayer insulating film 16 is formed on the gate electrode 15.
  • the surface electrode 5 shown in FIG. 21 is formed on the interlayer insulating film 16, and the surface electrode 5 and the gate electrode 15 are insulated by the interlayer insulating film 16. Further, contact holes reaching the n-type source region 13 and the high-concentration p region 7 are formed in the interlayer insulating film 16, and the surface electrode 5 is connected to the n-type source region 13 and the high-concentration p region through the contact holes. 7 (the surface electrode 5 and the high concentration p region 7 are in ohmic contact).
  • the surface electrode 5 functions as a source electrode of the MOSFET by being connected to the n-type source region 13 and is electrically connected to the p-type well region 12 through the high-concentration p region 7.
  • the back electrode 6 provided on the lower surface of the semiconductor substrate 4 functions as a drain electrode of the MOSFET.
  • the high-concentration p region 7 is also formed in the surface layer portion of the peripheral well region 12a, and the surface electrode 5 passes through the contact hole formed in the interlayer insulating film 16 and the high concentration of the peripheral well region 12a. It is also connected to the p region 7. That is, the surface electrode 5 is also electrically connected to the outer peripheral well region 12 a through the high concentration p region 7.
  • the gate insulating film 14 and the gate electrode 15 include a frame-like pattern that extends up to the outer peripheral well region 12a and surrounds the active region 11 together with the outer peripheral well region 12a. That is, the gate electrode 15 of each MOSFET cell is connected at the outer periphery of the active region 11. 21 is connected to the gate electrode 15 through a contact hole formed in the interlayer insulating film 16 in the outer peripheral portion of the active region 11.
  • the gate electrode 15 of each MOSFET cell may be connected inside the active region 11.
  • the gate wiring 15 b may be extended above the active region 11 so that the gate wiring 15 b and the gate electrode 15 are connected inside the active region 11.
  • a field insulating film 8 is formed on the drift layer 1 including the p-type pillar region 2.
  • the gate electrode 15 and the interlayer insulating film 16 may extend to the field insulating film 8.
  • the peripheral well region 12a is a portion of the p-type pillar region 2 curved at the corner portion of the active region 11 in plan view as shown in FIG. You may form so that it may be included.
  • a p-type RESURF region 3 as shown in FIGS. 6 and 7 may be provided in the termination region.
  • the RESURF region 3 is provided so as to surround the outer peripheral well region 12a while being in contact with the outer peripheral well region 12a.
  • the configuration of the RESURF region 3 described in the first embodiment with reference to FIGS. 8 and 9 is also applicable.
  • the configuration of the p-type pillar region 2 described with reference to FIG. 13 (configuration in which the bottom of the p-type pillar region 2 does not reach the bottom of the drift layer 1) is also applicable.
  • an n-type drift layer 1 is formed on the surface of a semiconductor substrate 4 made of n-type SiC, and a plurality of p-type pillar regions 2 are formed in the drift layer 1.
  • a super junction structure is obtained.
  • the thickness of the drift layer 1 is in the range of 2 ⁇ m to 150 ⁇ m
  • the width of the p-type pillar region 2 is in the range of 1 ⁇ m to 5 ⁇ m
  • the interval between the p-type pillar regions 2 is 1 ⁇ m to 15 ⁇ m.
  • the impurity concentration of the drift layer 1 and the p-type pillar region 2 is in the range of 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the width of the p-type pillar region 2 is set to the p-type in order to arrange the MOSFET cells at a high density. It is desirable to make it smaller than the interval between the pillar regions 2. In that case, the impurity concentration of the p-type pillar region 2 is preferably higher than that of the drift layer 1 so that the depletion layer extends to the drift layer 1 and the p-type pillar region 2.
  • a p-type well region 12, an outer peripheral well region 12a, a high-concentration p region 7 and an n-type source region 13 are formed on the surface of the drift layer 1.
  • a photolithography technique by repeating mask formation and ion implantation using a photolithography technique, a p-type well region 12, an outer peripheral well region 12a, a high-concentration p region 7 and an n-type source region 13 are formed on the surface of the drift layer 1. Form each one.
  • the RESURF region 3 may be formed by a similar method.
  • the p-type well region 12 and the peripheral well region 12a may be formed simultaneously in the same ion implantation process.
  • N or the like can be used as an ion species for forming the n-type semiconductor region.
  • the ion species for forming the p-type semiconductor region Al, B, or the like can be used.
  • the impurity concentration of the p-type well region 12 and the peripheral well region 12a is set in the range of 1.0 ⁇ 10 18 cm ⁇ 3 to 1.0 ⁇ 10 20 cm ⁇ 3 .
  • the impurity concentration of the high-concentration p region 7 and the n-type source region 13 is set higher than the impurity concentration of the p-type well region 12 and the peripheral well region 12a.
  • annealing is performed for 30 seconds to 1 hour in an inert gas atmosphere (1300 ° C. to 1900 ° C.) such as argon (Ar) gas using a heat treatment apparatus.
  • an inert gas atmosphere (1300 ° C. to 1900 ° C.) such as argon (Ar) gas
  • a heat treatment apparatus By this annealing, the ions implanted in the above process are electrically activated.
  • a silicon oxide film is formed on the surface of the drift layer 1 including the p-type pillar region 2 by a CVD method or the like, and the silicon oxide film is patterned by selective etching using a photolithography technique. 8 is formed.
  • the surfaces of the drift layer 1 and the p-type pillar region 2 that are not covered with the field insulating film 8 are thermally oxidized to form a gate insulating film 14 made of a silicon oxide film.
  • a polycrystalline silicon film having conductivity is formed on the gate insulating film 14 by low pressure CVD, and the gate electrode 15 is formed by patterning the film.
  • an interlayer insulating film 16 is formed by a low pressure CVD method. Then, the interlayer insulating film 16 is selectively etched to form various contact holes. Specifically, contact holes reaching the n-type source region 13 and the high-concentration p region 7 of the MOSFET cell are formed in the active region 11, and the high-concentration p region of the p-type well region 12 is formed in the outer peripheral portion of the active region 11. A contact hole reaching 7 and a contact hole reaching the gate electrode 15 are formed.
  • the surface electrode 5, the gate pad 15 a and the gate wiring 15 b are formed on the upper surface of the drift layer 1 and the back electrode 6 is formed on the lower surface of the semiconductor substrate 4 by sputtering or vapor deposition.
  • the semiconductor device 200 having the configuration shown in FIG. 24 is completed.
  • the material for the front electrode 5, the gate pad 15a, and the gate wiring 15b one or more of metals such as Ni, Ti, and Al can be used.
  • the material for the back electrode 6, for example, Ni, Au, and the like can be used.
  • One or more of the metals can be used.
  • silicide is formed between the front electrode 5 and the back electrode 6 and the silicon carbide layer by reacting the front electrode 5 and the back electrode 6 with the silicon carbide layer in contact therewith by heat treatment.
  • an inversion channel is formed in the channel region, and a path through which electrons as carriers flow between the n-type source region 13 and the drift layer 1 is formed. For this reason, when a voltage higher than that of the front electrode 5 is applied to the back electrode 6, a current flows through the drift layer 1. At this time, the current flowing between the front electrode 5 and the back electrode 6 is called “on current”, the voltage applied between the front electrode 5 and the back electrode 6 is called “on voltage”, and the on voltage is divided by the density of the on current. This value is called “on resistance”. The on-resistance is equal to the total resistance of the path through which the electrons flow.
  • the conduction loss consumed when the MOSFET is energized is the product of the on-resistance and the on-current square, it is preferable that the on-resistance is low.
  • the on-current flows only in the active region 11 where the channel exists, and does not flow in the termination region on the outer periphery of the active region 11.
  • the electrical resistance of the drift layer 1 having a very large impurity concentration is small, the on-resistance is very small as compared with those not having the super junction structure, and the power consumption is very low. Can be small.
  • the depletion layer extends in the lateral direction from the pn junction between the drift layer 1 and the p-type pillar region 2 in the active region 11, so that the impurity concentration of the drift layer 1 is very high. Even if it is large, a sufficient breakdown voltage can be secured. Furthermore, since the decrease in breakdown voltage is small even if the spacing between MOSFET cells is widened, the resistance can be reduced by increasing the path of electrons.
  • the outer peripheral well region 12 a provided on the outer periphery of the active region 11 is electrically connected to the surface electrode 5. Therefore, in the off state of the semiconductor device 200, a high electric field is prevented from being applied to the gate insulating film 14 and the field insulating film 8 between the outer peripheral well region 12a and the gate electrode 15 thereon.
  • the p-type pillar region 2 in the termination region acts in the same manner as the reverse bias state in the semiconductor device 100 of the first embodiment. That is, in the p-type pillar region 2 of the termination region in the off state, a depletion layer spreads widely from the outer peripheral side toward the inner peripheral side, and a potential gradient is generated in the region where the depletion layer has spread. Electric field concentration is reduced. By forming the p-type pillar region 2 extending from the inner peripheral side to the outer peripheral side of the termination region in the termination region, lateral electric field concentration is alleviated in the entire region of the termination region. Thereby, the pressure resistance performance of the semiconductor device 200 is improved.
  • the material of the semiconductor substrate 4 is SiC, but the material of the semiconductor substrate 4 may be silicon (Si) or another wide band gap semiconductor.
  • SiC silicon
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • the first conductivity type may be p-type and the second conductivity type may be n-type.
  • 1 drift layer 2 p-type pillar region, 2a local p-type pillar region, 3 RESURF region, 4 semiconductor substrate, 5 surface electrode, 6 back electrode, 7 high concentration p region, 8 field insulating film, 9 trench, 10 Photoresist, 11 active region, 12 p-type well region, 12a outer peripheral well region, 13 n-type source region, 14 gate insulating film, 15 gate electrode, 15a gate pad, 15b gate wiring, 16 interlayer insulating film, 100, 200 semiconductor apparatus.

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Abstract

La présente invention concerne un dispositif à semi-conducteur (100) qui est pourvu d'une couche de dérive de type n (1) formée sur un substrat semi-conducteur (4), d'une pluralité de régions de pilier de type p (2) formées à l'intérieur de la couche de dérive (1), et d'une électrode de surface (5) formée sur la couche de dérive (1) comprenant les régions de pilier de type p (2). Parmi la pluralité de régions de pilier de type p (2), les régions de pilier de type p (2) disposées dans une région active (11) s'étendent dans une direction fixe et, dans les parties de coin de la région active (11), sont incurvées dans la direction de courbure des parties de coin. En outre, parmi la pluralité de régions de pilier de type p (2), les régions de pilier de type p (2) disposées dans des régions terminales entourant la région active (11) s'étendent dans une direction orientée vers l'extérieur depuis le côté périphérique interne de la région terminale et, dans les parties de coin de la région terminale, sont disposées radialement de façon à s'étendre du côté périphérique interne au côté périphérique externe de la région terminale.
PCT/JP2017/011701 2016-04-27 2017-03-23 Dispositif à semi-conducteur WO2017187856A1 (fr)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10854762B2 (en) 2016-04-21 2020-12-01 Mitsubishi Electric Corporation Semiconductor device
CN114072927A (zh) * 2019-07-16 2022-02-18 三菱电机株式会社 半导体装置、电力变换装置以及半导体装置的制造方法
CN115440796A (zh) * 2022-10-24 2022-12-06 上海功成半导体科技有限公司 一种超结器件终端保护的版图结构
CN115602709A (zh) * 2022-10-24 2023-01-13 上海功成半导体科技有限公司（Cn） 一种超结器件终端保护的版图结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003258252A (ja) * 2001-12-27 2003-09-12 Toshiba Corp 半導体装置及びその製造方法
US20130292761A1 (en) * 2012-05-04 2013-11-07 Great Power Semiconductor Corp. Trench power mosfet and fabrication method thereof
US20140027819A1 (en) * 2011-08-25 2014-01-30 Alpha And Omega Semiconductor Incorporated Corner layout for high voltage semiconductor devices
JP2014192433A (ja) * 2013-03-28 2014-10-06 Sanken Electric Co Ltd 半導体装置
JP2015504610A (ja) * 2011-12-01 2015-02-12 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツングＲｏｂｅｒｔ Ｂｏｓｃｈ Ｇｍｂｈ 高電圧トレンチ接合ショットキーバリアダイオード

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6683363B2 (en) * 2001-07-03 2004-01-27 Fairchild Semiconductor Corporation Trench structure for semiconductor devices
WO2005065385A2 (fr) * 2003-12-30 2005-07-21 Fairchild Semiconductor Corporation Dispositifs d'energie a semi-conducteurs et procedes de fabrication associes
JP2007116190A (ja) * 2006-12-12 2007-05-10 Toshiba Corp 半導体素子およびその製造方法
JP6242633B2 (ja) * 2013-09-03 2017-12-06 株式会社東芝 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003258252A (ja) * 2001-12-27 2003-09-12 Toshiba Corp 半導体装置及びその製造方法
US20140027819A1 (en) * 2011-08-25 2014-01-30 Alpha And Omega Semiconductor Incorporated Corner layout for high voltage semiconductor devices
JP2015504610A (ja) * 2011-12-01 2015-02-12 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツングＲｏｂｅｒｔ Ｂｏｓｃｈ Ｇｍｂｈ 高電圧トレンチ接合ショットキーバリアダイオード
US20130292761A1 (en) * 2012-05-04 2013-11-07 Great Power Semiconductor Corp. Trench power mosfet and fabrication method thereof
JP2014192433A (ja) * 2013-03-28 2014-10-06 Sanken Electric Co Ltd 半導体装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10854762B2 (en) 2016-04-21 2020-12-01 Mitsubishi Electric Corporation Semiconductor device
CN114072927A (zh) * 2019-07-16 2022-02-18 三菱电机株式会社 半导体装置、电力变换装置以及半导体装置的制造方法
CN115440796A (zh) * 2022-10-24 2022-12-06 上海功成半导体科技有限公司 一种超结器件终端保护的版图结构
CN115602709A (zh) * 2022-10-24 2023-01-13 上海功成半导体科技有限公司（Cn） 一种超结器件终端保护的版图结构
CN115440796B (zh) * 2022-10-24 2023-08-15 上海功成半导体科技有限公司 一种超结器件终端保护的版图结构
CN115602709B (zh) * 2022-10-24 2023-12-19 上海功成半导体科技有限公司 一种超结器件终端保护的版图结构

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