WO2017186094A1 - 薄膜晶体管及制备方法、阵列基板及制备方法、显示面板、显示装置 - Google Patents
薄膜晶体管及制备方法、阵列基板及制备方法、显示面板、显示装置 Download PDFInfo
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- WO2017186094A1 WO2017186094A1 PCT/CN2017/081858 CN2017081858W WO2017186094A1 WO 2017186094 A1 WO2017186094 A1 WO 2017186094A1 CN 2017081858 W CN2017081858 W CN 2017081858W WO 2017186094 A1 WO2017186094 A1 WO 2017186094A1
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- film transistor
- thin film
- substrate
- active layer
- drain
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- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/772—Field effect transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
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- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor and a method for fabricating the same, an array substrate and a method for fabricating the same, a display panel, and a display device.
- a metal oxide thin film transistor which is relatively mature is a metal oxide thin film transistor which uses Indium Gallium Zinc Oxide (IGZO) as an active layer.
- IGZO Indium Gallium Zinc Oxide
- industrialized metal oxide thin film transistors are mainly prepared by physical vapor deposition (PVD), which requires expensive vacuum equipment and is costly.
- PVD physical vapor deposition
- the extremely low utilization of materials also greatly increases production costs.
- the solution method can realize processes such as spin coating, dripping, printing, and roll-to-roll, which is easy to operate, has high material utilization rate, lower cost, and has wider application prospects.
- the solution method inevitably introduces relatively more impurities, the mobility of the metal oxide thin film transistor is relatively low.
- the mobility is less than 1 cm 2 /Vs.
- Embodiments of the present disclosure provide a thin film transistor and a preparation method thereof, an array substrate and a preparation method thereof, a display panel, and a display device, and a high mobility metal oxide thin film transistor can be prepared by a solution method.
- a method of fabricating a thin film transistor comprising: forming a gate electrode, a gate insulating layer, an active layer, a source and a drain on a substrate; forming the active layer by a solution method,
- the material of the active layer is a zirconia indium semiconductor material.
- the percentage of zirconium atoms and the total number of zirconium indium atoms in the zirconia indium semiconductor material is between 0.1-20%.
- the step of preparing the active layer by a solution method comprises: forming the active layer by a method of inkjet printing.
- the solution used for inkjet printing is a mixed solution of In(NO 3 ) 3 ⁇ xH 2 O and ZrOCl 2 ⁇ xH 2 O dissolved in ethylene glycol monomethyl ether and ethylene glycol.
- the method further comprises: forming an etch barrier layer.
- the substrate is a hard substrate or a flexible substrate.
- a method of fabricating an array substrate includes forming a thin film transistor and a first electrode electrically coupled to a drain of the thin film transistor; wherein the thin film transistor is formed by the fabrication method of the first aspect.
- the first electrode is an anode
- the preparation method further includes: forming a cathode and an organic material functional layer between the anode and the cathode; or the first electrode is a pixel electrode.
- a third aspect provides a thin film transistor including a substrate, a gate disposed on the substrate, a gate insulating layer, an active layer, a source and a drain; and the active layer is made of zirconia indium semiconductors.
- the percentage of zirconium atoms and the total number of zirconium indium atoms in the zirconia indium semiconductor material is between 0.1% and 20%.
- the substrate is a hard substrate or a flexible substrate.
- an array substrate comprising the thin film transistor of the third aspect, further comprising a first electrode electrically coupled to a drain of the thin film transistor.
- a display panel comprising the array substrate of the fourth aspect.
- a display device comprising the display panel of the fifth aspect.
- Embodiments of the present disclosure provide a thin film transistor and a preparation method thereof, an array substrate and a preparation method thereof, a display panel, and a display device. Since zirconium indium oxide is used as a material of an active layer, zirconium in the zirconia indium has an oxygen vacancy inhibition. The effect is to improve the stability. At the same time, since the zirconia indium does not contain zinc, the sensitivity to water and oxygen can be reduced. In addition, zirconium can also replace the indium to generate a donor level, so that the carrier concentration can be maintained.
- the present disclosure can prepare a thin film transistor having high mobility by avoiding the problem that the carrier concentration is drastically lowered due to the impurity introduced by the solution method during film preparation, resulting in low mobility.
- the metal oxide thin film transistor provided by the embodiment of the present disclosure has the characteristics of low preparation cost, since the active layer is prepared by a solution method.
- FIG. 1 is a schematic structural view 1 of a thin film transistor according to an embodiment of the present disclosure
- FIG. 2 is a schematic structural view 2 of a thin film transistor according to an embodiment of the present disclosure
- FIG. 3 is a schematic structural view 3 of a thin film transistor according to an embodiment of the present disclosure.
- FIG. 4( a ) is a fourth structural diagram of a thin film transistor according to an embodiment of the present disclosure.
- FIG. 4(b) is a schematic structural view 5 of a thin film transistor according to an embodiment of the present disclosure
- FIG. 5( a ) is a schematic diagram 1 of a process for preparing a thin film transistor according to an embodiment of the present disclosure
- FIG. 5(b) is a second schematic diagram of a process for preparing a thin film transistor according to an embodiment of the present disclosure
- FIG. 7 is a second transfer characteristic curve of a thin film transistor according to an embodiment of the present disclosure.
- FIG. 8 is a schematic structural diagram 1 of an array substrate according to an embodiment of the present disclosure.
- FIG. 9 is a second schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
- FIG. 10 is a schematic structural diagram 3 of an array substrate according to an embodiment of the present disclosure.
- FIG. 11 is a schematic structural diagram 4 of an array substrate according to an embodiment of the present disclosure.
- Embodiments of the present disclosure provide a method of fabricating a thin film transistor, as shown in FIGS. 1 and 2, including forming a gate electrode 11, a gate insulating layer 12, an active layer 13, a source 14 and a drain on a substrate 10. 15; wherein the active layer 13 is formed by a solution method, and the material of the active layer 13 is a zirconia indium semiconductor material.
- Solution methods include spin coating, dispensing, printing, etc.
- Printing can include ink jet printing, transfer printing.
- the gate electrode 11 may be composed of a single layer or two or more layers.
- the material may be a conductive material such as a metal, an alloy, a conductive metal oxide, a doped silicon, a conductive polymer, or the like.
- the thickness of the gate electrode 11 may be between 100 nm and 2000 nm.
- the gate insulating layer 12 may be composed of a single layer or two or more layers.
- the material thereof may be, for example, silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxide oxide, hafnium oxide, titanium oxide, hafnium oxide, hafnium oxide, zirconium oxide, polymer insulation. Materials, photoresists, etc.
- two or more films composed of any combination of the above materials may be stacked.
- the thickness of the gate insulating layer 12 may be between 50 nm and 500 nm.
- the source 14 and the drain 15 may be composed of a single layer or two or more layers.
- the material may be a conductive material such as a metal, an alloy, a conductive metal oxide, a doped silicon, a conductive polymer, or the like.
- a conductive material such as a metal, an alloy, a conductive metal oxide, a doped silicon, a conductive polymer, or the like.
- two or more films composed of any combination of the above materials may be stacked.
- the thickness of the source 14 and the drain 15 may be between 100 nm and 2000 nm.
- the thickness of the active layer may be between 10 nm and 100 nm.
- the thin film transistor may be a bottom gate type, a top gate type, or a double gate type.
- the order in which the gate electrode 11, the source electrode 14 and the drain electrode 15 are formed is also different depending on the type of the thin film transistor.
- Embodiments of the present disclosure provide a method for fabricating a thin film transistor. Since zirconium indium oxide is used as a material of the active layer 13, and zirconium in the zirconia indium has an effect of suppressing oxygen vacancies, stability can be improved, and at the same time, Zirconia indium does not contain zinc, so it can reduce the sensitivity to water and oxygen. In addition, zirconium can also replace the indium to produce the donor level, so the carrier concentration can be maintained, thus avoiding the use of the solution method in the film preparation process. The problem that the carrier concentration caused by the introduced impurities sharply drops to cause a low mobility, the present disclosure can produce a thin film transistor having a high mobility.
- the thin film transistor provided by the embodiment of the present disclosure has the characteristics of low preparation cost, since the active layer 13 is prepared by a solution method.
- the percentage of zirconium atoms and the total number of zirconium indium atoms [Zr/(In+Zr)] in the zirconia indium semiconductor material is between 0.1% and 20%, more preferably from 1% to 16%.
- the active layer 13 is optionally formed by a method of inkjet printing.
- the inkjet printed material needs to be dissolved in a solvent to form a solution to be printed, and then the solvent in the solution is evaporated by an evaporation process to form the active layer 13.
- the evaporation process can be carried out at a temperature of 150 ° C to 300 ° C, and the duration can be controlled from 0.5 h to 3 h.
- the solution used for inkjet printing is In(NO 3 ) 3 ⁇ xH 2 O (indium nitrate) and ZrOCl 2 ⁇ xH 2 O (zirconium oxychloride) are dissolved in ethylene glycol monomethyl ether and ethylene glycol. mixture.
- the source 14 and the drain are formed.
- the method further includes forming an etch stop layer 16.
- the etch barrier layer 16 may have a thickness of 50 to 200 nm.
- the etch barrier layer 16 is formed.
- the zirconia indium is further prevented from being exposed to air to react with oxygen or water, and on the other hand, the process of subsequently forming the source 14 and the drain 15 can be avoided. The effect on the active layer 13 in the middle.
- the preparation method further includes: forming a buffer layer 17 on the surface of the substrate 10 .
- a buffer layer 17 on the surface of the substrate 10 .
- the buffer layer 17 may have a thickness of 100 nm to 300 nm.
- Embodiment 1 provides a method for preparing a thin film transistor as shown in FIG. 4(b). As shown in FIG. 5(a), the method includes the following steps:
- a buffer layer 17 of SiO 2 (silicon dioxide) is deposited by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method to a thickness of 200 nm.
- the substrate 10 may be an alkali-free glass.
- a three-layer metal film of Mo (molybdenum)/Al (aluminum)/Mo is sequentially deposited by a PVD method to a thickness of 25 nm/100 nm/25 nm, respectively, and processed by a photolithography process to form a gate electrode 11.
- SiN x silicon nitride
- SiO 2 are sequentially deposited by PECVD to have a thickness of 300 nm and 30 nm, respectively, to form a gate insulating layer 12.
- an active layer 13 of a zirconia indium semiconductor material is prepared by an inkjet printing method, and has a thickness of 20 nm.
- the solution used for inkjet printing is a mixed solution of In(NO 3 ) 3 ⁇ xH 2 O and ZrOCl 2 ⁇ xH 2 O dissolved in ethylene glycol monomethyl ether and ethylene glycol.
- the percentage of zirconium atoms and the total number of zirconium indium atoms [Zr/(In+Zr)] in the zirconia indium semiconductor material may be 1%, 6%, 11%, or 16%.
- the source 14 and the drain 15 of 300 nm are prepared by vacuum evaporation, and the material of the source 14 and the drain 15 is Al.
- the source 14 and the drain 15 may be formed by a printing method.
- the transfer characteristic curve of the metal oxide thin film transistor prepared for S10-S15 in air that is, the relationship between the drain current and the gate voltage.
- the test condition is that the source voltage (V S ) is 0V, the drain voltage (V D ) is constant at 20V, and the gate voltage (V G ) is first scanned from -20V to 20V, and then retraced from 20V to -20V. , test the drain current (I D ). It can be seen that the thin film transistor in which zirconia indium prepared by the solution method is used as an active layer has excellent performance, the mobility is greatly improved, and the drain current is also low.
- the following table shows the parameters of the metal oxide thin film transistor fabricated by S10-S15. It can be seen that when the Zr content is small, the electron surplus caused by Zr substitution of In dominates. At this time, the mobility is high and the off-state current is large. When the Zr content reaches 11%, the off-state current is significantly reduced. Although the mobility is also reduced, the mobility requirement is still met, and the hysteresis effect between the sweep and the retrace is also reduced. The role of Zr in suppressing oxygen vacancies begins to dominate.
- Embodiment 2 provides a method for preparing a thin film transistor as shown in FIG. 1 , as shown in FIG. 5( b ), including the following steps:
- an Al (aluminum) metal film is deposited by a PVD method to a thickness of 300 nm, and processed by a photolithography process to form a gate electrode 11.
- the substrate 10 may be a PEN (polyethylene naphthalate) flexible substrate.
- a gate insulating layer 12 of alumina is prepared by anodization to a thickness of 200 nm.
- the active layer 13 of the material has a thickness of 20 nm.
- the solution used for inkjet printing is a mixed solution of In(NO 3 ) 3 ⁇ xH 2 O and ZrOCl 2 ⁇ xH 2 O dissolved in ethylene glycol monomethyl ether and ethylene glycol.
- the percentage of the zirconium atom number and the total number of zirconium indium atoms [Zr/(In+Zr)] in the zirconia indium semiconductor material may be 12%.
- a ITO (Indium Tin Oxide) metal thin film was formed by a sputtering method to a thickness of 500 nm, and a source electrode 14 and a drain electrode 15 were formed by a lift-off patterning method.
- the transfer characteristic curve of the metal oxide thin film transistor prepared for S20-S24 in air that is, the relationship between the drain current and the gate voltage.
- the test condition is that the source voltage (V S ) is 0V, the drain voltage (V D ) is constant at 20V, and the gate voltage (V G ) is first scanned from -20V to 20V, and then retraced from 20V to -20V. , test drain current (I D ). It can be seen that the thin film transistor in which zirconia indium prepared by the solution method is used as an active layer has excellent performance, the mobility is greatly improved, and the drain current is also low.
- the prepared thin film transistor has a mobility of 9.8 cm 2 /Vs, which satisfies the requirement of a thin film transistor mobility of more than 5 cm 2 /Vs, and the metal oxide thin film transistor prepared by the embodiment of the present disclosure has a low annealing temperature.
- the high mobility is compatible with flexible substrates.
- the substrate 10 of the thin film transistor of the embodiment of the present disclosure may be a hard substrate or a flexible substrate.
- the hard substrate is, for example, glass, silicon wafer, metal foil, quartz, or the like.
- the flexible substrate may be made of, for example, PEN, PET (polyethylene terephthalate), PI (polyimide), PC (polycarbonate), PEI (polyetherimide), or the like.
- the embodiment of the present disclosure further provides a method for preparing an array substrate, wherein the thin film transistor can be formed by the above method, and further a first electrode is formed.
- the array substrate can be used for an LCD (Liquid Crystal Display). Based on this, as shown in FIG. 8 , the first electrode can be the pixel electrode 18 .
- the method for preparing the array substrate further includes: forming a common electrode 19.
- a common electrode 19 for an IPS (In-Plane Switch) type array
- the pixel electrode 18 and the common electrode 19 are disposed at the same layer and are strip electrodes;
- the pixel electrode 18 and the common electrode 19 are disposed in different layers, wherein the upper electrode is a strip electrode and the lower electrode is a plate electrode.
- the array substrate can also be used in an AMOLED (Active Matrix/Organic Light Emitting Diode) display.
- the first electrode may be the anode 20
- the method for preparing the array substrate further includes: forming the cathode 21 and the organic material functional layer 22 between the anode 20 and the cathode 21 . .
- the organic material functional layer 22 may include at least a light emitting layer, and further may further include an electron transport layer and a hole transport layer. On the basis of this, in order to improve the efficiency of injecting the electron and hole into the light emitting layer, The organic material functional layer 22 may further include an electron injection layer formed between the cathode 21 and the electron transport layer, and a hole injection layer formed between the anode 20 and the hole transport layer.
- the material of the anode 20 and the cathode 21 it can be divided into a single-sided light-emitting OLED array substrate and a double-sided light-emitting OLED array substrate; that is, when the material of one of the anode 20 and the cathode 21 is opaque material.
- the OLED array substrate is a single-sided illumination type; when the materials of the anode 20 and the cathode 21 are both transparent materials, the OLED array substrate is a double-sided illumination type.
- the single-sided light-emitting OLED array substrate can be further classified into an upper light-emitting type and a lower light-emitting type depending on the materials of the anode 20 and the cathode 21. Specifically, when the anode 20 is disposed close to the substrate, the cathode 21 is disposed away from the substrate, and the material of the anode 20 is a transparent conductive material, and the material of the cathode 21 is an opaque conductive material, since the light is from the anode 20 and then through the substrate side.
- the emission may be referred to as a lower emission type; when the material of the anode 20 is an opaque conductive material and the material of the cathode 21 is a transparent conductive material, since light is emitted from the cathode 21 side, it may be referred to as an upper emission type.
- the relative positions of the above two anodes 20 and cathodes 21 can also be replaced, and details are not described herein again.
- the embodiment of the present disclosure further provides a thin film transistor, as shown in FIGS. 1 and 2, including a substrate 10, a gate electrode 11 disposed on the substrate 10, a gate insulating layer 12, an active layer 13, a source 14 and The drain 15; the material of the active layer 12 is a zirconia indium semiconductor material.
- the gate electrode 11 may be composed of a single layer or two or more layers.
- the material may be a conductive material such as a metal, an alloy, a conductive metal oxide, a doped silicon, a conductive polymer, or the like.
- the thickness of the gate electrode 11 may be between 100 nm and 2000 nm.
- the gate insulating layer 12 may be composed of a single layer or two or more layers.
- the material thereof may be, for example, silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxide oxide, hafnium oxide, titanium oxide, hafnium oxide, hafnium oxide, zirconium oxide, polymer insulation. Materials, photoresists, etc.
- two or more films composed of any combination of the above materials may be stacked.
- the thickness of the gate insulating layer 12 may be between 50 nm and 500 nm.
- the source 14 and the drain 15 may be composed of a single layer or two or more layers.
- the material may be a conductive material such as a metal, an alloy, a conductive metal oxide, a doped silicon, a conductive polymer, or the like.
- a conductive material such as a metal, an alloy, a conductive metal oxide, a doped silicon, a conductive polymer, or the like.
- two or more films composed of any combination of the above materials may be stacked.
- the thickness of the source 14 and the drain 15 may be between 100 nm and 2000 nm.
- the thickness of the active layer may be between 10 nm and 100 nm.
- the thin film transistor may be a bottom gate type, a top gate type, or a double gate type.
- the order in which the gate electrode 11, the source electrode 14 and the drain electrode 15 are formed is also different depending on the type of the thin film transistor.
- Embodiments of the present disclosure provide a method for fabricating a thin film transistor. Since zirconium indium oxide is used as a material of the active layer 13, and zirconium in the zirconia indium has an effect of suppressing oxygen vacancies, stability can be improved, and at the same time, Zirconia indium does not contain zinc, so it can reduce the sensitivity to water and oxygen. In addition, zirconium can also replace the indium to produce the donor level, so the carrier concentration can be maintained, thus avoiding the use of the solution method in the film preparation process. The problem that the carrier concentration caused by the introduced impurities sharply drops to cause a low mobility, the present disclosure can produce a thin film transistor having a high mobility.
- the metal oxide thin film transistor provided by the embodiment of the present disclosure has the characteristics of low preparation cost, since the active layer 13 is prepared by a solution method.
- the percentage of zirconium atoms and the total number of zirconium indium atoms [Zr/(In+Zr)] in the zirconia indium semiconductor material is between 0.1% and 20%, more preferably from 1% to 16%.
- the thin film transistor further includes an etch barrier layer 16 disposed between the active layer 13 and the source 14 and the drain 15 .
- the etch barrier layer 16 may have a thickness of 50 to 200 nm.
- the etch barrier layer 16 is formed.
- the zirconia indium is further prevented from being exposed to air to react with oxygen or water, and on the other hand, the process of subsequently forming the source 14 and the drain 15 can be avoided. The effect on the active layer 13 in the middle.
- the thin film transistor further includes a buffer layer 17 disposed on the surface of the substrate 10.
- a buffer layer 17 disposed on the surface of the substrate 10.
- the buffer layer 17 may have a thickness of 100 nm to 300 nm.
- the substrate 10 may be a hard substrate or a flexible substrate.
- the hard substrate is, for example, glass, silicon wafer, metal foil, quartz, or the like.
- the flexible substrate may be made of, for example, PEN, PET, PI, PC, PEI, or the like.
- An embodiment of the present disclosure further provides an array substrate including the thin film transistor described above, further including a first electrode electrically coupled to a drain of the thin film transistor.
- the array substrate can be used for an LCD. Based on this, as shown in FIG. 8 , the first electrode can be the pixel electrode 18 .
- the method for preparing the array substrate further includes a common electrode 19.
- the array substrate can also be used for an AMOLED display.
- the first electrode may be the anode 20
- the array substrate further includes a cathode 21 and an organic material functional layer 22 between the anode 20 and the cathode 21 .
- Embodiments of the present disclosure also provide a display panel including the above array substrate.
- the display panel When the first electrode is the pixel electrode 18, the display panel further includes a counter substrate.
- the display panel further includes a package substrate.
- Embodiments of the present disclosure also provide a display device including the above display panel.
- the display device may be an LCD or an OLED display device.
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Abstract
Description
Zr/(In+Zr) | 1% | 6% | 11% | 16% |
迁移率(cm2/Vs) | 19.6 | 25.3 | 11.2 | 7.1 |
磁滞效应(V) | 1.0 | 1.2 | 0.4 | 0.4 |
关态电流(A) | 1×10-9 | 1×10-8 | 5×10-10 | 1×10-11 |
Claims (14)
- 一种薄膜晶体管的制备方法,包括在衬底上制备形成栅极、栅绝缘层、有源层、源极和漏极;其中,通过溶液法制备形成所述有源层,所述有源层的材料为氧化锆铟半导体材料。
- 根据权利要求1所述的制备方法,其中,所述氧化锆铟半导体材料中锆原子数与锆铟原子总数的百分比介于0.1-20%之间。
- 根据权利要求1所述的制备方法,其中,通过溶液法制备形成所述有源层的步骤包括:通过喷墨打印的方法制备形成所述有源层。
- 根据权利要求3所述的制备方法,其中,喷墨打印采用的溶液为In(NO3)3·xH2O和ZrOCl2·xH2O溶于乙二醇单甲醚和乙二醇的混合溶液。
- 根据权利要求1-4任一项所述的制备方法,其中,在形成所述有源层之后,形成所述源极与所述漏极之前,所述方法还包括:形成刻蚀阻挡层。
- 根据权利要求1-4任一项所述的制备方法,其中,所述衬底为硬质衬底或柔性衬底。
- 一种阵列基板的制备方法,包括形成薄膜晶体管和与所述薄膜晶体管的漏极电联接的第一电极;其中,通过权利要求1-6任一项所述的制备方法形成所述薄膜晶体管。
- 根据权利要求7所述的制备方法,其中,所述第一电极为阳极,所述制备方法还包括:形成阴极以及位于所述阳极和所述阴极之间的有机材料功能层;或者,所述第一电极为像素电极。
- 一种薄膜晶体管,包括衬底、设置在所述衬底上的栅极、栅绝缘层、有源层、源极和漏极;其中,所述有源层的材料为氧化锆铟半导体材料。
- 根据权利要求9所述的薄膜晶体管,其中,所述氧化锆铟半导体材料中锆原子数与锆铟原子总数的百分比介于0.1%至20%之间。
- 根据权利要求9所述的薄膜晶体管,其中,所述衬底为硬质衬底或柔性衬底。
- 一种阵列基板,其中,包括权利要求9-11任一项所述的薄膜晶体管,还包括与所述薄膜晶体管的漏极电联接的第一电极。
- 一种显示面板,其中,包括权利要求12所述的阵列基板。
- 一种显示装置,其中,包括权利要求13所述的显示面板。
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CN105655389B (zh) * | 2016-01-15 | 2018-05-11 | 京东方科技集团股份有限公司 | 有源层、薄膜晶体管、阵列基板、显示装置及制备方法 |
CN105914150A (zh) | 2016-04-29 | 2016-08-31 | 京东方科技集团股份有限公司 | 薄膜晶体管及制备方法、阵列基板及制备方法、显示面板、显示装置 |
CN107331622A (zh) * | 2017-07-04 | 2017-11-07 | 华南理工大学 | 一种采用溶液加工的高介电氧化物绝缘层薄膜晶体管的制备方法 |
CN108447790A (zh) * | 2018-04-10 | 2018-08-24 | 华南理工大学 | 一种基于低温氧化锆绝缘层的薄膜晶体管及其制备方法 |
CN108766889A (zh) * | 2018-05-28 | 2018-11-06 | 华南理工大学 | 一种溶液法制备氧化物薄膜晶体管的方法 |
CN110970308B (zh) * | 2018-09-30 | 2023-07-21 | 中国科学院苏州纳米技术与纳米仿生研究所 | 薄膜晶体管及其异质结有源层的制作方法 |
CN112951853A (zh) * | 2021-04-14 | 2021-06-11 | 昆山龙腾光电股份有限公司 | 薄膜晶体管阵列基板及其制作方法 |
CN113555398B (zh) * | 2021-07-16 | 2024-05-24 | 京东方科技集团股份有限公司 | 显示模组的背板及其制备方法、显示面板、显示装置 |
CN114709173A (zh) * | 2022-03-30 | 2022-07-05 | 广州华星光电半导体显示技术有限公司 | 阵列基板及其制备方法、显示面板 |
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